1 //===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the entry points for global functions defined in
10 // the LLVM NVPTX back-end.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTX_H
15 #define LLVM_LIB_TARGET_NVPTX_NVPTX_H
16 
17 #include "llvm/IR/PassManager.h"
18 #include "llvm/Pass.h"
19 #include "llvm/Support/CodeGen.h"
20 
21 namespace llvm {
22 class FunctionPass;
23 class MachineFunctionPass;
24 class NVPTXTargetMachine;
25 class PassRegistry;
26 
27 namespace NVPTXCC {
28 enum CondCodes {
29   EQ,
30   NE,
31   LT,
32   LE,
33   GT,
34   GE
35 };
36 }
37 
38 FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM,
39                                  llvm::CodeGenOpt::Level OptLevel);
40 ModulePass *createNVPTXAssignValidGlobalNamesPass();
41 ModulePass *createGenericToNVVMLegacyPass();
42 ModulePass *createNVPTXCtorDtorLoweringLegacyPass();
43 FunctionPass *createNVVMIntrRangePass(unsigned int SmVersion);
44 FunctionPass *createNVVMReflectPass(unsigned int SmVersion);
45 MachineFunctionPass *createNVPTXPrologEpilogPass();
46 MachineFunctionPass *createNVPTXReplaceImageHandlesPass();
47 FunctionPass *createNVPTXImageOptimizerPass();
48 FunctionPass *createNVPTXLowerArgsPass();
49 FunctionPass *createNVPTXLowerAllocaPass();
50 FunctionPass *createNVPTXLowerUnreachablePass();
51 MachineFunctionPass *createNVPTXPeephole();
52 MachineFunctionPass *createNVPTXProxyRegErasurePass();
53 
54 struct NVVMIntrRangePass : PassInfoMixin<NVVMIntrRangePass> {
55   NVVMIntrRangePass();
56   NVVMIntrRangePass(unsigned SmVersion) : SmVersion(SmVersion) {}
57   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
58 
59 private:
60   unsigned SmVersion;
61 };
62 
63 struct NVVMReflectPass : PassInfoMixin<NVVMReflectPass> {
64   NVVMReflectPass();
65   NVVMReflectPass(unsigned SmVersion) : SmVersion(SmVersion) {}
66   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
67 
68 private:
69   unsigned SmVersion;
70 };
71 
72 struct GenericToNVVMPass : PassInfoMixin<GenericToNVVMPass> {
73   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
74 };
75 
76 namespace NVPTX {
77 enum DrvInterface {
78   NVCL,
79   CUDA
80 };
81 
82 // A field inside TSFlags needs a shift and a mask. The usage is
83 // always as follows :
84 // ((TSFlags & fieldMask) >> fieldShift)
85 // The enum keeps the mask, the shift, and all valid values of the
86 // field in one place.
87 enum VecInstType {
88   VecInstTypeShift = 0,
89   VecInstTypeMask = 0xF,
90 
91   VecNOP = 0,
92   VecLoad = 1,
93   VecStore = 2,
94   VecBuild = 3,
95   VecShuffle = 4,
96   VecExtract = 5,
97   VecInsert = 6,
98   VecDest = 7,
99   VecOther = 15
100 };
101 
102 enum SimpleMove {
103   SimpleMoveMask = 0x10,
104   SimpleMoveShift = 4
105 };
106 enum LoadStore {
107   isLoadMask = 0x20,
108   isLoadShift = 5,
109   isStoreMask = 0x40,
110   isStoreShift = 6
111 };
112 
113 namespace PTXLdStInstCode {
114 enum AddressSpace {
115   GENERIC = 0,
116   GLOBAL = 1,
117   CONSTANT = 2,
118   SHARED = 3,
119   PARAM = 4,
120   LOCAL = 5
121 };
122 enum FromType {
123   Unsigned = 0,
124   Signed,
125   Float,
126   Untyped
127 };
128 enum VecType {
129   Scalar = 1,
130   V2 = 2,
131   V4 = 4
132 };
133 }
134 
135 /// PTXCvtMode - Conversion code enumeration
136 namespace PTXCvtMode {
137 enum CvtMode {
138   NONE = 0,
139   RNI,
140   RZI,
141   RMI,
142   RPI,
143   RN,
144   RZ,
145   RM,
146   RP,
147   RNA,
148 
149   BASE_MASK = 0x0F,
150   FTZ_FLAG = 0x10,
151   SAT_FLAG = 0x20,
152   RELU_FLAG = 0x40
153 };
154 }
155 
156 /// PTXCmpMode - Comparison mode enumeration
157 namespace PTXCmpMode {
158 enum CmpMode {
159   EQ = 0,
160   NE,
161   LT,
162   LE,
163   GT,
164   GE,
165   LO,
166   LS,
167   HI,
168   HS,
169   EQU,
170   NEU,
171   LTU,
172   LEU,
173   GTU,
174   GEU,
175   NUM,
176   // NAN is a MACRO
177   NotANumber,
178 
179   BASE_MASK = 0xFF,
180   FTZ_FLAG = 0x100
181 };
182 }
183 }
184 void initializeNVPTXDAGToDAGISelPass(PassRegistry &);
185 } // namespace llvm
186 
187 // Defines symbolic names for NVPTX registers.  This defines a mapping from
188 // register name to register number.
189 #define GET_REGINFO_ENUM
190 #include "NVPTXGenRegisterInfo.inc"
191 
192 // Defines symbolic names for the NVPTX instructions.
193 #define GET_INSTRINFO_ENUM
194 #define GET_INSTRINFO_MC_HELPER_DECLS
195 #include "NVPTXGenInstrInfo.inc"
196 
197 #endif
198