1//===- NVPTX.td - Describe the NVPTX Target Machine -----------*- tblgen -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// This is the top level entry point for the NVPTX target.
9//===----------------------------------------------------------------------===//
10
11//===----------------------------------------------------------------------===//
12// Target-independent interfaces
13//===----------------------------------------------------------------------===//
14
15include "llvm/Target/Target.td"
16
17include "NVPTXRegisterInfo.td"
18include "NVPTXInstrInfo.td"
19
20//===----------------------------------------------------------------------===//
21// Subtarget Features.
22// - We use the SM version number instead of explicit feature table.
23// - Need at least one feature to avoid generating zero sized array by
24//   TableGen in NVPTXGenSubtarget.inc.
25//===----------------------------------------------------------------------===//
26
27class FeatureSM<int version>:
28   SubtargetFeature<"sm_"# version, "SmVersion",
29                    "" # version,
30                    "Target SM " # version>;
31def SM90a: FeatureSM<90>;
32
33class FeaturePTX<int version>:
34   SubtargetFeature<"ptx"# version, "PTXVersion",
35                    "" # version,
36                    "Use PTX version " # version>;
37
38foreach version = [20, 21, 30, 32, 35, 37, 50, 52, 53,
39                   60, 61, 62, 70, 72, 75, 80, 86, 87, 89, 90] in
40  def SM#version: FeatureSM<version>;
41
42foreach version = [32, 40, 41, 42, 43, 50, 60, 61, 63, 64, 65,
43                   70, 71, 72, 73, 74, 75, 76, 77, 78, 80, 81] in
44  def PTX#version: FeaturePTX<version>;
45
46//===----------------------------------------------------------------------===//
47// NVPTX supported processors.
48//===----------------------------------------------------------------------===//
49
50class Proc<string Name, list<SubtargetFeature> Features>
51 : Processor<Name, NoItineraries, Features>;
52
53def : Proc<"sm_20", [SM20, PTX32]>;
54def : Proc<"sm_21", [SM21, PTX32]>;
55def : Proc<"sm_30", [SM30]>;
56def : Proc<"sm_32", [SM32, PTX40]>;
57def : Proc<"sm_35", [SM35, PTX32]>;
58def : Proc<"sm_37", [SM37, PTX41]>;
59def : Proc<"sm_50", [SM50, PTX40]>;
60def : Proc<"sm_52", [SM52, PTX41]>;
61def : Proc<"sm_53", [SM53, PTX42]>;
62def : Proc<"sm_60", [SM60, PTX50]>;
63def : Proc<"sm_61", [SM61, PTX50]>;
64def : Proc<"sm_62", [SM62, PTX50]>;
65def : Proc<"sm_70", [SM70, PTX60]>;
66def : Proc<"sm_72", [SM72, PTX61]>;
67def : Proc<"sm_75", [SM75, PTX63]>;
68def : Proc<"sm_80", [SM80, PTX70]>;
69def : Proc<"sm_86", [SM86, PTX71]>;
70def : Proc<"sm_87", [SM87, PTX74]>;
71def : Proc<"sm_89", [SM89, PTX78]>;
72def : Proc<"sm_90", [SM90, PTX78]>;
73def : Proc<"sm_90a", [SM90a, PTX80]>;
74
75def NVPTXInstrInfo : InstrInfo {
76}
77
78def NVPTX : Target {
79  let InstructionSet = NVPTXInstrInfo;
80}
81