1 //=======- NVPTXFrameLowering.cpp - NVPTX Frame Information ---*- C++ -*-=====//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the NVPTX implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "NVPTXFrameLowering.h"
14 #include "NVPTX.h"
15 #include "NVPTXRegisterInfo.h"
16 #include "NVPTXSubtarget.h"
17 #include "NVPTXTargetMachine.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/MC/MachineLocation.h"
24 
25 using namespace llvm;
26 
27 NVPTXFrameLowering::NVPTXFrameLowering()
28     : TargetFrameLowering(TargetFrameLowering::StackGrowsUp, Align(8), 0) {}
29 
30 bool NVPTXFrameLowering::hasFP(const MachineFunction &MF) const { return true; }
31 
32 void NVPTXFrameLowering::emitPrologue(MachineFunction &MF,
33                                       MachineBasicBlock &MBB) const {
34   if (MF.getFrameInfo().hasStackObjects()) {
35     assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
36     MachineBasicBlock::iterator MBBI = MBB.begin();
37     MachineRegisterInfo &MR = MF.getRegInfo();
38 
39     const NVPTXRegisterInfo *NRI =
40         MF.getSubtarget<NVPTXSubtarget>().getRegisterInfo();
41 
42     // This instruction really occurs before first instruction
43     // in the BB, so giving it no debug location.
44     DebugLoc dl = DebugLoc();
45 
46     // Emits
47     //   mov %SPL, %depot;
48     //   cvta.local %SP, %SPL;
49     // for local address accesses in MF.
50     bool Is64Bit =
51         static_cast<const NVPTXTargetMachine &>(MF.getTarget()).is64Bit();
52     unsigned CvtaLocalOpcode =
53         (Is64Bit ? NVPTX::cvta_local_yes_64 : NVPTX::cvta_local_yes);
54     unsigned MovDepotOpcode =
55         (Is64Bit ? NVPTX::MOV_DEPOT_ADDR_64 : NVPTX::MOV_DEPOT_ADDR);
56     if (!MR.use_empty(NRI->getFrameRegister(MF))) {
57       // If %SP is not used, do not bother emitting "cvta.local %SP, %SPL".
58       MBBI = BuildMI(MBB, MBBI, dl,
59                      MF.getSubtarget().getInstrInfo()->get(CvtaLocalOpcode),
60                      NRI->getFrameRegister(MF))
61                  .addReg(NRI->getFrameLocalRegister(MF));
62     }
63     BuildMI(MBB, MBBI, dl,
64             MF.getSubtarget().getInstrInfo()->get(MovDepotOpcode),
65             NRI->getFrameLocalRegister(MF))
66         .addImm(MF.getFunctionNumber());
67   }
68 }
69 
70 StackOffset
71 NVPTXFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
72                                            Register &FrameReg) const {
73   const MachineFrameInfo &MFI = MF.getFrameInfo();
74   FrameReg = NVPTX::VRDepot;
75   return StackOffset::getFixed(MFI.getObjectOffset(FI) -
76                                getOffsetOfLocalArea());
77 }
78 
79 void NVPTXFrameLowering::emitEpilogue(MachineFunction &MF,
80                                       MachineBasicBlock &MBB) const {}
81 
82 // This function eliminates ADJCALLSTACKDOWN,
83 // ADJCALLSTACKUP pseudo instructions
84 MachineBasicBlock::iterator NVPTXFrameLowering::eliminateCallFramePseudoInstr(
85     MachineFunction &MF, MachineBasicBlock &MBB,
86     MachineBasicBlock::iterator I) const {
87   // Simply discard ADJCALLSTACKDOWN,
88   // ADJCALLSTACKUP instructions.
89   return MBB.erase(I);
90 }
91 
92 TargetFrameLowering::DwarfFrameBase
93 NVPTXFrameLowering::getDwarfFrameBase(const MachineFunction &MF) const {
94   return {DwarfFrameBase::CFA, {0}};
95 }
96