1//===-- NVPTXRegisterInfo.td - NVPTX Register defs ---------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the PTX register file 11//===----------------------------------------------------------------------===// 12 13class NVPTXReg<string n> : Register<n> { 14 let Namespace = "NVPTX"; 15} 16 17class NVPTXRegClass<list<ValueType> regTypes, int alignment, dag regList> 18 : RegisterClass <"NVPTX", regTypes, alignment, regList>; 19 20//===----------------------------------------------------------------------===// 21// Registers 22//===----------------------------------------------------------------------===// 23 24// Special Registers used as stack pointer 25def VRFrame32 : NVPTXReg<"%SP">; 26def VRFrame64 : NVPTXReg<"%SP">; 27def VRFrameLocal32 : NVPTXReg<"%SPL">; 28def VRFrameLocal64 : NVPTXReg<"%SPL">; 29 30// Special Registers used as the stack 31def VRDepot : NVPTXReg<"%Depot">; 32 33// We use virtual registers, but define a few physical registers here to keep 34// SDAG and the MachineInstr layers happy. 35foreach i = 0...4 in { 36 def P#i : NVPTXReg<"%p"#i>; // Predicate 37 def RS#i : NVPTXReg<"%rs"#i>; // 16-bit 38 def R#i : NVPTXReg<"%r"#i>; // 32-bit 39 def RL#i : NVPTXReg<"%rd"#i>; // 64-bit 40 def H#i : NVPTXReg<"%h"#i>; // 16-bit float 41 def HH#i : NVPTXReg<"%hh"#i>; // 2x16-bit float 42 def F#i : NVPTXReg<"%f"#i>; // 32-bit float 43 def FL#i : NVPTXReg<"%fd"#i>; // 64-bit float 44 45 // Arguments 46 def ia#i : NVPTXReg<"%ia"#i>; 47 def la#i : NVPTXReg<"%la"#i>; 48 def fa#i : NVPTXReg<"%fa"#i>; 49 def da#i : NVPTXReg<"%da"#i>; 50} 51 52foreach i = 0...31 in { 53 def ENVREG#i : NVPTXReg<"%envreg"#i>; 54} 55 56//===----------------------------------------------------------------------===// 57// Register classes 58//===----------------------------------------------------------------------===// 59def Int1Regs : NVPTXRegClass<[i1], 8, (add (sequence "P%u", 0, 4))>; 60def Int16Regs : NVPTXRegClass<[i16], 16, (add (sequence "RS%u", 0, 4))>; 61def Int32Regs : NVPTXRegClass<[i32], 32, (add (sequence "R%u", 0, 4), VRFrame32, VRFrameLocal32)>; 62def Int64Regs : NVPTXRegClass<[i64], 64, (add (sequence "RL%u", 0, 4), VRFrame64, VRFrameLocal64)>; 63def Float16Regs : NVPTXRegClass<[f16], 16, (add (sequence "H%u", 0, 4))>; 64def Float16x2Regs : NVPTXRegClass<[v2f16], 32, (add (sequence "HH%u", 0, 4))>; 65def Float32Regs : NVPTXRegClass<[f32], 32, (add (sequence "F%u", 0, 4))>; 66def Float64Regs : NVPTXRegClass<[f64], 64, (add (sequence "FL%u", 0, 4))>; 67def Int32ArgRegs : NVPTXRegClass<[i32], 32, (add (sequence "ia%u", 0, 4))>; 68def Int64ArgRegs : NVPTXRegClass<[i64], 64, (add (sequence "la%u", 0, 4))>; 69def Float32ArgRegs : NVPTXRegClass<[f32], 32, (add (sequence "fa%u", 0, 4))>; 70def Float64ArgRegs : NVPTXRegClass<[f64], 64, (add (sequence "da%u", 0, 4))>; 71 72// Read NVPTXRegisterInfo.cpp to see how VRFrame and VRDepot are used. 73def SpecialRegs : NVPTXRegClass<[i32], 32, (add VRFrame32, VRFrameLocal32, VRDepot, 74 (sequence "ENVREG%u", 0, 31))>; 75