1 //===-- NVPTXTargetTransformInfo.h - NVPTX specific TTI ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file a TargetTransformInfo::Concept conforming object specific to the
10 /// NVPTX target machine. It uses the target's detailed information to
11 /// provide more precise answers to certain TTI queries, while letting the
12 /// target independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
18 
19 #include "NVPTXTargetMachine.h"
20 #include "MCTargetDesc/NVPTXBaseInfo.h"
21 #include "llvm/Analysis/TargetTransformInfo.h"
22 #include "llvm/CodeGen/BasicTTIImpl.h"
23 #include "llvm/CodeGen/TargetLowering.h"
24 
25 namespace llvm {
26 
27 class NVPTXTTIImpl : public BasicTTIImplBase<NVPTXTTIImpl> {
28   typedef BasicTTIImplBase<NVPTXTTIImpl> BaseT;
29   typedef TargetTransformInfo TTI;
30   friend BaseT;
31 
32   const NVPTXSubtarget *ST;
33   const NVPTXTargetLowering *TLI;
34 
35   const NVPTXSubtarget *getST() const { return ST; };
36   const NVPTXTargetLowering *getTLI() const { return TLI; };
37 
38 public:
39   explicit NVPTXTTIImpl(const NVPTXTargetMachine *TM, const Function &F)
40       : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl()),
41         TLI(ST->getTargetLowering()) {}
42 
43   bool hasBranchDivergence() { return true; }
44 
45   bool isSourceOfDivergence(const Value *V);
46 
47   unsigned getFlatAddressSpace() const {
48     return AddressSpace::ADDRESS_SPACE_GENERIC;
49   }
50 
51   Optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
52                                                IntrinsicInst &II) const;
53 
54   // Loads and stores can be vectorized if the alignment is at least as big as
55   // the load/store we want to vectorize.
56   bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
57                                    unsigned AddrSpace) const {
58     return Alignment >= ChainSizeInBytes;
59   }
60   bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
61                                     unsigned AddrSpace) const {
62     return isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment, AddrSpace);
63   }
64 
65   // NVPTX has infinite registers of all kinds, but the actual machine doesn't.
66   // We conservatively return 1 here which is just enough to enable the
67   // vectorizers but disables heuristics based on the number of registers.
68   // FIXME: Return a more reasonable number, while keeping an eye on
69   // LoopVectorizer's unrolling heuristics.
70   unsigned getNumberOfRegisters(bool Vector) const { return 1; }
71 
72   // Only <2 x half> should be vectorized, so always return 32 for the vector
73   // register size.
74   unsigned getRegisterBitWidth(bool Vector) const { return 32; }
75   unsigned getMinVectorRegisterBitWidth() const { return 32; }
76 
77   // We don't want to prevent inlining because of target-cpu and -features
78   // attributes that were added to newer versions of LLVM/Clang: There are
79   // no incompatible functions in PTX, ptxas will throw errors in such cases.
80   bool areInlineCompatible(const Function *Caller,
81                            const Function *Callee) const {
82     return true;
83   }
84 
85   // Increase the inlining cost threshold by a factor of 5, reflecting that
86   // calls are particularly expensive in NVPTX.
87   unsigned getInliningThresholdMultiplier() { return 5; }
88 
89   int getArithmeticInstrCost(
90       unsigned Opcode, Type *Ty,
91       TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput,
92       TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
93       TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
94       TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
95       TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
96       ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
97       const Instruction *CxtI = nullptr);
98 
99   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
100                                TTI::UnrollingPreferences &UP);
101 
102   void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
103                              TTI::PeelingPreferences &PP);
104 
105   bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) {
106     // Volatile loads/stores are only supported for shared and global address
107     // spaces, or for generic AS that maps to them.
108     if (!(AddrSpace == llvm::ADDRESS_SPACE_GENERIC ||
109           AddrSpace == llvm::ADDRESS_SPACE_GLOBAL ||
110           AddrSpace == llvm::ADDRESS_SPACE_SHARED))
111       return false;
112 
113     switch(I->getOpcode()){
114     default:
115       return false;
116     case Instruction::Load:
117     case Instruction::Store:
118       return true;
119     }
120   }
121 };
122 
123 } // end namespace llvm
124 
125 #endif
126