1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "MCTargetDesc/PPCMCExpr.h"
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "PPCTargetStreamer.h"
12 #include "TargetInfo/PowerPCTargetInfo.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrInfo.h"
19 #include "llvm/MC/MCParser/MCAsmLexer.h"
20 #include "llvm/MC/MCParser/MCAsmParser.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCSymbolELF.h"
26 #include "llvm/MC/TargetRegistry.h"
27 #include "llvm/Support/SourceMgr.h"
28 #include "llvm/Support/raw_ostream.h"
29 
30 using namespace llvm;
31 
32 DEFINE_PPC_REGCLASSES
33 
34 // Evaluate an expression containing condition register
35 // or condition register field symbols.  Returns positive
36 // value on success, or -1 on error.
37 static int64_t
EvaluateCRExpr(const MCExpr * E)38 EvaluateCRExpr(const MCExpr *E) {
39   switch (E->getKind()) {
40   case MCExpr::Target:
41     return -1;
42 
43   case MCExpr::Constant: {
44     int64_t Res = cast<MCConstantExpr>(E)->getValue();
45     return Res < 0 ? -1 : Res;
46   }
47 
48   case MCExpr::SymbolRef: {
49     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
50     StringRef Name = SRE->getSymbol().getName();
51 
52     if (Name == "lt") return 0;
53     if (Name == "gt") return 1;
54     if (Name == "eq") return 2;
55     if (Name == "so") return 3;
56     if (Name == "un") return 3;
57 
58     if (Name == "cr0") return 0;
59     if (Name == "cr1") return 1;
60     if (Name == "cr2") return 2;
61     if (Name == "cr3") return 3;
62     if (Name == "cr4") return 4;
63     if (Name == "cr5") return 5;
64     if (Name == "cr6") return 6;
65     if (Name == "cr7") return 7;
66 
67     return -1;
68   }
69 
70   case MCExpr::Unary:
71     return -1;
72 
73   case MCExpr::Binary: {
74     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
75     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
76     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
77     int64_t Res;
78 
79     if (LHSVal < 0 || RHSVal < 0)
80       return -1;
81 
82     switch (BE->getOpcode()) {
83     default: return -1;
84     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
85     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
86     }
87 
88     return Res < 0 ? -1 : Res;
89   }
90   }
91 
92   llvm_unreachable("Invalid expression kind!");
93 }
94 
95 namespace {
96 
97 struct PPCOperand;
98 
99 class PPCAsmParser : public MCTargetAsmParser {
100   bool IsPPC64;
101 
Warning(SMLoc L,const Twine & Msg)102   void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
103 
isPPC64() const104   bool isPPC64() const { return IsPPC64; }
105 
106   bool MatchRegisterName(MCRegister &RegNo, int64_t &IntVal);
107 
108   bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
109   ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
110                                SMLoc &EndLoc) override;
111 
112   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
113                                         PPCMCExpr::VariantKind &Variant);
114   const MCExpr *FixupVariantKind(const MCExpr *E);
115   bool ParseExpression(const MCExpr *&EVal);
116 
117   bool ParseOperand(OperandVector &Operands);
118 
119   bool ParseDirectiveWord(unsigned Size, AsmToken ID);
120   bool ParseDirectiveTC(unsigned Size, AsmToken ID);
121   bool ParseDirectiveMachine(SMLoc L);
122   bool ParseDirectiveAbiVersion(SMLoc L);
123   bool ParseDirectiveLocalEntry(SMLoc L);
124   bool ParseGNUAttribute(SMLoc L);
125 
126   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
127                                OperandVector &Operands, MCStreamer &Out,
128                                uint64_t &ErrorInfo,
129                                bool MatchingInlineAsm) override;
130 
131   void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
132 
133   /// @name Auto-generated Match Functions
134   /// {
135 
136 #define GET_ASSEMBLER_HEADER
137 #include "PPCGenAsmMatcher.inc"
138 
139   /// }
140 
141 
142 public:
PPCAsmParser(const MCSubtargetInfo & STI,MCAsmParser &,const MCInstrInfo & MII,const MCTargetOptions & Options)143   PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
144                const MCInstrInfo &MII, const MCTargetOptions &Options)
145     : MCTargetAsmParser(Options, STI, MII) {
146     // Check for 64-bit vs. 32-bit pointer mode.
147     const Triple &TheTriple = STI.getTargetTriple();
148     IsPPC64 = TheTriple.isPPC64();
149     // Initialize the set of available features.
150     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
151   }
152 
153   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
154                         SMLoc NameLoc, OperandVector &Operands) override;
155 
156   bool ParseDirective(AsmToken DirectiveID) override;
157 
158   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
159                                       unsigned Kind) override;
160 
161   const MCExpr *applyModifierToExpr(const MCExpr *E,
162                                     MCSymbolRefExpr::VariantKind,
163                                     MCContext &Ctx) override;
164 };
165 
166 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
167 /// instruction.
168 struct PPCOperand : public MCParsedAsmOperand {
169   enum KindTy {
170     Token,
171     Immediate,
172     ContextImmediate,
173     Expression,
174     TLSRegister
175   } Kind;
176 
177   SMLoc StartLoc, EndLoc;
178   bool IsPPC64;
179 
180   struct TokOp {
181     const char *Data;
182     unsigned Length;
183   };
184 
185   struct ImmOp {
186     int64_t Val;
187   };
188 
189   struct ExprOp {
190     const MCExpr *Val;
191     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
192   };
193 
194   struct TLSRegOp {
195     const MCSymbolRefExpr *Sym;
196   };
197 
198   union {
199     struct TokOp Tok;
200     struct ImmOp Imm;
201     struct ExprOp Expr;
202     struct TLSRegOp TLSReg;
203   };
204 
PPCOperand__anonadcd8acb0111::PPCOperand205   PPCOperand(KindTy K) : Kind(K) {}
206 
207 public:
PPCOperand__anonadcd8acb0111::PPCOperand208   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
209     Kind = o.Kind;
210     StartLoc = o.StartLoc;
211     EndLoc = o.EndLoc;
212     IsPPC64 = o.IsPPC64;
213     switch (Kind) {
214     case Token:
215       Tok = o.Tok;
216       break;
217     case Immediate:
218     case ContextImmediate:
219       Imm = o.Imm;
220       break;
221     case Expression:
222       Expr = o.Expr;
223       break;
224     case TLSRegister:
225       TLSReg = o.TLSReg;
226       break;
227     }
228   }
229 
230   // Disable use of sized deallocation due to overallocation of PPCOperand
231   // objects in CreateTokenWithStringCopy.
operator delete__anonadcd8acb0111::PPCOperand232   void operator delete(void *p) { ::operator delete(p); }
233 
234   /// getStartLoc - Get the location of the first token of this operand.
getStartLoc__anonadcd8acb0111::PPCOperand235   SMLoc getStartLoc() const override { return StartLoc; }
236 
237   /// getEndLoc - Get the location of the last token of this operand.
getEndLoc__anonadcd8acb0111::PPCOperand238   SMLoc getEndLoc() const override { return EndLoc; }
239 
240   /// getLocRange - Get the range between the first and last token of this
241   /// operand.
getLocRange__anonadcd8acb0111::PPCOperand242   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
243 
244   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
isPPC64__anonadcd8acb0111::PPCOperand245   bool isPPC64() const { return IsPPC64; }
246 
getImm__anonadcd8acb0111::PPCOperand247   int64_t getImm() const {
248     assert(Kind == Immediate && "Invalid access!");
249     return Imm.Val;
250   }
getImmS16Context__anonadcd8acb0111::PPCOperand251   int64_t getImmS16Context() const {
252     assert((Kind == Immediate || Kind == ContextImmediate) &&
253            "Invalid access!");
254     if (Kind == Immediate)
255       return Imm.Val;
256     return static_cast<int16_t>(Imm.Val);
257   }
getImmU16Context__anonadcd8acb0111::PPCOperand258   int64_t getImmU16Context() const {
259     assert((Kind == Immediate || Kind == ContextImmediate) &&
260            "Invalid access!");
261     return Imm.Val;
262   }
263 
getExpr__anonadcd8acb0111::PPCOperand264   const MCExpr *getExpr() const {
265     assert(Kind == Expression && "Invalid access!");
266     return Expr.Val;
267   }
268 
getExprCRVal__anonadcd8acb0111::PPCOperand269   int64_t getExprCRVal() const {
270     assert(Kind == Expression && "Invalid access!");
271     return Expr.CRVal;
272   }
273 
getTLSReg__anonadcd8acb0111::PPCOperand274   const MCExpr *getTLSReg() const {
275     assert(Kind == TLSRegister && "Invalid access!");
276     return TLSReg.Sym;
277   }
278 
getReg__anonadcd8acb0111::PPCOperand279   unsigned getReg() const override {
280     assert(isRegNumber() && "Invalid access!");
281     return (unsigned) Imm.Val;
282   }
283 
getFpReg__anonadcd8acb0111::PPCOperand284   unsigned getFpReg() const {
285     assert(isEvenRegNumber() && "Invalid access!");
286     return (unsigned)(Imm.Val >> 1);
287   }
288 
getVSReg__anonadcd8acb0111::PPCOperand289   unsigned getVSReg() const {
290     assert(isVSRegNumber() && "Invalid access!");
291     return (unsigned) Imm.Val;
292   }
293 
getACCReg__anonadcd8acb0111::PPCOperand294   unsigned getACCReg() const {
295     assert(isACCRegNumber() && "Invalid access!");
296     return (unsigned) Imm.Val;
297   }
298 
getDMRROWReg__anonadcd8acb0111::PPCOperand299   unsigned getDMRROWReg() const {
300     assert(isDMRROWRegNumber() && "Invalid access!");
301     return (unsigned)Imm.Val;
302   }
303 
getDMRROWpReg__anonadcd8acb0111::PPCOperand304   unsigned getDMRROWpReg() const {
305     assert(isDMRROWpRegNumber() && "Invalid access!");
306     return (unsigned)Imm.Val;
307   }
308 
getDMRReg__anonadcd8acb0111::PPCOperand309   unsigned getDMRReg() const {
310     assert(isDMRRegNumber() && "Invalid access!");
311     return (unsigned)Imm.Val;
312   }
313 
getDMRpReg__anonadcd8acb0111::PPCOperand314   unsigned getDMRpReg() const {
315     assert(isDMRpRegNumber() && "Invalid access!");
316     return (unsigned)Imm.Val;
317   }
318 
getVSRpEvenReg__anonadcd8acb0111::PPCOperand319   unsigned getVSRpEvenReg() const {
320     assert(isVSRpEvenRegNumber() && "Invalid access!");
321     return (unsigned) Imm.Val >> 1;
322   }
323 
getG8pReg__anonadcd8acb0111::PPCOperand324   unsigned getG8pReg() const {
325     assert(isEvenRegNumber() && "Invalid access!");
326     return (unsigned)Imm.Val;
327   }
328 
getCCReg__anonadcd8acb0111::PPCOperand329   unsigned getCCReg() const {
330     assert(isCCRegNumber() && "Invalid access!");
331     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
332   }
333 
getCRBit__anonadcd8acb0111::PPCOperand334   unsigned getCRBit() const {
335     assert(isCRBitNumber() && "Invalid access!");
336     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
337   }
338 
getCRBitMask__anonadcd8acb0111::PPCOperand339   unsigned getCRBitMask() const {
340     assert(isCRBitMask() && "Invalid access!");
341     return 7 - llvm::countr_zero<uint64_t>(Imm.Val);
342   }
343 
isToken__anonadcd8acb0111::PPCOperand344   bool isToken() const override { return Kind == Token; }
isImm__anonadcd8acb0111::PPCOperand345   bool isImm() const override {
346     return Kind == Immediate || Kind == Expression;
347   }
isU1Imm__anonadcd8acb0111::PPCOperand348   bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
isU2Imm__anonadcd8acb0111::PPCOperand349   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
isU3Imm__anonadcd8acb0111::PPCOperand350   bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
isU4Imm__anonadcd8acb0111::PPCOperand351   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
isU5Imm__anonadcd8acb0111::PPCOperand352   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
isS5Imm__anonadcd8acb0111::PPCOperand353   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
isU6Imm__anonadcd8acb0111::PPCOperand354   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
isU6ImmX2__anonadcd8acb0111::PPCOperand355   bool isU6ImmX2() const { return Kind == Immediate &&
356                                   isUInt<6>(getImm()) &&
357                                   (getImm() & 1) == 0; }
isU7Imm__anonadcd8acb0111::PPCOperand358   bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
isU7ImmX4__anonadcd8acb0111::PPCOperand359   bool isU7ImmX4() const { return Kind == Immediate &&
360                                   isUInt<7>(getImm()) &&
361                                   (getImm() & 3) == 0; }
isU8Imm__anonadcd8acb0111::PPCOperand362   bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
isU8ImmX8__anonadcd8acb0111::PPCOperand363   bool isU8ImmX8() const { return Kind == Immediate &&
364                                   isUInt<8>(getImm()) &&
365                                   (getImm() & 7) == 0; }
366 
isU10Imm__anonadcd8acb0111::PPCOperand367   bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
isU12Imm__anonadcd8acb0111::PPCOperand368   bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
isU16Imm__anonadcd8acb0111::PPCOperand369   bool isU16Imm() const { return isExtImm<16>(/*Signed*/ false, 1); }
isS16Imm__anonadcd8acb0111::PPCOperand370   bool isS16Imm() const { return isExtImm<16>(/*Signed*/ true, 1); }
isS16ImmX4__anonadcd8acb0111::PPCOperand371   bool isS16ImmX4() const { return isExtImm<16>(/*Signed*/ true, 4); }
isS16ImmX16__anonadcd8acb0111::PPCOperand372   bool isS16ImmX16() const { return isExtImm<16>(/*Signed*/ true, 16); }
isS17Imm__anonadcd8acb0111::PPCOperand373   bool isS17Imm() const { return isExtImm<17>(/*Signed*/ true, 1); }
374 
isHashImmX8__anonadcd8acb0111::PPCOperand375   bool isHashImmX8() const {
376     // The Hash Imm form is used for instructions that check or store a hash.
377     // These instructions have a small immediate range that spans between
378     // -8 and -512.
379     return (Kind == Immediate && getImm() <= -8 && getImm() >= -512 &&
380             (getImm() & 7) == 0);
381   }
382 
isS34ImmX16__anonadcd8acb0111::PPCOperand383   bool isS34ImmX16() const {
384     return Kind == Expression ||
385            (Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0);
386   }
isS34Imm__anonadcd8acb0111::PPCOperand387   bool isS34Imm() const {
388     // Once the PC-Rel ABI is finalized, evaluate whether a 34-bit
389     // ContextImmediate is needed.
390     return Kind == Expression || (Kind == Immediate && isInt<34>(getImm()));
391   }
392 
isTLSReg__anonadcd8acb0111::PPCOperand393   bool isTLSReg() const { return Kind == TLSRegister; }
isDirectBr__anonadcd8acb0111::PPCOperand394   bool isDirectBr() const {
395     if (Kind == Expression)
396       return true;
397     if (Kind != Immediate)
398       return false;
399     // Operand must be 64-bit aligned, signed 27-bit immediate.
400     if ((getImm() & 3) != 0)
401       return false;
402     if (isInt<26>(getImm()))
403       return true;
404     if (!IsPPC64) {
405       // In 32-bit mode, large 32-bit quantities wrap around.
406       if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
407         return true;
408     }
409     return false;
410   }
isCondBr__anonadcd8acb0111::PPCOperand411   bool isCondBr() const { return Kind == Expression ||
412                                  (Kind == Immediate && isInt<16>(getImm()) &&
413                                   (getImm() & 3) == 0); }
isImmZero__anonadcd8acb0111::PPCOperand414   bool isImmZero() const { return Kind == Immediate && getImm() == 0; }
isRegNumber__anonadcd8acb0111::PPCOperand415   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
isACCRegNumber__anonadcd8acb0111::PPCOperand416   bool isACCRegNumber() const {
417     return Kind == Immediate && isUInt<3>(getImm());
418   }
isDMRROWRegNumber__anonadcd8acb0111::PPCOperand419   bool isDMRROWRegNumber() const {
420     return Kind == Immediate && isUInt<6>(getImm());
421   }
isDMRROWpRegNumber__anonadcd8acb0111::PPCOperand422   bool isDMRROWpRegNumber() const {
423     return Kind == Immediate && isUInt<5>(getImm());
424   }
isDMRRegNumber__anonadcd8acb0111::PPCOperand425   bool isDMRRegNumber() const {
426     return Kind == Immediate && isUInt<3>(getImm());
427   }
isDMRpRegNumber__anonadcd8acb0111::PPCOperand428   bool isDMRpRegNumber() const {
429     return Kind == Immediate && isUInt<2>(getImm());
430   }
isVSRpEvenRegNumber__anonadcd8acb0111::PPCOperand431   bool isVSRpEvenRegNumber() const {
432     return Kind == Immediate && isUInt<6>(getImm()) && ((getImm() & 1) == 0);
433   }
isVSRegNumber__anonadcd8acb0111::PPCOperand434   bool isVSRegNumber() const {
435     return Kind == Immediate && isUInt<6>(getImm());
436   }
isCCRegNumber__anonadcd8acb0111::PPCOperand437   bool isCCRegNumber() const { return (Kind == Expression
438                                        && isUInt<3>(getExprCRVal())) ||
439                                       (Kind == Immediate
440                                        && isUInt<3>(getImm())); }
isCRBitNumber__anonadcd8acb0111::PPCOperand441   bool isCRBitNumber() const { return (Kind == Expression
442                                        && isUInt<5>(getExprCRVal())) ||
443                                       (Kind == Immediate
444                                        && isUInt<5>(getImm())); }
445 
isEvenRegNumber__anonadcd8acb0111::PPCOperand446   bool isEvenRegNumber() const { return isRegNumber() && (getImm() & 1) == 0; }
447 
isCRBitMask__anonadcd8acb0111::PPCOperand448   bool isCRBitMask() const {
449     return Kind == Immediate && isUInt<8>(getImm()) &&
450            llvm::has_single_bit<uint32_t>(getImm());
451   }
isATBitsAsHint__anonadcd8acb0111::PPCOperand452   bool isATBitsAsHint() const { return false; }
isMem__anonadcd8acb0111::PPCOperand453   bool isMem() const override { return false; }
isReg__anonadcd8acb0111::PPCOperand454   bool isReg() const override { return false; }
455 
addRegOperands__anonadcd8acb0111::PPCOperand456   void addRegOperands(MCInst &Inst, unsigned N) const {
457     llvm_unreachable("addRegOperands");
458   }
459 
addRegGPRCOperands__anonadcd8acb0111::PPCOperand460   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
461     assert(N == 1 && "Invalid number of operands!");
462     Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
463   }
464 
addRegGPRCNoR0Operands__anonadcd8acb0111::PPCOperand465   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
466     assert(N == 1 && "Invalid number of operands!");
467     Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
468   }
469 
addRegG8RCOperands__anonadcd8acb0111::PPCOperand470   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
471     assert(N == 1 && "Invalid number of operands!");
472     Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
473   }
474 
addRegG8RCNoX0Operands__anonadcd8acb0111::PPCOperand475   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
476     assert(N == 1 && "Invalid number of operands!");
477     Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
478   }
479 
addRegG8pRCOperands__anonadcd8acb0111::PPCOperand480   void addRegG8pRCOperands(MCInst &Inst, unsigned N) const {
481     assert(N == 1 && "Invalid number of operands!");
482     Inst.addOperand(MCOperand::createReg(XRegs[getG8pReg()]));
483   }
484 
addRegGxRCOperands__anonadcd8acb0111::PPCOperand485   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
486     if (isPPC64())
487       addRegG8RCOperands(Inst, N);
488     else
489       addRegGPRCOperands(Inst, N);
490   }
491 
addRegGxRCNoR0Operands__anonadcd8acb0111::PPCOperand492   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
493     if (isPPC64())
494       addRegG8RCNoX0Operands(Inst, N);
495     else
496       addRegGPRCNoR0Operands(Inst, N);
497   }
498 
addRegF4RCOperands__anonadcd8acb0111::PPCOperand499   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
500     assert(N == 1 && "Invalid number of operands!");
501     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
502   }
503 
addRegF8RCOperands__anonadcd8acb0111::PPCOperand504   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
505     assert(N == 1 && "Invalid number of operands!");
506     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
507   }
508 
addRegFpRCOperands__anonadcd8acb0111::PPCOperand509   void addRegFpRCOperands(MCInst &Inst, unsigned N) const {
510     assert(N == 1 && "Invalid number of operands!");
511     Inst.addOperand(MCOperand::createReg(FpRegs[getFpReg()]));
512   }
513 
addRegVFRCOperands__anonadcd8acb0111::PPCOperand514   void addRegVFRCOperands(MCInst &Inst, unsigned N) const {
515     assert(N == 1 && "Invalid number of operands!");
516     Inst.addOperand(MCOperand::createReg(VFRegs[getReg()]));
517   }
518 
addRegVRRCOperands__anonadcd8acb0111::PPCOperand519   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
520     assert(N == 1 && "Invalid number of operands!");
521     Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
522   }
523 
addRegVSRCOperands__anonadcd8acb0111::PPCOperand524   void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
525     assert(N == 1 && "Invalid number of operands!");
526     Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
527   }
528 
addRegVSFRCOperands__anonadcd8acb0111::PPCOperand529   void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
530     assert(N == 1 && "Invalid number of operands!");
531     Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
532   }
533 
addRegVSSRCOperands__anonadcd8acb0111::PPCOperand534   void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
535     assert(N == 1 && "Invalid number of operands!");
536     Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
537   }
538 
addRegSPE4RCOperands__anonadcd8acb0111::PPCOperand539   void addRegSPE4RCOperands(MCInst &Inst, unsigned N) const {
540     assert(N == 1 && "Invalid number of operands!");
541     Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
542   }
543 
addRegSPERCOperands__anonadcd8acb0111::PPCOperand544   void addRegSPERCOperands(MCInst &Inst, unsigned N) const {
545     assert(N == 1 && "Invalid number of operands!");
546     Inst.addOperand(MCOperand::createReg(SPERegs[getReg()]));
547   }
548 
addRegACCRCOperands__anonadcd8acb0111::PPCOperand549   void addRegACCRCOperands(MCInst &Inst, unsigned N) const {
550     assert(N == 1 && "Invalid number of operands!");
551     Inst.addOperand(MCOperand::createReg(ACCRegs[getACCReg()]));
552   }
553 
addRegDMRROWRCOperands__anonadcd8acb0111::PPCOperand554   void addRegDMRROWRCOperands(MCInst &Inst, unsigned N) const {
555     assert(N == 1 && "Invalid number of operands!");
556     Inst.addOperand(MCOperand::createReg(DMRROWRegs[getDMRROWReg()]));
557   }
558 
addRegDMRROWpRCOperands__anonadcd8acb0111::PPCOperand559   void addRegDMRROWpRCOperands(MCInst &Inst, unsigned N) const {
560     assert(N == 1 && "Invalid number of operands!");
561     Inst.addOperand(MCOperand::createReg(DMRROWpRegs[getDMRROWpReg()]));
562   }
563 
addRegDMRRCOperands__anonadcd8acb0111::PPCOperand564   void addRegDMRRCOperands(MCInst &Inst, unsigned N) const {
565     assert(N == 1 && "Invalid number of operands!");
566     Inst.addOperand(MCOperand::createReg(DMRRegs[getDMRReg()]));
567   }
568 
addRegDMRpRCOperands__anonadcd8acb0111::PPCOperand569   void addRegDMRpRCOperands(MCInst &Inst, unsigned N) const {
570     assert(N == 1 && "Invalid number of operands!");
571     Inst.addOperand(MCOperand::createReg(DMRpRegs[getDMRpReg()]));
572   }
573 
addRegWACCRCOperands__anonadcd8acb0111::PPCOperand574   void addRegWACCRCOperands(MCInst &Inst, unsigned N) const {
575     assert(N == 1 && "Invalid number of operands!");
576     Inst.addOperand(MCOperand::createReg(WACCRegs[getACCReg()]));
577   }
578 
addRegWACC_HIRCOperands__anonadcd8acb0111::PPCOperand579   void addRegWACC_HIRCOperands(MCInst &Inst, unsigned N) const {
580     assert(N == 1 && "Invalid number of operands!");
581     Inst.addOperand(MCOperand::createReg(WACC_HIRegs[getACCReg()]));
582   }
583 
addRegVSRpRCOperands__anonadcd8acb0111::PPCOperand584   void addRegVSRpRCOperands(MCInst &Inst, unsigned N) const {
585     assert(N == 1 && "Invalid number of operands!");
586     Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()]));
587   }
588 
addRegVSRpEvenRCOperands__anonadcd8acb0111::PPCOperand589   void addRegVSRpEvenRCOperands(MCInst &Inst, unsigned N) const {
590     assert(N == 1 && "Invalid number of operands!");
591     Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()]));
592   }
593 
addRegCRBITRCOperands__anonadcd8acb0111::PPCOperand594   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
595     assert(N == 1 && "Invalid number of operands!");
596     Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
597   }
598 
addRegCRRCOperands__anonadcd8acb0111::PPCOperand599   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
600     assert(N == 1 && "Invalid number of operands!");
601     Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
602   }
603 
addCRBitMaskOperands__anonadcd8acb0111::PPCOperand604   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
605     assert(N == 1 && "Invalid number of operands!");
606     Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
607   }
608 
addImmOperands__anonadcd8acb0111::PPCOperand609   void addImmOperands(MCInst &Inst, unsigned N) const {
610     assert(N == 1 && "Invalid number of operands!");
611     if (Kind == Immediate)
612       Inst.addOperand(MCOperand::createImm(getImm()));
613     else
614       Inst.addOperand(MCOperand::createExpr(getExpr()));
615   }
616 
addS16ImmOperands__anonadcd8acb0111::PPCOperand617   void addS16ImmOperands(MCInst &Inst, unsigned N) const {
618     assert(N == 1 && "Invalid number of operands!");
619     switch (Kind) {
620       case Immediate:
621         Inst.addOperand(MCOperand::createImm(getImm()));
622         break;
623       case ContextImmediate:
624         Inst.addOperand(MCOperand::createImm(getImmS16Context()));
625         break;
626       default:
627         Inst.addOperand(MCOperand::createExpr(getExpr()));
628         break;
629     }
630   }
631 
addU16ImmOperands__anonadcd8acb0111::PPCOperand632   void addU16ImmOperands(MCInst &Inst, unsigned N) const {
633     assert(N == 1 && "Invalid number of operands!");
634     switch (Kind) {
635       case Immediate:
636         Inst.addOperand(MCOperand::createImm(getImm()));
637         break;
638       case ContextImmediate:
639         Inst.addOperand(MCOperand::createImm(getImmU16Context()));
640         break;
641       default:
642         Inst.addOperand(MCOperand::createExpr(getExpr()));
643         break;
644     }
645   }
646 
addBranchTargetOperands__anonadcd8acb0111::PPCOperand647   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
648     assert(N == 1 && "Invalid number of operands!");
649     if (Kind == Immediate)
650       Inst.addOperand(MCOperand::createImm(getImm() / 4));
651     else
652       Inst.addOperand(MCOperand::createExpr(getExpr()));
653   }
654 
addTLSRegOperands__anonadcd8acb0111::PPCOperand655   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
656     assert(N == 1 && "Invalid number of operands!");
657     Inst.addOperand(MCOperand::createExpr(getTLSReg()));
658   }
659 
getToken__anonadcd8acb0111::PPCOperand660   StringRef getToken() const {
661     assert(Kind == Token && "Invalid access!");
662     return StringRef(Tok.Data, Tok.Length);
663   }
664 
665   void print(raw_ostream &OS) const override;
666 
CreateToken__anonadcd8acb0111::PPCOperand667   static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
668                                                  bool IsPPC64) {
669     auto Op = std::make_unique<PPCOperand>(Token);
670     Op->Tok.Data = Str.data();
671     Op->Tok.Length = Str.size();
672     Op->StartLoc = S;
673     Op->EndLoc = S;
674     Op->IsPPC64 = IsPPC64;
675     return Op;
676   }
677 
678   static std::unique_ptr<PPCOperand>
CreateTokenWithStringCopy__anonadcd8acb0111::PPCOperand679   CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
680     // Allocate extra memory for the string and copy it.
681     // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
682     // deleter which will destroy them by simply using "delete", not correctly
683     // calling operator delete on this extra memory after calling the dtor
684     // explicitly.
685     void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
686     std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
687     Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
688     Op->Tok.Length = Str.size();
689     std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
690     Op->StartLoc = S;
691     Op->EndLoc = S;
692     Op->IsPPC64 = IsPPC64;
693     return Op;
694   }
695 
CreateImm__anonadcd8acb0111::PPCOperand696   static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
697                                                bool IsPPC64) {
698     auto Op = std::make_unique<PPCOperand>(Immediate);
699     Op->Imm.Val = Val;
700     Op->StartLoc = S;
701     Op->EndLoc = E;
702     Op->IsPPC64 = IsPPC64;
703     return Op;
704   }
705 
CreateExpr__anonadcd8acb0111::PPCOperand706   static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
707                                                 SMLoc E, bool IsPPC64) {
708     auto Op = std::make_unique<PPCOperand>(Expression);
709     Op->Expr.Val = Val;
710     Op->Expr.CRVal = EvaluateCRExpr(Val);
711     Op->StartLoc = S;
712     Op->EndLoc = E;
713     Op->IsPPC64 = IsPPC64;
714     return Op;
715   }
716 
717   static std::unique_ptr<PPCOperand>
CreateTLSReg__anonadcd8acb0111::PPCOperand718   CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
719     auto Op = std::make_unique<PPCOperand>(TLSRegister);
720     Op->TLSReg.Sym = Sym;
721     Op->StartLoc = S;
722     Op->EndLoc = E;
723     Op->IsPPC64 = IsPPC64;
724     return Op;
725   }
726 
727   static std::unique_ptr<PPCOperand>
CreateContextImm__anonadcd8acb0111::PPCOperand728   CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
729     auto Op = std::make_unique<PPCOperand>(ContextImmediate);
730     Op->Imm.Val = Val;
731     Op->StartLoc = S;
732     Op->EndLoc = E;
733     Op->IsPPC64 = IsPPC64;
734     return Op;
735   }
736 
737   static std::unique_ptr<PPCOperand>
CreateFromMCExpr__anonadcd8acb0111::PPCOperand738   CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
739     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
740       return CreateImm(CE->getValue(), S, E, IsPPC64);
741 
742     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
743       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS ||
744           SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS_PCREL)
745         return CreateTLSReg(SRE, S, E, IsPPC64);
746 
747     if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
748       int64_t Res;
749       if (TE->evaluateAsConstant(Res))
750         return CreateContextImm(Res, S, E, IsPPC64);
751     }
752 
753     return CreateExpr(Val, S, E, IsPPC64);
754   }
755 
756 private:
757   template <unsigned Width>
isExtImm__anonadcd8acb0111::PPCOperand758   bool isExtImm(bool Signed, unsigned Multiple) const {
759     switch (Kind) {
760     default:
761       return false;
762     case Expression:
763       return true;
764     case Immediate:
765     case ContextImmediate:
766       if (Signed)
767         return isInt<Width>(getImmS16Context()) &&
768                (getImmS16Context() & (Multiple - 1)) == 0;
769       else
770         return isUInt<Width>(getImmU16Context()) &&
771                (getImmU16Context() & (Multiple - 1)) == 0;
772     }
773   }
774 };
775 
776 } // end anonymous namespace.
777 
print(raw_ostream & OS) const778 void PPCOperand::print(raw_ostream &OS) const {
779   switch (Kind) {
780   case Token:
781     OS << "'" << getToken() << "'";
782     break;
783   case Immediate:
784   case ContextImmediate:
785     OS << getImm();
786     break;
787   case Expression:
788     OS << *getExpr();
789     break;
790   case TLSRegister:
791     OS << *getTLSReg();
792     break;
793   }
794 }
795 
796 static void
addNegOperand(MCInst & Inst,MCOperand & Op,MCContext & Ctx)797 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
798   if (Op.isImm()) {
799     Inst.addOperand(MCOperand::createImm(-Op.getImm()));
800     return;
801   }
802   const MCExpr *Expr = Op.getExpr();
803   if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
804     if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
805       Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
806       return;
807     }
808   } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
809     if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
810       const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
811                                                  BinExpr->getLHS(), Ctx);
812       Inst.addOperand(MCOperand::createExpr(NE));
813       return;
814     }
815   }
816   Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx)));
817 }
818 
ProcessInstruction(MCInst & Inst,const OperandVector & Operands)819 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
820                                       const OperandVector &Operands) {
821   int Opcode = Inst.getOpcode();
822   switch (Opcode) {
823   case PPC::DCBTx:
824   case PPC::DCBTT:
825   case PPC::DCBTSTx:
826   case PPC::DCBTSTT: {
827     MCInst TmpInst;
828     TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
829                       PPC::DCBT : PPC::DCBTST);
830     TmpInst.addOperand(MCOperand::createImm(
831       (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
832     TmpInst.addOperand(Inst.getOperand(0));
833     TmpInst.addOperand(Inst.getOperand(1));
834     Inst = TmpInst;
835     break;
836   }
837   case PPC::DCBTCT:
838   case PPC::DCBTDS: {
839     MCInst TmpInst;
840     TmpInst.setOpcode(PPC::DCBT);
841     TmpInst.addOperand(Inst.getOperand(2));
842     TmpInst.addOperand(Inst.getOperand(0));
843     TmpInst.addOperand(Inst.getOperand(1));
844     Inst = TmpInst;
845     break;
846   }
847   case PPC::DCBTSTCT:
848   case PPC::DCBTSTDS: {
849     MCInst TmpInst;
850     TmpInst.setOpcode(PPC::DCBTST);
851     TmpInst.addOperand(Inst.getOperand(2));
852     TmpInst.addOperand(Inst.getOperand(0));
853     TmpInst.addOperand(Inst.getOperand(1));
854     Inst = TmpInst;
855     break;
856   }
857   case PPC::DCBFx:
858   case PPC::DCBFL:
859   case PPC::DCBFLP:
860   case PPC::DCBFPS:
861   case PPC::DCBSTPS: {
862     int L = 0;
863     if (Opcode == PPC::DCBFL)
864       L = 1;
865     else if (Opcode == PPC::DCBFLP)
866       L = 3;
867     else if (Opcode == PPC::DCBFPS)
868       L = 4;
869     else if (Opcode == PPC::DCBSTPS)
870       L = 6;
871 
872     MCInst TmpInst;
873     TmpInst.setOpcode(PPC::DCBF);
874     TmpInst.addOperand(MCOperand::createImm(L));
875     TmpInst.addOperand(Inst.getOperand(0));
876     TmpInst.addOperand(Inst.getOperand(1));
877     Inst = TmpInst;
878     break;
879   }
880   case PPC::LAx: {
881     MCInst TmpInst;
882     TmpInst.setOpcode(PPC::LA);
883     TmpInst.addOperand(Inst.getOperand(0));
884     TmpInst.addOperand(Inst.getOperand(2));
885     TmpInst.addOperand(Inst.getOperand(1));
886     Inst = TmpInst;
887     break;
888   }
889   case PPC::PLA8:
890   case PPC::PLA: {
891     MCInst TmpInst;
892     TmpInst.setOpcode(Opcode == PPC::PLA ? PPC::PADDI : PPC::PADDI8);
893     TmpInst.addOperand(Inst.getOperand(0));
894     TmpInst.addOperand(Inst.getOperand(1));
895     TmpInst.addOperand(Inst.getOperand(2));
896     Inst = TmpInst;
897     break;
898   }
899   case PPC::PLA8pc:
900   case PPC::PLApc: {
901     MCInst TmpInst;
902     TmpInst.setOpcode(Opcode == PPC::PLApc ? PPC::PADDIpc : PPC::PADDI8pc);
903     TmpInst.addOperand(Inst.getOperand(0));
904     TmpInst.addOperand(MCOperand::createImm(0));
905     TmpInst.addOperand(Inst.getOperand(1));
906     Inst = TmpInst;
907     break;
908   }
909   case PPC::SUBI: {
910     MCInst TmpInst;
911     TmpInst.setOpcode(PPC::ADDI);
912     TmpInst.addOperand(Inst.getOperand(0));
913     TmpInst.addOperand(Inst.getOperand(1));
914     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
915     Inst = TmpInst;
916     break;
917   }
918   case PPC::PSUBI: {
919     MCInst TmpInst;
920     TmpInst.setOpcode(PPC::PADDI);
921     TmpInst.addOperand(Inst.getOperand(0));
922     TmpInst.addOperand(Inst.getOperand(1));
923     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
924     Inst = TmpInst;
925     break;
926   }
927   case PPC::SUBIS: {
928     MCInst TmpInst;
929     TmpInst.setOpcode(PPC::ADDIS);
930     TmpInst.addOperand(Inst.getOperand(0));
931     TmpInst.addOperand(Inst.getOperand(1));
932     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
933     Inst = TmpInst;
934     break;
935   }
936   case PPC::SUBIC: {
937     MCInst TmpInst;
938     TmpInst.setOpcode(PPC::ADDIC);
939     TmpInst.addOperand(Inst.getOperand(0));
940     TmpInst.addOperand(Inst.getOperand(1));
941     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
942     Inst = TmpInst;
943     break;
944   }
945   case PPC::SUBIC_rec: {
946     MCInst TmpInst;
947     TmpInst.setOpcode(PPC::ADDIC_rec);
948     TmpInst.addOperand(Inst.getOperand(0));
949     TmpInst.addOperand(Inst.getOperand(1));
950     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
951     Inst = TmpInst;
952     break;
953   }
954   case PPC::EXTLWI:
955   case PPC::EXTLWI_rec: {
956     MCInst TmpInst;
957     int64_t N = Inst.getOperand(2).getImm();
958     int64_t B = Inst.getOperand(3).getImm();
959     TmpInst.setOpcode(Opcode == PPC::EXTLWI ? PPC::RLWINM : PPC::RLWINM_rec);
960     TmpInst.addOperand(Inst.getOperand(0));
961     TmpInst.addOperand(Inst.getOperand(1));
962     TmpInst.addOperand(MCOperand::createImm(B));
963     TmpInst.addOperand(MCOperand::createImm(0));
964     TmpInst.addOperand(MCOperand::createImm(N - 1));
965     Inst = TmpInst;
966     break;
967   }
968   case PPC::EXTRWI:
969   case PPC::EXTRWI_rec: {
970     MCInst TmpInst;
971     int64_t N = Inst.getOperand(2).getImm();
972     int64_t B = Inst.getOperand(3).getImm();
973     TmpInst.setOpcode(Opcode == PPC::EXTRWI ? PPC::RLWINM : PPC::RLWINM_rec);
974     TmpInst.addOperand(Inst.getOperand(0));
975     TmpInst.addOperand(Inst.getOperand(1));
976     TmpInst.addOperand(MCOperand::createImm(B + N));
977     TmpInst.addOperand(MCOperand::createImm(32 - N));
978     TmpInst.addOperand(MCOperand::createImm(31));
979     Inst = TmpInst;
980     break;
981   }
982   case PPC::INSLWI:
983   case PPC::INSLWI_rec: {
984     MCInst TmpInst;
985     int64_t N = Inst.getOperand(2).getImm();
986     int64_t B = Inst.getOperand(3).getImm();
987     TmpInst.setOpcode(Opcode == PPC::INSLWI ? PPC::RLWIMI : PPC::RLWIMI_rec);
988     TmpInst.addOperand(Inst.getOperand(0));
989     TmpInst.addOperand(Inst.getOperand(0));
990     TmpInst.addOperand(Inst.getOperand(1));
991     TmpInst.addOperand(MCOperand::createImm(32 - B));
992     TmpInst.addOperand(MCOperand::createImm(B));
993     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
994     Inst = TmpInst;
995     break;
996   }
997   case PPC::INSRWI:
998   case PPC::INSRWI_rec: {
999     MCInst TmpInst;
1000     int64_t N = Inst.getOperand(2).getImm();
1001     int64_t B = Inst.getOperand(3).getImm();
1002     TmpInst.setOpcode(Opcode == PPC::INSRWI ? PPC::RLWIMI : PPC::RLWIMI_rec);
1003     TmpInst.addOperand(Inst.getOperand(0));
1004     TmpInst.addOperand(Inst.getOperand(0));
1005     TmpInst.addOperand(Inst.getOperand(1));
1006     TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
1007     TmpInst.addOperand(MCOperand::createImm(B));
1008     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
1009     Inst = TmpInst;
1010     break;
1011   }
1012   case PPC::ROTRWI:
1013   case PPC::ROTRWI_rec: {
1014     MCInst TmpInst;
1015     int64_t N = Inst.getOperand(2).getImm();
1016     TmpInst.setOpcode(Opcode == PPC::ROTRWI ? PPC::RLWINM : PPC::RLWINM_rec);
1017     TmpInst.addOperand(Inst.getOperand(0));
1018     TmpInst.addOperand(Inst.getOperand(1));
1019     TmpInst.addOperand(MCOperand::createImm(32 - N));
1020     TmpInst.addOperand(MCOperand::createImm(0));
1021     TmpInst.addOperand(MCOperand::createImm(31));
1022     Inst = TmpInst;
1023     break;
1024   }
1025   case PPC::SLWI:
1026   case PPC::SLWI_rec: {
1027     MCInst TmpInst;
1028     int64_t N = Inst.getOperand(2).getImm();
1029     TmpInst.setOpcode(Opcode == PPC::SLWI ? PPC::RLWINM : PPC::RLWINM_rec);
1030     TmpInst.addOperand(Inst.getOperand(0));
1031     TmpInst.addOperand(Inst.getOperand(1));
1032     TmpInst.addOperand(MCOperand::createImm(N));
1033     TmpInst.addOperand(MCOperand::createImm(0));
1034     TmpInst.addOperand(MCOperand::createImm(31 - N));
1035     Inst = TmpInst;
1036     break;
1037   }
1038   case PPC::SRWI:
1039   case PPC::SRWI_rec: {
1040     MCInst TmpInst;
1041     int64_t N = Inst.getOperand(2).getImm();
1042     TmpInst.setOpcode(Opcode == PPC::SRWI ? PPC::RLWINM : PPC::RLWINM_rec);
1043     TmpInst.addOperand(Inst.getOperand(0));
1044     TmpInst.addOperand(Inst.getOperand(1));
1045     TmpInst.addOperand(MCOperand::createImm(32 - N));
1046     TmpInst.addOperand(MCOperand::createImm(N));
1047     TmpInst.addOperand(MCOperand::createImm(31));
1048     Inst = TmpInst;
1049     break;
1050   }
1051   case PPC::CLRRWI:
1052   case PPC::CLRRWI_rec: {
1053     MCInst TmpInst;
1054     int64_t N = Inst.getOperand(2).getImm();
1055     TmpInst.setOpcode(Opcode == PPC::CLRRWI ? PPC::RLWINM : PPC::RLWINM_rec);
1056     TmpInst.addOperand(Inst.getOperand(0));
1057     TmpInst.addOperand(Inst.getOperand(1));
1058     TmpInst.addOperand(MCOperand::createImm(0));
1059     TmpInst.addOperand(MCOperand::createImm(0));
1060     TmpInst.addOperand(MCOperand::createImm(31 - N));
1061     Inst = TmpInst;
1062     break;
1063   }
1064   case PPC::CLRLSLWI:
1065   case PPC::CLRLSLWI_rec: {
1066     MCInst TmpInst;
1067     int64_t B = Inst.getOperand(2).getImm();
1068     int64_t N = Inst.getOperand(3).getImm();
1069     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI ? PPC::RLWINM : PPC::RLWINM_rec);
1070     TmpInst.addOperand(Inst.getOperand(0));
1071     TmpInst.addOperand(Inst.getOperand(1));
1072     TmpInst.addOperand(MCOperand::createImm(N));
1073     TmpInst.addOperand(MCOperand::createImm(B - N));
1074     TmpInst.addOperand(MCOperand::createImm(31 - N));
1075     Inst = TmpInst;
1076     break;
1077   }
1078   case PPC::EXTLDI:
1079   case PPC::EXTLDI_rec: {
1080     MCInst TmpInst;
1081     int64_t N = Inst.getOperand(2).getImm();
1082     int64_t B = Inst.getOperand(3).getImm();
1083     TmpInst.setOpcode(Opcode == PPC::EXTLDI ? PPC::RLDICR : PPC::RLDICR_rec);
1084     TmpInst.addOperand(Inst.getOperand(0));
1085     TmpInst.addOperand(Inst.getOperand(1));
1086     TmpInst.addOperand(MCOperand::createImm(B));
1087     TmpInst.addOperand(MCOperand::createImm(N - 1));
1088     Inst = TmpInst;
1089     break;
1090   }
1091   case PPC::EXTRDI:
1092   case PPC::EXTRDI_rec: {
1093     MCInst TmpInst;
1094     int64_t N = Inst.getOperand(2).getImm();
1095     int64_t B = Inst.getOperand(3).getImm();
1096     TmpInst.setOpcode(Opcode == PPC::EXTRDI ? PPC::RLDICL : PPC::RLDICL_rec);
1097     TmpInst.addOperand(Inst.getOperand(0));
1098     TmpInst.addOperand(Inst.getOperand(1));
1099     TmpInst.addOperand(MCOperand::createImm(B + N));
1100     TmpInst.addOperand(MCOperand::createImm(64 - N));
1101     Inst = TmpInst;
1102     break;
1103   }
1104   case PPC::INSRDI:
1105   case PPC::INSRDI_rec: {
1106     MCInst TmpInst;
1107     int64_t N = Inst.getOperand(2).getImm();
1108     int64_t B = Inst.getOperand(3).getImm();
1109     TmpInst.setOpcode(Opcode == PPC::INSRDI ? PPC::RLDIMI : PPC::RLDIMI_rec);
1110     TmpInst.addOperand(Inst.getOperand(0));
1111     TmpInst.addOperand(Inst.getOperand(0));
1112     TmpInst.addOperand(Inst.getOperand(1));
1113     TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
1114     TmpInst.addOperand(MCOperand::createImm(B));
1115     Inst = TmpInst;
1116     break;
1117   }
1118   case PPC::ROTRDI:
1119   case PPC::ROTRDI_rec: {
1120     MCInst TmpInst;
1121     int64_t N = Inst.getOperand(2).getImm();
1122     TmpInst.setOpcode(Opcode == PPC::ROTRDI ? PPC::RLDICL : PPC::RLDICL_rec);
1123     TmpInst.addOperand(Inst.getOperand(0));
1124     TmpInst.addOperand(Inst.getOperand(1));
1125     TmpInst.addOperand(MCOperand::createImm(64 - N));
1126     TmpInst.addOperand(MCOperand::createImm(0));
1127     Inst = TmpInst;
1128     break;
1129   }
1130   case PPC::SLDI:
1131   case PPC::SLDI_rec: {
1132     MCInst TmpInst;
1133     int64_t N = Inst.getOperand(2).getImm();
1134     TmpInst.setOpcode(Opcode == PPC::SLDI ? PPC::RLDICR : PPC::RLDICR_rec);
1135     TmpInst.addOperand(Inst.getOperand(0));
1136     TmpInst.addOperand(Inst.getOperand(1));
1137     TmpInst.addOperand(MCOperand::createImm(N));
1138     TmpInst.addOperand(MCOperand::createImm(63 - N));
1139     Inst = TmpInst;
1140     break;
1141   }
1142   case PPC::SUBPCIS: {
1143     MCInst TmpInst;
1144     int64_t N = Inst.getOperand(1).getImm();
1145     TmpInst.setOpcode(PPC::ADDPCIS);
1146     TmpInst.addOperand(Inst.getOperand(0));
1147     TmpInst.addOperand(MCOperand::createImm(-N));
1148     Inst = TmpInst;
1149     break;
1150   }
1151   case PPC::SRDI:
1152   case PPC::SRDI_rec: {
1153     MCInst TmpInst;
1154     int64_t N = Inst.getOperand(2).getImm();
1155     TmpInst.setOpcode(Opcode == PPC::SRDI ? PPC::RLDICL : PPC::RLDICL_rec);
1156     TmpInst.addOperand(Inst.getOperand(0));
1157     TmpInst.addOperand(Inst.getOperand(1));
1158     TmpInst.addOperand(MCOperand::createImm(64 - N));
1159     TmpInst.addOperand(MCOperand::createImm(N));
1160     Inst = TmpInst;
1161     break;
1162   }
1163   case PPC::CLRRDI:
1164   case PPC::CLRRDI_rec: {
1165     MCInst TmpInst;
1166     int64_t N = Inst.getOperand(2).getImm();
1167     TmpInst.setOpcode(Opcode == PPC::CLRRDI ? PPC::RLDICR : PPC::RLDICR_rec);
1168     TmpInst.addOperand(Inst.getOperand(0));
1169     TmpInst.addOperand(Inst.getOperand(1));
1170     TmpInst.addOperand(MCOperand::createImm(0));
1171     TmpInst.addOperand(MCOperand::createImm(63 - N));
1172     Inst = TmpInst;
1173     break;
1174   }
1175   case PPC::CLRLSLDI:
1176   case PPC::CLRLSLDI_rec: {
1177     MCInst TmpInst;
1178     int64_t B = Inst.getOperand(2).getImm();
1179     int64_t N = Inst.getOperand(3).getImm();
1180     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI ? PPC::RLDIC : PPC::RLDIC_rec);
1181     TmpInst.addOperand(Inst.getOperand(0));
1182     TmpInst.addOperand(Inst.getOperand(1));
1183     TmpInst.addOperand(MCOperand::createImm(N));
1184     TmpInst.addOperand(MCOperand::createImm(B - N));
1185     Inst = TmpInst;
1186     break;
1187   }
1188   case PPC::RLWINMbm:
1189   case PPC::RLWINMbm_rec: {
1190     unsigned MB, ME;
1191     int64_t BM = Inst.getOperand(3).getImm();
1192     if (!isRunOfOnes(BM, MB, ME))
1193       break;
1194 
1195     MCInst TmpInst;
1196     TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINM_rec);
1197     TmpInst.addOperand(Inst.getOperand(0));
1198     TmpInst.addOperand(Inst.getOperand(1));
1199     TmpInst.addOperand(Inst.getOperand(2));
1200     TmpInst.addOperand(MCOperand::createImm(MB));
1201     TmpInst.addOperand(MCOperand::createImm(ME));
1202     Inst = TmpInst;
1203     break;
1204   }
1205   case PPC::RLWIMIbm:
1206   case PPC::RLWIMIbm_rec: {
1207     unsigned MB, ME;
1208     int64_t BM = Inst.getOperand(3).getImm();
1209     if (!isRunOfOnes(BM, MB, ME))
1210       break;
1211 
1212     MCInst TmpInst;
1213     TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMI_rec);
1214     TmpInst.addOperand(Inst.getOperand(0));
1215     TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1216     TmpInst.addOperand(Inst.getOperand(1));
1217     TmpInst.addOperand(Inst.getOperand(2));
1218     TmpInst.addOperand(MCOperand::createImm(MB));
1219     TmpInst.addOperand(MCOperand::createImm(ME));
1220     Inst = TmpInst;
1221     break;
1222   }
1223   case PPC::RLWNMbm:
1224   case PPC::RLWNMbm_rec: {
1225     unsigned MB, ME;
1226     int64_t BM = Inst.getOperand(3).getImm();
1227     if (!isRunOfOnes(BM, MB, ME))
1228       break;
1229 
1230     MCInst TmpInst;
1231     TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNM_rec);
1232     TmpInst.addOperand(Inst.getOperand(0));
1233     TmpInst.addOperand(Inst.getOperand(1));
1234     TmpInst.addOperand(Inst.getOperand(2));
1235     TmpInst.addOperand(MCOperand::createImm(MB));
1236     TmpInst.addOperand(MCOperand::createImm(ME));
1237     Inst = TmpInst;
1238     break;
1239   }
1240   case PPC::MFTB: {
1241     if (getSTI().hasFeature(PPC::FeatureMFTB)) {
1242       assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1243       Inst.setOpcode(PPC::MFSPR);
1244     }
1245     break;
1246   }
1247   }
1248 }
1249 
1250 static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,
1251                                          unsigned VariantID = 0);
1252 
MatchAndEmitInstruction(SMLoc IDLoc,unsigned & Opcode,OperandVector & Operands,MCStreamer & Out,uint64_t & ErrorInfo,bool MatchingInlineAsm)1253 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1254                                            OperandVector &Operands,
1255                                            MCStreamer &Out, uint64_t &ErrorInfo,
1256                                            bool MatchingInlineAsm) {
1257   MCInst Inst;
1258 
1259   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1260   case Match_Success:
1261     // Post-process instructions (typically extended mnemonics)
1262     ProcessInstruction(Inst, Operands);
1263     Inst.setLoc(IDLoc);
1264     Out.emitInstruction(Inst, getSTI());
1265     return false;
1266   case Match_MissingFeature:
1267     return Error(IDLoc, "instruction use requires an option to be enabled");
1268   case Match_MnemonicFail: {
1269     FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1270     std::string Suggestion = PPCMnemonicSpellCheck(
1271         ((PPCOperand &)*Operands[0]).getToken(), FBS);
1272     return Error(IDLoc, "invalid instruction" + Suggestion,
1273                  ((PPCOperand &)*Operands[0]).getLocRange());
1274   }
1275   case Match_InvalidOperand: {
1276     SMLoc ErrorLoc = IDLoc;
1277     if (ErrorInfo != ~0ULL) {
1278       if (ErrorInfo >= Operands.size())
1279         return Error(IDLoc, "too few operands for instruction");
1280 
1281       ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1282       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1283     }
1284 
1285     return Error(ErrorLoc, "invalid operand for instruction");
1286   }
1287   }
1288 
1289   llvm_unreachable("Implement any new match types added!");
1290 }
1291 
MatchRegisterName(MCRegister & RegNo,int64_t & IntVal)1292 bool PPCAsmParser::MatchRegisterName(MCRegister &RegNo, int64_t &IntVal) {
1293   if (getParser().getTok().is(AsmToken::Percent))
1294     getParser().Lex(); // Eat the '%'.
1295 
1296   if (!getParser().getTok().is(AsmToken::Identifier))
1297     return true;
1298 
1299   StringRef Name = getParser().getTok().getString();
1300   if (Name.equals_insensitive("lr")) {
1301     RegNo = isPPC64() ? PPC::LR8 : PPC::LR;
1302     IntVal = 8;
1303   } else if (Name.equals_insensitive("ctr")) {
1304     RegNo = isPPC64() ? PPC::CTR8 : PPC::CTR;
1305     IntVal = 9;
1306   } else if (Name.equals_insensitive("vrsave")) {
1307     RegNo = PPC::VRSAVE;
1308     IntVal = 256;
1309   } else if (Name.starts_with_insensitive("r") &&
1310              !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1311     RegNo = isPPC64() ? XRegs[IntVal] : RRegs[IntVal];
1312   } else if (Name.starts_with_insensitive("f") &&
1313              !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1314     RegNo = FRegs[IntVal];
1315   } else if (Name.starts_with_insensitive("vs") &&
1316              !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1317     RegNo = VSRegs[IntVal];
1318   } else if (Name.starts_with_insensitive("v") &&
1319              !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1320     RegNo = VRegs[IntVal];
1321   } else if (Name.starts_with_insensitive("cr") &&
1322              !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1323     RegNo = CRRegs[IntVal];
1324   } else if (Name.starts_with_insensitive("acc") &&
1325              !Name.substr(3).getAsInteger(10, IntVal) && IntVal < 8) {
1326     RegNo = ACCRegs[IntVal];
1327   } else if (Name.starts_with_insensitive("wacc_hi") &&
1328              !Name.substr(7).getAsInteger(10, IntVal) && IntVal < 8) {
1329     RegNo = ACCRegs[IntVal];
1330   } else if (Name.starts_with_insensitive("wacc") &&
1331              !Name.substr(4).getAsInteger(10, IntVal) && IntVal < 8) {
1332     RegNo = WACCRegs[IntVal];
1333   } else if (Name.starts_with_insensitive("dmrrowp") &&
1334              !Name.substr(7).getAsInteger(10, IntVal) && IntVal < 32) {
1335     RegNo = DMRROWpRegs[IntVal];
1336   } else if (Name.starts_with_insensitive("dmrrow") &&
1337              !Name.substr(6).getAsInteger(10, IntVal) && IntVal < 64) {
1338     RegNo = DMRROWRegs[IntVal];
1339   } else if (Name.starts_with_insensitive("dmrp") &&
1340              !Name.substr(4).getAsInteger(10, IntVal) && IntVal < 4) {
1341     RegNo = DMRROWpRegs[IntVal];
1342   } else if (Name.starts_with_insensitive("dmr") &&
1343              !Name.substr(3).getAsInteger(10, IntVal) && IntVal < 8) {
1344     RegNo = DMRRegs[IntVal];
1345   } else
1346     return true;
1347   getParser().Lex();
1348   return false;
1349 }
1350 
parseRegister(MCRegister & Reg,SMLoc & StartLoc,SMLoc & EndLoc)1351 bool PPCAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
1352                                  SMLoc &EndLoc) {
1353   if (!tryParseRegister(Reg, StartLoc, EndLoc).isSuccess())
1354     return TokError("invalid register name");
1355   return false;
1356 }
1357 
tryParseRegister(MCRegister & Reg,SMLoc & StartLoc,SMLoc & EndLoc)1358 ParseStatus PPCAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
1359                                            SMLoc &EndLoc) {
1360   const AsmToken &Tok = getParser().getTok();
1361   StartLoc = Tok.getLoc();
1362   EndLoc = Tok.getEndLoc();
1363   Reg = PPC::NoRegister;
1364   int64_t IntVal;
1365   if (MatchRegisterName(Reg, IntVal))
1366     return ParseStatus::NoMatch;
1367   return ParseStatus::Success;
1368 }
1369 
1370 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1371 /// the expression and check for VK_PPC_LO/HI/HA
1372 /// symbol variants.  If all symbols with modifier use the same
1373 /// variant, return the corresponding PPCMCExpr::VariantKind,
1374 /// and a modified expression using the default symbol variant.
1375 /// Otherwise, return NULL.
1376 const MCExpr *PPCAsmParser::
ExtractModifierFromExpr(const MCExpr * E,PPCMCExpr::VariantKind & Variant)1377 ExtractModifierFromExpr(const MCExpr *E,
1378                         PPCMCExpr::VariantKind &Variant) {
1379   MCContext &Context = getParser().getContext();
1380   Variant = PPCMCExpr::VK_PPC_None;
1381 
1382   switch (E->getKind()) {
1383   case MCExpr::Target:
1384   case MCExpr::Constant:
1385     return nullptr;
1386 
1387   case MCExpr::SymbolRef: {
1388     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1389 
1390     switch (SRE->getKind()) {
1391     case MCSymbolRefExpr::VK_PPC_LO:
1392       Variant = PPCMCExpr::VK_PPC_LO;
1393       break;
1394     case MCSymbolRefExpr::VK_PPC_HI:
1395       Variant = PPCMCExpr::VK_PPC_HI;
1396       break;
1397     case MCSymbolRefExpr::VK_PPC_HA:
1398       Variant = PPCMCExpr::VK_PPC_HA;
1399       break;
1400     case MCSymbolRefExpr::VK_PPC_HIGH:
1401       Variant = PPCMCExpr::VK_PPC_HIGH;
1402       break;
1403     case MCSymbolRefExpr::VK_PPC_HIGHA:
1404       Variant = PPCMCExpr::VK_PPC_HIGHA;
1405       break;
1406     case MCSymbolRefExpr::VK_PPC_HIGHER:
1407       Variant = PPCMCExpr::VK_PPC_HIGHER;
1408       break;
1409     case MCSymbolRefExpr::VK_PPC_HIGHERA:
1410       Variant = PPCMCExpr::VK_PPC_HIGHERA;
1411       break;
1412     case MCSymbolRefExpr::VK_PPC_HIGHEST:
1413       Variant = PPCMCExpr::VK_PPC_HIGHEST;
1414       break;
1415     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1416       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1417       break;
1418     default:
1419       return nullptr;
1420     }
1421 
1422     return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1423   }
1424 
1425   case MCExpr::Unary: {
1426     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1427     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1428     if (!Sub)
1429       return nullptr;
1430     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1431   }
1432 
1433   case MCExpr::Binary: {
1434     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1435     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1436     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1437     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1438 
1439     if (!LHS && !RHS)
1440       return nullptr;
1441 
1442     if (!LHS) LHS = BE->getLHS();
1443     if (!RHS) RHS = BE->getRHS();
1444 
1445     if (LHSVariant == PPCMCExpr::VK_PPC_None)
1446       Variant = RHSVariant;
1447     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1448       Variant = LHSVariant;
1449     else if (LHSVariant == RHSVariant)
1450       Variant = LHSVariant;
1451     else
1452       return nullptr;
1453 
1454     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1455   }
1456   }
1457 
1458   llvm_unreachable("Invalid expression kind!");
1459 }
1460 
1461 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1462 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1463 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1464 /// FIXME: This is a hack.
1465 const MCExpr *PPCAsmParser::
FixupVariantKind(const MCExpr * E)1466 FixupVariantKind(const MCExpr *E) {
1467   MCContext &Context = getParser().getContext();
1468 
1469   switch (E->getKind()) {
1470   case MCExpr::Target:
1471   case MCExpr::Constant:
1472     return E;
1473 
1474   case MCExpr::SymbolRef: {
1475     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1476     MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1477 
1478     switch (SRE->getKind()) {
1479     case MCSymbolRefExpr::VK_TLSGD:
1480       Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1481       break;
1482     case MCSymbolRefExpr::VK_TLSLD:
1483       Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1484       break;
1485     default:
1486       return E;
1487     }
1488     return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1489   }
1490 
1491   case MCExpr::Unary: {
1492     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1493     const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1494     if (Sub == UE->getSubExpr())
1495       return E;
1496     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1497   }
1498 
1499   case MCExpr::Binary: {
1500     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1501     const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1502     const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1503     if (LHS == BE->getLHS() && RHS == BE->getRHS())
1504       return E;
1505     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1506   }
1507   }
1508 
1509   llvm_unreachable("Invalid expression kind!");
1510 }
1511 
1512 /// ParseExpression.  This differs from the default "parseExpression" in that
1513 /// it handles modifiers.
1514 bool PPCAsmParser::
ParseExpression(const MCExpr * & EVal)1515 ParseExpression(const MCExpr *&EVal) {
1516   // (ELF Platforms)
1517   // Handle \code @l/@ha \endcode
1518   if (getParser().parseExpression(EVal))
1519     return true;
1520 
1521   EVal = FixupVariantKind(EVal);
1522 
1523   PPCMCExpr::VariantKind Variant;
1524   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1525   if (E)
1526     EVal = PPCMCExpr::create(Variant, E, getParser().getContext());
1527 
1528   return false;
1529 }
1530 
1531 /// ParseOperand
1532 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1533 /// rNN for MachO.
ParseOperand(OperandVector & Operands)1534 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1535   MCAsmParser &Parser = getParser();
1536   SMLoc S = Parser.getTok().getLoc();
1537   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1538   const MCExpr *EVal;
1539 
1540   // Attempt to parse the next token as an immediate
1541   switch (getLexer().getKind()) {
1542   // Special handling for register names.  These are interpreted
1543   // as immediates corresponding to the register number.
1544   case AsmToken::Percent: {
1545     MCRegister RegNo;
1546     int64_t IntVal;
1547     if (MatchRegisterName(RegNo, IntVal))
1548       return Error(S, "invalid register name");
1549 
1550     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1551     return false;
1552   }
1553   case AsmToken::Identifier:
1554   case AsmToken::LParen:
1555   case AsmToken::Plus:
1556   case AsmToken::Minus:
1557   case AsmToken::Integer:
1558   case AsmToken::Dot:
1559   case AsmToken::Dollar:
1560   case AsmToken::Exclaim:
1561   case AsmToken::Tilde:
1562     if (!ParseExpression(EVal))
1563       break;
1564     // Fall-through
1565     [[fallthrough]];
1566   default:
1567     return Error(S, "unknown operand");
1568   }
1569 
1570   // Push the parsed operand into the list of operands
1571   Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1572 
1573   // Check whether this is a TLS call expression
1574   const char TlsGetAddr[] = "__tls_get_addr";
1575   bool TlsCall = false;
1576   const MCExpr *TlsCallAddend = nullptr;
1577   if (auto *Ref = dyn_cast<MCSymbolRefExpr>(EVal)) {
1578     TlsCall = Ref->getSymbol().getName() == TlsGetAddr;
1579   } else if (auto *Bin = dyn_cast<MCBinaryExpr>(EVal);
1580              Bin && Bin->getOpcode() == MCBinaryExpr::Add) {
1581     if (auto *Ref = dyn_cast<MCSymbolRefExpr>(Bin->getLHS())) {
1582       TlsCall = Ref->getSymbol().getName() == TlsGetAddr;
1583       TlsCallAddend = Bin->getRHS();
1584     }
1585   }
1586 
1587   if (TlsCall && parseOptionalToken(AsmToken::LParen)) {
1588     const MCExpr *TLSSym;
1589     const SMLoc S2 = Parser.getTok().getLoc();
1590     if (ParseExpression(TLSSym))
1591       return Error(S2, "invalid TLS call expression");
1592     E = Parser.getTok().getLoc();
1593     if (parseToken(AsmToken::RParen, "expected ')'"))
1594       return true;
1595     // PPC32 allows bl __tls_get_addr[+a](x@tlsgd)@plt+b. Parse "@plt[+b]".
1596     if (!isPPC64() && parseOptionalToken(AsmToken::At)) {
1597       AsmToken Tok = getTok();
1598       if (!(parseOptionalToken(AsmToken::Identifier) &&
1599             Tok.getString().compare_insensitive("plt") == 0))
1600         return Error(Tok.getLoc(), "expected 'plt'");
1601       EVal = MCSymbolRefExpr::create(TlsGetAddr, MCSymbolRefExpr::VK_PLT,
1602                                      getContext());
1603       if (parseOptionalToken(AsmToken::Plus)) {
1604         const MCExpr *Addend = nullptr;
1605         SMLoc EndLoc;
1606         if (parsePrimaryExpr(Addend, EndLoc))
1607           return true;
1608         if (TlsCallAddend) // __tls_get_addr+a(x@tlsgd)@plt+b
1609           TlsCallAddend =
1610               MCBinaryExpr::createAdd(TlsCallAddend, Addend, getContext());
1611         else // __tls_get_addr(x@tlsgd)@plt+b
1612           TlsCallAddend = Addend;
1613       }
1614       if (TlsCallAddend)
1615         EVal = MCBinaryExpr::createAdd(EVal, TlsCallAddend, getContext());
1616       // Add a __tls_get_addr operand with addend a, b, or a+b.
1617       Operands.back() = PPCOperand::CreateFromMCExpr(
1618           EVal, S, Parser.getTok().getLoc(), false);
1619     }
1620 
1621     Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1622   }
1623 
1624   // Otherwise, check for D-form memory operands
1625   if (!TlsCall && parseOptionalToken(AsmToken::LParen)) {
1626     S = Parser.getTok().getLoc();
1627 
1628     int64_t IntVal;
1629     switch (getLexer().getKind()) {
1630     case AsmToken::Percent: {
1631       MCRegister RegNo;
1632       if (MatchRegisterName(RegNo, IntVal))
1633         return Error(S, "invalid register name");
1634       break;
1635     }
1636     case AsmToken::Integer:
1637       if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 ||
1638           IntVal > 31)
1639         return Error(S, "invalid register number");
1640       break;
1641     case AsmToken::Identifier:
1642     default:
1643       return Error(S, "invalid memory operand");
1644     }
1645 
1646     E = Parser.getTok().getLoc();
1647     if (parseToken(AsmToken::RParen, "missing ')'"))
1648       return true;
1649     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1650   }
1651 
1652   return false;
1653 }
1654 
1655 /// Parse an instruction mnemonic followed by its operands.
ParseInstruction(ParseInstructionInfo & Info,StringRef Name,SMLoc NameLoc,OperandVector & Operands)1656 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1657                                     SMLoc NameLoc, OperandVector &Operands) {
1658   // The first operand is the token for the instruction name.
1659   // If the next character is a '+' or '-', we need to add it to the
1660   // instruction name, to match what TableGen is doing.
1661   std::string NewOpcode;
1662   if (parseOptionalToken(AsmToken::Plus)) {
1663     NewOpcode = std::string(Name);
1664     NewOpcode += '+';
1665     Name = NewOpcode;
1666   }
1667   if (parseOptionalToken(AsmToken::Minus)) {
1668     NewOpcode = std::string(Name);
1669     NewOpcode += '-';
1670     Name = NewOpcode;
1671   }
1672   // If the instruction ends in a '.', we need to create a separate
1673   // token for it, to match what TableGen is doing.
1674   size_t Dot = Name.find('.');
1675   StringRef Mnemonic = Name.slice(0, Dot);
1676   if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1677     Operands.push_back(
1678         PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1679   else
1680     Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1681   if (Dot != StringRef::npos) {
1682     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1683     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1684     if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1685       Operands.push_back(
1686           PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1687     else
1688       Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1689   }
1690 
1691   // If there are no more operands then finish
1692   if (parseOptionalToken(AsmToken::EndOfStatement))
1693     return false;
1694 
1695   // Parse the first operand
1696   if (ParseOperand(Operands))
1697     return true;
1698 
1699   while (!parseOptionalToken(AsmToken::EndOfStatement)) {
1700     if (parseToken(AsmToken::Comma) || ParseOperand(Operands))
1701       return true;
1702   }
1703 
1704   // We'll now deal with an unfortunate special case: the syntax for the dcbt
1705   // and dcbtst instructions differs for server vs. embedded cores.
1706   //  The syntax for dcbt is:
1707   //    dcbt ra, rb, th [server]
1708   //    dcbt th, ra, rb [embedded]
1709   //  where th can be omitted when it is 0. dcbtst is the same. We take the
1710   //  server form to be the default, so swap the operands if we're parsing for
1711   //  an embedded core (they'll be swapped again upon printing).
1712   if (getSTI().hasFeature(PPC::FeatureBookE) &&
1713       Operands.size() == 4 &&
1714       (Name == "dcbt" || Name == "dcbtst")) {
1715     std::swap(Operands[1], Operands[3]);
1716     std::swap(Operands[2], Operands[1]);
1717   }
1718 
1719   // Handle base mnemonic for atomic loads where the EH bit is zero.
1720   if (Name == "lqarx" || Name == "ldarx" || Name == "lwarx" ||
1721       Name == "lharx" || Name == "lbarx") {
1722     if (Operands.size() != 5)
1723       return false;
1724     PPCOperand &EHOp = (PPCOperand &)*Operands[4];
1725     if (EHOp.isU1Imm() && EHOp.getImm() == 0)
1726       Operands.pop_back();
1727   }
1728 
1729   return false;
1730 }
1731 
1732 /// ParseDirective parses the PPC specific directives
ParseDirective(AsmToken DirectiveID)1733 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1734   StringRef IDVal = DirectiveID.getIdentifier();
1735   if (IDVal == ".word")
1736     ParseDirectiveWord(2, DirectiveID);
1737   else if (IDVal == ".llong")
1738     ParseDirectiveWord(8, DirectiveID);
1739   else if (IDVal == ".tc")
1740     ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID);
1741   else if (IDVal == ".machine")
1742     ParseDirectiveMachine(DirectiveID.getLoc());
1743   else if (IDVal == ".abiversion")
1744     ParseDirectiveAbiVersion(DirectiveID.getLoc());
1745   else if (IDVal == ".localentry")
1746     ParseDirectiveLocalEntry(DirectiveID.getLoc());
1747   else if (IDVal.starts_with(".gnu_attribute"))
1748     ParseGNUAttribute(DirectiveID.getLoc());
1749   else
1750     return true;
1751   return false;
1752 }
1753 
1754 /// ParseDirectiveWord
1755 ///  ::= .word [ expression (, expression)* ]
ParseDirectiveWord(unsigned Size,AsmToken ID)1756 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) {
1757   auto parseOp = [&]() -> bool {
1758     const MCExpr *Value;
1759     SMLoc ExprLoc = getParser().getTok().getLoc();
1760     if (getParser().parseExpression(Value))
1761       return true;
1762     if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1763       assert(Size <= 8 && "Invalid size");
1764       uint64_t IntValue = MCE->getValue();
1765       if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
1766         return Error(ExprLoc, "literal value out of range for '" +
1767                                   ID.getIdentifier() + "' directive");
1768       getStreamer().emitIntValue(IntValue, Size);
1769     } else
1770       getStreamer().emitValue(Value, Size, ExprLoc);
1771     return false;
1772   };
1773 
1774   if (parseMany(parseOp))
1775     return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive");
1776   return false;
1777 }
1778 
1779 /// ParseDirectiveTC
1780 ///  ::= .tc [ symbol (, expression)* ]
ParseDirectiveTC(unsigned Size,AsmToken ID)1781 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) {
1782   MCAsmParser &Parser = getParser();
1783   // Skip TC symbol, which is only used with XCOFF.
1784   while (getLexer().isNot(AsmToken::EndOfStatement)
1785          && getLexer().isNot(AsmToken::Comma))
1786     Parser.Lex();
1787   if (parseToken(AsmToken::Comma))
1788     return addErrorSuffix(" in '.tc' directive");
1789 
1790   // Align to word size.
1791   getParser().getStreamer().emitValueToAlignment(Align(Size));
1792 
1793   // Emit expressions.
1794   return ParseDirectiveWord(Size, ID);
1795 }
1796 
1797 /// ParseDirectiveMachine (ELF platforms)
1798 ///  ::= .machine [ cpu | "push" | "pop" ]
ParseDirectiveMachine(SMLoc L)1799 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1800   MCAsmParser &Parser = getParser();
1801   if (Parser.getTok().isNot(AsmToken::Identifier) &&
1802       Parser.getTok().isNot(AsmToken::String))
1803     return Error(L, "unexpected token in '.machine' directive");
1804 
1805   StringRef CPU = Parser.getTok().getIdentifier();
1806 
1807   // FIXME: Right now, the parser always allows any available
1808   // instruction, so the .machine directive is not useful.
1809   // In the wild, any/push/pop/ppc64/altivec/power[4-9] are seen.
1810 
1811   Parser.Lex();
1812 
1813   if (parseToken(AsmToken::EndOfStatement))
1814     return addErrorSuffix(" in '.machine' directive");
1815 
1816   PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>(
1817       getParser().getStreamer().getTargetStreamer());
1818   if (TStreamer != nullptr)
1819     TStreamer->emitMachine(CPU);
1820 
1821   return false;
1822 }
1823 
1824 /// ParseDirectiveAbiVersion
1825 ///  ::= .abiversion constant-expression
ParseDirectiveAbiVersion(SMLoc L)1826 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1827   int64_t AbiVersion;
1828   if (check(getParser().parseAbsoluteExpression(AbiVersion), L,
1829             "expected constant expression") ||
1830       parseToken(AsmToken::EndOfStatement))
1831     return addErrorSuffix(" in '.abiversion' directive");
1832 
1833   PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>(
1834       getParser().getStreamer().getTargetStreamer());
1835   if (TStreamer != nullptr)
1836     TStreamer->emitAbiVersion(AbiVersion);
1837 
1838   return false;
1839 }
1840 
1841 /// ParseDirectiveLocalEntry
1842 ///  ::= .localentry symbol, expression
ParseDirectiveLocalEntry(SMLoc L)1843 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1844   StringRef Name;
1845   if (getParser().parseIdentifier(Name))
1846     return Error(L, "expected identifier in '.localentry' directive");
1847 
1848   MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1849   const MCExpr *Expr;
1850 
1851   if (parseToken(AsmToken::Comma) ||
1852       check(getParser().parseExpression(Expr), L, "expected expression") ||
1853       parseToken(AsmToken::EndOfStatement))
1854     return addErrorSuffix(" in '.localentry' directive");
1855 
1856   PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>(
1857       getParser().getStreamer().getTargetStreamer());
1858   if (TStreamer != nullptr)
1859     TStreamer->emitLocalEntry(Sym, Expr);
1860 
1861   return false;
1862 }
1863 
ParseGNUAttribute(SMLoc L)1864 bool PPCAsmParser::ParseGNUAttribute(SMLoc L) {
1865   int64_t Tag;
1866   int64_t IntegerValue;
1867   if (!getParser().parseGNUAttribute(L, Tag, IntegerValue))
1868     return false;
1869 
1870   getParser().getStreamer().emitGNUAttribute(Tag, IntegerValue);
1871 
1872   return true;
1873 }
1874 
1875 /// Force static initialization.
LLVMInitializePowerPCAsmParser()1876 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCAsmParser() {
1877   RegisterMCAsmParser<PPCAsmParser> A(getThePPC32Target());
1878   RegisterMCAsmParser<PPCAsmParser> B(getThePPC32LETarget());
1879   RegisterMCAsmParser<PPCAsmParser> C(getThePPC64Target());
1880   RegisterMCAsmParser<PPCAsmParser> D(getThePPC64LETarget());
1881 }
1882 
1883 #define GET_REGISTER_MATCHER
1884 #define GET_MATCHER_IMPLEMENTATION
1885 #define GET_MNEMONIC_SPELL_CHECKER
1886 #include "PPCGenAsmMatcher.inc"
1887 
1888 // Define this matcher function after the auto-generated include so we
1889 // have the match class enum definitions.
validateTargetOperandClass(MCParsedAsmOperand & AsmOp,unsigned Kind)1890 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1891                                                   unsigned Kind) {
1892   // If the kind is a token for a literal immediate, check if our asm
1893   // operand matches. This is for InstAliases which have a fixed-value
1894   // immediate in the syntax.
1895   int64_t ImmVal;
1896   switch (Kind) {
1897     case MCK_0: ImmVal = 0; break;
1898     case MCK_1: ImmVal = 1; break;
1899     case MCK_2: ImmVal = 2; break;
1900     case MCK_3: ImmVal = 3; break;
1901     case MCK_4: ImmVal = 4; break;
1902     case MCK_5: ImmVal = 5; break;
1903     case MCK_6: ImmVal = 6; break;
1904     case MCK_7: ImmVal = 7; break;
1905     default: return Match_InvalidOperand;
1906   }
1907 
1908   PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1909   if (Op.isU3Imm() && Op.getImm() == ImmVal)
1910     return Match_Success;
1911 
1912   return Match_InvalidOperand;
1913 }
1914 
1915 const MCExpr *
applyModifierToExpr(const MCExpr * E,MCSymbolRefExpr::VariantKind Variant,MCContext & Ctx)1916 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1917                                   MCSymbolRefExpr::VariantKind Variant,
1918                                   MCContext &Ctx) {
1919   switch (Variant) {
1920   case MCSymbolRefExpr::VK_PPC_LO:
1921     return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, Ctx);
1922   case MCSymbolRefExpr::VK_PPC_HI:
1923     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, Ctx);
1924   case MCSymbolRefExpr::VK_PPC_HA:
1925     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, Ctx);
1926   case MCSymbolRefExpr::VK_PPC_HIGH:
1927     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGH, E, Ctx);
1928   case MCSymbolRefExpr::VK_PPC_HIGHA:
1929     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHA, E, Ctx);
1930   case MCSymbolRefExpr::VK_PPC_HIGHER:
1931     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, Ctx);
1932   case MCSymbolRefExpr::VK_PPC_HIGHERA:
1933     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, Ctx);
1934   case MCSymbolRefExpr::VK_PPC_HIGHEST:
1935     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, Ctx);
1936   case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1937     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, Ctx);
1938   default:
1939     return nullptr;
1940   }
1941 }
1942