1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an PPC MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/PPCInstPrinter.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCInstrInfo.h"
17 #include "llvm/CodeGen/TargetOpcodes.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/raw_ostream.h"
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "asm-printer"
29 
30 // FIXME: Once the integrated assembler supports full register names, tie this
31 // to the verbose-asm setting.
32 static cl::opt<bool>
33 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
34              cl::desc("Use full register names when printing assembly"));
35 
36 // Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
37 static cl::opt<bool>
38 ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
39              cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
40 
41 // Prints full register names with percent symbol.
42 static cl::opt<bool>
43 FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,
44                         cl::init(false),
45                         cl::desc("Prints full register names with percent"));
46 
47 #define PRINT_ALIAS_INSTR
48 #include "PPCGenAsmWriter.inc"
49 
50 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
51   const char *RegName = getRegisterName(RegNo);
52   OS << RegName;
53 }
54 
55 void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
56                                StringRef Annot, const MCSubtargetInfo &STI,
57                                raw_ostream &O) {
58   // Customize printing of the addis instruction on AIX. When an operand is a
59   // symbol reference, the instruction syntax is changed to look like a load
60   // operation, i.e:
61   //     Transform:  addis $rD, $rA, $src --> addis $rD, $src($rA).
62   if (TT.isOSAIX() &&
63       (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&
64       MI->getOperand(2).isExpr()) {
65     assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) &&
66            "The first and the second operand of an addis instruction"
67            " should be registers.");
68 
69     assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) &&
70            "The third operand of an addis instruction should be a symbol "
71            "reference expression if it is an expression at all.");
72 
73     O << "\taddis ";
74     printOperand(MI, 0, STI, O);
75     O << ", ";
76     printOperand(MI, 2, STI, O);
77     O << "(";
78     printOperand(MI, 1, STI, O);
79     O << ")";
80     return;
81   }
82 
83   // Check if the last operand is an expression with the variant kind
84   // VK_PPC_PCREL_OPT. If this is the case then this is a linker optimization
85   // relocation and the .reloc directive needs to be added.
86   unsigned LastOp = MI->getNumOperands() - 1;
87   if (MI->getNumOperands() > 1) {
88     const MCOperand &Operand = MI->getOperand(LastOp);
89     if (Operand.isExpr()) {
90       const MCExpr *Expr = Operand.getExpr();
91       const MCSymbolRefExpr *SymExpr =
92           static_cast<const MCSymbolRefExpr *>(Expr);
93 
94       if (SymExpr && SymExpr->getKind() == MCSymbolRefExpr::VK_PPC_PCREL_OPT) {
95         const MCSymbol &Symbol = SymExpr->getSymbol();
96         if (MI->getOpcode() == PPC::PLDpc) {
97           printInstruction(MI, Address, STI, O);
98           O << "\n";
99           Symbol.print(O, &MAI);
100           O << ":";
101           return;
102         } else {
103           O << "\t.reloc ";
104           Symbol.print(O, &MAI);
105           O << "-8,R_PPC64_PCREL_OPT,.-(";
106           Symbol.print(O, &MAI);
107           O << "-8)\n";
108         }
109       }
110     }
111   }
112 
113   // Check for slwi/srwi mnemonics.
114   if (MI->getOpcode() == PPC::RLWINM) {
115     unsigned char SH = MI->getOperand(2).getImm();
116     unsigned char MB = MI->getOperand(3).getImm();
117     unsigned char ME = MI->getOperand(4).getImm();
118     bool useSubstituteMnemonic = false;
119     if (SH <= 31 && MB == 0 && ME == (31-SH)) {
120       O << "\tslwi "; useSubstituteMnemonic = true;
121     }
122     if (SH <= 31 && MB == (32-SH) && ME == 31) {
123       O << "\tsrwi "; useSubstituteMnemonic = true;
124       SH = 32-SH;
125     }
126     if (useSubstituteMnemonic) {
127       printOperand(MI, 0, STI, O);
128       O << ", ";
129       printOperand(MI, 1, STI, O);
130       O << ", " << (unsigned int)SH;
131 
132       printAnnotation(O, Annot);
133       return;
134     }
135   }
136 
137   if (MI->getOpcode() == PPC::RLDICR ||
138       MI->getOpcode() == PPC::RLDICR_32) {
139     unsigned char SH = MI->getOperand(2).getImm();
140     unsigned char ME = MI->getOperand(3).getImm();
141     // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
142     if (63-SH == ME) {
143       O << "\tsldi ";
144       printOperand(MI, 0, STI, O);
145       O << ", ";
146       printOperand(MI, 1, STI, O);
147       O << ", " << (unsigned int)SH;
148       printAnnotation(O, Annot);
149       return;
150     }
151   }
152 
153   // dcbt[st] is printed manually here because:
154   //  1. The assembly syntax is different between embedded and server targets
155   //  2. We must print the short mnemonics for TH == 0 because the
156   //     embedded/server syntax default will not be stable across assemblers
157   //  The syntax for dcbt is:
158   //    dcbt ra, rb, th [server]
159   //    dcbt th, ra, rb [embedded]
160   //  where th can be omitted when it is 0. dcbtst is the same.
161   // On AIX, only emit the extended mnemonics for dcbt and dcbtst if
162   // the "modern assembler" is available.
163   if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
164       (!TT.isOSAIX() || STI.getFeatureBits()[PPC::FeatureModernAIXAs])) {
165     unsigned char TH = MI->getOperand(0).getImm();
166     O << "\tdcbt";
167     if (MI->getOpcode() == PPC::DCBTST)
168       O << "st";
169     if (TH == 16)
170       O << "t";
171     O << " ";
172 
173     bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
174     if (IsBookE && TH != 0 && TH != 16)
175       O << (unsigned int) TH << ", ";
176 
177     printOperand(MI, 1, STI, O);
178     O << ", ";
179     printOperand(MI, 2, STI, O);
180 
181     if (!IsBookE && TH != 0 && TH != 16)
182       O << ", " << (unsigned int) TH;
183 
184     printAnnotation(O, Annot);
185     return;
186   }
187 
188   if (MI->getOpcode() == PPC::DCBF) {
189     unsigned char L = MI->getOperand(0).getImm();
190     if (!L || L == 1 || L == 3 || L == 4 || L == 6) {
191       O << "\tdcb";
192       if (L != 6)
193         O << "f";
194       if (L == 1)
195         O << "l";
196       if (L == 3)
197         O << "lp";
198       if (L == 4)
199         O << "ps";
200       if (L == 6)
201         O << "stps";
202       O << " ";
203 
204       printOperand(MI, 1, STI, O);
205       O << ", ";
206       printOperand(MI, 2, STI, O);
207 
208       printAnnotation(O, Annot);
209       return;
210     }
211   }
212 
213   if (!printAliasInstr(MI, Address, STI, O))
214     printInstruction(MI, Address, STI, O);
215   printAnnotation(O, Annot);
216 }
217 
218 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
219                                            const MCSubtargetInfo &STI,
220                                            raw_ostream &O,
221                                            const char *Modifier) {
222   unsigned Code = MI->getOperand(OpNo).getImm();
223 
224   if (StringRef(Modifier) == "cc") {
225     switch ((PPC::Predicate)Code) {
226     case PPC::PRED_LT_MINUS:
227     case PPC::PRED_LT_PLUS:
228     case PPC::PRED_LT:
229       O << "lt";
230       return;
231     case PPC::PRED_LE_MINUS:
232     case PPC::PRED_LE_PLUS:
233     case PPC::PRED_LE:
234       O << "le";
235       return;
236     case PPC::PRED_EQ_MINUS:
237     case PPC::PRED_EQ_PLUS:
238     case PPC::PRED_EQ:
239       O << "eq";
240       return;
241     case PPC::PRED_GE_MINUS:
242     case PPC::PRED_GE_PLUS:
243     case PPC::PRED_GE:
244       O << "ge";
245       return;
246     case PPC::PRED_GT_MINUS:
247     case PPC::PRED_GT_PLUS:
248     case PPC::PRED_GT:
249       O << "gt";
250       return;
251     case PPC::PRED_NE_MINUS:
252     case PPC::PRED_NE_PLUS:
253     case PPC::PRED_NE:
254       O << "ne";
255       return;
256     case PPC::PRED_UN_MINUS:
257     case PPC::PRED_UN_PLUS:
258     case PPC::PRED_UN:
259       O << "un";
260       return;
261     case PPC::PRED_NU_MINUS:
262     case PPC::PRED_NU_PLUS:
263     case PPC::PRED_NU:
264       O << "nu";
265       return;
266     case PPC::PRED_BIT_SET:
267     case PPC::PRED_BIT_UNSET:
268       llvm_unreachable("Invalid use of bit predicate code");
269     }
270     llvm_unreachable("Invalid predicate code");
271   }
272 
273   if (StringRef(Modifier) == "pm") {
274     switch ((PPC::Predicate)Code) {
275     case PPC::PRED_LT:
276     case PPC::PRED_LE:
277     case PPC::PRED_EQ:
278     case PPC::PRED_GE:
279     case PPC::PRED_GT:
280     case PPC::PRED_NE:
281     case PPC::PRED_UN:
282     case PPC::PRED_NU:
283       return;
284     case PPC::PRED_LT_MINUS:
285     case PPC::PRED_LE_MINUS:
286     case PPC::PRED_EQ_MINUS:
287     case PPC::PRED_GE_MINUS:
288     case PPC::PRED_GT_MINUS:
289     case PPC::PRED_NE_MINUS:
290     case PPC::PRED_UN_MINUS:
291     case PPC::PRED_NU_MINUS:
292       O << "-";
293       return;
294     case PPC::PRED_LT_PLUS:
295     case PPC::PRED_LE_PLUS:
296     case PPC::PRED_EQ_PLUS:
297     case PPC::PRED_GE_PLUS:
298     case PPC::PRED_GT_PLUS:
299     case PPC::PRED_NE_PLUS:
300     case PPC::PRED_UN_PLUS:
301     case PPC::PRED_NU_PLUS:
302       O << "+";
303       return;
304     case PPC::PRED_BIT_SET:
305     case PPC::PRED_BIT_UNSET:
306       llvm_unreachable("Invalid use of bit predicate code");
307     }
308     llvm_unreachable("Invalid predicate code");
309   }
310 
311   assert(StringRef(Modifier) == "reg" &&
312          "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
313   printOperand(MI, OpNo + 1, STI, O);
314 }
315 
316 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
317                                        const MCSubtargetInfo &STI,
318                                        raw_ostream &O) {
319   unsigned Code = MI->getOperand(OpNo).getImm();
320   if (Code == 2)
321     O << "-";
322   else if (Code == 3)
323     O << "+";
324 }
325 
326 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
327                                        const MCSubtargetInfo &STI,
328                                        raw_ostream &O) {
329   unsigned int Value = MI->getOperand(OpNo).getImm();
330   assert(Value <= 1 && "Invalid u1imm argument!");
331   O << (unsigned int)Value;
332 }
333 
334 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
335                                        const MCSubtargetInfo &STI,
336                                        raw_ostream &O) {
337   unsigned int Value = MI->getOperand(OpNo).getImm();
338   assert(Value <= 3 && "Invalid u2imm argument!");
339   O << (unsigned int)Value;
340 }
341 
342 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
343                                        const MCSubtargetInfo &STI,
344                                        raw_ostream &O) {
345   unsigned int Value = MI->getOperand(OpNo).getImm();
346   assert(Value <= 8 && "Invalid u3imm argument!");
347   O << (unsigned int)Value;
348 }
349 
350 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
351                                        const MCSubtargetInfo &STI,
352                                        raw_ostream &O) {
353   unsigned int Value = MI->getOperand(OpNo).getImm();
354   assert(Value <= 15 && "Invalid u4imm argument!");
355   O << (unsigned int)Value;
356 }
357 
358 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
359                                        const MCSubtargetInfo &STI,
360                                        raw_ostream &O) {
361   int Value = MI->getOperand(OpNo).getImm();
362   Value = SignExtend32<5>(Value);
363   O << (int)Value;
364 }
365 
366 void PPCInstPrinter::printImmZeroOperand(const MCInst *MI, unsigned OpNo,
367                                          const MCSubtargetInfo &STI,
368                                          raw_ostream &O) {
369   unsigned int Value = MI->getOperand(OpNo).getImm();
370   assert(Value == 0 && "Operand must be zero");
371   O << (unsigned int)Value;
372 }
373 
374 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
375                                        const MCSubtargetInfo &STI,
376                                        raw_ostream &O) {
377   unsigned int Value = MI->getOperand(OpNo).getImm();
378   assert(Value <= 31 && "Invalid u5imm argument!");
379   O << (unsigned int)Value;
380 }
381 
382 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
383                                        const MCSubtargetInfo &STI,
384                                        raw_ostream &O) {
385   unsigned int Value = MI->getOperand(OpNo).getImm();
386   assert(Value <= 63 && "Invalid u6imm argument!");
387   O << (unsigned int)Value;
388 }
389 
390 void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
391                                        const MCSubtargetInfo &STI,
392                                        raw_ostream &O) {
393   unsigned int Value = MI->getOperand(OpNo).getImm();
394   assert(Value <= 127 && "Invalid u7imm argument!");
395   O << (unsigned int)Value;
396 }
397 
398 // Operands of BUILD_VECTOR are signed and we use this to print operands
399 // of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
400 // print as unsigned.
401 void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
402                                        const MCSubtargetInfo &STI,
403                                        raw_ostream &O) {
404   unsigned char Value = MI->getOperand(OpNo).getImm();
405   O << (unsigned int)Value;
406 }
407 
408 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
409                                         const MCSubtargetInfo &STI,
410                                         raw_ostream &O) {
411   unsigned short Value = MI->getOperand(OpNo).getImm();
412   assert(Value <= 1023 && "Invalid u10imm argument!");
413   O << (unsigned short)Value;
414 }
415 
416 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
417                                         const MCSubtargetInfo &STI,
418                                         raw_ostream &O) {
419   unsigned short Value = MI->getOperand(OpNo).getImm();
420   assert(Value <= 4095 && "Invalid u12imm argument!");
421   O << (unsigned short)Value;
422 }
423 
424 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
425                                         const MCSubtargetInfo &STI,
426                                         raw_ostream &O) {
427   if (MI->getOperand(OpNo).isImm())
428     O << (short)MI->getOperand(OpNo).getImm();
429   else
430     printOperand(MI, OpNo, STI, O);
431 }
432 
433 void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo,
434                                         const MCSubtargetInfo &STI,
435                                         raw_ostream &O) {
436   if (MI->getOperand(OpNo).isImm()) {
437     long long Value = MI->getOperand(OpNo).getImm();
438     assert(isInt<34>(Value) && "Invalid s34imm argument!");
439     O << (long long)Value;
440   }
441   else
442     printOperand(MI, OpNo, STI, O);
443 }
444 
445 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
446                                         const MCSubtargetInfo &STI,
447                                         raw_ostream &O) {
448   if (MI->getOperand(OpNo).isImm())
449     O << (unsigned short)MI->getOperand(OpNo).getImm();
450   else
451     printOperand(MI, OpNo, STI, O);
452 }
453 
454 void PPCInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
455                                         unsigned OpNo,
456                                         const MCSubtargetInfo &STI,
457                                         raw_ostream &O) {
458   if (!MI->getOperand(OpNo).isImm())
459     return printOperand(MI, OpNo, STI, O);
460   int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
461   if (PrintBranchImmAsAddress) {
462     uint64_t Target = Address + Imm;
463     if (!TT.isPPC64())
464       Target &= 0xffffffff;
465     O << formatHex(Target);
466   } else {
467     // Branches can take an immediate operand. This is used by the branch
468     // selection pass to print, for example `.+8` (for ELF) or `$+8` (for AIX)
469     // to express an eight byte displacement from the program counter.
470     if (!TT.isOSAIX())
471       O << ".";
472     else
473       O << "$";
474 
475     if (Imm >= 0)
476       O << "+";
477     O << Imm;
478   }
479 }
480 
481 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
482                                            const MCSubtargetInfo &STI,
483                                            raw_ostream &O) {
484   if (!MI->getOperand(OpNo).isImm())
485     return printOperand(MI, OpNo, STI, O);
486 
487   O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
488 }
489 
490 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
491                                  const MCSubtargetInfo &STI, raw_ostream &O) {
492   unsigned CCReg = MI->getOperand(OpNo).getReg();
493   unsigned RegNo;
494   switch (CCReg) {
495   default: llvm_unreachable("Unknown CR register");
496   case PPC::CR0: RegNo = 0; break;
497   case PPC::CR1: RegNo = 1; break;
498   case PPC::CR2: RegNo = 2; break;
499   case PPC::CR3: RegNo = 3; break;
500   case PPC::CR4: RegNo = 4; break;
501   case PPC::CR5: RegNo = 5; break;
502   case PPC::CR6: RegNo = 6; break;
503   case PPC::CR7: RegNo = 7; break;
504   }
505   O << (0x80 >> RegNo);
506 }
507 
508 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
509                                     const MCSubtargetInfo &STI,
510                                     raw_ostream &O) {
511   printS16ImmOperand(MI, OpNo, STI, O);
512   O << '(';
513   if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
514     O << "0";
515   else
516     printOperand(MI, OpNo + 1, STI, O);
517   O << ')';
518 }
519 
520 void PPCInstPrinter::printMemRegImmHash(const MCInst *MI, unsigned OpNo,
521                                         const MCSubtargetInfo &STI,
522                                         raw_ostream &O) {
523   O << MI->getOperand(OpNo).getImm();
524   O << '(';
525   printOperand(MI, OpNo + 1, STI, O);
526   O << ')';
527 }
528 
529 void PPCInstPrinter::printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo,
530                                            const MCSubtargetInfo &STI,
531                                            raw_ostream &O) {
532   printS34ImmOperand(MI, OpNo, STI, O);
533   O << '(';
534   printImmZeroOperand(MI, OpNo + 1, STI, O);
535   O << ')';
536 }
537 
538 void PPCInstPrinter::printMemRegImm34(const MCInst *MI, unsigned OpNo,
539                                       const MCSubtargetInfo &STI,
540                                       raw_ostream &O) {
541   printS34ImmOperand(MI, OpNo, STI, O);
542   O << '(';
543   printOperand(MI, OpNo + 1, STI, O);
544   O << ')';
545 }
546 
547 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
548                                     const MCSubtargetInfo &STI,
549                                     raw_ostream &O) {
550   // When used as the base register, r0 reads constant zero rather than
551   // the value contained in the register.  For this reason, the darwin
552   // assembler requires that we print r0 as 0 (no r) when used as the base.
553   if (MI->getOperand(OpNo).getReg() == PPC::R0)
554     O << "0";
555   else
556     printOperand(MI, OpNo, STI, O);
557   O << ", ";
558   printOperand(MI, OpNo + 1, STI, O);
559 }
560 
561 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
562                                   const MCSubtargetInfo &STI, raw_ostream &O) {
563   // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
564   // come at the _end_ of the expression.
565   const MCOperand &Op = MI->getOperand(OpNo);
566   const MCSymbolRefExpr *RefExp = nullptr;
567   const MCConstantExpr *ConstExp = nullptr;
568   if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) {
569     RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
570     ConstExp = cast<MCConstantExpr>(BinExpr->getRHS());
571   } else
572     RefExp = cast<MCSymbolRefExpr>(Op.getExpr());
573 
574   O << RefExp->getSymbol().getName();
575   // The variant kind VK_PPC_NOTOC needs to be handled as a special case
576   // because we do not want the assembly to print out the @notoc at the
577   // end like __tls_get_addr(x@tlsgd)@notoc. Instead we want it to look
578   // like __tls_get_addr@notoc(x@tlsgd).
579   if (RefExp->getKind() == MCSymbolRefExpr::VK_PPC_NOTOC)
580     O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
581   O << '(';
582   printOperand(MI, OpNo + 1, STI, O);
583   O << ')';
584   if (RefExp->getKind() != MCSymbolRefExpr::VK_None &&
585       RefExp->getKind() != MCSymbolRefExpr::VK_PPC_NOTOC)
586     O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
587   if (ConstExp != nullptr)
588     O << '+' << ConstExp->getValue();
589 }
590 
591 /// showRegistersWithPercentPrefix - Check if this register name should be
592 /// printed with a percentage symbol as prefix.
593 bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
594   if (!FullRegNamesWithPercent || TT.getOS() == Triple::AIX)
595     return false;
596 
597   switch (RegName[0]) {
598   default:
599     return false;
600   case 'r':
601   case 'f':
602   case 'q':
603   case 'v':
604   case 'c':
605     return true;
606   }
607 }
608 
609 /// getVerboseConditionalRegName - This method expands the condition register
610 /// when requested explicitly or targetting Darwin.
611 const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
612                                                        unsigned RegEncoding)
613                                                        const {
614   if (!FullRegNames)
615     return nullptr;
616   if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
617     return nullptr;
618   const char *CRBits[] = {
619     "lt", "gt", "eq", "un",
620     "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
621     "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
622     "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
623     "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
624     "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
625     "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
626     "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
627   };
628   return CRBits[RegEncoding];
629 }
630 
631 // showRegistersWithPrefix - This method determines whether registers
632 // should be number-only or include the prefix.
633 bool PPCInstPrinter::showRegistersWithPrefix() const {
634   return FullRegNamesWithPercent || FullRegNames;
635 }
636 
637 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
638                                   const MCSubtargetInfo &STI, raw_ostream &O) {
639   const MCOperand &Op = MI->getOperand(OpNo);
640   if (Op.isReg()) {
641     unsigned Reg = Op.getReg();
642     if (!ShowVSRNumsAsVR)
643       Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()),
644                                               Reg, OpNo);
645 
646     const char *RegName;
647     RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
648     if (RegName == nullptr)
649      RegName = getRegisterName(Reg);
650     if (showRegistersWithPercentPrefix(RegName))
651       O << "%";
652     if (!showRegistersWithPrefix())
653       RegName = PPCRegisterInfo::stripRegisterPrefix(RegName);
654 
655     O << RegName;
656     return;
657   }
658 
659   if (Op.isImm()) {
660     O << Op.getImm();
661     return;
662   }
663 
664   assert(Op.isExpr() && "unknown operand kind in printOperand");
665   Op.getExpr()->print(O, &MAI);
666 }
667