1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the PPCMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/PPCFixupKinds.h"
14 #include "PPCInstrInfo.h"
15 #include "PPCMCCodeEmitter.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCFixup.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/Endian.h"
23 #include "llvm/Support/EndianStream.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include <cassert>
28 #include <cstdint>
29 
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "mccodeemitter"
33 
34 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
35 
36 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
37                                             const MCRegisterInfo &MRI,
38                                             MCContext &Ctx) {
39   return new PPCMCCodeEmitter(MCII, Ctx);
40 }
41 
42 unsigned PPCMCCodeEmitter::
43 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
44                     SmallVectorImpl<MCFixup> &Fixups,
45                     const MCSubtargetInfo &STI) const {
46   const MCOperand &MO = MI.getOperand(OpNo);
47 
48   if (MO.isReg() || MO.isImm())
49     return getMachineOpValue(MI, MO, Fixups, STI);
50   // Add a fixup for the branch target.
51   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
52                                    ((MI.getOpcode() == PPC::BL8_NOTOC ||
53                                      MI.getOpcode() == PPC::BL8_NOTOC_TLS)
54                                         ? (MCFixupKind)PPC::fixup_ppc_br24_notoc
55                                         : (MCFixupKind)PPC::fixup_ppc_br24)));
56   return 0;
57 }
58 
59 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
60                                      SmallVectorImpl<MCFixup> &Fixups,
61                                      const MCSubtargetInfo &STI) const {
62   const MCOperand &MO = MI.getOperand(OpNo);
63   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
64 
65   // Add a fixup for the branch target.
66   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
67                                    (MCFixupKind)PPC::fixup_ppc_brcond14));
68   return 0;
69 }
70 
71 unsigned PPCMCCodeEmitter::
72 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
73                        SmallVectorImpl<MCFixup> &Fixups,
74                        const MCSubtargetInfo &STI) const {
75   const MCOperand &MO = MI.getOperand(OpNo);
76   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
77 
78   // Add a fixup for the branch target.
79   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
80                                    (MCFixupKind)PPC::fixup_ppc_br24abs));
81   return 0;
82 }
83 
84 unsigned PPCMCCodeEmitter::
85 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
86                      SmallVectorImpl<MCFixup> &Fixups,
87                      const MCSubtargetInfo &STI) const {
88   const MCOperand &MO = MI.getOperand(OpNo);
89   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
90 
91   // Add a fixup for the branch target.
92   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
93                                    (MCFixupKind)PPC::fixup_ppc_brcond14abs));
94   return 0;
95 }
96 
97 unsigned
98 PPCMCCodeEmitter::getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo,
99                                       SmallVectorImpl<MCFixup> &Fixups,
100                                       const MCSubtargetInfo &STI) const {
101   assert(MI.getOperand(OpNo).isReg() && "Operand should be a register");
102   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)
103                      << 1;
104   return RegBits;
105 }
106 
107 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
108                                        SmallVectorImpl<MCFixup> &Fixups,
109                                        const MCSubtargetInfo &STI) const {
110   const MCOperand &MO = MI.getOperand(OpNo);
111   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
112 
113   // Add a fixup for the immediate field.
114   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
115                                    (MCFixupKind)PPC::fixup_ppc_half16));
116   return 0;
117 }
118 
119 uint64_t PPCMCCodeEmitter::getImm34Encoding(const MCInst &MI, unsigned OpNo,
120                                             SmallVectorImpl<MCFixup> &Fixups,
121                                             const MCSubtargetInfo &STI,
122                                             MCFixupKind Fixup) const {
123   const MCOperand &MO = MI.getOperand(OpNo);
124   assert(!MO.isReg() && "Not expecting a register for this operand.");
125   if (MO.isImm())
126     return getMachineOpValue(MI, MO, Fixups, STI);
127 
128   // Add a fixup for the immediate field.
129   Fixups.push_back(MCFixup::create(0, MO.getExpr(), Fixup));
130   return 0;
131 }
132 
133 uint64_t
134 PPCMCCodeEmitter::getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo,
135                                           SmallVectorImpl<MCFixup> &Fixups,
136                                           const MCSubtargetInfo &STI) const {
137   return getImm34Encoding(MI, OpNo, Fixups, STI,
138                           (MCFixupKind)PPC::fixup_ppc_imm34);
139 }
140 
141 uint64_t
142 PPCMCCodeEmitter::getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo,
143                                         SmallVectorImpl<MCFixup> &Fixups,
144                                         const MCSubtargetInfo &STI) const {
145   return getImm34Encoding(MI, OpNo, Fixups, STI,
146                           (MCFixupKind)PPC::fixup_ppc_pcrel34);
147 }
148 
149 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
150                                             SmallVectorImpl<MCFixup> &Fixups,
151                                             const MCSubtargetInfo &STI) const {
152   // Encode (imm, reg) as a memri, which has the low 16-bits as the
153   // displacement and the next 5 bits as the register #.
154   assert(MI.getOperand(OpNo+1).isReg());
155   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
156 
157   const MCOperand &MO = MI.getOperand(OpNo);
158   if (MO.isImm())
159     return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
160 
161   // Add a fixup for the displacement field.
162   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
163                                    (MCFixupKind)PPC::fixup_ppc_half16));
164   return RegBits;
165 }
166 
167 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
168                                        SmallVectorImpl<MCFixup> &Fixups,
169                                        const MCSubtargetInfo &STI) const {
170   // Encode (imm, reg) as a memrix, which has the low 14-bits as the
171   // displacement and the next 5 bits as the register #.
172   assert(MI.getOperand(OpNo+1).isReg());
173   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;
174 
175   const MCOperand &MO = MI.getOperand(OpNo);
176   if (MO.isImm())
177     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
178 
179   // Add a fixup for the displacement field.
180   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
181                                    (MCFixupKind)PPC::fixup_ppc_half16ds));
182   return RegBits;
183 }
184 
185 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
186                                        SmallVectorImpl<MCFixup> &Fixups,
187                                        const MCSubtargetInfo &STI) const {
188   // Encode (imm, reg) as a memrix16, which has the low 12-bits as the
189   // displacement and the next 5 bits as the register #.
190   assert(MI.getOperand(OpNo+1).isReg());
191   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;
192 
193   const MCOperand &MO = MI.getOperand(OpNo);
194   if (MO.isImm()) {
195     assert(!(MO.getImm() % 16) &&
196            "Expecting an immediate that is a multiple of 16");
197     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
198   }
199 
200   // Otherwise add a fixup for the displacement field.
201   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
202                                    (MCFixupKind)PPC::fixup_ppc_half16ds));
203   return RegBits;
204 }
205 
206 uint64_t
207 PPCMCCodeEmitter::getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
208                                           SmallVectorImpl<MCFixup> &Fixups,
209                                           const MCSubtargetInfo &STI) const {
210   // Encode the PCRelative version of memri34: imm34(r0).
211   // In the PC relative version the register for the address must be zero.
212   // The 34 bit immediate can fall into one of three cases:
213   // 1) It is a relocation to be filled in by the linker represented as:
214   //    (MCExpr::SymbolRef)
215   // 2) It is a relocation + SignedOffset represented as:
216   //    (MCExpr::Binary(MCExpr::SymbolRef + MCExpr::Constant))
217   // 3) It is a known value at compile time.
218 
219   // Make sure that the register is a zero as expected.
220   assert(MI.getOperand(OpNo + 1).isImm() && "Expecting an immediate.");
221   uint64_t RegBits =
222     getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34;
223   assert(RegBits == 0 && "Operand must be 0.");
224 
225   // If this is not a MCExpr then we are in case 3) and we are dealing with
226   // a value known at compile time, not a relocation.
227   const MCOperand &MO = MI.getOperand(OpNo);
228   if (!MO.isExpr())
229     return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
230 
231   // At this point in the function it is known that MO is of type MCExpr.
232   // Therefore we are dealing with either case 1) a symbol ref or
233   // case 2) a symbol ref plus a constant.
234   const MCExpr *Expr = MO.getExpr();
235   switch (Expr->getKind()) {
236   default:
237     llvm_unreachable("Unsupported MCExpr for getMemRI34PCRelEncoding.");
238   case MCExpr::SymbolRef: {
239     // Relocation alone.
240     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
241     (void)SRE;
242     // Currently these are the only valid PCRelative Relocations.
243     assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL ||
244             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_PCREL ||
245             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TLSGD_PCREL ||
246             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TLSLD_PCREL ||
247             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TPREL_PCREL) &&
248            "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL or "
249            "VK_PPC_GOT_TLSGD_PCREL or VK_PPC_GOT_TLSLD_PCREL or "
250            "VK_PPC_GOT_TPREL_PCREL.");
251     // Generate the fixup for the relocation.
252     Fixups.push_back(
253         MCFixup::create(0, Expr,
254                         static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
255     // Put zero in the location of the immediate. The linker will fill in the
256     // correct value based on the relocation.
257     return 0;
258   }
259   case MCExpr::Binary: {
260     // Relocation plus some offset.
261     const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
262     assert(BE->getOpcode() == MCBinaryExpr::Add &&
263            "Binary expression opcode must be an add.");
264 
265     const MCExpr *LHS = BE->getLHS();
266     const MCExpr *RHS = BE->getRHS();
267 
268     // Need to check in both directions. Reloc+Offset and Offset+Reloc.
269     if (LHS->getKind() != MCExpr::SymbolRef)
270       std::swap(LHS, RHS);
271 
272     if (LHS->getKind() != MCExpr::SymbolRef ||
273         RHS->getKind() != MCExpr::Constant)
274       llvm_unreachable("Expecting to have one constant and one relocation.");
275 
276     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(LHS);
277     (void)SRE;
278     assert(isInt<34>(cast<MCConstantExpr>(RHS)->getValue()) &&
279            "Value must fit in 34 bits.");
280 
281     // Currently these are the only valid PCRelative Relocations.
282     assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL ||
283             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_PCREL) &&
284            "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL");
285     // Generate the fixup for the relocation.
286     Fixups.push_back(
287         MCFixup::create(0, Expr,
288                         static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
289     // Put zero in the location of the immediate. The linker will fill in the
290     // correct value based on the relocation.
291     return 0;
292     }
293   }
294 }
295 
296 uint64_t
297 PPCMCCodeEmitter::getMemRI34Encoding(const MCInst &MI, unsigned OpNo,
298                                      SmallVectorImpl<MCFixup> &Fixups,
299                                      const MCSubtargetInfo &STI) const {
300   // Encode (imm, reg) as a memri34, which has the low 34-bits as the
301   // displacement and the next 5 bits as the register #.
302   assert(MI.getOperand(OpNo + 1).isReg() && "Expecting a register.");
303   uint64_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI)
304                      << 34;
305   const MCOperand &MO = MI.getOperand(OpNo);
306   return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
307 }
308 
309 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
310                                               SmallVectorImpl<MCFixup> &Fixups,
311                                               const MCSubtargetInfo &STI)
312                                               const {
313   // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
314   // as the displacement and the next 5 bits as the register #.
315   assert(MI.getOperand(OpNo+1).isReg());
316   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
317 
318   const MCOperand &MO = MI.getOperand(OpNo);
319   assert(MO.isImm());
320   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
321   return reverseBits(Imm | RegBits) >> 22;
322 }
323 
324 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
325                                               SmallVectorImpl<MCFixup> &Fixups,
326                                               const MCSubtargetInfo &STI)
327                                               const {
328   // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4)
329   // as the displacement and the next 5 bits as the register #.
330   assert(MI.getOperand(OpNo+1).isReg());
331   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
332 
333   const MCOperand &MO = MI.getOperand(OpNo);
334   assert(MO.isImm());
335   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;
336   return reverseBits(Imm | RegBits) >> 22;
337 }
338 
339 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
340                                               SmallVectorImpl<MCFixup> &Fixups,
341                                               const MCSubtargetInfo &STI)
342                                               const {
343   // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2)
344   // as the displacement and the next 5 bits as the register #.
345   assert(MI.getOperand(OpNo+1).isReg());
346   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
347 
348   const MCOperand &MO = MI.getOperand(OpNo);
349   assert(MO.isImm());
350   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;
351   return reverseBits(Imm | RegBits) >> 22;
352 }
353 
354 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
355                                        SmallVectorImpl<MCFixup> &Fixups,
356                                        const MCSubtargetInfo &STI) const {
357   const MCOperand &MO = MI.getOperand(OpNo);
358   if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
359 
360   // Add a fixup for the TLS register, which simply provides a relocation
361   // hint to the linker that this statement is part of a relocation sequence.
362   // Return the thread-pointer register's encoding. Add a one byte displacement
363   // if using PC relative memops.
364   const MCExpr *Expr = MO.getExpr();
365   const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
366   bool IsPCRel = SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS_PCREL;
367   Fixups.push_back(MCFixup::create(IsPCRel ? 1 : 0, Expr,
368                                    (MCFixupKind)PPC::fixup_ppc_nofixup));
369   const Triple &TT = STI.getTargetTriple();
370   bool isPPC64 = TT.isPPC64();
371   return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
372 }
373 
374 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
375                                        SmallVectorImpl<MCFixup> &Fixups,
376                                        const MCSubtargetInfo &STI) const {
377   // For special TLS calls, we need two fixups; one for the branch target
378   // (__tls_get_addr), which we create via getDirectBrEncoding as usual,
379   // and one for the TLSGD or TLSLD symbol, which is emitted here.
380   const MCOperand &MO = MI.getOperand(OpNo+1);
381   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
382                                    (MCFixupKind)PPC::fixup_ppc_nofixup));
383   return getDirectBrEncoding(MI, OpNo, Fixups, STI);
384 }
385 
386 unsigned PPCMCCodeEmitter::
387 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
388                     SmallVectorImpl<MCFixup> &Fixups,
389                     const MCSubtargetInfo &STI) const {
390   const MCOperand &MO = MI.getOperand(OpNo);
391   assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
392           MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
393          (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
394   return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
395 }
396 
397 // Get the index for this operand in this instruction. This is needed for
398 // computing the register number in PPCInstrInfo::getRegNumForOperand() for
399 // any instructions that use a different numbering scheme for registers in
400 // different operands.
401 static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) {
402   for (unsigned i = 0; i < MI.getNumOperands(); i++) {
403     const MCOperand &Op = MI.getOperand(i);
404     if (&Op == &MO)
405       return i;
406   }
407   llvm_unreachable("This operand is not part of this instruction");
408   return ~0U; // Silence any warnings about no return.
409 }
410 
411 uint64_t PPCMCCodeEmitter::
412 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
413                   SmallVectorImpl<MCFixup> &Fixups,
414                   const MCSubtargetInfo &STI) const {
415   if (MO.isReg()) {
416     // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
417     // The GPR operand should come through here though.
418     assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
419             MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
420            MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
421     unsigned OpNo = getOpIdxForMO(MI, MO);
422     unsigned Reg =
423       PPCInstrInfo::getRegNumForOperand(MCII.get(MI.getOpcode()),
424                                         MO.getReg(), OpNo);
425     return CTX.getRegisterInfo()->getEncodingValue(Reg);
426   }
427 
428   assert(MO.isImm() &&
429          "Relocation required in an instruction that we cannot encode!");
430   return MO.getImm();
431 }
432 
433 void PPCMCCodeEmitter::encodeInstruction(
434     const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
435     const MCSubtargetInfo &STI) const {
436   verifyInstructionPredicates(MI,
437                               computeAvailableFeatures(STI.getFeatureBits()));
438 
439   uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
440 
441   // Output the constant in big/little endian byte order.
442   unsigned Size = getInstSizeInBytes(MI);
443   support::endianness E = IsLittleEndian ? support::little : support::big;
444   switch (Size) {
445   case 0:
446     break;
447   case 4:
448     support::endian::write<uint32_t>(OS, Bits, E);
449     break;
450   case 8:
451     // If we emit a pair of instructions, the first one is
452     // always in the top 32 bits, even on little-endian.
453     support::endian::write<uint32_t>(OS, Bits >> 32, E);
454     support::endian::write<uint32_t>(OS, Bits, E);
455     break;
456   default:
457     llvm_unreachable("Invalid instruction size");
458   }
459 
460   ++MCNumEmitted; // Keep track of the # of mi's emitted.
461 }
462 
463 // Get the number of bytes used to encode the given MCInst.
464 unsigned PPCMCCodeEmitter::getInstSizeInBytes(const MCInst &MI) const {
465   unsigned Opcode = MI.getOpcode();
466   const MCInstrDesc &Desc = MCII.get(Opcode);
467   return Desc.getSize();
468 }
469 
470 bool PPCMCCodeEmitter::isPrefixedInstruction(const MCInst &MI) const {
471   unsigned Opcode = MI.getOpcode();
472   const PPCInstrInfo *InstrInfo = static_cast<const PPCInstrInfo*>(&MCII);
473   return InstrInfo->isPrefixed(Opcode);
474 }
475 
476 #define ENABLE_INSTR_PREDICATE_VERIFIER
477 #include "PPCGenMCCodeEmitter.inc"
478