1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the PPCMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/PPCFixupKinds.h"
14 #include "PPCInstrInfo.h"
15 #include "PPCMCCodeEmitter.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCFixup.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/Endian.h"
23 #include "llvm/Support/EndianStream.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include <cassert>
28 #include <cstdint>
29 
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "mccodeemitter"
33 
34 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
35 
36 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
37                                             const MCRegisterInfo &MRI,
38                                             MCContext &Ctx) {
39   return new PPCMCCodeEmitter(MCII, Ctx);
40 }
41 
42 unsigned PPCMCCodeEmitter::
43 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
44                     SmallVectorImpl<MCFixup> &Fixups,
45                     const MCSubtargetInfo &STI) const {
46   const MCOperand &MO = MI.getOperand(OpNo);
47 
48   if (MO.isReg() || MO.isImm())
49     return getMachineOpValue(MI, MO, Fixups, STI);
50   // Add a fixup for the branch target.
51   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
52                                    ((MI.getOpcode() == PPC::BL8_NOTOC ||
53                                      MI.getOpcode() == PPC::BL8_NOTOC_TLS)
54                                         ? (MCFixupKind)PPC::fixup_ppc_br24_notoc
55                                         : (MCFixupKind)PPC::fixup_ppc_br24)));
56   return 0;
57 }
58 
59 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
60                                      SmallVectorImpl<MCFixup> &Fixups,
61                                      const MCSubtargetInfo &STI) const {
62   const MCOperand &MO = MI.getOperand(OpNo);
63   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
64 
65   // Add a fixup for the branch target.
66   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
67                                    (MCFixupKind)PPC::fixup_ppc_brcond14));
68   return 0;
69 }
70 
71 unsigned PPCMCCodeEmitter::
72 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
73                        SmallVectorImpl<MCFixup> &Fixups,
74                        const MCSubtargetInfo &STI) const {
75   const MCOperand &MO = MI.getOperand(OpNo);
76   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
77 
78   // Add a fixup for the branch target.
79   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
80                                    (MCFixupKind)PPC::fixup_ppc_br24abs));
81   return 0;
82 }
83 
84 unsigned PPCMCCodeEmitter::
85 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
86                      SmallVectorImpl<MCFixup> &Fixups,
87                      const MCSubtargetInfo &STI) const {
88   const MCOperand &MO = MI.getOperand(OpNo);
89   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
90 
91   // Add a fixup for the branch target.
92   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
93                                    (MCFixupKind)PPC::fixup_ppc_brcond14abs));
94   return 0;
95 }
96 
97 unsigned
98 PPCMCCodeEmitter::getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo,
99                                       SmallVectorImpl<MCFixup> &Fixups,
100                                       const MCSubtargetInfo &STI) const {
101   assert(MI.getOperand(OpNo).isReg() && "Operand should be a register");
102   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)
103                      << 1;
104   return RegBits;
105 }
106 
107 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
108                                        SmallVectorImpl<MCFixup> &Fixups,
109                                        const MCSubtargetInfo &STI) const {
110   const MCOperand &MO = MI.getOperand(OpNo);
111   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
112 
113   // Add a fixup for the immediate field.
114   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
115                                    (MCFixupKind)PPC::fixup_ppc_half16));
116   return 0;
117 }
118 
119 uint64_t PPCMCCodeEmitter::getImm34Encoding(const MCInst &MI, unsigned OpNo,
120                                             SmallVectorImpl<MCFixup> &Fixups,
121                                             const MCSubtargetInfo &STI,
122                                             MCFixupKind Fixup) const {
123   const MCOperand &MO = MI.getOperand(OpNo);
124   assert(!MO.isReg() && "Not expecting a register for this operand.");
125   if (MO.isImm())
126     return getMachineOpValue(MI, MO, Fixups, STI);
127 
128   // Add a fixup for the immediate field.
129   Fixups.push_back(MCFixup::create(0, MO.getExpr(), Fixup));
130   return 0;
131 }
132 
133 uint64_t
134 PPCMCCodeEmitter::getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo,
135                                           SmallVectorImpl<MCFixup> &Fixups,
136                                           const MCSubtargetInfo &STI) const {
137   return getImm34Encoding(MI, OpNo, Fixups, STI,
138                           (MCFixupKind)PPC::fixup_ppc_imm34);
139 }
140 
141 uint64_t
142 PPCMCCodeEmitter::getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo,
143                                         SmallVectorImpl<MCFixup> &Fixups,
144                                         const MCSubtargetInfo &STI) const {
145   return getImm34Encoding(MI, OpNo, Fixups, STI,
146                           (MCFixupKind)PPC::fixup_ppc_pcrel34);
147 }
148 
149 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
150                                             SmallVectorImpl<MCFixup> &Fixups,
151                                             const MCSubtargetInfo &STI) const {
152   // Encode (imm, reg) as a memri, which has the low 16-bits as the
153   // displacement and the next 5 bits as the register #.
154   assert(MI.getOperand(OpNo+1).isReg());
155   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
156 
157   const MCOperand &MO = MI.getOperand(OpNo);
158   if (MO.isImm())
159     return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
160 
161   // Add a fixup for the displacement field.
162   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
163                                    (MCFixupKind)PPC::fixup_ppc_half16));
164   return RegBits;
165 }
166 
167 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
168                                        SmallVectorImpl<MCFixup> &Fixups,
169                                        const MCSubtargetInfo &STI) const {
170   // Encode (imm, reg) as a memrix, which has the low 14-bits as the
171   // displacement and the next 5 bits as the register #.
172   assert(MI.getOperand(OpNo+1).isReg());
173   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;
174 
175   const MCOperand &MO = MI.getOperand(OpNo);
176   if (MO.isImm())
177     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
178 
179   // Add a fixup for the displacement field.
180   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
181                                    (MCFixupKind)PPC::fixup_ppc_half16ds));
182   return RegBits;
183 }
184 
185 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
186                                        SmallVectorImpl<MCFixup> &Fixups,
187                                        const MCSubtargetInfo &STI) const {
188   // Encode (imm, reg) as a memrix16, which has the low 12-bits as the
189   // displacement and the next 5 bits as the register #.
190   assert(MI.getOperand(OpNo+1).isReg());
191   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;
192 
193   const MCOperand &MO = MI.getOperand(OpNo);
194   if (MO.isImm()) {
195     assert(!(MO.getImm() % 16) &&
196            "Expecting an immediate that is a multiple of 16");
197     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
198   }
199 
200   // Otherwise add a fixup for the displacement field.
201   Fixups.push_back(MCFixup::create(IsLittleEndian ? 0 : 2, MO.getExpr(),
202                                    (MCFixupKind)PPC::fixup_ppc_half16dq));
203   return RegBits;
204 }
205 
206 unsigned
207 PPCMCCodeEmitter::getMemRIHashEncoding(const MCInst &MI, unsigned OpNo,
208                                        SmallVectorImpl<MCFixup> &Fixups,
209                                        const MCSubtargetInfo &STI) const {
210   // Encode (imm, reg) for the hash load/store to stack for the ROP Protection
211   // instructions.
212   const MCOperand &RegMO = MI.getOperand(OpNo + 1);
213   const MCOperand &MO = MI.getOperand(OpNo);
214 
215   assert(RegMO.isReg() && "Base address must be a register.");
216   assert(MO.isImm() && "Expecting an immediate operand.");
217   assert(!(MO.getImm() % 8) && "Expecting offset to be 8 byte aligned.");
218 
219   unsigned RegBits = getMachineOpValue(MI, RegMO, Fixups, STI) << 6;
220   unsigned DX = (MO.getImm() >> 3) & 0x3F;
221   return RegBits | DX;
222 }
223 
224 uint64_t
225 PPCMCCodeEmitter::getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
226                                           SmallVectorImpl<MCFixup> &Fixups,
227                                           const MCSubtargetInfo &STI) const {
228   // Encode the PCRelative version of memri34: imm34(r0).
229   // In the PC relative version the register for the address must be zero.
230   // The 34 bit immediate can fall into one of three cases:
231   // 1) It is a relocation to be filled in by the linker represented as:
232   //    (MCExpr::SymbolRef)
233   // 2) It is a relocation + SignedOffset represented as:
234   //    (MCExpr::Binary(MCExpr::SymbolRef + MCExpr::Constant))
235   // 3) It is a known value at compile time.
236 
237   // Make sure that the register is a zero as expected.
238   assert(MI.getOperand(OpNo + 1).isImm() && "Expecting an immediate.");
239   uint64_t RegBits =
240     getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34;
241   assert(RegBits == 0 && "Operand must be 0.");
242 
243   // If this is not a MCExpr then we are in case 3) and we are dealing with
244   // a value known at compile time, not a relocation.
245   const MCOperand &MO = MI.getOperand(OpNo);
246   if (!MO.isExpr())
247     return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
248 
249   // At this point in the function it is known that MO is of type MCExpr.
250   // Therefore we are dealing with either case 1) a symbol ref or
251   // case 2) a symbol ref plus a constant.
252   const MCExpr *Expr = MO.getExpr();
253   switch (Expr->getKind()) {
254   default:
255     llvm_unreachable("Unsupported MCExpr for getMemRI34PCRelEncoding.");
256   case MCExpr::SymbolRef: {
257     // Relocation alone.
258     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
259     (void)SRE;
260     // Currently these are the only valid PCRelative Relocations.
261     assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL ||
262             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_PCREL ||
263             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TLSGD_PCREL ||
264             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TLSLD_PCREL ||
265             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TPREL_PCREL) &&
266            "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL or "
267            "VK_PPC_GOT_TLSGD_PCREL or VK_PPC_GOT_TLSLD_PCREL or "
268            "VK_PPC_GOT_TPREL_PCREL.");
269     // Generate the fixup for the relocation.
270     Fixups.push_back(
271         MCFixup::create(0, Expr,
272                         static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
273     // Put zero in the location of the immediate. The linker will fill in the
274     // correct value based on the relocation.
275     return 0;
276   }
277   case MCExpr::Binary: {
278     // Relocation plus some offset.
279     const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
280     assert(BE->getOpcode() == MCBinaryExpr::Add &&
281            "Binary expression opcode must be an add.");
282 
283     const MCExpr *LHS = BE->getLHS();
284     const MCExpr *RHS = BE->getRHS();
285 
286     // Need to check in both directions. Reloc+Offset and Offset+Reloc.
287     if (LHS->getKind() != MCExpr::SymbolRef)
288       std::swap(LHS, RHS);
289 
290     if (LHS->getKind() != MCExpr::SymbolRef ||
291         RHS->getKind() != MCExpr::Constant)
292       llvm_unreachable("Expecting to have one constant and one relocation.");
293 
294     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(LHS);
295     (void)SRE;
296     assert(isInt<34>(cast<MCConstantExpr>(RHS)->getValue()) &&
297            "Value must fit in 34 bits.");
298 
299     // Currently these are the only valid PCRelative Relocations.
300     assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL ||
301             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_PCREL) &&
302            "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL");
303     // Generate the fixup for the relocation.
304     Fixups.push_back(
305         MCFixup::create(0, Expr,
306                         static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
307     // Put zero in the location of the immediate. The linker will fill in the
308     // correct value based on the relocation.
309     return 0;
310     }
311   }
312 }
313 
314 uint64_t
315 PPCMCCodeEmitter::getMemRI34Encoding(const MCInst &MI, unsigned OpNo,
316                                      SmallVectorImpl<MCFixup> &Fixups,
317                                      const MCSubtargetInfo &STI) const {
318   // Encode (imm, reg) as a memri34, which has the low 34-bits as the
319   // displacement and the next 5 bits as the register #.
320   assert(MI.getOperand(OpNo + 1).isReg() && "Expecting a register.");
321   uint64_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI)
322                      << 34;
323   const MCOperand &MO = MI.getOperand(OpNo);
324   return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
325 }
326 
327 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
328                                               SmallVectorImpl<MCFixup> &Fixups,
329                                               const MCSubtargetInfo &STI)
330                                               const {
331   // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
332   // as the displacement and the next 5 bits as the register #.
333   assert(MI.getOperand(OpNo+1).isReg());
334   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
335 
336   const MCOperand &MO = MI.getOperand(OpNo);
337   assert(MO.isImm());
338   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
339   return reverseBits(Imm | RegBits) >> 22;
340 }
341 
342 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
343                                               SmallVectorImpl<MCFixup> &Fixups,
344                                               const MCSubtargetInfo &STI)
345                                               const {
346   // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4)
347   // as the displacement and the next 5 bits as the register #.
348   assert(MI.getOperand(OpNo+1).isReg());
349   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
350 
351   const MCOperand &MO = MI.getOperand(OpNo);
352   assert(MO.isImm());
353   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;
354   return reverseBits(Imm | RegBits) >> 22;
355 }
356 
357 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
358                                               SmallVectorImpl<MCFixup> &Fixups,
359                                               const MCSubtargetInfo &STI)
360                                               const {
361   // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2)
362   // as the displacement and the next 5 bits as the register #.
363   assert(MI.getOperand(OpNo+1).isReg());
364   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
365 
366   const MCOperand &MO = MI.getOperand(OpNo);
367   assert(MO.isImm());
368   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;
369   return reverseBits(Imm | RegBits) >> 22;
370 }
371 
372 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
373                                        SmallVectorImpl<MCFixup> &Fixups,
374                                        const MCSubtargetInfo &STI) const {
375   const MCOperand &MO = MI.getOperand(OpNo);
376   if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
377 
378   // Add a fixup for the TLS register, which simply provides a relocation
379   // hint to the linker that this statement is part of a relocation sequence.
380   // Return the thread-pointer register's encoding. Add a one byte displacement
381   // if using PC relative memops.
382   const MCExpr *Expr = MO.getExpr();
383   const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
384   bool IsPCRel = SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS_PCREL;
385   Fixups.push_back(MCFixup::create(IsPCRel ? 1 : 0, Expr,
386                                    (MCFixupKind)PPC::fixup_ppc_nofixup));
387   const Triple &TT = STI.getTargetTriple();
388   bool isPPC64 = TT.isPPC64();
389   return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
390 }
391 
392 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
393                                        SmallVectorImpl<MCFixup> &Fixups,
394                                        const MCSubtargetInfo &STI) const {
395   // For special TLS calls, we need two fixups; one for the branch target
396   // (__tls_get_addr), which we create via getDirectBrEncoding as usual,
397   // and one for the TLSGD or TLSLD symbol, which is emitted here.
398   const MCOperand &MO = MI.getOperand(OpNo+1);
399   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
400                                    (MCFixupKind)PPC::fixup_ppc_nofixup));
401   return getDirectBrEncoding(MI, OpNo, Fixups, STI);
402 }
403 
404 unsigned PPCMCCodeEmitter::
405 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
406                     SmallVectorImpl<MCFixup> &Fixups,
407                     const MCSubtargetInfo &STI) const {
408   const MCOperand &MO = MI.getOperand(OpNo);
409   assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
410           MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
411          (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
412   return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
413 }
414 
415 // Get the index for this operand in this instruction. This is needed for
416 // computing the register number in PPCInstrInfo::getRegNumForOperand() for
417 // any instructions that use a different numbering scheme for registers in
418 // different operands.
419 static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) {
420   for (unsigned i = 0; i < MI.getNumOperands(); i++) {
421     const MCOperand &Op = MI.getOperand(i);
422     if (&Op == &MO)
423       return i;
424   }
425   llvm_unreachable("This operand is not part of this instruction");
426   return ~0U; // Silence any warnings about no return.
427 }
428 
429 uint64_t PPCMCCodeEmitter::
430 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
431                   SmallVectorImpl<MCFixup> &Fixups,
432                   const MCSubtargetInfo &STI) const {
433   if (MO.isReg()) {
434     // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
435     // The GPR operand should come through here though.
436     assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
437             MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
438            MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
439     unsigned OpNo = getOpIdxForMO(MI, MO);
440     unsigned Reg =
441       PPCInstrInfo::getRegNumForOperand(MCII.get(MI.getOpcode()),
442                                         MO.getReg(), OpNo);
443     return CTX.getRegisterInfo()->getEncodingValue(Reg);
444   }
445 
446   assert(MO.isImm() &&
447          "Relocation required in an instruction that we cannot encode!");
448   return MO.getImm();
449 }
450 
451 void PPCMCCodeEmitter::encodeInstruction(
452     const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
453     const MCSubtargetInfo &STI) const {
454   verifyInstructionPredicates(MI,
455                               computeAvailableFeatures(STI.getFeatureBits()));
456 
457   uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
458 
459   // Output the constant in big/little endian byte order.
460   unsigned Size = getInstSizeInBytes(MI);
461   support::endianness E = IsLittleEndian ? support::little : support::big;
462   switch (Size) {
463   case 0:
464     break;
465   case 4:
466     support::endian::write<uint32_t>(OS, Bits, E);
467     break;
468   case 8:
469     // If we emit a pair of instructions, the first one is
470     // always in the top 32 bits, even on little-endian.
471     support::endian::write<uint32_t>(OS, Bits >> 32, E);
472     support::endian::write<uint32_t>(OS, Bits, E);
473     break;
474   default:
475     llvm_unreachable("Invalid instruction size");
476   }
477 
478   ++MCNumEmitted; // Keep track of the # of mi's emitted.
479 }
480 
481 // Get the number of bytes used to encode the given MCInst.
482 unsigned PPCMCCodeEmitter::getInstSizeInBytes(const MCInst &MI) const {
483   unsigned Opcode = MI.getOpcode();
484   const MCInstrDesc &Desc = MCII.get(Opcode);
485   return Desc.getSize();
486 }
487 
488 bool PPCMCCodeEmitter::isPrefixedInstruction(const MCInst &MI) const {
489   unsigned Opcode = MI.getOpcode();
490   const PPCInstrInfo *InstrInfo = static_cast<const PPCInstrInfo*>(&MCII);
491   return InstrInfo->isPrefixed(Opcode);
492 }
493 
494 #define ENABLE_INSTR_PREDICATE_VERIFIER
495 #include "PPCGenMCCodeEmitter.inc"
496