10b57cec5SDimitry Andric //===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===//
20b57cec5SDimitry Andric //
30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric //
70b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric //
90b57cec5SDimitry Andric // This file provides PowerPC specific target descriptions.
100b57cec5SDimitry Andric //
110b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
120b57cec5SDimitry Andric
130b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
140b57cec5SDimitry Andric #define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
150b57cec5SDimitry Andric
160b57cec5SDimitry Andric // GCC #defines PPC on Linux but we use it as our namespace name
170b57cec5SDimitry Andric #undef PPC
180b57cec5SDimitry Andric
190b57cec5SDimitry Andric #include "llvm/MC/MCRegisterInfo.h"
200b57cec5SDimitry Andric #include "llvm/Support/MathExtras.h"
210b57cec5SDimitry Andric #include <cstdint>
220b57cec5SDimitry Andric #include <memory>
230b57cec5SDimitry Andric
240b57cec5SDimitry Andric namespace llvm {
250b57cec5SDimitry Andric
260b57cec5SDimitry Andric class MCAsmBackend;
270b57cec5SDimitry Andric class MCCodeEmitter;
280b57cec5SDimitry Andric class MCContext;
295f757f3fSDimitry Andric class MCInstrDesc;
300b57cec5SDimitry Andric class MCInstrInfo;
310b57cec5SDimitry Andric class MCObjectTargetWriter;
320b57cec5SDimitry Andric class MCRegisterInfo;
330b57cec5SDimitry Andric class MCSubtargetInfo;
340b57cec5SDimitry Andric class MCTargetOptions;
350b57cec5SDimitry Andric class Target;
360b57cec5SDimitry Andric
375f757f3fSDimitry Andric namespace PPC {
385f757f3fSDimitry Andric /// stripRegisterPrefix - This method strips the character prefix from a
395f757f3fSDimitry Andric /// register name so that only the number is left. Used by for linux asm.
405f757f3fSDimitry Andric const char *stripRegisterPrefix(const char *RegName);
415f757f3fSDimitry Andric
425f757f3fSDimitry Andric /// getRegNumForOperand - some operands use different numbering schemes
435f757f3fSDimitry Andric /// for the same registers. For example, a VSX instruction may have any of
445f757f3fSDimitry Andric /// vs0-vs63 allocated whereas an Altivec instruction could only have
455f757f3fSDimitry Andric /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
465f757f3fSDimitry Andric /// register number needed for the opcode/operand number combination.
475f757f3fSDimitry Andric /// The operand number argument will be useful when we need to extend this
485f757f3fSDimitry Andric /// to instructions that use both Altivec and VSX numbering (for different
495f757f3fSDimitry Andric /// operands).
505f757f3fSDimitry Andric unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg,
515f757f3fSDimitry Andric unsigned OpNo);
525f757f3fSDimitry Andric
535f757f3fSDimitry Andric } // namespace PPC
545f757f3fSDimitry Andric
550b57cec5SDimitry Andric MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
560b57cec5SDimitry Andric MCContext &Ctx);
570b57cec5SDimitry Andric
580b57cec5SDimitry Andric MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI,
590b57cec5SDimitry Andric const MCRegisterInfo &MRI,
600b57cec5SDimitry Andric const MCTargetOptions &Options);
610b57cec5SDimitry Andric
620b57cec5SDimitry Andric /// Construct an PPC ELF object writer.
630b57cec5SDimitry Andric std::unique_ptr<MCObjectTargetWriter> createPPCELFObjectWriter(bool Is64Bit,
640b57cec5SDimitry Andric uint8_t OSABI);
650b57cec5SDimitry Andric /// Construct a PPC Mach-O object writer.
660b57cec5SDimitry Andric std::unique_ptr<MCObjectTargetWriter>
670b57cec5SDimitry Andric createPPCMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype);
680b57cec5SDimitry Andric
690b57cec5SDimitry Andric /// Construct a PPC XCOFF object writer.
700b57cec5SDimitry Andric std::unique_ptr<MCObjectTargetWriter> createPPCXCOFFObjectWriter(bool Is64Bit);
710b57cec5SDimitry Andric
720b57cec5SDimitry Andric /// Returns true iff Val consists of one contiguous run of 1s with any number of
730b57cec5SDimitry Andric /// 0s on either side. The 1s are allowed to wrap from LSB to MSB, so
740b57cec5SDimitry Andric /// 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is not,
750b57cec5SDimitry Andric /// since all 1s are not contiguous.
isRunOfOnes(unsigned Val,unsigned & MB,unsigned & ME)760b57cec5SDimitry Andric static inline bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
770b57cec5SDimitry Andric if (!Val)
780b57cec5SDimitry Andric return false;
790b57cec5SDimitry Andric
800b57cec5SDimitry Andric if (isShiftedMask_32(Val)) {
810b57cec5SDimitry Andric // look for the first non-zero bit
8206c3fb27SDimitry Andric MB = llvm::countl_zero(Val);
830b57cec5SDimitry Andric // look for the first zero bit after the run of ones
8406c3fb27SDimitry Andric ME = llvm::countl_zero((Val - 1) ^ Val);
850b57cec5SDimitry Andric return true;
860b57cec5SDimitry Andric } else {
870b57cec5SDimitry Andric Val = ~Val; // invert mask
880b57cec5SDimitry Andric if (isShiftedMask_32(Val)) {
890b57cec5SDimitry Andric // effectively look for the first zero bit
9006c3fb27SDimitry Andric ME = llvm::countl_zero(Val) - 1;
910b57cec5SDimitry Andric // effectively look for the first one bit after the run of zeros
9206c3fb27SDimitry Andric MB = llvm::countl_zero((Val - 1) ^ Val) + 1;
930b57cec5SDimitry Andric return true;
940b57cec5SDimitry Andric }
950b57cec5SDimitry Andric }
960b57cec5SDimitry Andric // no run present
970b57cec5SDimitry Andric return false;
980b57cec5SDimitry Andric }
990b57cec5SDimitry Andric
isRunOfOnes64(uint64_t Val,unsigned & MB,unsigned & ME)100480093f4SDimitry Andric static inline bool isRunOfOnes64(uint64_t Val, unsigned &MB, unsigned &ME) {
101480093f4SDimitry Andric if (!Val)
102480093f4SDimitry Andric return false;
103480093f4SDimitry Andric
104480093f4SDimitry Andric if (isShiftedMask_64(Val)) {
105480093f4SDimitry Andric // look for the first non-zero bit
10606c3fb27SDimitry Andric MB = llvm::countl_zero(Val);
107480093f4SDimitry Andric // look for the first zero bit after the run of ones
10806c3fb27SDimitry Andric ME = llvm::countl_zero((Val - 1) ^ Val);
109480093f4SDimitry Andric return true;
110480093f4SDimitry Andric } else {
111480093f4SDimitry Andric Val = ~Val; // invert mask
112480093f4SDimitry Andric if (isShiftedMask_64(Val)) {
113480093f4SDimitry Andric // effectively look for the first zero bit
11406c3fb27SDimitry Andric ME = llvm::countl_zero(Val) - 1;
115480093f4SDimitry Andric // effectively look for the first one bit after the run of zeros
11606c3fb27SDimitry Andric MB = llvm::countl_zero((Val - 1) ^ Val) + 1;
117480093f4SDimitry Andric return true;
118480093f4SDimitry Andric }
119480093f4SDimitry Andric }
120480093f4SDimitry Andric // no run present
121480093f4SDimitry Andric return false;
122480093f4SDimitry Andric }
123480093f4SDimitry Andric
1245f757f3fSDimitry Andric /// PPCII - This namespace holds all of the PowerPC target-specific
1255f757f3fSDimitry Andric /// per-instruction flags. These must match the corresponding definitions in
1265f757f3fSDimitry Andric /// PPC.td and PPCInstrFormats.td.
1275f757f3fSDimitry Andric namespace PPCII {
1285f757f3fSDimitry Andric enum {
1295f757f3fSDimitry Andric // PPC970 Instruction Flags. These flags describe the characteristics of the
1305f757f3fSDimitry Andric // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
1315f757f3fSDimitry Andric // raw machine instructions.
1320b57cec5SDimitry Andric
1335f757f3fSDimitry Andric /// PPC970_First - This instruction starts a new dispatch group, so it will
1345f757f3fSDimitry Andric /// always be the first one in the group.
1355f757f3fSDimitry Andric PPC970_First = 0x1,
1365f757f3fSDimitry Andric
1375f757f3fSDimitry Andric /// PPC970_Single - This instruction starts a new dispatch group and
1385f757f3fSDimitry Andric /// terminates it, so it will be the sole instruction in the group.
1395f757f3fSDimitry Andric PPC970_Single = 0x2,
1405f757f3fSDimitry Andric
1415f757f3fSDimitry Andric /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
1425f757f3fSDimitry Andric /// two dispatch pipes to be available to issue.
1435f757f3fSDimitry Andric PPC970_Cracked = 0x4,
1445f757f3fSDimitry Andric
1455f757f3fSDimitry Andric /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
1465f757f3fSDimitry Andric /// an instruction is issued to.
1475f757f3fSDimitry Andric PPC970_Shift = 3,
1485f757f3fSDimitry Andric PPC970_Mask = 0x07 << PPC970_Shift
1495f757f3fSDimitry Andric };
1505f757f3fSDimitry Andric enum PPC970_Unit {
1515f757f3fSDimitry Andric /// These are the various PPC970 execution unit pipelines. Each instruction
1525f757f3fSDimitry Andric /// is one of these.
1535f757f3fSDimitry Andric PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
1545f757f3fSDimitry Andric PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
1555f757f3fSDimitry Andric PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
1565f757f3fSDimitry Andric PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
1575f757f3fSDimitry Andric PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
1585f757f3fSDimitry Andric PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
1595f757f3fSDimitry Andric PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
1605f757f3fSDimitry Andric PPC970_BRU = 7 << PPC970_Shift // Branch Unit
1615f757f3fSDimitry Andric };
1625f757f3fSDimitry Andric
1635f757f3fSDimitry Andric enum {
1645f757f3fSDimitry Andric /// Shift count to bypass PPC970 flags
1655f757f3fSDimitry Andric NewDef_Shift = 6,
1665f757f3fSDimitry Andric
1675f757f3fSDimitry Andric /// This instruction is an X-Form memory operation.
1685f757f3fSDimitry Andric XFormMemOp = 0x1 << NewDef_Shift,
1695f757f3fSDimitry Andric /// This instruction is prefixed.
1705f757f3fSDimitry Andric Prefixed = 0x1 << (NewDef_Shift + 1),
1715f757f3fSDimitry Andric /// This instruction produced a sign extended result.
1725f757f3fSDimitry Andric SExt32To64 = 0x1 << (NewDef_Shift + 2),
1735f757f3fSDimitry Andric /// This instruction produced a zero extended result.
1745f757f3fSDimitry Andric ZExt32To64 = 0x1 << (NewDef_Shift + 3)
1755f757f3fSDimitry Andric };
1765f757f3fSDimitry Andric } // end namespace PPCII
1775f757f3fSDimitry Andric
1785f757f3fSDimitry Andric } // end namespace llvm
1790b57cec5SDimitry Andric
1800b57cec5SDimitry Andric // Defines symbolic names for PowerPC registers. This defines a mapping from
1810b57cec5SDimitry Andric // register name to register number.
1820b57cec5SDimitry Andric //
1830b57cec5SDimitry Andric #define GET_REGINFO_ENUM
1840b57cec5SDimitry Andric #include "PPCGenRegisterInfo.inc"
1850b57cec5SDimitry Andric
1860b57cec5SDimitry Andric // Defines symbolic names for the PowerPC instructions.
1870b57cec5SDimitry Andric //
1880b57cec5SDimitry Andric #define GET_INSTRINFO_ENUM
1890b57cec5SDimitry Andric #define GET_INSTRINFO_SCHED_ENUM
190753f127fSDimitry Andric #define GET_INSTRINFO_MC_HELPER_DECLS
1910b57cec5SDimitry Andric #include "PPCGenInstrInfo.inc"
1920b57cec5SDimitry Andric
1930b57cec5SDimitry Andric #define GET_SUBTARGETINFO_ENUM
1940b57cec5SDimitry Andric #include "PPCGenSubtargetInfo.inc"
1950b57cec5SDimitry Andric
196e8d8bef9SDimitry Andric #define PPC_REGS0_7(X) \
197e8d8bef9SDimitry Andric { \
198e8d8bef9SDimitry Andric X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
199e8d8bef9SDimitry Andric }
200e8d8bef9SDimitry Andric
2010b57cec5SDimitry Andric #define PPC_REGS0_31(X) \
2020b57cec5SDimitry Andric { \
2030b57cec5SDimitry Andric X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
2040b57cec5SDimitry Andric X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
2050b57cec5SDimitry Andric X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
2060b57cec5SDimitry Andric }
2070b57cec5SDimitry Andric
20806c3fb27SDimitry Andric #define PPC_REGS_EVEN0_30(X) \
20906c3fb27SDimitry Andric { \
21006c3fb27SDimitry Andric X##0, X##2, X##4, X##6, X##8, X##10, X##12, X##14, X##16, X##18, X##20, \
21106c3fb27SDimitry Andric X##22, X##24, X##26, X##28, X##30 \
21206c3fb27SDimitry Andric }
21306c3fb27SDimitry Andric
214bdd1243dSDimitry Andric #define PPC_REGS0_63(X) \
215bdd1243dSDimitry Andric { \
216bdd1243dSDimitry Andric X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
217bdd1243dSDimitry Andric X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
218bdd1243dSDimitry Andric X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31, \
219bdd1243dSDimitry Andric X##32, X##33, X##34, X##35, X##36, X##37, X##38, X##39, X##40, X##41, \
220bdd1243dSDimitry Andric X##42, X##43, X##44, X##45, X##46, X##47, X##48, X##49, X##50, X##51, \
221bdd1243dSDimitry Andric X##52, X##53, X##54, X##55, X##56, X##57, X##58, X##59, X##60, X##61, \
222bdd1243dSDimitry Andric X##62, X##63 \
223bdd1243dSDimitry Andric }
224bdd1243dSDimitry Andric
2250b57cec5SDimitry Andric #define PPC_REGS_NO0_31(Z, X) \
2260b57cec5SDimitry Andric { \
2270b57cec5SDimitry Andric Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
2280b57cec5SDimitry Andric X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
2290b57cec5SDimitry Andric X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
2300b57cec5SDimitry Andric }
2310b57cec5SDimitry Andric
2320b57cec5SDimitry Andric #define PPC_REGS_LO_HI(LO, HI) \
2330b57cec5SDimitry Andric { \
2340b57cec5SDimitry Andric LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, LO##9, \
2350b57cec5SDimitry Andric LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, LO##16, LO##17, \
2360b57cec5SDimitry Andric LO##18, LO##19, LO##20, LO##21, LO##22, LO##23, LO##24, LO##25, \
2370b57cec5SDimitry Andric LO##26, LO##27, LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \
2380b57cec5SDimitry Andric HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, HI##10, HI##11, \
2390b57cec5SDimitry Andric HI##12, HI##13, HI##14, HI##15, HI##16, HI##17, HI##18, HI##19, \
2400b57cec5SDimitry Andric HI##20, HI##21, HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \
2410b57cec5SDimitry Andric HI##28, HI##29, HI##30, HI##31 \
2420b57cec5SDimitry Andric }
2430b57cec5SDimitry Andric
244bdd1243dSDimitry Andric #define PPC_REGS0_7(X) \
245bdd1243dSDimitry Andric { \
246bdd1243dSDimitry Andric X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
247bdd1243dSDimitry Andric }
248bdd1243dSDimitry Andric
249bdd1243dSDimitry Andric #define PPC_REGS0_3(X) \
250bdd1243dSDimitry Andric { \
251bdd1243dSDimitry Andric X##0, X##1, X##2, X##3 \
252bdd1243dSDimitry Andric }
253bdd1243dSDimitry Andric
2540b57cec5SDimitry Andric using llvm::MCPhysReg;
2550b57cec5SDimitry Andric
2560b57cec5SDimitry Andric #define DEFINE_PPC_REGCLASSES \
2570b57cec5SDimitry Andric static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
2580b57cec5SDimitry Andric static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
2590b57cec5SDimitry Andric static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
26006c3fb27SDimitry Andric static const MCPhysReg FpRegs[16] = PPC_REGS_EVEN0_30(PPC::Fpair); \
261e8d8bef9SDimitry Andric static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \
2620b57cec5SDimitry Andric static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
2630b57cec5SDimitry Andric static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \
2640b57cec5SDimitry Andric static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
26506c3fb27SDimitry Andric static const MCPhysReg RRegsNoR0[32] = PPC_REGS_NO0_31(PPC::ZERO, PPC::R); \
26606c3fb27SDimitry Andric static const MCPhysReg XRegsNoX0[32] = PPC_REGS_NO0_31(PPC::ZERO8, PPC::X); \
26706c3fb27SDimitry Andric static const MCPhysReg VSRegs[64] = PPC_REGS_LO_HI(PPC::VSL, PPC::V); \
26806c3fb27SDimitry Andric static const MCPhysReg VSFRegs[64] = PPC_REGS_LO_HI(PPC::F, PPC::VF); \
26906c3fb27SDimitry Andric static const MCPhysReg VSSRegs[64] = PPC_REGS_LO_HI(PPC::F, PPC::VF); \
2700b57cec5SDimitry Andric static const MCPhysReg CRBITRegs[32] = { \
27106c3fb27SDimitry Andric PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, PPC::CR1LT, PPC::CR1GT, \
27206c3fb27SDimitry Andric PPC::CR1EQ, PPC::CR1UN, PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, \
27306c3fb27SDimitry Andric PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, PPC::CR4LT, PPC::CR4GT, \
27406c3fb27SDimitry Andric PPC::CR4EQ, PPC::CR4UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, \
27506c3fb27SDimitry Andric PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, \
27606c3fb27SDimitry Andric PPC::CR7EQ, PPC::CR7UN}; \
277e8d8bef9SDimitry Andric static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC::CR); \
278bdd1243dSDimitry Andric static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC::ACC); \
279bdd1243dSDimitry Andric static const MCPhysReg WACCRegs[8] = PPC_REGS0_7(PPC::WACC); \
280bdd1243dSDimitry Andric static const MCPhysReg WACC_HIRegs[8] = PPC_REGS0_7(PPC::WACC_HI); \
281bdd1243dSDimitry Andric static const MCPhysReg DMRROWpRegs[32] = PPC_REGS0_31(PPC::DMRROWp); \
282bdd1243dSDimitry Andric static const MCPhysReg DMRROWRegs[64] = PPC_REGS0_63(PPC::DMRROW); \
283bdd1243dSDimitry Andric static const MCPhysReg DMRRegs[8] = PPC_REGS0_7(PPC::DMR); \
284bdd1243dSDimitry Andric static const MCPhysReg DMRpRegs[4] = PPC_REGS0_3(PPC::DMRp);
285bdd1243dSDimitry Andric
2865f757f3fSDimitry Andric namespace llvm {
2875f757f3fSDimitry Andric namespace PPC {
isVFRegister(unsigned Reg)2885f757f3fSDimitry Andric static inline bool isVFRegister(unsigned Reg) {
2895f757f3fSDimitry Andric return Reg >= PPC::VF0 && Reg <= PPC::VF31;
2905f757f3fSDimitry Andric }
2915f757f3fSDimitry Andric
isVRRegister(unsigned Reg)2925f757f3fSDimitry Andric static inline bool isVRRegister(unsigned Reg) {
2935f757f3fSDimitry Andric return Reg >= PPC::V0 && Reg <= PPC::V31;
2945f757f3fSDimitry Andric }
2955f757f3fSDimitry Andric } // namespace PPC
2965f757f3fSDimitry Andric } // namespace llvm
2975f757f3fSDimitry Andric
2980b57cec5SDimitry Andric #endif // LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
299