10b57cec5SDimitry Andric//===- P9InstrResources.td - P9 Instruction Resource Defs -*- tablegen -*-==// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file defines the resources required by P9 instructions. This is part of 100b57cec5SDimitry Andric// the P9 processor model used for instruction scheduling. This file should 110b57cec5SDimitry Andric// contain all the instructions that may be used on Power 9. This is not 120b57cec5SDimitry Andric// just instructions that are new on Power 9 but also instructions that were 130b57cec5SDimitry Andric// available on earlier architectures and are still used in Power 9. 140b57cec5SDimitry Andric// 150b57cec5SDimitry Andric// The makeup of the P9 CPU is modeled as follows: 160b57cec5SDimitry Andric// - Each CPU is made up of two superslices. 170b57cec5SDimitry Andric// - Each superslice is made up of two slices. Therefore, there are 4 slices 180b57cec5SDimitry Andric// for each CPU. 190b57cec5SDimitry Andric// - Up to 6 instructions can be dispatched to each CPU. Three per superslice. 200b57cec5SDimitry Andric// - Each CPU has: 210b57cec5SDimitry Andric// - One CY (Crypto) unit P9_CY_* 220b57cec5SDimitry Andric// - One DFU (Decimal Floating Point and Quad Precision) unit P9_DFU_* 230b57cec5SDimitry Andric// - Two PM (Permute) units. One on each superslice. P9_PM_* 240b57cec5SDimitry Andric// - Two DIV (Fixed Point Divide) units. One on each superslize. P9_DIV_* 250b57cec5SDimitry Andric// - Four ALU (Fixed Point Arithmetic) units. One on each slice. P9_ALU_* 260b57cec5SDimitry Andric// - Four DP (Floating Point) units. One on each slice. P9_DP_* 270b57cec5SDimitry Andric// This also includes fixed point multiply add. 280b57cec5SDimitry Andric// - Four AGEN (Address Generation) units. One for each slice. P9_AGEN_* 290b57cec5SDimitry Andric// - Four Load/Store Queues. P9_LS_* 300b57cec5SDimitry Andric// - Each set of instructions will require a number of these resources. 310b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 320b57cec5SDimitry Andric 330b57cec5SDimitry Andric// Two cycle ALU vector operation that uses an entire superslice. 340b57cec5SDimitry Andric// Uses both ALU units (the even ALUE and odd ALUO units), two pipelines 350b57cec5SDimitry Andric// (EXECE, EXECO) and 1 dispatch (DISP) to the given superslice. 360b57cec5SDimitry Andricdef : InstRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C], 370b57cec5SDimitry Andric (instrs 380b57cec5SDimitry Andric (instregex "VADDU(B|H|W|D)M$"), 390b57cec5SDimitry Andric (instregex "VAND(C)?$"), 400b57cec5SDimitry Andric (instregex "VEXTS(B|H|W)2(D|W)(s)?$"), 410b57cec5SDimitry Andric (instregex "V_SET0(B|H)?$"), 420b57cec5SDimitry Andric (instregex "VS(R|L)(B|H|W|D)$"), 430b57cec5SDimitry Andric (instregex "VSUBU(B|H|W|D)M$"), 440b57cec5SDimitry Andric (instregex "VPOPCNT(B|H)$"), 450b57cec5SDimitry Andric (instregex "VRL(B|H|W|D)$"), 460b57cec5SDimitry Andric (instregex "VSRA(B|H|W|D)$"), 470b57cec5SDimitry Andric (instregex "XV(N)?ABS(D|S)P$"), 480b57cec5SDimitry Andric (instregex "XVCPSGN(D|S)P$"), 490b57cec5SDimitry Andric (instregex "XV(I|X)EXP(D|S)P$"), 500b57cec5SDimitry Andric (instregex "VRL(D|W)(MI|NM)$"), 510b57cec5SDimitry Andric (instregex "VMRG(E|O)W$"), 520b57cec5SDimitry Andric MTVSRDD, 530b57cec5SDimitry Andric VEQV, 540b57cec5SDimitry Andric VNAND, 550b57cec5SDimitry Andric VNEGD, 560b57cec5SDimitry Andric VNEGW, 570b57cec5SDimitry Andric VNOR, 580b57cec5SDimitry Andric VOR, 590b57cec5SDimitry Andric VORC, 600b57cec5SDimitry Andric VSEL, 610b57cec5SDimitry Andric VXOR, 620b57cec5SDimitry Andric XVNEGDP, 630b57cec5SDimitry Andric XVNEGSP, 640b57cec5SDimitry Andric XXLAND, 650b57cec5SDimitry Andric XXLANDC, 660b57cec5SDimitry Andric XXLEQV, 678bcb0991SDimitry Andric XXLEQVOnes, 680b57cec5SDimitry Andric XXLNAND, 690b57cec5SDimitry Andric XXLNOR, 700b57cec5SDimitry Andric XXLOR, 710b57cec5SDimitry Andric XXLORf, 720b57cec5SDimitry Andric XXLORC, 730b57cec5SDimitry Andric XXLXOR, 740b57cec5SDimitry Andric XXLXORdpz, 750b57cec5SDimitry Andric XXLXORspz, 760b57cec5SDimitry Andric XXLXORz, 770b57cec5SDimitry Andric XXSEL, 780b57cec5SDimitry Andric XSABSQP, 790b57cec5SDimitry Andric XSCPSGNQP, 800b57cec5SDimitry Andric XSIEXPQP, 810b57cec5SDimitry Andric XSNABSQP, 820b57cec5SDimitry Andric XSNEGQP, 830b57cec5SDimitry Andric XSXEXPQP 840b57cec5SDimitry Andric)>; 850b57cec5SDimitry Andric 860b57cec5SDimitry Andric// Restricted Dispatch ALU operation for 3 cycles. The operation runs on a 870b57cec5SDimitry Andric// single slice. However, since it is Restricted, it requires all 3 dispatches 880b57cec5SDimitry Andric// (DISP) for that superslice. 890b57cec5SDimitry Andricdef : InstRW<[P9_ALU_3C, IP_EXEC_1C, DISP_3SLOTS_1C], 900b57cec5SDimitry Andric (instrs 910b57cec5SDimitry Andric (instregex "TABORT(D|W)C(I)?$"), 920b57cec5SDimitry Andric (instregex "MTFSB(0|1)$"), 930b57cec5SDimitry Andric (instregex "MFFSC(D)?RN(I)?$"), 940b57cec5SDimitry Andric (instregex "CMPRB(8)?$"), 950b57cec5SDimitry Andric (instregex "TD(I)?$"), 960b57cec5SDimitry Andric (instregex "TW(I)?$"), 97e8d8bef9SDimitry Andric (instregex "FCMP(O|U)(S|D)$"), 980b57cec5SDimitry Andric (instregex "XSTSTDC(S|D)P$"), 990b57cec5SDimitry Andric FTDIV, 1000b57cec5SDimitry Andric FTSQRT, 1010b57cec5SDimitry Andric CMPEQB 1020b57cec5SDimitry Andric)>; 1030b57cec5SDimitry Andric 1040b57cec5SDimitry Andric// Standard Dispatch ALU operation for 3 cycles. Only one slice used. 1050b57cec5SDimitry Andricdef : InstRW<[P9_ALU_3C, IP_EXEC_1C, DISP_1C], 1060b57cec5SDimitry Andric (instrs 1070b57cec5SDimitry Andric (instregex "XSMAX(C|J)?DP$"), 1080b57cec5SDimitry Andric (instregex "XSMIN(C|J)?DP$"), 1090b57cec5SDimitry Andric (instregex "XSCMP(EQ|EXP|GE|GT|O|U)DP$"), 110480093f4SDimitry Andric (instregex "CNT(L|T)Z(D|W)(8)?(_rec)?$"), 1110b57cec5SDimitry Andric (instregex "POPCNT(D|W)$"), 1120b57cec5SDimitry Andric (instregex "CMPB(8)?$"), 1130b57cec5SDimitry Andric (instregex "SETB(8)?$"), 1140b57cec5SDimitry Andric XSTDIVDP, 1150b57cec5SDimitry Andric XSTSQRTDP, 1160b57cec5SDimitry Andric XSXSIGDP, 1170b57cec5SDimitry Andric XSCVSPDPN, 1180b57cec5SDimitry Andric BPERMD 1190b57cec5SDimitry Andric)>; 1200b57cec5SDimitry Andric 1210b57cec5SDimitry Andric// Standard Dispatch ALU operation for 2 cycles. Only one slice used. 1220b57cec5SDimitry Andricdef : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C], 1230b57cec5SDimitry Andric (instrs 1240b57cec5SDimitry Andric (instregex "S(L|R)D$"), 1250b57cec5SDimitry Andric (instregex "SRAD(I)?$"), 1260b57cec5SDimitry Andric (instregex "EXTSWSLI_32_64$"), 1270b57cec5SDimitry Andric (instregex "MFV(S)?RD$"), 1288bcb0991SDimitry Andric (instregex "MTV(S)?RD$"), 1298bcb0991SDimitry Andric (instregex "MTV(S)?RW(A|Z)$"), 1300b57cec5SDimitry Andric (instregex "CMP(WI|LWI|W|LW)(8)?$"), 1310b57cec5SDimitry Andric (instregex "CMP(L)?D(I)?$"), 132c14a5a88SDimitry Andric (instregex "SUBF(I)?C(8)?(O)?$"), 133480093f4SDimitry Andric (instregex "ANDI(S)?(8)?(_rec)?$"), 134c14a5a88SDimitry Andric (instregex "ADDC(8)?(O)?$"), 135480093f4SDimitry Andric (instregex "ADDIC(8)?(_rec)?$"), 136480093f4SDimitry Andric (instregex "ADD(8|4)(O)?(_rec)?$"), 137480093f4SDimitry Andric (instregex "ADD(E|ME|ZE)(8)?(O)?(_rec)?$"), 138480093f4SDimitry Andric (instregex "SUBF(E|ME|ZE)?(8)?(O)?(_rec)?$"), 139480093f4SDimitry Andric (instregex "NEG(8)?(O)?(_rec)?$"), 1400b57cec5SDimitry Andric (instregex "POPCNTB$"), 141fe6060f1SDimitry Andric (instregex "POPCNTB8$"), 1420b57cec5SDimitry Andric (instregex "ADD(I|IS)?(8)?$"), 1430b57cec5SDimitry Andric (instregex "LI(S)?(8)?$"), 144480093f4SDimitry Andric (instregex "(X)?OR(I|IS)?(8)?(_rec)?$"), 145480093f4SDimitry Andric (instregex "NAND(8)?(_rec)?$"), 146480093f4SDimitry Andric (instregex "AND(C)?(8)?(_rec)?$"), 147480093f4SDimitry Andric (instregex "NOR(8)?(_rec)?$"), 148480093f4SDimitry Andric (instregex "OR(C)?(8)?(_rec)?$"), 149480093f4SDimitry Andric (instregex "EQV(8)?(_rec)?$"), 150480093f4SDimitry Andric (instregex "EXTS(B|H|W)(8)?(_32)?(_64)?(_rec)?$"), 1510b57cec5SDimitry Andric (instregex "ADD(4|8)(TLS)?(_)?$"), 152c14a5a88SDimitry Andric (instregex "NEG(8)?(O)?$"), 1538bcb0991SDimitry Andric (instregex "ADDI(S)?toc(HA|L)(8)?$"), 1544824e7fdSDimitry Andric (instregex "LA(8)?$"), 1550b57cec5SDimitry Andric COPY, 1560b57cec5SDimitry Andric MCRF, 1570b57cec5SDimitry Andric MCRXRX, 1580b57cec5SDimitry Andric XSNABSDP, 15981ad6265SDimitry Andric XSNABSDPs, 1600b57cec5SDimitry Andric XSXEXPDP, 1610b57cec5SDimitry Andric XSABSDP, 1620b57cec5SDimitry Andric XSNEGDP, 1630b57cec5SDimitry Andric XSCPSGNDP, 1640b57cec5SDimitry Andric MFVSRWZ, 1658bcb0991SDimitry Andric MFVRWZ, 1660b57cec5SDimitry Andric EXTSWSLI, 1670b57cec5SDimitry Andric SRADI_32, 1680b57cec5SDimitry Andric RLDIC, 1690b57cec5SDimitry Andric RFEBB, 1700b57cec5SDimitry Andric TBEGIN, 1710b57cec5SDimitry Andric TRECHKPT, 1720b57cec5SDimitry Andric NOP, 1730b57cec5SDimitry Andric WAIT 1740b57cec5SDimitry Andric)>; 1750b57cec5SDimitry Andric 1760b57cec5SDimitry Andric// Restricted Dispatch ALU operation for 2 cycles. The operation runs on a 1770b57cec5SDimitry Andric// single slice. However, since it is Restricted, it requires all 3 dispatches 1780b57cec5SDimitry Andric// (DISP) for that superslice. 1790b57cec5SDimitry Andricdef : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_3SLOTS_1C], 1800b57cec5SDimitry Andric (instrs 1810b57cec5SDimitry Andric (instregex "RLDC(L|R)$"), 1820b57cec5SDimitry Andric (instregex "RLWIMI(8)?$"), 1830b57cec5SDimitry Andric (instregex "RLDIC(L|R)(_32)?(_64)?$"), 1840b57cec5SDimitry Andric (instregex "M(F|T)OCRF(8)?$"), 1850b57cec5SDimitry Andric (instregex "CR(6)?(UN)?SET$"), 1860b57cec5SDimitry Andric (instregex "CR(N)?(OR|AND)(C)?$"), 1870b57cec5SDimitry Andric (instregex "S(L|R)W(8)?$"), 1880b57cec5SDimitry Andric (instregex "RLW(INM|NM)(8)?$"), 1890b57cec5SDimitry Andric (instregex "F(N)?ABS(D|S)$"), 1900b57cec5SDimitry Andric (instregex "FNEG(D|S)$"), 1910b57cec5SDimitry Andric (instregex "FCPSGN(D|S)$"), 1920b57cec5SDimitry Andric (instregex "SRAW(I)?$"), 1930b57cec5SDimitry Andric (instregex "ISEL(8)?$"), 1940b57cec5SDimitry Andric RLDIMI, 1950b57cec5SDimitry Andric XSIEXPDP, 1960b57cec5SDimitry Andric FMR, 1970b57cec5SDimitry Andric CREQV, 198bdd1243dSDimitry Andric CRNOT, 1990b57cec5SDimitry Andric CRXOR, 2000b57cec5SDimitry Andric TRECLAIM, 2010b57cec5SDimitry Andric TSR, 2020b57cec5SDimitry Andric TABORT 2030b57cec5SDimitry Andric)>; 2040b57cec5SDimitry Andric 2050b57cec5SDimitry Andric// Three cycle ALU vector operation that uses an entire superslice. 2060b57cec5SDimitry Andric// Uses both ALU units (the even ALUE and odd ALUO units), two pipelines 2070b57cec5SDimitry Andric// (EXECE, EXECO) and 1 dispatch (DISP) to the given superslice. 2080b57cec5SDimitry Andricdef : InstRW<[P9_ALUE_3C, P9_ALUO_3C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C], 2090b57cec5SDimitry Andric (instrs 2100b57cec5SDimitry Andric (instregex "M(T|F)VSCR$"), 2110b57cec5SDimitry Andric (instregex "VCMPNEZ(B|H|W)$"), 2120b57cec5SDimitry Andric (instregex "VCMPEQU(B|H|W|D)$"), 2130b57cec5SDimitry Andric (instregex "VCMPNE(B|H|W)$"), 2140b57cec5SDimitry Andric (instregex "VABSDU(B|H|W)$"), 2150b57cec5SDimitry Andric (instregex "VADDU(B|H|W)S$"), 2160b57cec5SDimitry Andric (instregex "VAVG(S|U)(B|H|W)$"), 217480093f4SDimitry Andric (instregex "VCMP(EQ|GE|GT)FP(_rec)?$"), 218480093f4SDimitry Andric (instregex "VCMPBFP(_rec)?$"), 2190b57cec5SDimitry Andric (instregex "VC(L|T)Z(B|H|W|D)$"), 2200b57cec5SDimitry Andric (instregex "VADDS(B|H|W)S$"), 2210b57cec5SDimitry Andric (instregex "V(MIN|MAX)FP$"), 2220b57cec5SDimitry Andric (instregex "V(MIN|MAX)(S|U)(B|H|W|D)$"), 2230b57cec5SDimitry Andric VBPERMD, 2240b57cec5SDimitry Andric VADDCUW, 2250b57cec5SDimitry Andric VPOPCNTW, 2260b57cec5SDimitry Andric VPOPCNTD, 2270b57cec5SDimitry Andric VPRTYBD, 2280b57cec5SDimitry Andric VPRTYBW, 2290b57cec5SDimitry Andric VSHASIGMAD, 2300b57cec5SDimitry Andric VSHASIGMAW, 2310b57cec5SDimitry Andric VSUBSBS, 2320b57cec5SDimitry Andric VSUBSHS, 2330b57cec5SDimitry Andric VSUBSWS, 2340b57cec5SDimitry Andric VSUBUBS, 2350b57cec5SDimitry Andric VSUBUHS, 2360b57cec5SDimitry Andric VSUBUWS, 2370b57cec5SDimitry Andric VSUBCUW, 2380b57cec5SDimitry Andric VCMPGTSB, 239480093f4SDimitry Andric VCMPGTSB_rec, 2400b57cec5SDimitry Andric VCMPGTSD, 241480093f4SDimitry Andric VCMPGTSD_rec, 2420b57cec5SDimitry Andric VCMPGTSH, 243480093f4SDimitry Andric VCMPGTSH_rec, 2440b57cec5SDimitry Andric VCMPGTSW, 245480093f4SDimitry Andric VCMPGTSW_rec, 2460b57cec5SDimitry Andric VCMPGTUB, 247480093f4SDimitry Andric VCMPGTUB_rec, 2480b57cec5SDimitry Andric VCMPGTUD, 249480093f4SDimitry Andric VCMPGTUD_rec, 2500b57cec5SDimitry Andric VCMPGTUH, 251480093f4SDimitry Andric VCMPGTUH_rec, 2520b57cec5SDimitry Andric VCMPGTUW, 253480093f4SDimitry Andric VCMPGTUW_rec, 254480093f4SDimitry Andric VCMPNEB_rec, 255480093f4SDimitry Andric VCMPNEH_rec, 256480093f4SDimitry Andric VCMPNEW_rec, 257480093f4SDimitry Andric VCMPNEZB_rec, 258480093f4SDimitry Andric VCMPNEZH_rec, 259480093f4SDimitry Andric VCMPNEZW_rec, 260480093f4SDimitry Andric VCMPEQUB_rec, 261480093f4SDimitry Andric VCMPEQUD_rec, 262480093f4SDimitry Andric VCMPEQUH_rec, 263480093f4SDimitry Andric VCMPEQUW_rec, 2640b57cec5SDimitry Andric XVCMPEQDP, 265480093f4SDimitry Andric XVCMPEQDP_rec, 2660b57cec5SDimitry Andric XVCMPEQSP, 267480093f4SDimitry Andric XVCMPEQSP_rec, 2680b57cec5SDimitry Andric XVCMPGEDP, 269480093f4SDimitry Andric XVCMPGEDP_rec, 2700b57cec5SDimitry Andric XVCMPGESP, 271480093f4SDimitry Andric XVCMPGESP_rec, 2720b57cec5SDimitry Andric XVCMPGTDP, 273480093f4SDimitry Andric XVCMPGTDP_rec, 2740b57cec5SDimitry Andric XVCMPGTSP, 275480093f4SDimitry Andric XVCMPGTSP_rec, 2760b57cec5SDimitry Andric XVMAXDP, 2770b57cec5SDimitry Andric XVMAXSP, 2780b57cec5SDimitry Andric XVMINDP, 2790b57cec5SDimitry Andric XVMINSP, 2800b57cec5SDimitry Andric XVTDIVDP, 2810b57cec5SDimitry Andric XVTDIVSP, 2820b57cec5SDimitry Andric XVTSQRTDP, 2830b57cec5SDimitry Andric XVTSQRTSP, 2840b57cec5SDimitry Andric XVTSTDCDP, 2850b57cec5SDimitry Andric XVTSTDCSP, 2860b57cec5SDimitry Andric XVXSIGDP, 2870b57cec5SDimitry Andric XVXSIGSP 2880b57cec5SDimitry Andric)>; 2890b57cec5SDimitry Andric 2900b57cec5SDimitry Andric// 7 cycle DP vector operation that uses an entire superslice. 2910b57cec5SDimitry Andric// Uses both DP units (the even DPE and odd DPO units), two pipelines (EXECE, 2920b57cec5SDimitry Andric// EXECO) and all three dispatches (DISP) to the given superslice. 2930b57cec5SDimitry Andricdef : InstRW<[P9_DPE_7C, P9_DPO_7C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C], 2940b57cec5SDimitry Andric (instrs 2950b57cec5SDimitry Andric VADDFP, 2960b57cec5SDimitry Andric VCTSXS, 2970b57cec5SDimitry Andric VCTSXS_0, 2980b57cec5SDimitry Andric VCTUXS, 2990b57cec5SDimitry Andric VCTUXS_0, 3000b57cec5SDimitry Andric VEXPTEFP, 3010b57cec5SDimitry Andric VLOGEFP, 3020b57cec5SDimitry Andric VMADDFP, 3030b57cec5SDimitry Andric VMHADDSHS, 3040b57cec5SDimitry Andric VNMSUBFP, 3050b57cec5SDimitry Andric VREFP, 3060b57cec5SDimitry Andric VRFIM, 3070b57cec5SDimitry Andric VRFIN, 3080b57cec5SDimitry Andric VRFIP, 3090b57cec5SDimitry Andric VRFIZ, 3100b57cec5SDimitry Andric VRSQRTEFP, 3110b57cec5SDimitry Andric VSUBFP, 3120b57cec5SDimitry Andric XVADDDP, 3130b57cec5SDimitry Andric XVADDSP, 3140b57cec5SDimitry Andric XVCVDPSP, 3150b57cec5SDimitry Andric XVCVDPSXDS, 3160b57cec5SDimitry Andric XVCVDPSXWS, 3170b57cec5SDimitry Andric XVCVDPUXDS, 3180b57cec5SDimitry Andric XVCVDPUXWS, 3190b57cec5SDimitry Andric XVCVHPSP, 3200b57cec5SDimitry Andric XVCVSPDP, 3210b57cec5SDimitry Andric XVCVSPHP, 3220b57cec5SDimitry Andric XVCVSPSXDS, 3230b57cec5SDimitry Andric XVCVSPSXWS, 3240b57cec5SDimitry Andric XVCVSPUXDS, 3250b57cec5SDimitry Andric XVCVSPUXWS, 3260b57cec5SDimitry Andric XVCVSXDDP, 3270b57cec5SDimitry Andric XVCVSXDSP, 3280b57cec5SDimitry Andric XVCVSXWDP, 3290b57cec5SDimitry Andric XVCVSXWSP, 3300b57cec5SDimitry Andric XVCVUXDDP, 3310b57cec5SDimitry Andric XVCVUXDSP, 3320b57cec5SDimitry Andric XVCVUXWDP, 3330b57cec5SDimitry Andric XVCVUXWSP, 3340b57cec5SDimitry Andric XVMADDADP, 3350b57cec5SDimitry Andric XVMADDASP, 3360b57cec5SDimitry Andric XVMADDMDP, 3370b57cec5SDimitry Andric XVMADDMSP, 3380b57cec5SDimitry Andric XVMSUBADP, 3390b57cec5SDimitry Andric XVMSUBASP, 3400b57cec5SDimitry Andric XVMSUBMDP, 3410b57cec5SDimitry Andric XVMSUBMSP, 3420b57cec5SDimitry Andric XVMULDP, 3430b57cec5SDimitry Andric XVMULSP, 3440b57cec5SDimitry Andric XVNMADDADP, 3450b57cec5SDimitry Andric XVNMADDASP, 3460b57cec5SDimitry Andric XVNMADDMDP, 3470b57cec5SDimitry Andric XVNMADDMSP, 3480b57cec5SDimitry Andric XVNMSUBADP, 3490b57cec5SDimitry Andric XVNMSUBASP, 3500b57cec5SDimitry Andric XVNMSUBMDP, 3510b57cec5SDimitry Andric XVNMSUBMSP, 3520b57cec5SDimitry Andric XVRDPI, 3530b57cec5SDimitry Andric XVRDPIC, 3540b57cec5SDimitry Andric XVRDPIM, 3550b57cec5SDimitry Andric XVRDPIP, 3560b57cec5SDimitry Andric XVRDPIZ, 3570b57cec5SDimitry Andric XVREDP, 3580b57cec5SDimitry Andric XVRESP, 3590b57cec5SDimitry Andric XVRSPI, 3600b57cec5SDimitry Andric XVRSPIC, 3610b57cec5SDimitry Andric XVRSPIM, 3620b57cec5SDimitry Andric XVRSPIP, 3630b57cec5SDimitry Andric XVRSPIZ, 3640b57cec5SDimitry Andric XVRSQRTEDP, 3650b57cec5SDimitry Andric XVRSQRTESP, 3660b57cec5SDimitry Andric XVSUBDP, 3670b57cec5SDimitry Andric XVSUBSP, 3680b57cec5SDimitry Andric VCFSX, 3690b57cec5SDimitry Andric VCFSX_0, 3700b57cec5SDimitry Andric VCFUX, 3710b57cec5SDimitry Andric VCFUX_0, 3720b57cec5SDimitry Andric VMHRADDSHS, 3730b57cec5SDimitry Andric VMLADDUHM, 3740b57cec5SDimitry Andric VMSUMMBM, 3750b57cec5SDimitry Andric VMSUMSHM, 3760b57cec5SDimitry Andric VMSUMSHS, 3770b57cec5SDimitry Andric VMSUMUBM, 3780b57cec5SDimitry Andric VMSUMUHM, 3790946e70aSDimitry Andric VMSUMUDM, 3800b57cec5SDimitry Andric VMSUMUHS, 3810b57cec5SDimitry Andric VMULESB, 3820b57cec5SDimitry Andric VMULESH, 3830b57cec5SDimitry Andric VMULESW, 3840b57cec5SDimitry Andric VMULEUB, 3850b57cec5SDimitry Andric VMULEUH, 3860b57cec5SDimitry Andric VMULEUW, 3870b57cec5SDimitry Andric VMULOSB, 3880b57cec5SDimitry Andric VMULOSH, 3890b57cec5SDimitry Andric VMULOSW, 3900b57cec5SDimitry Andric VMULOUB, 3910b57cec5SDimitry Andric VMULOUH, 3920b57cec5SDimitry Andric VMULOUW, 3930b57cec5SDimitry Andric VMULUWM, 3940b57cec5SDimitry Andric VSUM2SWS, 3950b57cec5SDimitry Andric VSUM4SBS, 3960b57cec5SDimitry Andric VSUM4SHS, 3970b57cec5SDimitry Andric VSUM4UBS, 3980b57cec5SDimitry Andric VSUMSWS 3990b57cec5SDimitry Andric)>; 4000b57cec5SDimitry Andric 4010b57cec5SDimitry Andric// 5 cycle Restricted DP operation. One DP unit, one EXEC pipeline and all three 4020b57cec5SDimitry Andric// dispatch units for the superslice. 4030b57cec5SDimitry Andricdef : InstRW<[P9_DP_5C, IP_EXEC_1C, DISP_3SLOTS_1C], 4040b57cec5SDimitry Andric (instrs 4050b57cec5SDimitry Andric (instregex "MADD(HD|HDU|LD|LD8)$"), 406c14a5a88SDimitry Andric (instregex "MUL(HD|HW|LD|LI|LI8|LW)(U)?(O)?$") 4070b57cec5SDimitry Andric)>; 4080b57cec5SDimitry Andric 4090b57cec5SDimitry Andric// 7 cycle Restricted DP operation. One DP unit, one EXEC pipeline and all three 4100b57cec5SDimitry Andric// dispatch units for the superslice. 4110b57cec5SDimitry Andricdef : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_3SLOTS_1C], 4120b57cec5SDimitry Andric (instrs 4130b57cec5SDimitry Andric FRSP, 4140b57cec5SDimitry Andric (instregex "FRI(N|P|Z|M)(D|S)$"), 4150b57cec5SDimitry Andric (instregex "FRE(S)?$"), 4160b57cec5SDimitry Andric (instregex "FADD(S)?$"), 4170b57cec5SDimitry Andric (instregex "FMSUB(S)?$"), 4180b57cec5SDimitry Andric (instregex "FMADD(S)?$"), 4190b57cec5SDimitry Andric (instregex "FSUB(S)?$"), 4200b57cec5SDimitry Andric (instregex "FCFID(U)?(S)?$"), 4210b57cec5SDimitry Andric (instregex "FCTID(U)?(Z)?$"), 4220b57cec5SDimitry Andric (instregex "FCTIW(U)?(Z)?$"), 4230b57cec5SDimitry Andric (instregex "FRSQRTE(S)?$"), 4240b57cec5SDimitry Andric FNMADDS, 4250b57cec5SDimitry Andric FNMADD, 4260b57cec5SDimitry Andric FNMSUBS, 4270b57cec5SDimitry Andric FNMSUB, 4280b57cec5SDimitry Andric FSELD, 4290b57cec5SDimitry Andric FSELS, 4300b57cec5SDimitry Andric FMULS, 4310b57cec5SDimitry Andric FMUL, 4320b57cec5SDimitry Andric XSMADDADP, 4330b57cec5SDimitry Andric XSMADDASP, 4340b57cec5SDimitry Andric XSMADDMDP, 4350b57cec5SDimitry Andric XSMADDMSP, 4360b57cec5SDimitry Andric XSMSUBADP, 4370b57cec5SDimitry Andric XSMSUBASP, 4380b57cec5SDimitry Andric XSMSUBMDP, 4390b57cec5SDimitry Andric XSMSUBMSP, 4400b57cec5SDimitry Andric XSMULDP, 4410b57cec5SDimitry Andric XSMULSP, 4420b57cec5SDimitry Andric XSNMADDADP, 4430b57cec5SDimitry Andric XSNMADDASP, 4440b57cec5SDimitry Andric XSNMADDMDP, 4450b57cec5SDimitry Andric XSNMADDMSP, 4460b57cec5SDimitry Andric XSNMSUBADP, 4470b57cec5SDimitry Andric XSNMSUBASP, 4480b57cec5SDimitry Andric XSNMSUBMDP, 4490b57cec5SDimitry Andric XSNMSUBMSP 4500b57cec5SDimitry Andric)>; 4510b57cec5SDimitry Andric 4520b57cec5SDimitry Andric// 7 cycle Restricted DP operation and one 3 cycle ALU operation. 4530b57cec5SDimitry Andric// These operations can be done in parallel. The DP is restricted so we need a 4540b57cec5SDimitry Andric// full 4 dispatches. 4550b57cec5SDimitry Andricdef : InstRW<[P9_DP_7C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C, 4560b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_1C], 4570b57cec5SDimitry Andric (instrs 458480093f4SDimitry Andric (instregex "FSEL(D|S)_rec$") 4590b57cec5SDimitry Andric)>; 4600b57cec5SDimitry Andric 4610b57cec5SDimitry Andric// 5 Cycle Restricted DP operation and one 2 cycle ALU operation. 4620b57cec5SDimitry Andricdef : InstRW<[P9_DPOpAndALUOp_7C, IP_EXEC_1C, IP_EXEC_1C, 4630b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_1C], 4640b57cec5SDimitry Andric (instrs 465480093f4SDimitry Andric (instregex "MUL(H|L)(D|W)(U)?(O)?_rec$") 4660b57cec5SDimitry Andric)>; 4670b57cec5SDimitry Andric 4680b57cec5SDimitry Andric// 7 cycle Restricted DP operation and one 3 cycle ALU operation. 4690b57cec5SDimitry Andric// These operations must be done sequentially.The DP is restricted so we need a 4700b57cec5SDimitry Andric// full 4 dispatches. 4710b57cec5SDimitry Andricdef : InstRW<[P9_DPOpAndALU2Op_10C, IP_EXEC_1C, IP_EXEC_1C, 4720b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_1C], 4730b57cec5SDimitry Andric (instrs 474480093f4SDimitry Andric (instregex "FRI(N|P|Z|M)(D|S)_rec$"), 475480093f4SDimitry Andric (instregex "FRE(S)?_rec$"), 476480093f4SDimitry Andric (instregex "FADD(S)?_rec$"), 477480093f4SDimitry Andric (instregex "FSUB(S)?_rec$"), 478480093f4SDimitry Andric (instregex "F(N)?MSUB(S)?_rec$"), 479480093f4SDimitry Andric (instregex "F(N)?MADD(S)?_rec$"), 480480093f4SDimitry Andric (instregex "FCFID(U)?(S)?_rec$"), 481480093f4SDimitry Andric (instregex "FCTID(U)?(Z)?_rec$"), 482480093f4SDimitry Andric (instregex "FCTIW(U)?(Z)?_rec$"), 483480093f4SDimitry Andric (instregex "FMUL(S)?_rec$"), 484480093f4SDimitry Andric (instregex "FRSQRTE(S)?_rec$"), 485480093f4SDimitry Andric FRSP_rec 4860b57cec5SDimitry Andric)>; 4870b57cec5SDimitry Andric 4880b57cec5SDimitry Andric// 7 cycle DP operation. One DP unit, one EXEC pipeline and 1 dispatch units. 4890b57cec5SDimitry Andricdef : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C], 4900b57cec5SDimitry Andric (instrs 4910b57cec5SDimitry Andric XSADDDP, 4920b57cec5SDimitry Andric XSADDSP, 4930b57cec5SDimitry Andric XSCVDPHP, 4940b57cec5SDimitry Andric XSCVDPSP, 4950b57cec5SDimitry Andric XSCVDPSXDS, 4960b57cec5SDimitry Andric XSCVDPSXDSs, 4970b57cec5SDimitry Andric XSCVDPSXWS, 4980b57cec5SDimitry Andric XSCVDPUXDS, 4990b57cec5SDimitry Andric XSCVDPUXDSs, 5000b57cec5SDimitry Andric XSCVDPUXWS, 5010b57cec5SDimitry Andric XSCVDPSXWSs, 5020b57cec5SDimitry Andric XSCVDPUXWSs, 5030b57cec5SDimitry Andric XSCVHPDP, 5040b57cec5SDimitry Andric XSCVSPDP, 5050b57cec5SDimitry Andric XSCVSXDDP, 5060b57cec5SDimitry Andric XSCVSXDSP, 5070b57cec5SDimitry Andric XSCVUXDDP, 5080b57cec5SDimitry Andric XSCVUXDSP, 5090b57cec5SDimitry Andric XSRDPI, 5100b57cec5SDimitry Andric XSRDPIC, 5110b57cec5SDimitry Andric XSRDPIM, 5120b57cec5SDimitry Andric XSRDPIP, 5130b57cec5SDimitry Andric XSRDPIZ, 5140b57cec5SDimitry Andric XSREDP, 5150b57cec5SDimitry Andric XSRESP, 5160b57cec5SDimitry Andric XSRSQRTEDP, 5170b57cec5SDimitry Andric XSRSQRTESP, 5180b57cec5SDimitry Andric XSSUBDP, 5190b57cec5SDimitry Andric XSSUBSP, 5200b57cec5SDimitry Andric XSCVDPSPN, 5210b57cec5SDimitry Andric XSRSP 5220b57cec5SDimitry Andric)>; 5230b57cec5SDimitry Andric 5240b57cec5SDimitry Andric// Three Cycle PM operation. Only one PM unit per superslice so we use the whole 5250b57cec5SDimitry Andric// superslice. That includes both exec pipelines (EXECO, EXECE) and one 5260b57cec5SDimitry Andric// dispatch. 5270b57cec5SDimitry Andricdef : InstRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C], 5280b57cec5SDimitry Andric (instrs 5290b57cec5SDimitry Andric (instregex "LVS(L|R)$"), 5300b57cec5SDimitry Andric (instregex "VSPLTIS(W|H|B)$"), 5310b57cec5SDimitry Andric (instregex "VSPLT(W|H|B)(s)?$"), 5320b57cec5SDimitry Andric (instregex "V_SETALLONES(B|H)?$"), 5330b57cec5SDimitry Andric (instregex "VEXTRACTU(B|H|W)$"), 5340b57cec5SDimitry Andric (instregex "VINSERT(B|H|W|D)$"), 5350b57cec5SDimitry Andric MFVSRLD, 5360b57cec5SDimitry Andric MTVSRWS, 5370b57cec5SDimitry Andric VBPERMQ, 5380b57cec5SDimitry Andric VCLZLSBB, 5390b57cec5SDimitry Andric VCTZLSBB, 5400b57cec5SDimitry Andric VEXTRACTD, 5410b57cec5SDimitry Andric VEXTUBLX, 5420b57cec5SDimitry Andric VEXTUBRX, 5430b57cec5SDimitry Andric VEXTUHLX, 5440b57cec5SDimitry Andric VEXTUHRX, 5450b57cec5SDimitry Andric VEXTUWLX, 5460b57cec5SDimitry Andric VEXTUWRX, 5470b57cec5SDimitry Andric VGBBD, 5480b57cec5SDimitry Andric VMRGHB, 5490b57cec5SDimitry Andric VMRGHH, 5500b57cec5SDimitry Andric VMRGHW, 5510b57cec5SDimitry Andric VMRGLB, 5520b57cec5SDimitry Andric VMRGLH, 5530b57cec5SDimitry Andric VMRGLW, 5540b57cec5SDimitry Andric VPERM, 5550b57cec5SDimitry Andric VPERMR, 5560b57cec5SDimitry Andric VPERMXOR, 5570b57cec5SDimitry Andric VPKPX, 5580b57cec5SDimitry Andric VPKSDSS, 5590b57cec5SDimitry Andric VPKSDUS, 5600b57cec5SDimitry Andric VPKSHSS, 5610b57cec5SDimitry Andric VPKSHUS, 5620b57cec5SDimitry Andric VPKSWSS, 5630b57cec5SDimitry Andric VPKSWUS, 5640b57cec5SDimitry Andric VPKUDUM, 5650b57cec5SDimitry Andric VPKUDUS, 5660b57cec5SDimitry Andric VPKUHUM, 5670b57cec5SDimitry Andric VPKUHUS, 5680b57cec5SDimitry Andric VPKUWUM, 5690b57cec5SDimitry Andric VPKUWUS, 5700b57cec5SDimitry Andric VPRTYBQ, 5710b57cec5SDimitry Andric VSL, 5720b57cec5SDimitry Andric VSLDOI, 5730b57cec5SDimitry Andric VSLO, 5740b57cec5SDimitry Andric VSLV, 5750b57cec5SDimitry Andric VSR, 5760b57cec5SDimitry Andric VSRO, 5770b57cec5SDimitry Andric VSRV, 5780b57cec5SDimitry Andric VUPKHPX, 5790b57cec5SDimitry Andric VUPKHSB, 5800b57cec5SDimitry Andric VUPKHSH, 5810b57cec5SDimitry Andric VUPKHSW, 5820b57cec5SDimitry Andric VUPKLPX, 5830b57cec5SDimitry Andric VUPKLSB, 5840b57cec5SDimitry Andric VUPKLSH, 5850b57cec5SDimitry Andric VUPKLSW, 5860b57cec5SDimitry Andric XXBRD, 5870b57cec5SDimitry Andric XXBRH, 5880b57cec5SDimitry Andric XXBRQ, 5890b57cec5SDimitry Andric XXBRW, 5900b57cec5SDimitry Andric XXEXTRACTUW, 5910b57cec5SDimitry Andric XXINSERTW, 5920b57cec5SDimitry Andric XXMRGHW, 5930b57cec5SDimitry Andric XXMRGLW, 5940b57cec5SDimitry Andric XXPERM, 5950b57cec5SDimitry Andric XXPERMR, 5960b57cec5SDimitry Andric XXSLDWI, 5970b57cec5SDimitry Andric XXSLDWIs, 5980b57cec5SDimitry Andric XXSPLTIB, 5990b57cec5SDimitry Andric XXSPLTW, 6000b57cec5SDimitry Andric XXSPLTWs, 6010b57cec5SDimitry Andric XXPERMDI, 6020b57cec5SDimitry Andric XXPERMDIs, 6030b57cec5SDimitry Andric VADDCUQ, 6040b57cec5SDimitry Andric VADDECUQ, 6050b57cec5SDimitry Andric VADDEUQM, 6060b57cec5SDimitry Andric VADDUQM, 6070b57cec5SDimitry Andric VMUL10CUQ, 6080b57cec5SDimitry Andric VMUL10ECUQ, 6090b57cec5SDimitry Andric VMUL10EUQ, 6100b57cec5SDimitry Andric VMUL10UQ, 6110b57cec5SDimitry Andric VSUBCUQ, 6120b57cec5SDimitry Andric VSUBECUQ, 6130b57cec5SDimitry Andric VSUBEUQM, 6140b57cec5SDimitry Andric VSUBUQM, 6150b57cec5SDimitry Andric XSCMPEXPQP, 6160b57cec5SDimitry Andric XSCMPOQP, 6170b57cec5SDimitry Andric XSCMPUQP, 6180b57cec5SDimitry Andric XSTSTDCQP, 6190b57cec5SDimitry Andric XSXSIGQP, 620480093f4SDimitry Andric BCDCFN_rec, 621480093f4SDimitry Andric BCDCFZ_rec, 622480093f4SDimitry Andric BCDCPSGN_rec, 623480093f4SDimitry Andric BCDCTN_rec, 624480093f4SDimitry Andric BCDCTZ_rec, 625480093f4SDimitry Andric BCDSETSGN_rec, 626480093f4SDimitry Andric BCDS_rec, 627480093f4SDimitry Andric BCDTRUNC_rec, 628480093f4SDimitry Andric BCDUS_rec, 6294824e7fdSDimitry Andric BCDUTRUNC_rec, 6304824e7fdSDimitry Andric BCDADD_rec, 6314824e7fdSDimitry Andric BCDSUB_rec 6320b57cec5SDimitry Andric)>; 6330b57cec5SDimitry Andric 6340b57cec5SDimitry Andric// 12 Cycle DFU operation. Only one DFU unit per CPU so we use a whole 6350b57cec5SDimitry Andric// superslice. That includes both exec pipelines (EXECO, EXECE) and one 6360b57cec5SDimitry Andric// dispatch. 6370b57cec5SDimitry Andricdef : InstRW<[P9_DFU_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C], 6380b57cec5SDimitry Andric (instrs 639480093f4SDimitry Andric BCDSR_rec, 6400b57cec5SDimitry Andric XSADDQP, 6410b57cec5SDimitry Andric XSADDQPO, 6420b57cec5SDimitry Andric XSCVDPQP, 6430b57cec5SDimitry Andric XSCVQPDP, 6440b57cec5SDimitry Andric XSCVQPDPO, 6450b57cec5SDimitry Andric XSCVQPSDZ, 6460b57cec5SDimitry Andric XSCVQPSWZ, 6470b57cec5SDimitry Andric XSCVQPUDZ, 6480b57cec5SDimitry Andric XSCVQPUWZ, 6490b57cec5SDimitry Andric XSCVSDQP, 6500b57cec5SDimitry Andric XSCVUDQP, 6510b57cec5SDimitry Andric XSRQPI, 6520b57cec5SDimitry Andric XSRQPIX, 6530b57cec5SDimitry Andric XSRQPXP, 6540b57cec5SDimitry Andric XSSUBQP, 6550b57cec5SDimitry Andric XSSUBQPO 6560b57cec5SDimitry Andric)>; 6570b57cec5SDimitry Andric 6580b57cec5SDimitry Andric// 23 Cycle DFU operation. Only one DFU unit per CPU so we use a whole 6590b57cec5SDimitry Andric// superslice. That includes both exec pipelines (EXECO, EXECE) and one 6600b57cec5SDimitry Andric// dispatch. 6610b57cec5SDimitry Andricdef : InstRW<[P9_DFU_23C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C], 6620b57cec5SDimitry Andric (instrs 663480093f4SDimitry Andric BCDCTSQ_rec 6640b57cec5SDimitry Andric)>; 6650b57cec5SDimitry Andric 6660b57cec5SDimitry Andric// 24 Cycle DFU operation. Only one DFU unit per CPU so we use a whole 6670b57cec5SDimitry Andric// superslice. That includes both exec pipelines (EXECO, EXECE) and one 6680b57cec5SDimitry Andric// dispatch. 6690b57cec5SDimitry Andricdef : InstRW<[P9_DFU_24C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C], 6700b57cec5SDimitry Andric (instrs 6710b57cec5SDimitry Andric XSMADDQP, 6720b57cec5SDimitry Andric XSMADDQPO, 6730b57cec5SDimitry Andric XSMSUBQP, 6740b57cec5SDimitry Andric XSMSUBQPO, 6750b57cec5SDimitry Andric XSMULQP, 6760b57cec5SDimitry Andric XSMULQPO, 6770b57cec5SDimitry Andric XSNMADDQP, 6780b57cec5SDimitry Andric XSNMADDQPO, 6790b57cec5SDimitry Andric XSNMSUBQP, 6800b57cec5SDimitry Andric XSNMSUBQPO 6810b57cec5SDimitry Andric)>; 6820b57cec5SDimitry Andric 6830b57cec5SDimitry Andric// 37 Cycle DFU operation. Only one DFU unit per CPU so we use a whole 6840b57cec5SDimitry Andric// superslice. That includes both exec pipelines (EXECO, EXECE) and one 6850b57cec5SDimitry Andric// dispatch. 6860b57cec5SDimitry Andricdef : InstRW<[P9_DFU_37C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C], 6870b57cec5SDimitry Andric (instrs 688480093f4SDimitry Andric BCDCFSQ_rec 6890b57cec5SDimitry Andric)>; 6900b57cec5SDimitry Andric 6910b57cec5SDimitry Andric// 58 Cycle DFU operation. Only one DFU unit per CPU so we use a whole 6920b57cec5SDimitry Andric// superslice. That includes both exec pipelines (EXECO, EXECE) and one 6930b57cec5SDimitry Andric// dispatch. 6940b57cec5SDimitry Andricdef : InstRW<[P9_DFU_58C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C], 6950b57cec5SDimitry Andric (instrs 6960b57cec5SDimitry Andric XSDIVQP, 6970b57cec5SDimitry Andric XSDIVQPO 6980b57cec5SDimitry Andric)>; 6990b57cec5SDimitry Andric 7000b57cec5SDimitry Andric// 76 Cycle DFU operation. Only one DFU unit per CPU so we use a whole 7010b57cec5SDimitry Andric// superslice. That includes both exec pipelines (EXECO, EXECE) and all three 7020b57cec5SDimitry Andric// dispatches. 7030b57cec5SDimitry Andricdef : InstRW<[P9_DFU_76C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C], 7040b57cec5SDimitry Andric (instrs 7050b57cec5SDimitry Andric XSSQRTQP, 7060b57cec5SDimitry Andric XSSQRTQPO 7070b57cec5SDimitry Andric)>; 7080b57cec5SDimitry Andric 7090b57cec5SDimitry Andric// 6 Cycle Load uses a single slice. 7100b57cec5SDimitry Andricdef : InstRW<[P9_LS_6C, IP_AGEN_1C, DISP_1C], 7110b57cec5SDimitry Andric (instrs 7120b57cec5SDimitry Andric (instregex "LXVL(L)?") 7130b57cec5SDimitry Andric)>; 7140b57cec5SDimitry Andric 7150b57cec5SDimitry Andric// 5 Cycle Load uses a single slice. 7160b57cec5SDimitry Andricdef : InstRW<[P9_LS_5C, IP_AGEN_1C, DISP_1C], 7170b57cec5SDimitry Andric (instrs 7180b57cec5SDimitry Andric (instregex "LVE(B|H|W)X$"), 7190b57cec5SDimitry Andric (instregex "LVX(L)?"), 7200b57cec5SDimitry Andric (instregex "LXSI(B|H)ZX$"), 7210b57cec5SDimitry Andric LXSDX, 7220b57cec5SDimitry Andric LXVB16X, 7230b57cec5SDimitry Andric LXVD2X, 7240b57cec5SDimitry Andric LXVWSX, 7250b57cec5SDimitry Andric LXSIWZX, 7260b57cec5SDimitry Andric LXV, 7270b57cec5SDimitry Andric LXVX, 7280b57cec5SDimitry Andric LXSD, 7290b57cec5SDimitry Andric DFLOADf64, 7300b57cec5SDimitry Andric XFLOADf64, 7310b57cec5SDimitry Andric LIWZX 7320b57cec5SDimitry Andric)>; 7330b57cec5SDimitry Andric 7340b57cec5SDimitry Andric// 4 Cycle Load uses a single slice. 7350b57cec5SDimitry Andricdef : InstRW<[P9_LS_4C, IP_AGEN_1C, DISP_1C], 7360b57cec5SDimitry Andric (instrs 7370b57cec5SDimitry Andric (instregex "DCB(F|T|ST)(EP)?$"), 7380b57cec5SDimitry Andric (instregex "DCBZ(L)?(EP)?$"), 7390b57cec5SDimitry Andric (instregex "DCBTST(EP)?$"), 7400b57cec5SDimitry Andric (instregex "CP_COPY(8)?$"), 7410b57cec5SDimitry Andric (instregex "ICBI(EP)?$"), 7420b57cec5SDimitry Andric (instregex "ICBT(LS)?$"), 7430b57cec5SDimitry Andric (instregex "LBARX(L)?$"), 7440b57cec5SDimitry Andric (instregex "LBZ(CIX|8|X|X8|XTLS|XTLS_32)?(_)?$"), 7450b57cec5SDimitry Andric (instregex "LD(ARX|ARXL|BRX|CIX|X|XTLS)?(_)?$"), 7460b57cec5SDimitry Andric (instregex "LH(A|B)RX(L)?(8)?$"), 7470b57cec5SDimitry Andric (instregex "LHZ(8|CIX|X|X8|XTLS|XTLS_32)?(_)?$"), 7480b57cec5SDimitry Andric (instregex "LWARX(L)?$"), 7490b57cec5SDimitry Andric (instregex "LWBRX(8)?$"), 7500b57cec5SDimitry Andric (instregex "LWZ(8|CIX|X|X8|XTLS|XTLS_32)?(_)?$"), 7510b57cec5SDimitry Andric CP_ABORT, 7520b57cec5SDimitry Andric DARN, 7530b57cec5SDimitry Andric EnforceIEIO, 7540b57cec5SDimitry Andric ISYNC, 7550b57cec5SDimitry Andric MSGSYNC, 7560b57cec5SDimitry Andric TLBSYNC, 7570b57cec5SDimitry Andric SYNC, 7580b57cec5SDimitry Andric LMW, 7590b57cec5SDimitry Andric LSWI 7600b57cec5SDimitry Andric)>; 7610b57cec5SDimitry Andric 7620b57cec5SDimitry Andric// 4 Cycle Restricted load uses a single slice but the dispatch for the whole 7630b57cec5SDimitry Andric// superslice. 7640b57cec5SDimitry Andricdef : InstRW<[P9_LS_4C, IP_AGEN_1C, DISP_3SLOTS_1C], 7650b57cec5SDimitry Andric (instrs 7660b57cec5SDimitry Andric LFIWZX, 7670b57cec5SDimitry Andric LFDX, 76806c3fb27SDimitry Andric (instregex "LFDXTLS?(_)?$"), 7690b57cec5SDimitry Andric LFD 7700b57cec5SDimitry Andric)>; 7710b57cec5SDimitry Andric 7720b57cec5SDimitry Andric// Cracked Load Instructions. 7730b57cec5SDimitry Andric// Load instructions that can be done in parallel. 7740b57cec5SDimitry Andricdef : InstRW<[P9_LS_4C, P9_LS_4C, IP_AGEN_1C, IP_AGEN_1C, 7750b57cec5SDimitry Andric DISP_PAIR_1C], 7760b57cec5SDimitry Andric (instrs 7770b57cec5SDimitry Andric SLBIA, 7780b57cec5SDimitry Andric SLBIE, 7790b57cec5SDimitry Andric SLBMFEE, 7800b57cec5SDimitry Andric SLBMFEV, 7810b57cec5SDimitry Andric SLBMTE, 7820b57cec5SDimitry Andric TLBIEL 7830b57cec5SDimitry Andric)>; 7840b57cec5SDimitry Andric 7850b57cec5SDimitry Andric// Cracked Load Instruction. 7860b57cec5SDimitry Andric// Requires Load and ALU pieces totaling 6 cycles. The Load and ALU 7870b57cec5SDimitry Andric// operations can be run in parallel. 7880b57cec5SDimitry Andricdef : InstRW<[P9_LS_4C, P9_ALU_2C, IP_EXEC_1C, IP_AGEN_1C, 7890b57cec5SDimitry Andric DISP_PAIR_1C, DISP_PAIR_1C], 7900b57cec5SDimitry Andric (instrs 7910b57cec5SDimitry Andric (instregex "L(W|H)ZU(X)?(8)?$") 7920b57cec5SDimitry Andric)>; 7930b57cec5SDimitry Andric 7940b57cec5SDimitry Andric// Cracked TEND Instruction. 7950b57cec5SDimitry Andric// Requires Load and ALU pieces totaling 6 cycles. The Load and ALU 7960b57cec5SDimitry Andric// operations can be run in parallel. 7970b57cec5SDimitry Andricdef : InstRW<[P9_LS_4C, P9_ALU_2C, IP_EXEC_1C, IP_AGEN_1C, 7980b57cec5SDimitry Andric DISP_1C, DISP_1C], 7990b57cec5SDimitry Andric (instrs 8000b57cec5SDimitry Andric TEND 8010b57cec5SDimitry Andric)>; 8020b57cec5SDimitry Andric 8030b57cec5SDimitry Andric 8040b57cec5SDimitry Andric// Cracked Store Instruction 8050b57cec5SDimitry Andric// Consecutive Store and ALU instructions. The store is restricted and requires 8060b57cec5SDimitry Andric// three dispatches. 8070b57cec5SDimitry Andricdef : InstRW<[P9_StoreAndALUOp_3C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C, 8080b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_1C], 8090b57cec5SDimitry Andric (instrs 8100b57cec5SDimitry Andric (instregex "ST(B|H|W|D)CX$") 8110b57cec5SDimitry Andric)>; 8120b57cec5SDimitry Andric 8130b57cec5SDimitry Andric// Cracked Load instruction. 8140b57cec5SDimitry Andric// Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU 8150b57cec5SDimitry Andric// operations cannot be done at the same time and so their latencies are added. 8160b57cec5SDimitry Andricdef : InstRW<[P9_LoadAndALUOp_6C, IP_EXEC_1C, IP_AGEN_1C, 8170b57cec5SDimitry Andric DISP_1C, DISP_1C], 8180b57cec5SDimitry Andric (instrs 81906c3fb27SDimitry Andric (instregex "LHA(X)?(TLS)?(8)?(_32)?(_)?$"), 820480093f4SDimitry Andric (instregex "CP_PASTE(8)?_rec$"), 82106c3fb27SDimitry Andric (instregex "LWA(X)?(TLS)?(_32)?(_)?$"), 8220b57cec5SDimitry Andric TCHECK 8230b57cec5SDimitry Andric)>; 8240b57cec5SDimitry Andric 8250b57cec5SDimitry Andric// Cracked Restricted Load instruction. 8260b57cec5SDimitry Andric// Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU 8270b57cec5SDimitry Andric// operations cannot be done at the same time and so their latencies are added. 8280b57cec5SDimitry Andric// Full 6 dispatches are required as this is both cracked and restricted. 8290b57cec5SDimitry Andricdef : InstRW<[P9_LoadAndALUOp_6C, IP_EXEC_1C, IP_AGEN_1C, 8300b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_3SLOTS_1C], 8310b57cec5SDimitry Andric (instrs 8320b57cec5SDimitry Andric LFIWAX 8330b57cec5SDimitry Andric)>; 8340b57cec5SDimitry Andric 8350b57cec5SDimitry Andric// Cracked Load instruction. 8360b57cec5SDimitry Andric// Requires consecutive Load and ALU pieces totaling 7 cycles. The Load and ALU 8370b57cec5SDimitry Andric// operations cannot be done at the same time and so their latencies are added. 8380b57cec5SDimitry Andric// Full 4 dispatches are required as this is a cracked instruction. 8390b57cec5SDimitry Andricdef : InstRW<[P9_LoadAndALUOp_7C, IP_AGEN_1C, IP_EXEC_1C, DISP_1C, DISP_1C], 8400b57cec5SDimitry Andric (instrs 8410b57cec5SDimitry Andric LXSIWAX, 8420b57cec5SDimitry Andric LIWAX 8430b57cec5SDimitry Andric)>; 8440b57cec5SDimitry Andric 8450b57cec5SDimitry Andric// Cracked Load instruction. 8460b57cec5SDimitry Andric// Requires consecutive Load (4 cycles) and ALU (3 cycles) pieces totaling 7 8470b57cec5SDimitry Andric// cycles. The Load and ALU operations cannot be done at the same time and so 8480b57cec5SDimitry Andric// their latencies are added. 8490b57cec5SDimitry Andric// Full 6 dispatches are required as this is a restricted instruction. 8500b57cec5SDimitry Andricdef : InstRW<[P9_LoadAndALU2Op_7C, IP_AGEN_1C, IP_EXEC_1C, 8510b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_3SLOTS_1C], 8520b57cec5SDimitry Andric (instrs 8530b57cec5SDimitry Andric LFSX, 85406c3fb27SDimitry Andric (instregex "LFSXTLS?(_)?$"), 8550b57cec5SDimitry Andric LFS 8560b57cec5SDimitry Andric)>; 8570b57cec5SDimitry Andric 8580b57cec5SDimitry Andric// Cracked Load instruction. 8590b57cec5SDimitry Andric// Requires consecutive Load and ALU pieces totaling 8 cycles. The Load and ALU 8600b57cec5SDimitry Andric// operations cannot be done at the same time and so their latencies are added. 8610b57cec5SDimitry Andric// Full 4 dispatches are required as this is a cracked instruction. 8620b57cec5SDimitry Andricdef : InstRW<[P9_LoadAndALU2Op_8C, IP_AGEN_1C, IP_EXEC_1C, DISP_1C, DISP_1C], 8630b57cec5SDimitry Andric (instrs 8640b57cec5SDimitry Andric LXSSP, 8650b57cec5SDimitry Andric LXSSPX, 8660b57cec5SDimitry Andric XFLOADf32, 8670b57cec5SDimitry Andric DFLOADf32 8680b57cec5SDimitry Andric)>; 8690b57cec5SDimitry Andric 8700b57cec5SDimitry Andric// Cracked 3-Way Load Instruction 8710b57cec5SDimitry Andric// Load with two ALU operations that depend on each other 8720b57cec5SDimitry Andricdef : InstRW<[P9_LoadAndALUOp_6C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C, IP_EXEC_1C, 8730b57cec5SDimitry Andric DISP_PAIR_1C, DISP_PAIR_1C, DISP_1C], 8740b57cec5SDimitry Andric (instrs 8750b57cec5SDimitry Andric (instregex "LHAU(X)?(8)?$"), 8760b57cec5SDimitry Andric LWAUX 8770b57cec5SDimitry Andric)>; 8780b57cec5SDimitry Andric 8790b57cec5SDimitry Andric// Cracked Load that requires the PM resource. 8800b57cec5SDimitry Andric// Since the Load and the PM cannot be done at the same time the latencies are 8810b57cec5SDimitry Andric// added. Requires 8 cycles. Since the PM requires the full superslice we need 8820b57cec5SDimitry Andric// both EXECE, EXECO pipelines as well as 1 dispatch for the PM. The Load 8830b57cec5SDimitry Andric// requires the remaining 1 dispatch. 8840b57cec5SDimitry Andricdef : InstRW<[P9_LoadAndPMOp_8C, IP_AGEN_1C, IP_EXECE_1C, IP_EXECO_1C, 8850b57cec5SDimitry Andric DISP_1C, DISP_1C], 8860b57cec5SDimitry Andric (instrs 8870b57cec5SDimitry Andric LXVH8X, 8880b57cec5SDimitry Andric LXVDSX, 8890b57cec5SDimitry Andric LXVW4X 8900b57cec5SDimitry Andric)>; 8910b57cec5SDimitry Andric 8920b57cec5SDimitry Andric// Single slice Restricted store operation. The restricted operation requires 8930b57cec5SDimitry Andric// all three dispatches for the superslice. 8940b57cec5SDimitry Andricdef : InstRW<[P9_LS_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_3SLOTS_1C], 8950b57cec5SDimitry Andric (instrs 89606c3fb27SDimitry Andric (instregex "STF(S|D|IWX|SX|DX|SXTLS|DXTLS|SXTLS_|DXTLS_)$"), 8970b57cec5SDimitry Andric (instregex "STXS(D|DX|SPX|IWX|IBX|IHX|SP)(v)?$"), 8980b57cec5SDimitry Andric (instregex "STW(8)?$"), 8990b57cec5SDimitry Andric (instregex "(D|X)FSTORE(f32|f64)$"), 9000b57cec5SDimitry Andric (instregex "ST(W|H|D)BRX$"), 9010b57cec5SDimitry Andric (instregex "ST(B|H|D)(8)?$"), 9020b57cec5SDimitry Andric (instregex "ST(B|W|H|D)(CI)?X(TLS|TLS_32)?(8)?(_)?$"), 9030b57cec5SDimitry Andric STIWX, 9040b57cec5SDimitry Andric SLBIEG, 9050b57cec5SDimitry Andric STMW, 9060b57cec5SDimitry Andric STSWI, 9070b57cec5SDimitry Andric TLBIE 9080b57cec5SDimitry Andric)>; 9090b57cec5SDimitry Andric 9100b57cec5SDimitry Andric// Vector Store Instruction 9110b57cec5SDimitry Andric// Requires the whole superslice and therefore requires one dispatch 9120b57cec5SDimitry Andric// as well as both the Even and Odd exec pipelines. 9130b57cec5SDimitry Andricdef : InstRW<[P9_LS_1C, IP_EXECE_1C, IP_EXECO_1C, IP_AGEN_1C, DISP_1C], 9140b57cec5SDimitry Andric (instrs 9150b57cec5SDimitry Andric (instregex "STVE(B|H|W)X$"), 9160b57cec5SDimitry Andric (instregex "STVX(L)?$"), 9170b57cec5SDimitry Andric (instregex "STXV(B16X|H8X|W4X|D2X|L|LL|X)?$") 9180b57cec5SDimitry Andric)>; 9190b57cec5SDimitry Andric 9200b57cec5SDimitry Andric// 5 Cycle DIV operation. Only one DIV unit per superslice so we use the whole 9210b57cec5SDimitry Andric// superslice. That includes both exec pipelines (EXECO, EXECE) and two 9220b57cec5SDimitry Andric// dispatches. 9230b57cec5SDimitry Andricdef : InstRW<[P9_DIV_5C, IP_EXECE_1C, IP_EXECO_1C, DISP_EVEN_1C], 9240b57cec5SDimitry Andric (instrs 9250b57cec5SDimitry Andric (instregex "MTCTR(8)?(loop)?$"), 9260b57cec5SDimitry Andric (instregex "MTLR(8)?$") 9270b57cec5SDimitry Andric)>; 9280b57cec5SDimitry Andric 9290b57cec5SDimitry Andric// 12 Cycle DIV operation. Only one DIV unit per superslice so we use the whole 9300b57cec5SDimitry Andric// superslice. That includes both exec pipelines (EXECO, EXECE) and two 9310b57cec5SDimitry Andric// dispatches. 9320b57cec5SDimitry Andricdef : InstRW<[P9_DIV_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_EVEN_1C], 9330b57cec5SDimitry Andric (instrs 9340b57cec5SDimitry Andric (instregex "M(T|F)VRSAVE(v)?$"), 9350b57cec5SDimitry Andric (instregex "M(T|F)PMR$"), 9360b57cec5SDimitry Andric (instregex "M(T|F)TB(8)?$"), 9370b57cec5SDimitry Andric (instregex "MF(SPR|CTR|LR)(8)?$"), 9380b57cec5SDimitry Andric (instregex "M(T|F)MSR(D)?$"), 93981ad6265SDimitry Andric (instregex "M(T|F)(U)?DSCR$"), 9400b57cec5SDimitry Andric (instregex "MTSPR(8)?$") 9410b57cec5SDimitry Andric)>; 9420b57cec5SDimitry Andric 9430b57cec5SDimitry Andric// 16 Cycle DIV operation. Only one DIV unit per superslice so we use the whole 9440b57cec5SDimitry Andric// superslice. That includes both exec pipelines (EXECO, EXECE) and two 9450b57cec5SDimitry Andric// dispatches. 9460b57cec5SDimitry Andricdef : InstRW<[P9_DIV_16C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C], 9470b57cec5SDimitry Andric (instrs 9480b57cec5SDimitry Andric DIVW, 949c14a5a88SDimitry Andric DIVWO, 9500b57cec5SDimitry Andric DIVWU, 951c14a5a88SDimitry Andric DIVWUO, 9520b57cec5SDimitry Andric MODSW 9530b57cec5SDimitry Andric)>; 9540b57cec5SDimitry Andric 9550b57cec5SDimitry Andric// 24 Cycle DIV operation. Only one DIV unit per superslice so we use the whole 9560b57cec5SDimitry Andric// superslice. That includes both exec pipelines (EXECO, EXECE) and two 9570b57cec5SDimitry Andric// dispatches. 9580b57cec5SDimitry Andricdef : InstRW<[P9_DIV_24C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C], 9590b57cec5SDimitry Andric (instrs 9600b57cec5SDimitry Andric DIVWE, 961c14a5a88SDimitry Andric DIVWEO, 9620b57cec5SDimitry Andric DIVD, 963c14a5a88SDimitry Andric DIVDO, 9640b57cec5SDimitry Andric DIVWEU, 965c14a5a88SDimitry Andric DIVWEUO, 9660b57cec5SDimitry Andric DIVDU, 967c14a5a88SDimitry Andric DIVDUO, 9680b57cec5SDimitry Andric MODSD, 9690b57cec5SDimitry Andric MODUD, 9700b57cec5SDimitry Andric MODUW 9710b57cec5SDimitry Andric)>; 9720b57cec5SDimitry Andric 9730b57cec5SDimitry Andric// 40 Cycle DIV operation. Only one DIV unit per superslice so we use the whole 9740b57cec5SDimitry Andric// superslice. That includes both exec pipelines (EXECO, EXECE) and all three 9750b57cec5SDimitry Andric// dispatches. 9760b57cec5SDimitry Andricdef : InstRW<[P9_DIV_40C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C], 9770b57cec5SDimitry Andric (instrs 9780b57cec5SDimitry Andric DIVDE, 979c14a5a88SDimitry Andric DIVDEO, 980c14a5a88SDimitry Andric DIVDEU, 981c14a5a88SDimitry Andric DIVDEUO 9820b57cec5SDimitry Andric)>; 9830b57cec5SDimitry Andric 9840b57cec5SDimitry Andric// Cracked DIV and ALU operation. Requires one full slice for the ALU operation 9850b57cec5SDimitry Andric// and one full superslice for the DIV operation since there is only one DIV per 9860b57cec5SDimitry Andric// superslice. Latency of DIV plus ALU is 26. 9870b57cec5SDimitry Andricdef : InstRW<[P9_IntDivAndALUOp_18C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C, 9880b57cec5SDimitry Andric DISP_EVEN_1C, DISP_1C], 9890b57cec5SDimitry Andric (instrs 990480093f4SDimitry Andric (instregex "DIVW(U)?(O)?_rec$") 9910b57cec5SDimitry Andric)>; 9920b57cec5SDimitry Andric 9930b57cec5SDimitry Andric// Cracked DIV and ALU operation. Requires one full slice for the ALU operation 9940b57cec5SDimitry Andric// and one full superslice for the DIV operation since there is only one DIV per 9950b57cec5SDimitry Andric// superslice. Latency of DIV plus ALU is 26. 9960b57cec5SDimitry Andricdef : InstRW<[P9_IntDivAndALUOp_26C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C, 9970b57cec5SDimitry Andric DISP_EVEN_1C, DISP_1C], 9980b57cec5SDimitry Andric (instrs 999480093f4SDimitry Andric DIVD_rec, 1000480093f4SDimitry Andric DIVDO_rec, 1001480093f4SDimitry Andric DIVDU_rec, 1002480093f4SDimitry Andric DIVDUO_rec, 1003480093f4SDimitry Andric DIVWE_rec, 1004480093f4SDimitry Andric DIVWEO_rec, 1005480093f4SDimitry Andric DIVWEU_rec, 1006480093f4SDimitry Andric DIVWEUO_rec 10070b57cec5SDimitry Andric)>; 10080b57cec5SDimitry Andric 10090b57cec5SDimitry Andric// Cracked DIV and ALU operation. Requires one full slice for the ALU operation 10100b57cec5SDimitry Andric// and one full superslice for the DIV operation since there is only one DIV per 10110b57cec5SDimitry Andric// superslice. Latency of DIV plus ALU is 42. 10120b57cec5SDimitry Andricdef : InstRW<[P9_IntDivAndALUOp_42C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C, 10130b57cec5SDimitry Andric DISP_EVEN_1C, DISP_1C], 10140b57cec5SDimitry Andric (instrs 1015480093f4SDimitry Andric DIVDE_rec, 1016480093f4SDimitry Andric DIVDEO_rec, 1017480093f4SDimitry Andric DIVDEU_rec, 1018480093f4SDimitry Andric DIVDEUO_rec 10190b57cec5SDimitry Andric)>; 10200b57cec5SDimitry Andric 10210b57cec5SDimitry Andric// CR access instructions in _BrMCR, IIC_BrMCRX. 10220b57cec5SDimitry Andric 10230b57cec5SDimitry Andric// Cracked, restricted, ALU operations. 10240b57cec5SDimitry Andric// Here the two ALU ops can actually be done in parallel and therefore the 10250b57cec5SDimitry Andric// latencies are not added together. Otherwise this is like having two 10260b57cec5SDimitry Andric// instructions running together on two pipelines and 6 dispatches. ALU ops are 10270b57cec5SDimitry Andric// 2 cycles each. 10280b57cec5SDimitry Andricdef : InstRW<[P9_ALU_2C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C, 10290b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_3SLOTS_1C], 10300b57cec5SDimitry Andric (instrs 10310b57cec5SDimitry Andric MTCRF, 10320b57cec5SDimitry Andric MTCRF8 10330b57cec5SDimitry Andric)>; 10340b57cec5SDimitry Andric 10350b57cec5SDimitry Andric// Cracked ALU operations. 10360b57cec5SDimitry Andric// Here the two ALU ops can actually be done in parallel and therefore the 10370b57cec5SDimitry Andric// latencies are not added together. Otherwise this is like having two 10380b57cec5SDimitry Andric// instructions running together on two pipelines and 2 dispatches. ALU ops are 10390b57cec5SDimitry Andric// 2 cycles each. 10400b57cec5SDimitry Andricdef : InstRW<[P9_ALU_2C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C, 10410b57cec5SDimitry Andric DISP_1C, DISP_1C], 10420b57cec5SDimitry Andric (instrs 1043480093f4SDimitry Andric (instregex "ADDC(8)?(O)?_rec$"), 1044480093f4SDimitry Andric (instregex "SUBFC(8)?(O)?_rec$") 10450b57cec5SDimitry Andric)>; 10460b57cec5SDimitry Andric 10470b57cec5SDimitry Andric// Cracked ALU operations. 10480b57cec5SDimitry Andric// Two ALU ops can be done in parallel. 10490b57cec5SDimitry Andric// One is three cycle ALU the ohter is a two cycle ALU. 10500b57cec5SDimitry Andric// One of the ALU ops is restricted the other is not so we have a total of 10510b57cec5SDimitry Andric// 5 dispatches. 10520b57cec5SDimitry Andricdef : InstRW<[P9_ALU_2C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C, 10530b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_1C], 10540b57cec5SDimitry Andric (instrs 1055480093f4SDimitry Andric (instregex "F(N)?ABS(D|S)_rec$"), 1056480093f4SDimitry Andric (instregex "FCPSGN(D|S)_rec$"), 1057480093f4SDimitry Andric (instregex "FNEG(D|S)_rec$"), 1058480093f4SDimitry Andric FMR_rec 10590b57cec5SDimitry Andric)>; 10600b57cec5SDimitry Andric 10610b57cec5SDimitry Andric// Cracked ALU operations. 10620b57cec5SDimitry Andric// Here the two ALU ops can actually be done in parallel and therefore the 10630b57cec5SDimitry Andric// latencies are not added together. Otherwise this is like having two 10640b57cec5SDimitry Andric// instructions running together on two pipelines and 2 dispatches. 10650b57cec5SDimitry Andric// ALU ops are 3 cycles each. 10660b57cec5SDimitry Andricdef : InstRW<[P9_ALU_3C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C, 10670b57cec5SDimitry Andric DISP_1C, DISP_1C], 10680b57cec5SDimitry Andric (instrs 10690b57cec5SDimitry Andric MCRFS 10700b57cec5SDimitry Andric)>; 10710b57cec5SDimitry Andric 10720b57cec5SDimitry Andric// Cracked Restricted ALU operations. 10730b57cec5SDimitry Andric// Here the two ALU ops can actually be done in parallel and therefore the 10740b57cec5SDimitry Andric// latencies are not added together. Otherwise this is like having two 10750b57cec5SDimitry Andric// instructions running together on two pipelines and 6 dispatches. 10760b57cec5SDimitry Andric// ALU ops are 3 cycles each. 10770b57cec5SDimitry Andricdef : InstRW<[P9_ALU_3C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C, 10780b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_3SLOTS_1C], 10790b57cec5SDimitry Andric (instrs 1080480093f4SDimitry Andric (instregex "MTFSF(b|_rec)?$"), 1081fe6060f1SDimitry Andric (instregex "MTFSFI(_rec)?$"), 1082fe6060f1SDimitry Andric MTFSFIb 10830b57cec5SDimitry Andric)>; 10840b57cec5SDimitry Andric 10850b57cec5SDimitry Andric// Cracked instruction made of two ALU ops. 10860b57cec5SDimitry Andric// The two ops cannot be done in parallel. 10870b57cec5SDimitry Andric// One of the ALU ops is restricted and takes 3 dispatches. 10880b57cec5SDimitry Andricdef : InstRW<[P9_ALUOpAndALUOp_4C, IP_EXEC_1C, IP_EXEC_1C, 10890b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_1C], 10900b57cec5SDimitry Andric (instrs 1091480093f4SDimitry Andric (instregex "RLD(I)?C(R|L)_rec$"), 1092480093f4SDimitry Andric (instregex "RLW(IMI|INM|NM)(8)?_rec$"), 1093480093f4SDimitry Andric (instregex "SLW(8)?_rec$"), 1094480093f4SDimitry Andric (instregex "SRAW(I)?_rec$"), 1095480093f4SDimitry Andric (instregex "SRW(8)?_rec$"), 1096480093f4SDimitry Andric RLDICL_32_rec, 1097480093f4SDimitry Andric RLDIMI_rec 10980b57cec5SDimitry Andric)>; 10990b57cec5SDimitry Andric 11000b57cec5SDimitry Andric// Cracked instruction made of two ALU ops. 11010b57cec5SDimitry Andric// The two ops cannot be done in parallel. 11020b57cec5SDimitry Andric// Both of the ALU ops are restricted and take 3 dispatches. 11030b57cec5SDimitry Andricdef : InstRW<[P9_ALU2OpAndALU2Op_6C, IP_EXEC_1C, IP_EXEC_1C, 11040b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_3SLOTS_1C], 11050b57cec5SDimitry Andric (instrs 1106480093f4SDimitry Andric (instregex "MFFS(L|CE|_rec)?$") 11070b57cec5SDimitry Andric)>; 11080b57cec5SDimitry Andric 11090b57cec5SDimitry Andric// Cracked ALU instruction composed of three consecutive 2 cycle loads for a 11100b57cec5SDimitry Andric// total of 6 cycles. All of the ALU operations are also restricted so each 11110b57cec5SDimitry Andric// takes 3 dispatches for a total of 9. 11120b57cec5SDimitry Andricdef : InstRW<[P9_ALUOpAndALUOpAndALUOp_6C, IP_EXEC_1C, IP_EXEC_1C, IP_EXEC_1C, 11130b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_3SLOTS_1C, DISP_3SLOTS_1C], 11140b57cec5SDimitry Andric (instrs 11150b57cec5SDimitry Andric (instregex "MFCR(8)?$") 11160b57cec5SDimitry Andric)>; 11170b57cec5SDimitry Andric 11180b57cec5SDimitry Andric// Cracked instruction made of two ALU ops. 11190b57cec5SDimitry Andric// The two ops cannot be done in parallel. 11200b57cec5SDimitry Andricdef : InstRW<[P9_ALUOpAndALUOp_4C, IP_EXEC_1C, IP_EXEC_1C, DISP_1C, DISP_1C], 11210b57cec5SDimitry Andric (instrs 1122480093f4SDimitry Andric (instregex "EXTSWSLI_32_64_rec$"), 1123480093f4SDimitry Andric (instregex "SRAD(I)?_rec$"), 1124480093f4SDimitry Andric EXTSWSLI_rec, 1125480093f4SDimitry Andric SLD_rec, 1126480093f4SDimitry Andric SRD_rec, 1127480093f4SDimitry Andric RLDIC_rec 11280b57cec5SDimitry Andric)>; 11290b57cec5SDimitry Andric 11300b57cec5SDimitry Andric// 33 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches. 11310b57cec5SDimitry Andricdef : InstRW<[P9_DP_33C_8, IP_EXEC_1C, DISP_3SLOTS_1C], 11320b57cec5SDimitry Andric (instrs 11330b57cec5SDimitry Andric FDIV 11340b57cec5SDimitry Andric)>; 11350b57cec5SDimitry Andric 11360b57cec5SDimitry Andric// 33 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU. 11370b57cec5SDimitry Andricdef : InstRW<[P9_DPOpAndALU2Op_36C_8, IP_EXEC_1C, IP_EXEC_1C, 11380b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_1C], 11390b57cec5SDimitry Andric (instrs 1140480093f4SDimitry Andric FDIV_rec 11410b57cec5SDimitry Andric)>; 11420b57cec5SDimitry Andric 11430b57cec5SDimitry Andric// 36 Cycle DP Instruction. 11440b57cec5SDimitry Andric// Instruction can be done on a single slice. 11450b57cec5SDimitry Andricdef : InstRW<[P9_DP_36C_10, IP_EXEC_1C, DISP_1C], 11460b57cec5SDimitry Andric (instrs 11470b57cec5SDimitry Andric XSSQRTDP 11480b57cec5SDimitry Andric)>; 11490b57cec5SDimitry Andric 11500b57cec5SDimitry Andric// 36 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches. 11510b57cec5SDimitry Andricdef : InstRW<[P9_DP_36C_10, IP_EXEC_1C, DISP_3SLOTS_1C], 11520b57cec5SDimitry Andric (instrs 11530b57cec5SDimitry Andric FSQRT 11540b57cec5SDimitry Andric)>; 11550b57cec5SDimitry Andric 11560b57cec5SDimitry Andric// 36 Cycle DP Vector Instruction. 11570b57cec5SDimitry Andricdef : InstRW<[P9_DPE_36C_10, P9_DPO_36C_10, IP_EXECE_1C, IP_EXECO_1C, 11580b57cec5SDimitry Andric DISP_1C], 11590b57cec5SDimitry Andric (instrs 11600b57cec5SDimitry Andric XVSQRTDP 11610b57cec5SDimitry Andric)>; 11620b57cec5SDimitry Andric 11630b57cec5SDimitry Andric// 27 Cycle DP Vector Instruction. 11640b57cec5SDimitry Andricdef : InstRW<[P9_DPE_27C_10, P9_DPO_27C_10, IP_EXECE_1C, IP_EXECO_1C, 11650b57cec5SDimitry Andric DISP_1C], 11660b57cec5SDimitry Andric (instrs 11670b57cec5SDimitry Andric XVSQRTSP 11680b57cec5SDimitry Andric)>; 11690b57cec5SDimitry Andric 11700b57cec5SDimitry Andric// 36 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU. 11710b57cec5SDimitry Andricdef : InstRW<[P9_DPOpAndALU2Op_39C_10, IP_EXEC_1C, IP_EXEC_1C, 11720b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_1C], 11730b57cec5SDimitry Andric (instrs 1174480093f4SDimitry Andric FSQRT_rec 11750b57cec5SDimitry Andric)>; 11760b57cec5SDimitry Andric 11770b57cec5SDimitry Andric// 26 Cycle DP Instruction. 11780b57cec5SDimitry Andricdef : InstRW<[P9_DP_26C_5, IP_EXEC_1C, DISP_1C], 11790b57cec5SDimitry Andric (instrs 11800b57cec5SDimitry Andric XSSQRTSP 11810b57cec5SDimitry Andric)>; 11820b57cec5SDimitry Andric 11830b57cec5SDimitry Andric// 26 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches. 11840b57cec5SDimitry Andricdef : InstRW<[P9_DP_26C_5, IP_EXEC_1C, DISP_3SLOTS_1C], 11850b57cec5SDimitry Andric (instrs 11860b57cec5SDimitry Andric FSQRTS 11870b57cec5SDimitry Andric)>; 11880b57cec5SDimitry Andric 11890b57cec5SDimitry Andric// 26 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU. 11900b57cec5SDimitry Andricdef : InstRW<[P9_DPOpAndALU2Op_29C_5, IP_EXEC_1C, IP_EXEC_1C, 11910b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_1C], 11920b57cec5SDimitry Andric (instrs 1193480093f4SDimitry Andric FSQRTS_rec 11940b57cec5SDimitry Andric)>; 11950b57cec5SDimitry Andric 11960b57cec5SDimitry Andric// 33 Cycle DP Instruction. Takes one slice and 1 dispatch. 11970b57cec5SDimitry Andricdef : InstRW<[P9_DP_33C_8, IP_EXEC_1C, DISP_1C], 11980b57cec5SDimitry Andric (instrs 11990b57cec5SDimitry Andric XSDIVDP 12000b57cec5SDimitry Andric)>; 12010b57cec5SDimitry Andric 12020b57cec5SDimitry Andric// 22 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches. 12030b57cec5SDimitry Andricdef : InstRW<[P9_DP_22C_5, IP_EXEC_1C, DISP_3SLOTS_1C], 12040b57cec5SDimitry Andric (instrs 12050b57cec5SDimitry Andric FDIVS 12060b57cec5SDimitry Andric)>; 12070b57cec5SDimitry Andric 12080b57cec5SDimitry Andric// 22 Cycle DP Instruction Restricted and Cracked with 2 Cycle ALU. 12090b57cec5SDimitry Andricdef : InstRW<[P9_DPOpAndALU2Op_25C_5, IP_EXEC_1C, IP_EXEC_1C, 12100b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_1C], 12110b57cec5SDimitry Andric (instrs 1212480093f4SDimitry Andric FDIVS_rec 12130b57cec5SDimitry Andric)>; 12140b57cec5SDimitry Andric 12150b57cec5SDimitry Andric// 22 Cycle DP Instruction. Takes one slice and 1 dispatch. 12160b57cec5SDimitry Andricdef : InstRW<[P9_DP_22C_5, IP_EXEC_1C, DISP_1C], 12170b57cec5SDimitry Andric (instrs 12180b57cec5SDimitry Andric XSDIVSP 12190b57cec5SDimitry Andric)>; 12200b57cec5SDimitry Andric 12210b57cec5SDimitry Andric// 24 Cycle DP Vector Instruction. Takes one full superslice. 12220b57cec5SDimitry Andric// Includes both EXECE, EXECO pipelines and 1 dispatch for the given 12230b57cec5SDimitry Andric// superslice. 12240b57cec5SDimitry Andricdef : InstRW<[P9_DPE_24C_8, P9_DPO_24C_8, IP_EXECE_1C, IP_EXECO_1C, 12250b57cec5SDimitry Andric DISP_1C], 12260b57cec5SDimitry Andric (instrs 12270b57cec5SDimitry Andric XVDIVSP 12280b57cec5SDimitry Andric)>; 12290b57cec5SDimitry Andric 12300b57cec5SDimitry Andric// 33 Cycle DP Vector Instruction. Takes one full superslice. 12310b57cec5SDimitry Andric// Includes both EXECE, EXECO pipelines and 1 dispatch for the given 12320b57cec5SDimitry Andric// superslice. 12330b57cec5SDimitry Andricdef : InstRW<[P9_DPE_33C_8, P9_DPO_33C_8, IP_EXECE_1C, IP_EXECO_1C, 12340b57cec5SDimitry Andric DISP_1C], 12350b57cec5SDimitry Andric (instrs 12360b57cec5SDimitry Andric XVDIVDP 12370b57cec5SDimitry Andric)>; 12380b57cec5SDimitry Andric 12390b57cec5SDimitry Andric// Instruction cracked into three pieces. One Load and two ALU operations. 12400b57cec5SDimitry Andric// The Load and one of the ALU ops cannot be run at the same time and so the 12410b57cec5SDimitry Andric// latencies are added together for 6 cycles. The remainaing ALU is 2 cycles. 12420b57cec5SDimitry Andric// Both the load and the ALU that depends on it are restricted and so they take 12430b57cec5SDimitry Andric// a total of 7 dispatches. The final 2 dispatches come from the second ALU op. 12440b57cec5SDimitry Andric// The two EXEC pipelines are for the 2 ALUs while the AGEN is for the load. 12450b57cec5SDimitry Andricdef : InstRW<[P9_LoadAndALU2Op_7C, P9_ALU_2C, 12460b57cec5SDimitry Andric IP_AGEN_1C, IP_EXEC_1C, IP_EXEC_1C, 12470b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_3SLOTS_1C, DISP_1C], 12480b57cec5SDimitry Andric (instrs 12490b57cec5SDimitry Andric (instregex "LF(SU|SUX)$") 12500b57cec5SDimitry Andric)>; 12510b57cec5SDimitry Andric 12520b57cec5SDimitry Andric// Cracked instruction made up of a Store and an ALU. The ALU does not depend on 12530b57cec5SDimitry Andric// the store and so it can be run at the same time as the store. The store is 12540b57cec5SDimitry Andric// also restricted. 12550b57cec5SDimitry Andricdef : InstRW<[P9_LS_1C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C, IP_EXEC_1C, 12560b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_1C], 12570b57cec5SDimitry Andric (instrs 12580b57cec5SDimitry Andric (instregex "STF(S|D)U(X)?$"), 12590b57cec5SDimitry Andric (instregex "ST(B|H|W|D)U(X)?(8)?$") 12600b57cec5SDimitry Andric)>; 12610b57cec5SDimitry Andric 12620b57cec5SDimitry Andric// Cracked instruction made up of a Load and an ALU. The ALU does not depend on 12630b57cec5SDimitry Andric// the load and so it can be run at the same time as the load. 12640b57cec5SDimitry Andricdef : InstRW<[P9_LS_4C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C, 12650b57cec5SDimitry Andric DISP_PAIR_1C, DISP_PAIR_1C], 12660b57cec5SDimitry Andric (instrs 12670b57cec5SDimitry Andric (instregex "LBZU(X)?(8)?$"), 12680b57cec5SDimitry Andric (instregex "LDU(X)?$") 12690b57cec5SDimitry Andric)>; 12700b57cec5SDimitry Andric 12710b57cec5SDimitry Andric// Cracked instruction made up of a Load and an ALU. The ALU does not depend on 12720b57cec5SDimitry Andric// the load and so it can be run at the same time as the load. The load is also 12730b57cec5SDimitry Andric// restricted. 3 dispatches are from the restricted load while the other two 12740b57cec5SDimitry Andric// are from the ALU. The AGEN pipeline is from the load and the EXEC pipeline 12750b57cec5SDimitry Andric// is required for the ALU. 12760b57cec5SDimitry Andricdef : InstRW<[P9_LS_4C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C, 12770b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_1C], 12780b57cec5SDimitry Andric (instrs 12790b57cec5SDimitry Andric (instregex "LF(DU|DUX)$") 12800b57cec5SDimitry Andric)>; 12810b57cec5SDimitry Andric 12820b57cec5SDimitry Andric// Crypto Instructions 12830b57cec5SDimitry Andric 12840b57cec5SDimitry Andric// 6 Cycle CY operation. Only one CY unit per CPU so we use a whole 12850b57cec5SDimitry Andric// superslice. That includes both exec pipelines (EXECO, EXECE) and one 12860b57cec5SDimitry Andric// dispatch. 12870b57cec5SDimitry Andricdef : InstRW<[P9_CY_6C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C], 12880b57cec5SDimitry Andric (instrs 12890b57cec5SDimitry Andric (instregex "VPMSUM(B|H|W|D)$"), 12900b57cec5SDimitry Andric (instregex "V(N)?CIPHER(LAST)?$"), 12910b57cec5SDimitry Andric VSBOX 12920b57cec5SDimitry Andric)>; 12930b57cec5SDimitry Andric 12940b57cec5SDimitry Andric// Branch Instructions 12950b57cec5SDimitry Andric 12960b57cec5SDimitry Andric// Two Cycle Branch 12970b57cec5SDimitry Andricdef : InstRW<[P9_BR_2C, DISP_BR_1C], 12980b57cec5SDimitry Andric (instrs 12990b57cec5SDimitry Andric (instregex "BCCCTR(L)?(8)?$"), 13000b57cec5SDimitry Andric (instregex "BCCL(A|R|RL)?$"), 13010b57cec5SDimitry Andric (instregex "BCCTR(L)?(8)?(n)?$"), 13020b57cec5SDimitry Andric (instregex "BD(N)?Z(8|A|Am|Ap|m|p)?$"), 13030b57cec5SDimitry Andric (instregex "BD(N)?ZL(A|Am|Ap|R|R8|RL|RLm|RLp|Rm|Rp|m|p)?$"), 1304349cc55cSDimitry Andric (instregex "BL(_TLS|_NOP)?(_RM)?$"), 1305349cc55cSDimitry Andric (instregex "BL8(_TLS|_NOP|_NOP_TLS|_TLS_)?(_RM)?$"), 1306349cc55cSDimitry Andric (instregex "BLA(8|8_NOP)?(_RM)?$"), 13070b57cec5SDimitry Andric (instregex "BLR(8|L)?$"), 13080b57cec5SDimitry Andric (instregex "TAILB(A)?(8)?$"), 13090b57cec5SDimitry Andric (instregex "TAILBCTR(8)?$"), 13100b57cec5SDimitry Andric (instregex "gBC(A|Aat|CTR|CTRL|L|LA|LAat|LR|LRL|Lat|at)?$"), 13110b57cec5SDimitry Andric (instregex "BCLR(L)?(n)?$"), 1312349cc55cSDimitry Andric (instregex "BCTR(L)?(8)?(_RM)?$"), 13130b57cec5SDimitry Andric B, 13140b57cec5SDimitry Andric BA, 13150b57cec5SDimitry Andric BC, 13160b57cec5SDimitry Andric BCC, 13170b57cec5SDimitry Andric BCCA, 13180b57cec5SDimitry Andric BCL, 13190b57cec5SDimitry Andric BCLalways, 13200b57cec5SDimitry Andric BCLn, 13210b57cec5SDimitry Andric BCTRL8_LDinto_toc, 1322480093f4SDimitry Andric BCTRL_LWZinto_toc, 1323349cc55cSDimitry Andric BCTRL8_LDinto_toc_RM, 1324349cc55cSDimitry Andric BCTRL_LWZinto_toc_RM, 13250b57cec5SDimitry Andric BCn, 13260b57cec5SDimitry Andric CTRL_DEP 13270b57cec5SDimitry Andric)>; 13280b57cec5SDimitry Andric 13290b57cec5SDimitry Andric// Five Cycle Branch with a 2 Cycle ALU Op 13300b57cec5SDimitry Andric// Operations must be done consecutively and not in parallel. 13310b57cec5SDimitry Andricdef : InstRW<[P9_BROpAndALUOp_7C, IP_EXEC_1C, DISP_BR_1C, DISP_1C], 13320b57cec5SDimitry Andric (instrs 13330b57cec5SDimitry Andric ADDPCIS 13340b57cec5SDimitry Andric)>; 13350b57cec5SDimitry Andric 13360b57cec5SDimitry Andric// Special Extracted Instructions For Atomics 13370b57cec5SDimitry Andric 13380b57cec5SDimitry Andric// Atomic Load 13390b57cec5SDimitry Andricdef : InstRW<[P9_LS_1C, P9_LS_1C, P9_LS_4C, P9_LS_4C, P9_LS_4C, 13400b57cec5SDimitry Andric IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C, IP_AGEN_1C, IP_AGEN_1C, 13410b57cec5SDimitry Andric IP_AGEN_1C, IP_AGEN_1C, DISP_1C, DISP_3SLOTS_1C, 13420b57cec5SDimitry Andric DISP_3SLOTS_1C, DISP_1C, DISP_1C, DISP_1C], 13430b57cec5SDimitry Andric (instrs 13440b57cec5SDimitry Andric (instregex "L(D|W)AT$") 13450b57cec5SDimitry Andric)>; 13460b57cec5SDimitry Andric 13470b57cec5SDimitry Andric// Atomic Store 13480b57cec5SDimitry Andricdef : InstRW<[P9_LS_1C, P9_LS_4C, P9_LS_4C, IP_EXEC_1C, IP_AGEN_1C, IP_AGEN_1C, 13490b57cec5SDimitry Andric IP_AGEN_1C, DISP_1C, DISP_3SLOTS_1C, DISP_1C], 13500b57cec5SDimitry Andric (instrs 13510b57cec5SDimitry Andric (instregex "ST(D|W)AT$") 13520b57cec5SDimitry Andric)>; 13530b57cec5SDimitry Andric 13540b57cec5SDimitry Andric// Signal Processing Engine (SPE) Instructions 13550b57cec5SDimitry Andric// These instructions are not supported on Power 9 13560b57cec5SDimitry Andricdef : InstRW<[], 13570b57cec5SDimitry Andric (instrs 13580b57cec5SDimitry Andric BRINC, 13590b57cec5SDimitry Andric EVABS, 13600b57cec5SDimitry Andric EVEQV, 13610b57cec5SDimitry Andric EVMRA, 13620b57cec5SDimitry Andric EVNAND, 13630b57cec5SDimitry Andric EVNEG, 13640b57cec5SDimitry Andric (instregex "EVADD(I)?W$"), 13650b57cec5SDimitry Andric (instregex "EVADD(SM|SS|UM|US)IAAW$"), 13660b57cec5SDimitry Andric (instregex "EVAND(C)?$"), 13670b57cec5SDimitry Andric (instregex "EVCMP(EQ|GTS|GTU|LTS|LTU)$"), 13680b57cec5SDimitry Andric (instregex "EVCNTL(S|Z)W$"), 13690b57cec5SDimitry Andric (instregex "EVDIVW(S|U)$"), 13700b57cec5SDimitry Andric (instregex "EVEXTS(B|H)$"), 13710b57cec5SDimitry Andric (instregex "EVLD(H|W|D)(X)?$"), 13720b57cec5SDimitry Andric (instregex "EVLHH(E|OS|OU)SPLAT(X)?$"), 13730b57cec5SDimitry Andric (instregex "EVLWHE(X)?$"), 13740b57cec5SDimitry Andric (instregex "EVLWHO(S|U)(X)?$"), 13750b57cec5SDimitry Andric (instregex "EVLW(H|W)SPLAT(X)?$"), 13760b57cec5SDimitry Andric (instregex "EVMERGE(HI|LO|HILO|LOHI)$"), 13770b57cec5SDimitry Andric (instregex "EVMHEG(S|U)M(F|I)A(A|N)$"), 13780b57cec5SDimitry Andric (instregex "EVMHES(M|S)(F|I)(A|AA|AAW|ANW)?$"), 13790b57cec5SDimitry Andric (instregex "EVMHEU(M|S)I(A|AA|AAW|ANW)?$"), 13800b57cec5SDimitry Andric (instregex "EVMHOG(U|S)M(F|I)A(A|N)$"), 13810b57cec5SDimitry Andric (instregex "EVMHOS(M|S)(F|I)(A|AA|AAW|ANW)?$"), 13820b57cec5SDimitry Andric (instregex "EVMHOU(M|S)I(A|AA|ANW|AAW)?$"), 13830b57cec5SDimitry Andric (instregex "EVMWHS(M|S)(F|FA|I|IA)$"), 13840b57cec5SDimitry Andric (instregex "EVMWHUMI(A)?$"), 13850b57cec5SDimitry Andric (instregex "EVMWLS(M|S)IA(A|N)W$"), 13860b57cec5SDimitry Andric (instregex "EVMWLU(M|S)I(A|AA|AAW|ANW)?$"), 13870b57cec5SDimitry Andric (instregex "EVMWSM(F|I)(A|AA|AN)?$"), 13880b57cec5SDimitry Andric (instregex "EVMWSSF(A|AA|AN)?$"), 13890b57cec5SDimitry Andric (instregex "EVMWUMI(A|AA|AN)?$"), 13900b57cec5SDimitry Andric (instregex "EV(N|X)?OR(C)?$"), 13910b57cec5SDimitry Andric (instregex "EVR(LW|LWI|NDW)$"), 13920b57cec5SDimitry Andric (instregex "EVSLW(I)?$"), 13930b57cec5SDimitry Andric (instregex "EVSPLAT(F)?I$"), 13940b57cec5SDimitry Andric (instregex "EVSRW(I)?(S|U)$"), 13950b57cec5SDimitry Andric (instregex "EVST(DD|DH|DW|WHE|WHO|WWE|WWO)(X)?$"), 13960b57cec5SDimitry Andric (instregex "EVSUBF(S|U)(M|S)IAAW$"), 13970b57cec5SDimitry Andric (instregex "EVSUB(I)?FW$") 13980b57cec5SDimitry Andric)> { let Unsupported = 1; } 13990b57cec5SDimitry Andric 14000b57cec5SDimitry Andric// General Instructions without scheduling support. 14010b57cec5SDimitry Andricdef : InstRW<[], 14020b57cec5SDimitry Andric (instrs 14030b57cec5SDimitry Andric (instregex "(H)?RFI(D)?$"), 14040b57cec5SDimitry Andric (instregex "DSS(ALL)?$"), 14050b57cec5SDimitry Andric (instregex "DST(ST)?(T)?(64)?$"), 14060b57cec5SDimitry Andric (instregex "ICBL(C|Q)$"), 14070b57cec5SDimitry Andric (instregex "L(W|H|B)EPX$"), 14080b57cec5SDimitry Andric (instregex "ST(W|H|B)EPX$"), 14090b57cec5SDimitry Andric (instregex "(L|ST)FDEPX$"), 14100b57cec5SDimitry Andric (instregex "M(T|F)SR(IN)?$"), 14110b57cec5SDimitry Andric (instregex "M(T|F)DCR$"), 14120b57cec5SDimitry Andric (instregex "NOP_GT_PWR(6|7)$"), 14130b57cec5SDimitry Andric (instregex "TLB(IA|IVAX|SX|SX2|SX2D|LD|LI|RE|RE2|WE|WE2)$"), 14140b57cec5SDimitry Andric (instregex "WRTEE(I)?$"), 141504eeddc0SDimitry Andric (instregex "HASH(ST|STP|CHK|CHKP)(8)?$"), 14160b57cec5SDimitry Andric ATTN, 14170b57cec5SDimitry Andric CLRBHRB, 14180b57cec5SDimitry Andric MFBHRBE, 14190b57cec5SDimitry Andric MBAR, 14200b57cec5SDimitry Andric MSYNC, 14210b57cec5SDimitry Andric SLBSYNC, 1422480093f4SDimitry Andric SLBFEE_rec, 14230b57cec5SDimitry Andric NAP, 14240b57cec5SDimitry Andric STOP, 14250b57cec5SDimitry Andric TRAP, 14260b57cec5SDimitry Andric RFCI, 14270b57cec5SDimitry Andric RFDI, 14280b57cec5SDimitry Andric RFMCI, 14290b57cec5SDimitry Andric SC, 14300b57cec5SDimitry Andric DCBA, 14310b57cec5SDimitry Andric DCBI, 14320b57cec5SDimitry Andric DCCCI, 1433fe6060f1SDimitry Andric ICCCI, 1434349cc55cSDimitry Andric ADDEX, 143506c3fb27SDimitry Andric ADDEX8, 143606c3fb27SDimitry Andric CDTBCD, CDTBCD8, 143706c3fb27SDimitry Andric CBCDTD, CBCDTD8, 143806c3fb27SDimitry Andric ADDG6S, ADDG6S8 14390b57cec5SDimitry Andric)> { let Unsupported = 1; } 1440