1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This is the top level entry point for the PowerPC target.
10//
11//===----------------------------------------------------------------------===//
12
13// Get the target-independent interfaces which we are implementing.
14//
15include "llvm/Target/Target.td"
16
17//===----------------------------------------------------------------------===//
18// PowerPC Subtarget features.
19//
20
21//===----------------------------------------------------------------------===//
22// CPU Directives                                                             //
23//===----------------------------------------------------------------------===//
24
25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">;
26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">;
27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">;
28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">;
32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">;
33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">;
34def Directive32  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">;
35def Directive64  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">;
36def DirectiveA2  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">;
37def DirectiveE500   : SubtargetFeature<"", "CPUDirective",
38                                       "PPC::DIR_E500", "">;
39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective",
40                                       "PPC::DIR_E500mc", "">;
41def DirectiveE5500  : SubtargetFeature<"", "CPUDirective",
42                                       "PPC::DIR_E5500", "">;
43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">;
44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">;
45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">;
46def DirectivePwr5x
47    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">;
48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">;
49def DirectivePwr6x
50    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">;
51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">;
52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">;
53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">;
54def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">;
55def DirectivePwrFuture
56    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;
57
58// Specifies that the selected CPU supports 64-bit instructions, regardless of
59// whether we are in 32-bit or 64-bit mode.
60def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
61                                        "Enable 64-bit instructions">;
62def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">;
63def FeatureModernAIXAs
64    : SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true",
65                       "AIX system assembler is modern enough to support new mnes">;
66def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
67                              "Enable floating-point instructions">;
68
69// Specifies that we are in 64-bit mode or that we should use 64-bit registers
70// in 32-bit mode when possible. Requires Feature64Bit to be enabled.
71def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
72                              "Enable 64-bit registers usage for ppc32 [beta]">;
73
74// Specify if we should store and manipulate i1 values in the individual
75// condition register bits.
76def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
77                              "Use condition-register bits individually">;
78def FeatureFPU       : SubtargetFeature<"fpu","HasFPU","true",
79                                        "Enable classic FPU instructions",
80                                        [FeatureHardFloat]>;
81def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
82                                        "Enable Altivec instructions",
83                                        [FeatureFPU]>;
84def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
85                                        "Enable SPE instructions",
86                                        [FeatureHardFloat]>;
87def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true",
88                                        "Enable Embedded Floating-Point APU 2 instructions",
89                                        [FeatureSPE]>;
90def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
91                                        "Enable the MFOCRF instruction">;
92def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
93                                        "Enable the fsqrt instruction",
94                                        [FeatureFPU]>;
95def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
96                                        "Enable the fcpsgn instruction",
97                                        [FeatureFPU]>;
98def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
99                                        "Enable the fre instruction",
100                                        [FeatureFPU]>;
101def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
102                                        "Enable the fres instruction",
103                                        [FeatureFPU]>;
104def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
105                                        "Enable the frsqrte instruction",
106                                        [FeatureFPU]>;
107def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
108                                        "Enable the frsqrtes instruction",
109                                        [FeatureFPU]>;
110def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
111                              "Assume higher precision reciprocal estimates">;
112def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
113                                        "Enable the stfiwx instruction",
114                                        [FeatureFPU]>;
115def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
116                                        "Enable the lfiwax instruction",
117                                        [FeatureFPU]>;
118def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
119                                        "Enable the fri[mnpz] instructions",
120                                        [FeatureFPU]>;
121def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
122  "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
123                                        [FeatureFPU]>;
124def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
125                                        "Enable the isel instruction">;
126def FeatureBPERMD    : SubtargetFeature<"bpermd", "HasBPERMD", "true",
127                                        "Enable the bpermd instruction">;
128def FeatureExtDiv    : SubtargetFeature<"extdiv", "HasExtDiv", "true",
129                                        "Enable extended divide instructions">;
130def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
131                                        "Enable the ldbrx instruction">;
132def FeatureCMPB      : SubtargetFeature<"cmpb", "HasCMPB", "true",
133                                        "Enable the cmpb instruction">;
134def FeatureICBT      : SubtargetFeature<"icbt","HasICBT", "true",
135                                        "Enable icbt instruction">;
136def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
137                                        "Enable Book E instructions",
138                                        [FeatureICBT]>;
139def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
140                              "Has only the msync instruction instead of sync",
141                              [FeatureBookE]>;
142def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
143                                        "Enable E500/E500mc instructions">;
144def FeatureSecurePlt : SubtargetFeature<"secure-plt","IsSecurePlt", "true",
145                                        "Enable secure plt mode">;
146def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
147                                        "Enable PPC 4xx instructions">;
148def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
149                                        "Enable PPC 6xx instructions">;
150def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
151                                        "Enable VSX instructions",
152                                        [FeatureAltivec]>;
153def FeatureTwoConstNR :
154  SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true",
155                   "Requires two constant Newton-Raphson computation">;
156def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
157                                        "Enable POWER8 Altivec instructions",
158                                        [FeatureAltivec]>;
159def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
160                                       "Enable POWER8 Crypto instructions",
161                                       [FeatureP8Altivec]>;
162def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
163                                        "Enable POWER8 vector instructions",
164                                        [FeatureVSX, FeatureP8Altivec]>;
165def FeatureDirectMove :
166  SubtargetFeature<"direct-move", "HasDirectMove", "true",
167                   "Enable Power8 direct move instructions",
168                   [FeatureVSX]>;
169def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
170                                             "HasPartwordAtomics", "true",
171                                             "Enable l[bh]arx and st[bh]cx.">;
172def FeatureQuadwordAtomic : SubtargetFeature<"quadword-atomics",
173                                             "HasQuadwordAtomics", "true",
174                                             "Enable lqarx and stqcx.">;
175def FeatureInvariantFunctionDescriptors :
176  SubtargetFeature<"invariant-function-descriptors",
177                   "HasInvariantFunctionDescriptors", "true",
178                   "Assume function descriptors are invariant">;
179def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
180                                       "Always use indirect calls">;
181def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
182                                  "Enable Hardware Transactional Memory instructions">;
183def FeatureMFTB   : SubtargetFeature<"", "IsFeatureMFTB", "true",
184                                        "Implement mftb using the mfspr instruction">;
185def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
186                                     "Target supports instruction fusion">;
187def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load",
188                                             "HasAddiLoadFusion", "true",
189                                             "Power8 Addi-Load fusion",
190                                             [FeatureFusion]>;
191def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load",
192                                              "HasAddisLoadFusion", "true",
193                                              "Power8 Addis-Load fusion",
194                                              [FeatureFusion]>;
195def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true",
196                                          "Target supports store clustering",
197                                          [FeatureFusion]>;
198def FeatureArithAddFusion :
199  SubtargetFeature<"fuse-arith-add", "HasArithAddFusion", "true",
200                   "Target supports Arithmetic Operations with Add fusion",
201                   [FeatureFusion]>;
202def FeatureAddLogicalFusion :
203  SubtargetFeature<"fuse-add-logical", "HasAddLogicalFusion", "true",
204                   "Target supports Add with Logical Operations fusion",
205                   [FeatureFusion]>;
206def FeatureLogicalAddFusion :
207  SubtargetFeature<"fuse-logical-add", "HasLogicalAddFusion", "true",
208                   "Target supports Logical with Add Operations fusion",
209                   [FeatureFusion]>;
210def FeatureLogicalFusion :
211  SubtargetFeature<"fuse-logical", "HasLogicalFusion", "true",
212                   "Target supports Logical Operations fusion",
213                   [FeatureFusion]>;
214def FeatureSha3Fusion :
215  SubtargetFeature<"fuse-sha3", "HasSha3Fusion", "true",
216                   "Target supports SHA3 assist fusion",
217                   [FeatureFusion]>;
218def FeatureCompareFusion:
219  SubtargetFeature<"fuse-cmp", "HasCompareFusion", "true",
220                   "Target supports Comparison Operations fusion",
221                   [FeatureFusion]>;
222def FeatureWideImmFusion:
223  SubtargetFeature<"fuse-wideimm", "HasWideImmFusion", "true",
224                   "Target supports Wide-Immediate fusion",
225                   [FeatureFusion]>;
226def FeatureZeroMoveFusion:
227  SubtargetFeature<"fuse-zeromove", "HasZeroMoveFusion", "true",
228                   "Target supports move to SPR with branch fusion",
229                   [FeatureFusion]>;
230def FeatureBack2BackFusion:
231  SubtargetFeature<"fuse-back2back", "HasBack2BackFusion", "true",
232                   "Target supports general back to back fusion",
233                   [FeatureFusion]>;
234def FeatureUnalignedFloats :
235  SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess",
236                   "true", "CPU does not trap on unaligned FP access">;
237def FeaturePPCPreRASched:
238  SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true",
239                   "Use PowerPC pre-RA scheduling strategy">;
240def FeaturePPCPostRASched:
241  SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true",
242                   "Use PowerPC post-RA scheduling strategy">;
243def FeatureFloat128 :
244  SubtargetFeature<"float128", "HasFloat128", "true",
245                   "Enable the __float128 data type for IEEE-754R Binary128.",
246                   [FeatureVSX]>;
247def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD",
248                                        "POPCNTD_Fast",
249                                        "Enable the popcnt[dw] instructions">;
250// Note that for the a2 processor models we should not use popcnt[dw] by
251// default. These processors do support the instructions, but they're
252// microcoded, and the software emulation is about twice as fast.
253def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
254                                          "POPCNTD_Slow",
255                                          "Has slow popcnt[dw] instructions">;
256
257def DeprecatedDST    : SubtargetFeature<"", "IsDeprecatedDST", "true",
258  "Treat vector data stream cache control instructions as deprecated">;
259
260def FeatureISA2_06 : SubtargetFeature<"isa-v206-instructions", "IsISA2_06",
261                                      "true",
262                                      "Enable instructions in ISA 2.06.">;
263def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07",
264                                      "true",
265                                      "Enable instructions in ISA 2.07.">;
266def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
267                                     "true",
268                                     "Enable instructions in ISA 3.0.",
269                                     [FeatureISA2_07]>;
270def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1",
271                                     "true",
272                                     "Enable instructions in ISA 3.1.",
273                                     [FeatureISA3_0]>;
274def FeatureISAFuture : SubtargetFeature<"isa-future-instructions",
275                                        "IsISAFuture", "true",
276                                        "Enable instructions for Future ISA.",
277                                        [FeatureISA3_1]>;
278def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
279                                        "Enable POWER9 Altivec instructions",
280                                        [FeatureISA3_0, FeatureP8Altivec]>;
281def FeatureP9Vector  : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
282                                        "Enable POWER9 vector instructions",
283                                        [FeatureISA3_0, FeatureP8Vector,
284                                         FeatureP9Altivec]>;
285def FeatureP10Vector  : SubtargetFeature<"power10-vector", "HasP10Vector",
286                                         "true",
287                                         "Enable POWER10 vector instructions",
288                                         [FeatureISA3_1, FeatureP9Vector]>;
289// A separate feature for this even though it is equivalent to P9Vector
290// because this is a feature of the implementation rather than the architecture
291// and may go away with future CPU's.
292def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
293                                                 "VectorsUseTwoUnits",
294                                                 "true",
295                                                 "Vectors use two units">;
296def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs",
297                                           "true",
298                                           "Enable prefixed instructions",
299                                           [FeatureISA3_0, FeatureP8Vector,
300                                            FeatureP9Altivec]>;
301def FeaturePCRelativeMemops :
302  SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
303                   "Enable PC relative Memory Ops",
304                   [FeatureISA3_0, FeaturePrefixInstrs]>;
305def FeaturePairedVectorMemops:
306  SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
307                   "32Byte load and store instructions",
308                   [FeatureISA3_0]>;
309def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true",
310                                  "Enable MMA instructions",
311                                  [FeatureP8Vector, FeatureP9Altivec,
312                                   FeaturePairedVectorMemops]>;
313def FeatureROPProtect :
314  SubtargetFeature<"rop-protect", "HasROPProtect", "true",
315                   "Add ROP protect">;
316
317def FeaturePrivileged :
318  SubtargetFeature<"privileged", "HasPrivileged", "true",
319                   "Add privileged instructions">;
320
321// Specifies that local-exec TLS accesses in any function with this target
322// attribute should use the optimized TOC-free sequence (where the offset is an
323// immediate off of R13 for which the linker might add fix-up code if the
324// immediate is too large).
325// Clearly, this isn't really a feature of the subtarget, but is used as a
326// convenient way to affect code generation for individual functions.
327def FeatureAIXLocalExecTLS :
328  SubtargetFeature<"aix-small-local-exec-tls", "HasAIXSmallLocalExecTLS", "true",
329                   "Produce a TOC-free local-exec TLS sequence for this function "
330                   "for 64-bit AIX">;
331
332def FeaturePredictableSelectIsExpensive :
333  SubtargetFeature<"predictable-select-expensive",
334                   "PredictableSelectIsExpensive",
335                   "true",
336                   "Prefer likely predicted branches over selects">;
337
338def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true",
339                                       "MFLR is a fast instruction">;
340
341// Since new processors generally contain a superset of features of those that
342// came before them, the idea is to make implementations of new processors
343// less error prone and easier to read.
344// Namely:
345//     list<SubtargetFeature> P8InheritableFeatures = ...
346//     list<SubtargetFeature> FutureProcessorAddtionalFeatures =
347//         [ features that Power8 does not support but inheritable ]
348//     list<SubtargetFeature> FutureProcessorSpecificFeatures =
349//         [ features that Power8 does not support and not inheritable ]
350//     list<SubtargetFeature> FutureProcessorInheritableFeatures =
351//         !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures)
352//     list<SubtargetFeature> FutureProcessorFeatures =
353//         !listconcat(FutureProcessorInheritableFeatures,
354//                     FutureProcessorSpecificFeatures)
355
356// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as
357// well as providing a single point of definition if the feature set will be
358// used elsewhere.
359def ProcessorFeatures {
360  // Power7
361  list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7,
362                                                  FeatureAltivec,
363                                                  FeatureVSX,
364                                                  FeatureMFOCRF,
365                                                  FeatureFCPSGN,
366                                                  FeatureFSqrt,
367                                                  FeatureFRE,
368                                                  FeatureFRES,
369                                                  FeatureFRSQRTE,
370                                                  FeatureFRSQRTES,
371                                                  FeatureRecipPrec,
372                                                  FeatureSTFIWX,
373                                                  FeatureLFIWAX,
374                                                  FeatureFPRND,
375                                                  FeatureFPCVT,
376                                                  FeatureISEL,
377                                                  FeaturePOPCNTD,
378                                                  FeatureCMPB,
379                                                  FeatureLDBRX,
380                                                  Feature64Bit,
381                                                  /* Feature64BitRegs, */
382                                                  FeatureBPERMD,
383                                                  FeatureExtDiv,
384                                                  FeatureMFTB,
385                                                  DeprecatedDST,
386                                                  FeatureTwoConstNR,
387                                                  FeatureUnalignedFloats,
388                                                  FeatureISA2_06];
389  list<SubtargetFeature> P7SpecificFeatures = [];
390  list<SubtargetFeature> P7Features =
391    !listconcat(P7InheritableFeatures, P7SpecificFeatures);
392
393  // Power8
394  list<SubtargetFeature> P8AdditionalFeatures =
395    [DirectivePwr8,
396     FeatureP8Altivec,
397     FeatureP8Vector,
398     FeatureP8Crypto,
399     FeatureHTM,
400     FeatureDirectMove,
401     FeatureICBT,
402     FeaturePartwordAtomic,
403     FeatureQuadwordAtomic,
404     FeaturePredictableSelectIsExpensive,
405     FeatureISA2_07,
406     FeatureCRBits
407    ];
408
409  list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion,
410                                               FeatureAddisLoadFusion];
411  list<SubtargetFeature> P8InheritableFeatures =
412    !listconcat(P7InheritableFeatures, P8AdditionalFeatures);
413  list<SubtargetFeature> P8Features =
414    !listconcat(P8InheritableFeatures, P8SpecificFeatures);
415
416  // Power9
417  list<SubtargetFeature> P9AdditionalFeatures =
418    [DirectivePwr9,
419     FeatureP9Altivec,
420     FeatureP9Vector,
421     FeaturePPCPreRASched,
422     FeaturePPCPostRASched,
423     FeatureISA3_0,
424     FeaturePredictableSelectIsExpensive
425    ];
426
427  // Some features are unique to Power9 and there is no reason to assume
428  // they will be part of any future CPUs. One example is the narrower
429  // dispatch for vector operations than scalar ones. For the time being,
430  // this list also includes scheduling-related features since we do not have
431  // enough info to create custom scheduling strategies for future CPUs.
432  list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits];
433  list<SubtargetFeature> P9InheritableFeatures =
434    !listconcat(P8InheritableFeatures, P9AdditionalFeatures);
435  list<SubtargetFeature> P9Features =
436    !listconcat(P9InheritableFeatures, P9SpecificFeatures);
437
438  // Power10
439  // For P10 CPU we assume that all of the existing features from Power9
440  // still exist with the exception of those we know are Power9 specific.
441  list<SubtargetFeature> FusionFeatures = [
442    FeatureStoreFusion, FeatureAddLogicalFusion, FeatureLogicalAddFusion,
443    FeatureLogicalFusion, FeatureArithAddFusion, FeatureSha3Fusion,
444  ];
445  list<SubtargetFeature> P10AdditionalFeatures =
446    !listconcat(FusionFeatures, [
447       DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
448       FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA,
449       FeaturePairedVectorMemops, FeatureFastMFLR]);
450  list<SubtargetFeature> P10SpecificFeatures = [];
451  list<SubtargetFeature> P10InheritableFeatures =
452    !listconcat(P9InheritableFeatures, P10AdditionalFeatures);
453  list<SubtargetFeature> P10Features =
454    !listconcat(P10InheritableFeatures, P10SpecificFeatures);
455
456  // Future
457  // For future CPU we assume that all of the existing features from Power10
458  // still exist with the exception of those we know are Power10 specific.
459  list<SubtargetFeature> FutureAdditionalFeatures = [FeatureISAFuture];
460  list<SubtargetFeature> FutureSpecificFeatures = [];
461  list<SubtargetFeature> FutureInheritableFeatures =
462    !listconcat(P10InheritableFeatures, FutureAdditionalFeatures);
463  list<SubtargetFeature> FutureFeatures =
464    !listconcat(FutureInheritableFeatures, FutureSpecificFeatures);
465}
466
467// Note: Future features to add when support is extended to more
468// recent ISA levels:
469//
470// DFP          p6, p6x, p7        decimal floating-point instructions
471// POPCNTB      p5 through p7      popcntb and related instructions
472
473//===----------------------------------------------------------------------===//
474// Classes used for relation maps.
475//===----------------------------------------------------------------------===//
476// RecFormRel - Filter class used to relate non-record-form instructions with
477// their record-form variants.
478class RecFormRel;
479
480// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
481// FMA instruction forms with their corresponding factor-killing forms.
482class AltVSXFMARel {
483  bit IsVSXFMAAlt = 0;
484}
485
486//===----------------------------------------------------------------------===//
487// Relation Map Definitions.
488//===----------------------------------------------------------------------===//
489
490def getRecordFormOpcode : InstrMapping {
491  let FilterClass = "RecFormRel";
492  // Instructions with the same BaseName and Interpretation64Bit values
493  // form a row.
494  let RowFields = ["BaseName", "Interpretation64Bit"];
495  // Instructions with the same RC value form a column.
496  let ColFields = ["RC"];
497  // The key column are the non-record-form instructions.
498  let KeyCol = ["0"];
499  // Value columns RC=1
500  let ValueCols = [["1"]];
501}
502
503def getNonRecordFormOpcode : InstrMapping {
504  let FilterClass = "RecFormRel";
505  // Instructions with the same BaseName and Interpretation64Bit values
506  // form a row.
507  let RowFields = ["BaseName", "Interpretation64Bit"];
508  // Instructions with the same RC value form a column.
509  let ColFields = ["RC"];
510  // The key column are the record-form instructions.
511  let KeyCol = ["1"];
512  // Value columns are RC=0
513  let ValueCols = [["0"]];
514}
515
516def getAltVSXFMAOpcode : InstrMapping {
517  let FilterClass = "AltVSXFMARel";
518  // Instructions with the same BaseName value form a row.
519  let RowFields = ["BaseName"];
520  // Instructions with the same IsVSXFMAAlt value form a column.
521  let ColFields = ["IsVSXFMAAlt"];
522  // The key column are the (default) addend-killing instructions.
523  let KeyCol = ["0"];
524  // Value columns IsVSXFMAAlt=1
525  let ValueCols = [["1"]];
526}
527
528//===----------------------------------------------------------------------===//
529// Register File Description
530//===----------------------------------------------------------------------===//
531
532include "PPCRegisterInfo.td"
533include "PPCSchedule.td"
534include "GISel/PPCRegisterBanks.td"
535
536//===----------------------------------------------------------------------===//
537// PowerPC processors supported.
538//
539
540def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
541                                           FeatureMFTB]>;
542def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
543                                          FeatureFRES, FeatureFRSQRTE,
544                                          FeatureICBT, FeatureBookE,
545                                          FeatureMSYNC, FeatureMFTB]>;
546def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
547                                          FeatureFRES, FeatureFRSQRTE,
548                                          FeatureICBT, FeatureBookE,
549                                          FeatureMSYNC, FeatureMFTB]>;
550def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
551def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
552                                       FeatureMFTB]>;
553def : Processor<"603", G3Itineraries, [Directive603,
554                                       FeatureFRES, FeatureFRSQRTE,
555                                       FeatureMFTB]>;
556def : Processor<"603e", G3Itineraries, [Directive603,
557                                        FeatureFRES, FeatureFRSQRTE,
558                                        FeatureMFTB]>;
559def : Processor<"603ev", G3Itineraries, [Directive603,
560                                         FeatureFRES, FeatureFRSQRTE,
561                                         FeatureMFTB]>;
562def : Processor<"604", G3Itineraries, [Directive604,
563                                       FeatureFRES, FeatureFRSQRTE,
564                                       FeatureMFTB]>;
565def : Processor<"604e", G3Itineraries, [Directive604,
566                                        FeatureFRES, FeatureFRSQRTE,
567                                        FeatureMFTB]>;
568def : Processor<"620", G3Itineraries, [Directive620,
569                                       FeatureFRES, FeatureFRSQRTE,
570                                       FeatureMFTB]>;
571def : Processor<"750", G4Itineraries, [Directive750,
572                                       FeatureFRES, FeatureFRSQRTE,
573                                       FeatureMFTB]>;
574def : Processor<"g3", G3Itineraries, [Directive750,
575                                      FeatureFRES, FeatureFRSQRTE,
576                                      FeatureMFTB]>;
577def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
578                                        FeatureFRES, FeatureFRSQRTE,
579                                        FeatureMFTB]>;
580def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
581                                      FeatureFRES, FeatureFRSQRTE,
582                                      FeatureMFTB]>;
583def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
584                                            FeatureFRES, FeatureFRSQRTE,
585                                            FeatureMFTB]>;
586def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
587                                           FeatureFRES, FeatureFRSQRTE,
588                                           FeatureMFTB]>;
589
590def : ProcessorModel<"970", G5Model,
591                  [Directive970, FeatureAltivec,
592                   FeatureMFOCRF, FeatureFSqrt,
593                   FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
594                   Feature64Bit /*, Feature64BitRegs */,
595                   FeatureMFTB]>;
596def : ProcessorModel<"g5", G5Model,
597                  [Directive970, FeatureAltivec,
598                   FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
599                   FeatureFRES, FeatureFRSQRTE,
600                   Feature64Bit /*, Feature64BitRegs */,
601                   FeatureMFTB, DeprecatedDST]>;
602def : ProcessorModel<"e500", PPCE500Model,
603                  [DirectiveE500,
604                   FeatureICBT, FeatureBookE,
605                   FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>;
606def : ProcessorModel<"e500mc", PPCE500mcModel,
607                  [DirectiveE500mc,
608                   FeatureSTFIWX, FeatureICBT, FeatureBookE,
609                   FeatureISEL, FeatureMFTB]>;
610def : ProcessorModel<"e5500", PPCE5500Model,
611                  [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
612                   FeatureSTFIWX, FeatureICBT, FeatureBookE,
613                   FeatureISEL, FeatureMFTB]>;
614def : ProcessorModel<"a2", PPCA2Model,
615                  [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
616                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
617                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
618                   FeatureSTFIWX, FeatureLFIWAX,
619                   FeatureFPRND, FeatureFPCVT, FeatureISEL,
620                   FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
621                   Feature64Bit /*, Feature64BitRegs */, FeatureMFTB,
622                   FeatureISA2_06]>;
623def : ProcessorModel<"pwr3", G5Model,
624                  [DirectivePwr3, FeatureAltivec,
625                   FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
626                   FeatureSTFIWX, Feature64Bit]>;
627def : ProcessorModel<"pwr4", G5Model,
628                  [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
629                   FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
630                   FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
631def : ProcessorModel<"pwr5", G5Model,
632                  [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
633                   FeatureFSqrt, FeatureFRE, FeatureFRES,
634                   FeatureFRSQRTE, FeatureFRSQRTES,
635                   FeatureSTFIWX, Feature64Bit,
636                   FeatureMFTB, DeprecatedDST]>;
637def : ProcessorModel<"pwr5x", G5Model,
638                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
639                   FeatureFSqrt, FeatureFRE, FeatureFRES,
640                   FeatureFRSQRTE, FeatureFRSQRTES,
641                   FeatureSTFIWX, FeatureFPRND, Feature64Bit,
642                   FeatureMFTB, DeprecatedDST]>;
643def : ProcessorModel<"pwr6", G5Model,
644                  [DirectivePwr6, FeatureAltivec,
645                   FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
646                   FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
647                   FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
648                   FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
649                   FeatureMFTB, DeprecatedDST]>;
650def : ProcessorModel<"pwr6x", G5Model,
651                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
652                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
653                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
654                   FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
655                   FeatureFPRND, Feature64Bit,
656                   FeatureMFTB, DeprecatedDST]>;
657def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;
658def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
659def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;
660def : ProcessorModel<"pwr10", P10Model, ProcessorFeatures.P10Features>;
661// No scheduler model for future CPU.
662def : ProcessorModel<"future", NoSchedModel,
663                  ProcessorFeatures.FutureFeatures>;
664def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
665                                       FeatureMFTB]>;
666def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
667                                         FeatureMFTB]>;
668def : ProcessorModel<"ppc64", G5Model,
669                  [Directive64, FeatureAltivec,
670                   FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
671                   FeatureFRSQRTE, FeatureSTFIWX,
672                   Feature64Bit /*, Feature64BitRegs */,
673                   FeatureMFTB]>;
674def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>;
675
676//===----------------------------------------------------------------------===//
677// Calling Conventions
678//===----------------------------------------------------------------------===//
679
680include "PPCCallingConv.td"
681
682def PPCInstrInfo : InstrInfo {
683  let isLittleEndianEncoding = 1;
684}
685
686def PPCAsmWriter : AsmWriter {
687  string AsmWriterClassName  = "InstPrinter";
688  int PassSubtarget = 1;
689  int Variant = 0;
690  bit isMCAsmWriter = 1;
691}
692
693def PPCAsmParser : AsmParser {
694  let ShouldEmitMatchRegisterName = 0;
695}
696
697def PPCAsmParserVariant : AsmParserVariant {
698  int Variant = 0;
699
700  // We do not use hard coded registers in asm strings.  However, some
701  // InstAlias definitions use immediate literals.  Set RegisterPrefix
702  // so that those are not misinterpreted as registers.
703  string RegisterPrefix = "%";
704  string BreakCharacters = ".";
705}
706
707def PPC : Target {
708  // Information about the instructions.
709  let InstructionSet = PPCInstrInfo;
710
711  let AssemblyWriters = [PPCAsmWriter];
712  let AssemblyParsers = [PPCAsmParser];
713  let AssemblyParserVariants = [PPCAsmParserVariant];
714  let AllowRegisterRenaming = 1;
715}
716
717//===----------------------------------------------------------------------===//
718// Pfm Counters
719//===----------------------------------------------------------------------===//
720
721include "PPCPfmCounters.td"
722