1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This is the top level entry point for the PowerPC target.
10//
11//===----------------------------------------------------------------------===//
12
13// Get the target-independent interfaces which we are implementing.
14//
15include "llvm/Target/Target.td"
16
17//===----------------------------------------------------------------------===//
18// PowerPC Subtarget features.
19//
20
21//===----------------------------------------------------------------------===//
22// CPU Directives                                                             //
23//===----------------------------------------------------------------------===//
24
25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">;
26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">;
27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">;
28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">;
32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">;
33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">;
34def Directive32  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">;
35def Directive64  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">;
36def DirectiveA2  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">;
37def DirectiveE500   : SubtargetFeature<"", "CPUDirective",
38                                       "PPC::DIR_E500", "">;
39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective",
40                                       "PPC::DIR_E500mc", "">;
41def DirectiveE5500  : SubtargetFeature<"", "CPUDirective",
42                                       "PPC::DIR_E5500", "">;
43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">;
44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">;
45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">;
46def DirectivePwr5x
47    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">;
48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">;
49def DirectivePwr6x
50    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">;
51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">;
52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">;
53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">;
54def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">;
55def DirectivePwrFuture
56    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;
57
58// Specifies that the selected CPU supports 64-bit instructions, regardless of
59// whether we are in 32-bit or 64-bit mode.
60def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
61                                        "Enable 64-bit instructions">;
62def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">;
63def FeatureModernAIXAs
64    : SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true",
65                       "AIX system assembler is modern enough to support new mnes">;
66def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
67                              "Enable floating-point instructions">;
68
69// Specifies that we are in 64-bit mode or that we should use 64-bit registers
70// in 32-bit mode when possible. Requires Feature64Bit to be enabled.
71def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
72                              "Enable 64-bit registers usage for ppc32 [beta]">;
73
74// Specify if we should store and manipulate i1 values in the individual
75// condition register bits.
76def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
77                              "Use condition-register bits individually">;
78def FeatureFPU       : SubtargetFeature<"fpu","HasFPU","true",
79                                        "Enable classic FPU instructions",
80                                        [FeatureHardFloat]>;
81def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
82                                        "Enable Altivec instructions",
83                                        [FeatureFPU]>;
84def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
85                                        "Enable SPE instructions",
86                                        [FeatureHardFloat]>;
87def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true",
88                                        "Enable Embedded Floating-Point APU 2 instructions",
89                                        [FeatureSPE]>;
90def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
91                                        "Enable the MFOCRF instruction">;
92def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
93                                        "Enable the fsqrt instruction",
94                                        [FeatureFPU]>;
95def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
96                                        "Enable the fcpsgn instruction",
97                                        [FeatureFPU]>;
98def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
99                                        "Enable the fre instruction",
100                                        [FeatureFPU]>;
101def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
102                                        "Enable the fres instruction",
103                                        [FeatureFPU]>;
104def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
105                                        "Enable the frsqrte instruction",
106                                        [FeatureFPU]>;
107def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
108                                        "Enable the frsqrtes instruction",
109                                        [FeatureFPU]>;
110def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
111                              "Assume higher precision reciprocal estimates">;
112def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
113                                        "Enable the stfiwx instruction",
114                                        [FeatureFPU]>;
115def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
116                                        "Enable the lfiwax instruction",
117                                        [FeatureFPU]>;
118def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
119                                        "Enable the fri[mnpz] instructions",
120                                        [FeatureFPU]>;
121def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
122  "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
123                                        [FeatureFPU]>;
124def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
125                                        "Enable the isel instruction">;
126def FeatureBPERMD    : SubtargetFeature<"bpermd", "HasBPERMD", "true",
127                                        "Enable the bpermd instruction">;
128def FeatureExtDiv    : SubtargetFeature<"extdiv", "HasExtDiv", "true",
129                                        "Enable extended divide instructions">;
130def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
131                                        "Enable the ldbrx instruction">;
132def FeatureCMPB      : SubtargetFeature<"cmpb", "HasCMPB", "true",
133                                        "Enable the cmpb instruction">;
134def FeatureICBT      : SubtargetFeature<"icbt","HasICBT", "true",
135                                        "Enable icbt instruction">;
136def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
137                                        "Enable Book E instructions",
138                                        [FeatureICBT]>;
139def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
140                              "Has only the msync instruction instead of sync",
141                              [FeatureBookE]>;
142def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
143                                        "Enable E500/E500mc instructions">;
144def FeatureSecurePlt : SubtargetFeature<"secure-plt","IsSecurePlt", "true",
145                                        "Enable secure plt mode">;
146def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
147                                        "Enable PPC 4xx instructions">;
148def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
149                                        "Enable PPC 6xx instructions">;
150def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
151                                        "Enable VSX instructions",
152                                        [FeatureAltivec]>;
153def FeatureTwoConstNR :
154  SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true",
155                   "Requires two constant Newton-Raphson computation">;
156def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
157                                        "Enable POWER8 Altivec instructions",
158                                        [FeatureAltivec]>;
159def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
160                                       "Enable POWER8 Crypto instructions",
161                                       [FeatureP8Altivec]>;
162def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
163                                        "Enable POWER8 vector instructions",
164                                        [FeatureVSX, FeatureP8Altivec]>;
165def FeatureDirectMove :
166  SubtargetFeature<"direct-move", "HasDirectMove", "true",
167                   "Enable Power8 direct move instructions",
168                   [FeatureVSX]>;
169def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
170                                             "HasPartwordAtomics", "true",
171                                             "Enable l[bh]arx and st[bh]cx.">;
172def FeatureQuadwordAtomic : SubtargetFeature<"quadword-atomics",
173                                             "HasQuadwordAtomics", "true",
174                                             "Enable lqarx and stqcx.">;
175def FeatureInvariantFunctionDescriptors :
176  SubtargetFeature<"invariant-function-descriptors",
177                   "HasInvariantFunctionDescriptors", "true",
178                   "Assume function descriptors are invariant">;
179def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
180                                       "Always use indirect calls">;
181def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
182                                  "Enable Hardware Transactional Memory instructions">;
183def FeatureMFTB   : SubtargetFeature<"", "IsFeatureMFTB", "true",
184                                        "Implement mftb using the mfspr instruction">;
185def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
186                                     "Target supports instruction fusion">;
187def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load",
188                                             "HasAddiLoadFusion", "true",
189                                             "Power8 Addi-Load fusion",
190                                             [FeatureFusion]>;
191def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load",
192                                              "HasAddisLoadFusion", "true",
193                                              "Power8 Addis-Load fusion",
194                                              [FeatureFusion]>;
195def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true",
196                                          "Target supports store clustering",
197                                          [FeatureFusion]>;
198def FeatureArithAddFusion :
199  SubtargetFeature<"fuse-arith-add", "HasArithAddFusion", "true",
200                   "Target supports Arithmetic Operations with Add fusion",
201                   [FeatureFusion]>;
202def FeatureAddLogicalFusion :
203  SubtargetFeature<"fuse-add-logical", "HasAddLogicalFusion", "true",
204                   "Target supports Add with Logical Operations fusion",
205                   [FeatureFusion]>;
206def FeatureLogicalAddFusion :
207  SubtargetFeature<"fuse-logical-add", "HasLogicalAddFusion", "true",
208                   "Target supports Logical with Add Operations fusion",
209                   [FeatureFusion]>;
210def FeatureLogicalFusion :
211  SubtargetFeature<"fuse-logical", "HasLogicalFusion", "true",
212                   "Target supports Logical Operations fusion",
213                   [FeatureFusion]>;
214def FeatureSha3Fusion :
215  SubtargetFeature<"fuse-sha3", "HasSha3Fusion", "true",
216                   "Target supports SHA3 assist fusion",
217                   [FeatureFusion]>;
218def FeatureCompareFusion:
219  SubtargetFeature<"fuse-cmp", "HasCompareFusion", "true",
220                   "Target supports Comparison Operations fusion",
221                   [FeatureFusion]>;
222def FeatureWideImmFusion:
223  SubtargetFeature<"fuse-wideimm", "HasWideImmFusion", "true",
224                   "Target supports Wide-Immediate fusion",
225                   [FeatureFusion]>;
226def FeatureZeroMoveFusion:
227  SubtargetFeature<"fuse-zeromove", "HasZeroMoveFusion", "true",
228                   "Target supports move to SPR with branch fusion",
229                   [FeatureFusion]>;
230def FeatureBack2BackFusion:
231  SubtargetFeature<"fuse-back2back", "HasBack2BackFusion", "true",
232                   "Target supports general back to back fusion",
233                   [FeatureFusion]>;
234def FeatureUnalignedFloats :
235  SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess",
236                   "true", "CPU does not trap on unaligned FP access">;
237def FeaturePPCPreRASched:
238  SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true",
239                   "Use PowerPC pre-RA scheduling strategy">;
240def FeaturePPCPostRASched:
241  SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true",
242                   "Use PowerPC post-RA scheduling strategy">;
243def FeatureFloat128 :
244  SubtargetFeature<"float128", "HasFloat128", "true",
245                   "Enable the __float128 data type for IEEE-754R Binary128.",
246                   [FeatureVSX]>;
247def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD",
248                                        "POPCNTD_Fast",
249                                        "Enable the popcnt[dw] instructions">;
250// Note that for the a2 processor models we should not use popcnt[dw] by
251// default. These processors do support the instructions, but they're
252// microcoded, and the software emulation is about twice as fast.
253def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
254                                          "POPCNTD_Slow",
255                                          "Has slow popcnt[dw] instructions">;
256
257def DeprecatedDST    : SubtargetFeature<"", "IsDeprecatedDST", "true",
258  "Treat vector data stream cache control instructions as deprecated">;
259
260def FeatureISA2_06 : SubtargetFeature<"isa-v206-instructions", "IsISA2_06",
261                                      "true",
262                                      "Enable instructions in ISA 2.06.">;
263def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07",
264                                      "true",
265                                      "Enable instructions in ISA 2.07.">;
266def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
267                                     "true",
268                                     "Enable instructions in ISA 3.0.",
269                                     [FeatureISA2_07]>;
270def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1",
271                                     "true",
272                                     "Enable instructions in ISA 3.1.",
273                                     [FeatureISA3_0]>;
274def FeatureISAFuture : SubtargetFeature<"isa-future-instructions",
275                                        "IsISAFuture", "true",
276                                        "Enable instructions for Future ISA.",
277                                        [FeatureISA3_1]>;
278def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
279                                        "Enable POWER9 Altivec instructions",
280                                        [FeatureISA3_0, FeatureP8Altivec]>;
281def FeatureP9Vector  : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
282                                        "Enable POWER9 vector instructions",
283                                        [FeatureISA3_0, FeatureP8Vector,
284                                         FeatureP9Altivec]>;
285def FeatureP10Vector  : SubtargetFeature<"power10-vector", "HasP10Vector",
286                                         "true",
287                                         "Enable POWER10 vector instructions",
288                                         [FeatureISA3_1, FeatureP9Vector]>;
289// A separate feature for this even though it is equivalent to P9Vector
290// because this is a feature of the implementation rather than the architecture
291// and may go away with future CPU's.
292def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
293                                                 "VectorsUseTwoUnits",
294                                                 "true",
295                                                 "Vectors use two units">;
296def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs",
297                                           "true",
298                                           "Enable prefixed instructions",
299                                           [FeatureISA3_0, FeatureP8Vector,
300                                            FeatureP9Altivec]>;
301def FeaturePCRelativeMemops :
302  SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
303                   "Enable PC relative Memory Ops",
304                   [FeatureISA3_0, FeaturePrefixInstrs]>;
305def FeaturePairedVectorMemops:
306  SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
307                   "32Byte load and store instructions",
308                   [FeatureISA3_0]>;
309def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true",
310                                  "Enable MMA instructions",
311                                  [FeatureP8Vector, FeatureP9Altivec,
312                                   FeaturePairedVectorMemops]>;
313def FeatureROPProtect :
314  SubtargetFeature<"rop-protect", "HasROPProtect", "true",
315                   "Add ROP protect">;
316
317def FeaturePrivileged :
318  SubtargetFeature<"privileged", "HasPrivileged", "true",
319                   "Add privileged instructions">;
320
321def FeaturePredictableSelectIsExpensive :
322  SubtargetFeature<"predictable-select-expensive",
323                   "PredictableSelectIsExpensive",
324                   "true",
325                   "Prefer likely predicted branches over selects">;
326
327def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true",
328                                       "MFLR is a fast instruction">;
329
330// Since new processors generally contain a superset of features of those that
331// came before them, the idea is to make implementations of new processors
332// less error prone and easier to read.
333// Namely:
334//     list<SubtargetFeature> P8InheritableFeatures = ...
335//     list<SubtargetFeature> FutureProcessorAddtionalFeatures =
336//         [ features that Power8 does not support but inheritable ]
337//     list<SubtargetFeature> FutureProcessorSpecificFeatures =
338//         [ features that Power8 does not support and not inheritable ]
339//     list<SubtargetFeature> FutureProcessorInheritableFeatures =
340//         !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures)
341//     list<SubtargetFeature> FutureProcessorFeatures =
342//         !listconcat(FutureProcessorInheritableFeatures,
343//                     FutureProcessorSpecificFeatures)
344
345// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as
346// well as providing a single point of definition if the feature set will be
347// used elsewhere.
348def ProcessorFeatures {
349  // Power7
350  list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7,
351                                                  FeatureAltivec,
352                                                  FeatureVSX,
353                                                  FeatureMFOCRF,
354                                                  FeatureFCPSGN,
355                                                  FeatureFSqrt,
356                                                  FeatureFRE,
357                                                  FeatureFRES,
358                                                  FeatureFRSQRTE,
359                                                  FeatureFRSQRTES,
360                                                  FeatureRecipPrec,
361                                                  FeatureSTFIWX,
362                                                  FeatureLFIWAX,
363                                                  FeatureFPRND,
364                                                  FeatureFPCVT,
365                                                  FeatureISEL,
366                                                  FeaturePOPCNTD,
367                                                  FeatureCMPB,
368                                                  FeatureLDBRX,
369                                                  Feature64Bit,
370                                                  /* Feature64BitRegs, */
371                                                  FeatureBPERMD,
372                                                  FeatureExtDiv,
373                                                  FeatureMFTB,
374                                                  DeprecatedDST,
375                                                  FeatureTwoConstNR,
376                                                  FeatureUnalignedFloats,
377                                                  FeatureISA2_06];
378  list<SubtargetFeature> P7SpecificFeatures = [];
379  list<SubtargetFeature> P7Features =
380    !listconcat(P7InheritableFeatures, P7SpecificFeatures);
381
382  // Power8
383  list<SubtargetFeature> P8AdditionalFeatures =
384    [DirectivePwr8,
385     FeatureP8Altivec,
386     FeatureP8Vector,
387     FeatureP8Crypto,
388     FeatureHTM,
389     FeatureDirectMove,
390     FeatureICBT,
391     FeaturePartwordAtomic,
392     FeatureQuadwordAtomic,
393     FeaturePredictableSelectIsExpensive,
394     FeatureISA2_07,
395     FeatureCRBits
396    ];
397
398  list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion,
399                                               FeatureAddisLoadFusion];
400  list<SubtargetFeature> P8InheritableFeatures =
401    !listconcat(P7InheritableFeatures, P8AdditionalFeatures);
402  list<SubtargetFeature> P8Features =
403    !listconcat(P8InheritableFeatures, P8SpecificFeatures);
404
405  // Power9
406  list<SubtargetFeature> P9AdditionalFeatures =
407    [DirectivePwr9,
408     FeatureP9Altivec,
409     FeatureP9Vector,
410     FeaturePPCPreRASched,
411     FeaturePPCPostRASched,
412     FeatureISA3_0,
413     FeaturePredictableSelectIsExpensive
414    ];
415
416  // Some features are unique to Power9 and there is no reason to assume
417  // they will be part of any future CPUs. One example is the narrower
418  // dispatch for vector operations than scalar ones. For the time being,
419  // this list also includes scheduling-related features since we do not have
420  // enough info to create custom scheduling strategies for future CPUs.
421  list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits];
422  list<SubtargetFeature> P9InheritableFeatures =
423    !listconcat(P8InheritableFeatures, P9AdditionalFeatures);
424  list<SubtargetFeature> P9Features =
425    !listconcat(P9InheritableFeatures, P9SpecificFeatures);
426
427  // Power10
428  // For P10 CPU we assume that all of the existing features from Power9
429  // still exist with the exception of those we know are Power9 specific.
430  list<SubtargetFeature> FusionFeatures = [
431    FeatureStoreFusion, FeatureAddLogicalFusion, FeatureLogicalAddFusion,
432    FeatureLogicalFusion, FeatureArithAddFusion, FeatureSha3Fusion,
433  ];
434  list<SubtargetFeature> P10AdditionalFeatures =
435    !listconcat(FusionFeatures, [
436       DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
437       FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA,
438       FeaturePairedVectorMemops, FeatureFastMFLR]);
439  list<SubtargetFeature> P10SpecificFeatures = [];
440  list<SubtargetFeature> P10InheritableFeatures =
441    !listconcat(P9InheritableFeatures, P10AdditionalFeatures);
442  list<SubtargetFeature> P10Features =
443    !listconcat(P10InheritableFeatures, P10SpecificFeatures);
444
445  // Future
446  // For future CPU we assume that all of the existing features from Power10
447  // still exist with the exception of those we know are Power10 specific.
448  list<SubtargetFeature> FutureAdditionalFeatures = [FeatureISAFuture];
449  list<SubtargetFeature> FutureSpecificFeatures = [];
450  list<SubtargetFeature> FutureInheritableFeatures =
451    !listconcat(P10InheritableFeatures, FutureAdditionalFeatures);
452  list<SubtargetFeature> FutureFeatures =
453    !listconcat(FutureInheritableFeatures, FutureSpecificFeatures);
454}
455
456// Note: Future features to add when support is extended to more
457// recent ISA levels:
458//
459// DFP          p6, p6x, p7        decimal floating-point instructions
460// POPCNTB      p5 through p7      popcntb and related instructions
461
462//===----------------------------------------------------------------------===//
463// Classes used for relation maps.
464//===----------------------------------------------------------------------===//
465// RecFormRel - Filter class used to relate non-record-form instructions with
466// their record-form variants.
467class RecFormRel;
468
469// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
470// FMA instruction forms with their corresponding factor-killing forms.
471class AltVSXFMARel {
472  bit IsVSXFMAAlt = 0;
473}
474
475//===----------------------------------------------------------------------===//
476// Relation Map Definitions.
477//===----------------------------------------------------------------------===//
478
479def getRecordFormOpcode : InstrMapping {
480  let FilterClass = "RecFormRel";
481  // Instructions with the same BaseName and Interpretation64Bit values
482  // form a row.
483  let RowFields = ["BaseName", "Interpretation64Bit"];
484  // Instructions with the same RC value form a column.
485  let ColFields = ["RC"];
486  // The key column are the non-record-form instructions.
487  let KeyCol = ["0"];
488  // Value columns RC=1
489  let ValueCols = [["1"]];
490}
491
492def getNonRecordFormOpcode : InstrMapping {
493  let FilterClass = "RecFormRel";
494  // Instructions with the same BaseName and Interpretation64Bit values
495  // form a row.
496  let RowFields = ["BaseName", "Interpretation64Bit"];
497  // Instructions with the same RC value form a column.
498  let ColFields = ["RC"];
499  // The key column are the record-form instructions.
500  let KeyCol = ["1"];
501  // Value columns are RC=0
502  let ValueCols = [["0"]];
503}
504
505def getAltVSXFMAOpcode : InstrMapping {
506  let FilterClass = "AltVSXFMARel";
507  // Instructions with the same BaseName value form a row.
508  let RowFields = ["BaseName"];
509  // Instructions with the same IsVSXFMAAlt value form a column.
510  let ColFields = ["IsVSXFMAAlt"];
511  // The key column are the (default) addend-killing instructions.
512  let KeyCol = ["0"];
513  // Value columns IsVSXFMAAlt=1
514  let ValueCols = [["1"]];
515}
516
517//===----------------------------------------------------------------------===//
518// Register File Description
519//===----------------------------------------------------------------------===//
520
521include "PPCRegisterInfo.td"
522include "PPCSchedule.td"
523include "GISel/PPCRegisterBanks.td"
524
525//===----------------------------------------------------------------------===//
526// PowerPC processors supported.
527//
528
529def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
530                                           FeatureMFTB]>;
531def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
532                                          FeatureFRES, FeatureFRSQRTE,
533                                          FeatureICBT, FeatureBookE,
534                                          FeatureMSYNC, FeatureMFTB]>;
535def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
536                                          FeatureFRES, FeatureFRSQRTE,
537                                          FeatureICBT, FeatureBookE,
538                                          FeatureMSYNC, FeatureMFTB]>;
539def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
540def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
541                                       FeatureMFTB]>;
542def : Processor<"603", G3Itineraries, [Directive603,
543                                       FeatureFRES, FeatureFRSQRTE,
544                                       FeatureMFTB]>;
545def : Processor<"603e", G3Itineraries, [Directive603,
546                                        FeatureFRES, FeatureFRSQRTE,
547                                        FeatureMFTB]>;
548def : Processor<"603ev", G3Itineraries, [Directive603,
549                                         FeatureFRES, FeatureFRSQRTE,
550                                         FeatureMFTB]>;
551def : Processor<"604", G3Itineraries, [Directive604,
552                                       FeatureFRES, FeatureFRSQRTE,
553                                       FeatureMFTB]>;
554def : Processor<"604e", G3Itineraries, [Directive604,
555                                        FeatureFRES, FeatureFRSQRTE,
556                                        FeatureMFTB]>;
557def : Processor<"620", G3Itineraries, [Directive620,
558                                       FeatureFRES, FeatureFRSQRTE,
559                                       FeatureMFTB]>;
560def : Processor<"750", G4Itineraries, [Directive750,
561                                       FeatureFRES, FeatureFRSQRTE,
562                                       FeatureMFTB]>;
563def : Processor<"g3", G3Itineraries, [Directive750,
564                                      FeatureFRES, FeatureFRSQRTE,
565                                      FeatureMFTB]>;
566def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
567                                        FeatureFRES, FeatureFRSQRTE,
568                                        FeatureMFTB]>;
569def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
570                                      FeatureFRES, FeatureFRSQRTE,
571                                      FeatureMFTB]>;
572def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
573                                            FeatureFRES, FeatureFRSQRTE,
574                                            FeatureMFTB]>;
575def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
576                                           FeatureFRES, FeatureFRSQRTE,
577                                           FeatureMFTB]>;
578
579def : ProcessorModel<"970", G5Model,
580                  [Directive970, FeatureAltivec,
581                   FeatureMFOCRF, FeatureFSqrt,
582                   FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
583                   Feature64Bit /*, Feature64BitRegs */,
584                   FeatureMFTB]>;
585def : ProcessorModel<"g5", G5Model,
586                  [Directive970, FeatureAltivec,
587                   FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
588                   FeatureFRES, FeatureFRSQRTE,
589                   Feature64Bit /*, Feature64BitRegs */,
590                   FeatureMFTB, DeprecatedDST]>;
591def : ProcessorModel<"e500", PPCE500Model,
592                  [DirectiveE500,
593                   FeatureICBT, FeatureBookE,
594                   FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>;
595def : ProcessorModel<"e500mc", PPCE500mcModel,
596                  [DirectiveE500mc,
597                   FeatureSTFIWX, FeatureICBT, FeatureBookE,
598                   FeatureISEL, FeatureMFTB]>;
599def : ProcessorModel<"e5500", PPCE5500Model,
600                  [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
601                   FeatureSTFIWX, FeatureICBT, FeatureBookE,
602                   FeatureISEL, FeatureMFTB]>;
603def : ProcessorModel<"a2", PPCA2Model,
604                  [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
605                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
606                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
607                   FeatureSTFIWX, FeatureLFIWAX,
608                   FeatureFPRND, FeatureFPCVT, FeatureISEL,
609                   FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
610                   Feature64Bit /*, Feature64BitRegs */, FeatureMFTB,
611                   FeatureISA2_06]>;
612def : ProcessorModel<"pwr3", G5Model,
613                  [DirectivePwr3, FeatureAltivec,
614                   FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
615                   FeatureSTFIWX, Feature64Bit]>;
616def : ProcessorModel<"pwr4", G5Model,
617                  [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
618                   FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
619                   FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
620def : ProcessorModel<"pwr5", G5Model,
621                  [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
622                   FeatureFSqrt, FeatureFRE, FeatureFRES,
623                   FeatureFRSQRTE, FeatureFRSQRTES,
624                   FeatureSTFIWX, Feature64Bit,
625                   FeatureMFTB, DeprecatedDST]>;
626def : ProcessorModel<"pwr5x", G5Model,
627                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
628                   FeatureFSqrt, FeatureFRE, FeatureFRES,
629                   FeatureFRSQRTE, FeatureFRSQRTES,
630                   FeatureSTFIWX, FeatureFPRND, Feature64Bit,
631                   FeatureMFTB, DeprecatedDST]>;
632def : ProcessorModel<"pwr6", G5Model,
633                  [DirectivePwr6, FeatureAltivec,
634                   FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
635                   FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
636                   FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
637                   FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
638                   FeatureMFTB, DeprecatedDST]>;
639def : ProcessorModel<"pwr6x", G5Model,
640                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
641                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
642                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
643                   FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
644                   FeatureFPRND, Feature64Bit,
645                   FeatureMFTB, DeprecatedDST]>;
646def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;
647def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
648def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;
649def : ProcessorModel<"pwr10", P10Model, ProcessorFeatures.P10Features>;
650// No scheduler model for future CPU.
651def : ProcessorModel<"future", NoSchedModel,
652                  ProcessorFeatures.FutureFeatures>;
653def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
654                                       FeatureMFTB]>;
655def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
656                                         FeatureMFTB]>;
657def : ProcessorModel<"ppc64", G5Model,
658                  [Directive64, FeatureAltivec,
659                   FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
660                   FeatureFRSQRTE, FeatureSTFIWX,
661                   Feature64Bit /*, Feature64BitRegs */,
662                   FeatureMFTB]>;
663def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>;
664
665//===----------------------------------------------------------------------===//
666// Calling Conventions
667//===----------------------------------------------------------------------===//
668
669include "PPCCallingConv.td"
670
671def PPCInstrInfo : InstrInfo {
672  let isLittleEndianEncoding = 1;
673}
674
675def PPCAsmWriter : AsmWriter {
676  string AsmWriterClassName  = "InstPrinter";
677  int PassSubtarget = 1;
678  int Variant = 0;
679  bit isMCAsmWriter = 1;
680}
681
682def PPCAsmParser : AsmParser {
683  let ShouldEmitMatchRegisterName = 0;
684}
685
686def PPCAsmParserVariant : AsmParserVariant {
687  int Variant = 0;
688
689  // We do not use hard coded registers in asm strings.  However, some
690  // InstAlias definitions use immediate literals.  Set RegisterPrefix
691  // so that those are not misinterpreted as registers.
692  string RegisterPrefix = "%";
693  string BreakCharacters = ".";
694}
695
696def PPC : Target {
697  // Information about the instructions.
698  let InstructionSet = PPCInstrInfo;
699
700  let AssemblyWriters = [PPCAsmWriter];
701  let AssemblyParsers = [PPCAsmParser];
702  let AssemblyParserVariants = [PPCAsmParserVariant];
703  let AllowRegisterRenaming = 1;
704}
705
706//===----------------------------------------------------------------------===//
707// Pfm Counters
708//===----------------------------------------------------------------------===//
709
710include "PPCPfmCounters.td"
711