1 //===-- PPCFastISel.cpp - PowerPC FastISel implementation -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the PowerPC-specific support for the FastISel class. Some
10 // of the target-specific code is generated by tablegen in the file
11 // PPCGenFastISel.inc, which is #included here.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPC.h"
17 #include "PPCCCState.h"
18 #include "PPCCallingConv.h"
19 #include "PPCISelLowering.h"
20 #include "PPCMachineFunctionInfo.h"
21 #include "PPCSubtarget.h"
22 #include "PPCTargetMachine.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/TargetLowering.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/GetElementPtrTypeIterator.h"
34 #include "llvm/IR/GlobalAlias.h"
35 #include "llvm/IR/GlobalVariable.h"
36 #include "llvm/IR/IntrinsicInst.h"
37 #include "llvm/IR/Operator.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Target/TargetMachine.h"
40 
41 //===----------------------------------------------------------------------===//
42 //
43 // TBD:
44 //   fastLowerArguments: Handle simple cases.
45 //   PPCMaterializeGV: Handle TLS.
46 //   SelectCall: Handle function pointers.
47 //   SelectCall: Handle multi-register return values.
48 //   SelectCall: Optimize away nops for local calls.
49 //   processCallArgs: Handle bit-converted arguments.
50 //   finishCall: Handle multi-register return values.
51 //   PPCComputeAddress: Handle parameter references as FrameIndex's.
52 //   PPCEmitCmp: Handle immediate as operand 1.
53 //   SelectCall: Handle small byval arguments.
54 //   SelectIntrinsicCall: Implement.
55 //   SelectSelect: Implement.
56 //   Consider factoring isTypeLegal into the base class.
57 //   Implement switches and jump tables.
58 //
59 //===----------------------------------------------------------------------===//
60 using namespace llvm;
61 
62 #define DEBUG_TYPE "ppcfastisel"
63 
64 namespace {
65 
66 struct Address {
67   enum {
68     RegBase,
69     FrameIndexBase
70   } BaseType;
71 
72   union {
73     unsigned Reg;
74     int FI;
75   } Base;
76 
77   long Offset;
78 
79   // Innocuous defaults for our address.
80   Address()
81    : BaseType(RegBase), Offset(0) {
82      Base.Reg = 0;
83    }
84 };
85 
86 class PPCFastISel final : public FastISel {
87 
88   const TargetMachine &TM;
89   const PPCSubtarget *Subtarget;
90   PPCFunctionInfo *PPCFuncInfo;
91   const TargetInstrInfo &TII;
92   const TargetLowering &TLI;
93   LLVMContext *Context;
94 
95   public:
96     explicit PPCFastISel(FunctionLoweringInfo &FuncInfo,
97                          const TargetLibraryInfo *LibInfo)
98         : FastISel(FuncInfo, LibInfo), TM(FuncInfo.MF->getTarget()),
99           Subtarget(&FuncInfo.MF->getSubtarget<PPCSubtarget>()),
100           PPCFuncInfo(FuncInfo.MF->getInfo<PPCFunctionInfo>()),
101           TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()),
102           Context(&FuncInfo.Fn->getContext()) {}
103 
104     // Backend specific FastISel code.
105   private:
106     bool fastSelectInstruction(const Instruction *I) override;
107     unsigned fastMaterializeConstant(const Constant *C) override;
108     unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
109     bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
110                              const LoadInst *LI) override;
111     bool fastLowerArguments() override;
112     unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
113     unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
114                              const TargetRegisterClass *RC,
115                              unsigned Op0, uint64_t Imm);
116     unsigned fastEmitInst_r(unsigned MachineInstOpcode,
117                             const TargetRegisterClass *RC, unsigned Op0);
118     unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
119                              const TargetRegisterClass *RC,
120                              unsigned Op0, unsigned Op1);
121 
122     bool fastLowerCall(CallLoweringInfo &CLI) override;
123 
124   // Instruction selection routines.
125   private:
126     bool SelectLoad(const Instruction *I);
127     bool SelectStore(const Instruction *I);
128     bool SelectBranch(const Instruction *I);
129     bool SelectIndirectBr(const Instruction *I);
130     bool SelectFPExt(const Instruction *I);
131     bool SelectFPTrunc(const Instruction *I);
132     bool SelectIToFP(const Instruction *I, bool IsSigned);
133     bool SelectFPToI(const Instruction *I, bool IsSigned);
134     bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
135     bool SelectRet(const Instruction *I);
136     bool SelectTrunc(const Instruction *I);
137     bool SelectIntExt(const Instruction *I);
138 
139   // Utility routines.
140   private:
141     bool isTypeLegal(Type *Ty, MVT &VT);
142     bool isLoadTypeLegal(Type *Ty, MVT &VT);
143     bool isValueAvailable(const Value *V) const;
144     bool isVSFRCRegClass(const TargetRegisterClass *RC) const {
145       return RC->getID() == PPC::VSFRCRegClassID;
146     }
147     bool isVSSRCRegClass(const TargetRegisterClass *RC) const {
148       return RC->getID() == PPC::VSSRCRegClassID;
149     }
150     unsigned copyRegToRegClass(const TargetRegisterClass *ToRC,
151                                unsigned SrcReg, unsigned Flag = 0,
152                                unsigned SubReg = 0) {
153       Register TmpReg = createResultReg(ToRC);
154       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
155               TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg);
156       return TmpReg;
157     }
158     bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
159                     bool isZExt, unsigned DestReg,
160                     const PPC::Predicate Pred);
161     bool PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
162                      const TargetRegisterClass *RC, bool IsZExt = true,
163                      unsigned FP64LoadOpc = PPC::LFD);
164     bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
165     bool PPCComputeAddress(const Value *Obj, Address &Addr);
166     void PPCSimplifyAddress(Address &Addr, bool &UseOffset,
167                             unsigned &IndexReg);
168     bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
169                            unsigned DestReg, bool IsZExt);
170     unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
171     unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
172     unsigned PPCMaterializeInt(const ConstantInt *CI, MVT VT,
173                                bool UseSExt = true);
174     unsigned PPCMaterialize32BitInt(int64_t Imm,
175                                     const TargetRegisterClass *RC);
176     unsigned PPCMaterialize64BitInt(int64_t Imm,
177                                     const TargetRegisterClass *RC);
178     unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
179                              unsigned SrcReg, bool IsSigned);
180     unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
181 
182   // Call handling routines.
183   private:
184     bool processCallArgs(SmallVectorImpl<Value*> &Args,
185                          SmallVectorImpl<unsigned> &ArgRegs,
186                          SmallVectorImpl<MVT> &ArgVTs,
187                          SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
188                          SmallVectorImpl<unsigned> &RegArgs,
189                          CallingConv::ID CC,
190                          unsigned &NumBytes,
191                          bool IsVarArg);
192     bool finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes);
193 
194   private:
195   #include "PPCGenFastISel.inc"
196 
197 };
198 
199 } // end anonymous namespace
200 
201 static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
202   switch (Pred) {
203     // These are not representable with any single compare.
204     case CmpInst::FCMP_FALSE:
205     case CmpInst::FCMP_TRUE:
206     // Major concern about the following 6 cases is NaN result. The comparison
207     // result consists of 4 bits, indicating lt, eq, gt and un (unordered),
208     // only one of which will be set. The result is generated by fcmpu
209     // instruction. However, bc instruction only inspects one of the first 3
210     // bits, so when un is set, bc instruction may jump to an undesired
211     // place.
212     //
213     // More specifically, if we expect an unordered comparison and un is set, we
214     // expect to always go to true branch; in such case UEQ, UGT and ULT still
215     // give false, which are undesired; but UNE, UGE, ULE happen to give true,
216     // since they are tested by inspecting !eq, !lt, !gt, respectively.
217     //
218     // Similarly, for ordered comparison, when un is set, we always expect the
219     // result to be false. In such case OGT, OLT and OEQ is good, since they are
220     // actually testing GT, LT, and EQ respectively, which are false. OGE, OLE
221     // and ONE are tested through !lt, !gt and !eq, and these are true.
222     case CmpInst::FCMP_UEQ:
223     case CmpInst::FCMP_UGT:
224     case CmpInst::FCMP_ULT:
225     case CmpInst::FCMP_OGE:
226     case CmpInst::FCMP_OLE:
227     case CmpInst::FCMP_ONE:
228     default:
229       return Optional<PPC::Predicate>();
230 
231     case CmpInst::FCMP_OEQ:
232     case CmpInst::ICMP_EQ:
233       return PPC::PRED_EQ;
234 
235     case CmpInst::FCMP_OGT:
236     case CmpInst::ICMP_UGT:
237     case CmpInst::ICMP_SGT:
238       return PPC::PRED_GT;
239 
240     case CmpInst::FCMP_UGE:
241     case CmpInst::ICMP_UGE:
242     case CmpInst::ICMP_SGE:
243       return PPC::PRED_GE;
244 
245     case CmpInst::FCMP_OLT:
246     case CmpInst::ICMP_ULT:
247     case CmpInst::ICMP_SLT:
248       return PPC::PRED_LT;
249 
250     case CmpInst::FCMP_ULE:
251     case CmpInst::ICMP_ULE:
252     case CmpInst::ICMP_SLE:
253       return PPC::PRED_LE;
254 
255     case CmpInst::FCMP_UNE:
256     case CmpInst::ICMP_NE:
257       return PPC::PRED_NE;
258 
259     case CmpInst::FCMP_ORD:
260       return PPC::PRED_NU;
261 
262     case CmpInst::FCMP_UNO:
263       return PPC::PRED_UN;
264   }
265 }
266 
267 // Determine whether the type Ty is simple enough to be handled by
268 // fast-isel, and return its equivalent machine type in VT.
269 // FIXME: Copied directly from ARM -- factor into base class?
270 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {
271   EVT Evt = TLI.getValueType(DL, Ty, true);
272 
273   // Only handle simple types.
274   if (Evt == MVT::Other || !Evt.isSimple()) return false;
275   VT = Evt.getSimpleVT();
276 
277   // Handle all legal types, i.e. a register that will directly hold this
278   // value.
279   return TLI.isTypeLegal(VT);
280 }
281 
282 // Determine whether the type Ty is simple enough to be handled by
283 // fast-isel as a load target, and return its equivalent machine type in VT.
284 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
285   if (isTypeLegal(Ty, VT)) return true;
286 
287   // If this is a type than can be sign or zero-extended to a basic operation
288   // go ahead and accept it now.
289   if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
290     return true;
291   }
292 
293   return false;
294 }
295 
296 bool PPCFastISel::isValueAvailable(const Value *V) const {
297   if (!isa<Instruction>(V))
298     return true;
299 
300   const auto *I = cast<Instruction>(V);
301   return FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB;
302 }
303 
304 // Given a value Obj, create an Address object Addr that represents its
305 // address.  Return false if we can't handle it.
306 bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
307   const User *U = nullptr;
308   unsigned Opcode = Instruction::UserOp1;
309   if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
310     // Don't walk into other basic blocks unless the object is an alloca from
311     // another block, otherwise it may not have a virtual register assigned.
312     if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
313         FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
314       Opcode = I->getOpcode();
315       U = I;
316     }
317   } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
318     Opcode = C->getOpcode();
319     U = C;
320   }
321 
322   switch (Opcode) {
323     default:
324       break;
325     case Instruction::BitCast:
326       // Look through bitcasts.
327       return PPCComputeAddress(U->getOperand(0), Addr);
328     case Instruction::IntToPtr:
329       // Look past no-op inttoptrs.
330       if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
331           TLI.getPointerTy(DL))
332         return PPCComputeAddress(U->getOperand(0), Addr);
333       break;
334     case Instruction::PtrToInt:
335       // Look past no-op ptrtoints.
336       if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
337         return PPCComputeAddress(U->getOperand(0), Addr);
338       break;
339     case Instruction::GetElementPtr: {
340       Address SavedAddr = Addr;
341       long TmpOffset = Addr.Offset;
342 
343       // Iterate through the GEP folding the constants into offsets where
344       // we can.
345       gep_type_iterator GTI = gep_type_begin(U);
346       for (User::const_op_iterator II = U->op_begin() + 1, IE = U->op_end();
347            II != IE; ++II, ++GTI) {
348         const Value *Op = *II;
349         if (StructType *STy = GTI.getStructTypeOrNull()) {
350           const StructLayout *SL = DL.getStructLayout(STy);
351           unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
352           TmpOffset += SL->getElementOffset(Idx);
353         } else {
354           uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
355           for (;;) {
356             if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
357               // Constant-offset addressing.
358               TmpOffset += CI->getSExtValue() * S;
359               break;
360             }
361             if (canFoldAddIntoGEP(U, Op)) {
362               // A compatible add with a constant operand. Fold the constant.
363               ConstantInt *CI =
364               cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
365               TmpOffset += CI->getSExtValue() * S;
366               // Iterate on the other operand.
367               Op = cast<AddOperator>(Op)->getOperand(0);
368               continue;
369             }
370             // Unsupported
371             goto unsupported_gep;
372           }
373         }
374       }
375 
376       // Try to grab the base operand now.
377       Addr.Offset = TmpOffset;
378       if (PPCComputeAddress(U->getOperand(0), Addr)) return true;
379 
380       // We failed, restore everything and try the other options.
381       Addr = SavedAddr;
382 
383       unsupported_gep:
384       break;
385     }
386     case Instruction::Alloca: {
387       const AllocaInst *AI = cast<AllocaInst>(Obj);
388       DenseMap<const AllocaInst*, int>::iterator SI =
389         FuncInfo.StaticAllocaMap.find(AI);
390       if (SI != FuncInfo.StaticAllocaMap.end()) {
391         Addr.BaseType = Address::FrameIndexBase;
392         Addr.Base.FI = SI->second;
393         return true;
394       }
395       break;
396     }
397   }
398 
399   // FIXME: References to parameters fall through to the behavior
400   // below.  They should be able to reference a frame index since
401   // they are stored to the stack, so we can get "ld rx, offset(r1)"
402   // instead of "addi ry, r1, offset / ld rx, 0(ry)".  Obj will
403   // just contain the parameter.  Try to handle this with a FI.
404 
405   // Try to get this in a register if nothing else has worked.
406   if (Addr.Base.Reg == 0)
407     Addr.Base.Reg = getRegForValue(Obj);
408 
409   // Prevent assignment of base register to X0, which is inappropriate
410   // for loads and stores alike.
411   if (Addr.Base.Reg != 0)
412     MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
413 
414   return Addr.Base.Reg != 0;
415 }
416 
417 // Fix up some addresses that can't be used directly.  For example, if
418 // an offset won't fit in an instruction field, we may need to move it
419 // into an index register.
420 void PPCFastISel::PPCSimplifyAddress(Address &Addr, bool &UseOffset,
421                                      unsigned &IndexReg) {
422 
423   // Check whether the offset fits in the instruction field.
424   if (!isInt<16>(Addr.Offset))
425     UseOffset = false;
426 
427   // If this is a stack pointer and the offset needs to be simplified then
428   // put the alloca address into a register, set the base type back to
429   // register and continue. This should almost never happen.
430   if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) {
431     Register ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
432     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
433             ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
434     Addr.Base.Reg = ResultReg;
435     Addr.BaseType = Address::RegBase;
436   }
437 
438   if (!UseOffset) {
439     IntegerType *OffsetTy = Type::getInt64Ty(*Context);
440     const ConstantInt *Offset =
441       ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset));
442     IndexReg = PPCMaterializeInt(Offset, MVT::i64);
443     assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
444   }
445 }
446 
447 // Emit a load instruction if possible, returning true if we succeeded,
448 // otherwise false.  See commentary below for how the register class of
449 // the load is determined.
450 bool PPCFastISel::PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
451                               const TargetRegisterClass *RC,
452                               bool IsZExt, unsigned FP64LoadOpc) {
453   unsigned Opc;
454   bool UseOffset = true;
455   bool HasSPE = Subtarget->hasSPE();
456 
457   // If ResultReg is given, it determines the register class of the load.
458   // Otherwise, RC is the register class to use.  If the result of the
459   // load isn't anticipated in this block, both may be zero, in which
460   // case we must make a conservative guess.  In particular, don't assign
461   // R0 or X0 to the result register, as the result may be used in a load,
462   // store, add-immediate, or isel that won't permit this.  (Though
463   // perhaps the spill and reload of live-exit values would handle this?)
464   const TargetRegisterClass *UseRC =
465     (ResultReg ? MRI.getRegClass(ResultReg) :
466      (RC ? RC :
467       (VT == MVT::f64 ? (HasSPE ? &PPC::SPERCRegClass : &PPC::F8RCRegClass) :
468        (VT == MVT::f32 ? (HasSPE ? &PPC::GPRCRegClass : &PPC::F4RCRegClass) :
469         (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
470          &PPC::GPRC_and_GPRC_NOR0RegClass)))));
471 
472   bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
473 
474   switch (VT.SimpleTy) {
475     default: // e.g., vector types not handled
476       return false;
477     case MVT::i8:
478       Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
479       break;
480     case MVT::i16:
481       Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8)
482                     : (Is32BitInt ? PPC::LHA : PPC::LHA8));
483       break;
484     case MVT::i32:
485       Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8)
486                     : (Is32BitInt ? PPC::LWA_32 : PPC::LWA));
487       if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
488         UseOffset = false;
489       break;
490     case MVT::i64:
491       Opc = PPC::LD;
492       assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
493              "64-bit load with 32-bit target??");
494       UseOffset = ((Addr.Offset & 3) == 0);
495       break;
496     case MVT::f32:
497       Opc = Subtarget->hasSPE() ? PPC::SPELWZ : PPC::LFS;
498       break;
499     case MVT::f64:
500       Opc = FP64LoadOpc;
501       break;
502   }
503 
504   // If necessary, materialize the offset into a register and use
505   // the indexed form.  Also handle stack pointers with special needs.
506   unsigned IndexReg = 0;
507   PPCSimplifyAddress(Addr, UseOffset, IndexReg);
508 
509   // If this is a potential VSX load with an offset of 0, a VSX indexed load can
510   // be used.
511   bool IsVSSRC = isVSSRCRegClass(UseRC);
512   bool IsVSFRC = isVSFRCRegClass(UseRC);
513   bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS;
514   bool Is64VSXLoad = IsVSFRC && Opc == PPC::LFD;
515   if ((Is32VSXLoad || Is64VSXLoad) &&
516       (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
517       (Addr.Offset == 0)) {
518     UseOffset = false;
519   }
520 
521   if (ResultReg == 0)
522     ResultReg = createResultReg(UseRC);
523 
524   // Note: If we still have a frame index here, we know the offset is
525   // in range, as otherwise PPCSimplifyAddress would have converted it
526   // into a RegBase.
527   if (Addr.BaseType == Address::FrameIndexBase) {
528     // VSX only provides an indexed load.
529     if (Is32VSXLoad || Is64VSXLoad) return false;
530 
531     MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
532         MachinePointerInfo::getFixedStack(*FuncInfo.MF, Addr.Base.FI,
533                                           Addr.Offset),
534         MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI),
535         MFI.getObjectAlign(Addr.Base.FI));
536 
537     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
538       .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
539 
540   // Base reg with offset in range.
541   } else if (UseOffset) {
542     // VSX only provides an indexed load.
543     if (Is32VSXLoad || Is64VSXLoad) return false;
544 
545     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
546       .addImm(Addr.Offset).addReg(Addr.Base.Reg);
547 
548   // Indexed form.
549   } else {
550     // Get the RR opcode corresponding to the RI one.  FIXME: It would be
551     // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
552     // is hard to get at.
553     switch (Opc) {
554       default:        llvm_unreachable("Unexpected opcode!");
555       case PPC::LBZ:    Opc = PPC::LBZX;    break;
556       case PPC::LBZ8:   Opc = PPC::LBZX8;   break;
557       case PPC::LHZ:    Opc = PPC::LHZX;    break;
558       case PPC::LHZ8:   Opc = PPC::LHZX8;   break;
559       case PPC::LHA:    Opc = PPC::LHAX;    break;
560       case PPC::LHA8:   Opc = PPC::LHAX8;   break;
561       case PPC::LWZ:    Opc = PPC::LWZX;    break;
562       case PPC::LWZ8:   Opc = PPC::LWZX8;   break;
563       case PPC::LWA:    Opc = PPC::LWAX;    break;
564       case PPC::LWA_32: Opc = PPC::LWAX_32; break;
565       case PPC::LD:     Opc = PPC::LDX;     break;
566       case PPC::LFS:    Opc = IsVSSRC ? PPC::LXSSPX : PPC::LFSX; break;
567       case PPC::LFD:    Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX; break;
568       case PPC::EVLDD:  Opc = PPC::EVLDDX;  break;
569       case PPC::SPELWZ: Opc = PPC::SPELWZX;    break;
570     }
571 
572     auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
573                        ResultReg);
574 
575     // If we have an index register defined we use it in the store inst,
576     // otherwise we use X0 as base as it makes the vector instructions to
577     // use zero in the computation of the effective address regardless the
578     // content of the register.
579     if (IndexReg)
580       MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
581     else
582       MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
583   }
584 
585   return true;
586 }
587 
588 // Attempt to fast-select a load instruction.
589 bool PPCFastISel::SelectLoad(const Instruction *I) {
590   // FIXME: No atomic loads are supported.
591   if (cast<LoadInst>(I)->isAtomic())
592     return false;
593 
594   // Verify we have a legal type before going any further.
595   MVT VT;
596   if (!isLoadTypeLegal(I->getType(), VT))
597     return false;
598 
599   // See if we can handle this address.
600   Address Addr;
601   if (!PPCComputeAddress(I->getOperand(0), Addr))
602     return false;
603 
604   // Look at the currently assigned register for this instruction
605   // to determine the required register class.  This is necessary
606   // to constrain RA from using R0/X0 when this is not legal.
607   Register AssignedReg = FuncInfo.ValueMap[I];
608   const TargetRegisterClass *RC =
609     AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
610 
611   Register ResultReg = 0;
612   if (!PPCEmitLoad(VT, ResultReg, Addr, RC, true,
613                    Subtarget->hasSPE() ? PPC::EVLDD : PPC::LFD))
614     return false;
615   updateValueMap(I, ResultReg);
616   return true;
617 }
618 
619 // Emit a store instruction to store SrcReg at Addr.
620 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
621   assert(SrcReg && "Nothing to store!");
622   unsigned Opc;
623   bool UseOffset = true;
624 
625   const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
626   bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass);
627 
628   switch (VT.SimpleTy) {
629     default: // e.g., vector types not handled
630       return false;
631     case MVT::i8:
632       Opc = Is32BitInt ? PPC::STB : PPC::STB8;
633       break;
634     case MVT::i16:
635       Opc = Is32BitInt ? PPC::STH : PPC::STH8;
636       break;
637     case MVT::i32:
638       assert(Is32BitInt && "Not GPRC for i32??");
639       Opc = PPC::STW;
640       break;
641     case MVT::i64:
642       Opc = PPC::STD;
643       UseOffset = ((Addr.Offset & 3) == 0);
644       break;
645     case MVT::f32:
646       Opc = Subtarget->hasSPE() ? PPC::SPESTW : PPC::STFS;
647       break;
648     case MVT::f64:
649       Opc = Subtarget->hasSPE() ? PPC::EVSTDD : PPC::STFD;
650       break;
651   }
652 
653   // If necessary, materialize the offset into a register and use
654   // the indexed form.  Also handle stack pointers with special needs.
655   unsigned IndexReg = 0;
656   PPCSimplifyAddress(Addr, UseOffset, IndexReg);
657 
658   // If this is a potential VSX store with an offset of 0, a VSX indexed store
659   // can be used.
660   bool IsVSSRC = isVSSRCRegClass(RC);
661   bool IsVSFRC = isVSFRCRegClass(RC);
662   bool Is32VSXStore = IsVSSRC && Opc == PPC::STFS;
663   bool Is64VSXStore = IsVSFRC && Opc == PPC::STFD;
664   if ((Is32VSXStore || Is64VSXStore) &&
665       (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
666       (Addr.Offset == 0)) {
667     UseOffset = false;
668   }
669 
670   // Note: If we still have a frame index here, we know the offset is
671   // in range, as otherwise PPCSimplifyAddress would have converted it
672   // into a RegBase.
673   if (Addr.BaseType == Address::FrameIndexBase) {
674     // VSX only provides an indexed store.
675     if (Is32VSXStore || Is64VSXStore) return false;
676 
677     MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
678         MachinePointerInfo::getFixedStack(*FuncInfo.MF, Addr.Base.FI,
679                                           Addr.Offset),
680         MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI),
681         MFI.getObjectAlign(Addr.Base.FI));
682 
683     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
684         .addReg(SrcReg)
685         .addImm(Addr.Offset)
686         .addFrameIndex(Addr.Base.FI)
687         .addMemOperand(MMO);
688 
689   // Base reg with offset in range.
690   } else if (UseOffset) {
691     // VSX only provides an indexed store.
692     if (Is32VSXStore || Is64VSXStore)
693       return false;
694 
695     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
696       .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
697 
698   // Indexed form.
699   } else {
700     // Get the RR opcode corresponding to the RI one.  FIXME: It would be
701     // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
702     // is hard to get at.
703     switch (Opc) {
704       default:        llvm_unreachable("Unexpected opcode!");
705       case PPC::STB:  Opc = PPC::STBX;  break;
706       case PPC::STH : Opc = PPC::STHX;  break;
707       case PPC::STW : Opc = PPC::STWX;  break;
708       case PPC::STB8: Opc = PPC::STBX8; break;
709       case PPC::STH8: Opc = PPC::STHX8; break;
710       case PPC::STW8: Opc = PPC::STWX8; break;
711       case PPC::STD:  Opc = PPC::STDX;  break;
712       case PPC::STFS: Opc = IsVSSRC ? PPC::STXSSPX : PPC::STFSX; break;
713       case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX; break;
714       case PPC::EVSTDD: Opc = PPC::EVSTDDX; break;
715       case PPC::SPESTW: Opc = PPC::SPESTWX; break;
716     }
717 
718     auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
719         .addReg(SrcReg);
720 
721     // If we have an index register defined we use it in the store inst,
722     // otherwise we use X0 as base as it makes the vector instructions to
723     // use zero in the computation of the effective address regardless the
724     // content of the register.
725     if (IndexReg)
726       MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
727     else
728       MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
729   }
730 
731   return true;
732 }
733 
734 // Attempt to fast-select a store instruction.
735 bool PPCFastISel::SelectStore(const Instruction *I) {
736   Value *Op0 = I->getOperand(0);
737   unsigned SrcReg = 0;
738 
739   // FIXME: No atomics loads are supported.
740   if (cast<StoreInst>(I)->isAtomic())
741     return false;
742 
743   // Verify we have a legal type before going any further.
744   MVT VT;
745   if (!isLoadTypeLegal(Op0->getType(), VT))
746     return false;
747 
748   // Get the value to be stored into a register.
749   SrcReg = getRegForValue(Op0);
750   if (SrcReg == 0)
751     return false;
752 
753   // See if we can handle this address.
754   Address Addr;
755   if (!PPCComputeAddress(I->getOperand(1), Addr))
756     return false;
757 
758   if (!PPCEmitStore(VT, SrcReg, Addr))
759     return false;
760 
761   return true;
762 }
763 
764 // Attempt to fast-select a branch instruction.
765 bool PPCFastISel::SelectBranch(const Instruction *I) {
766   const BranchInst *BI = cast<BranchInst>(I);
767   MachineBasicBlock *BrBB = FuncInfo.MBB;
768   MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
769   MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
770 
771   // For now, just try the simplest case where it's fed by a compare.
772   if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
773     if (isValueAvailable(CI)) {
774       Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate());
775       if (!OptPPCPred)
776         return false;
777 
778       PPC::Predicate PPCPred = *OptPPCPred;
779 
780       // Take advantage of fall-through opportunities.
781       if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
782         std::swap(TBB, FBB);
783         PPCPred = PPC::InvertPredicate(PPCPred);
784       }
785 
786       Register CondReg = createResultReg(&PPC::CRRCRegClass);
787 
788       if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
789                       CondReg, PPCPred))
790         return false;
791 
792       BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC))
793           .addImm(Subtarget->hasSPE() ? PPC::PRED_SPE : PPCPred)
794           .addReg(CondReg)
795           .addMBB(TBB);
796       finishCondBranch(BI->getParent(), TBB, FBB);
797       return true;
798     }
799   } else if (const ConstantInt *CI =
800              dyn_cast<ConstantInt>(BI->getCondition())) {
801     uint64_t Imm = CI->getZExtValue();
802     MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
803     fastEmitBranch(Target, DbgLoc);
804     return true;
805   }
806 
807   // FIXME: ARM looks for a case where the block containing the compare
808   // has been split from the block containing the branch.  If this happens,
809   // there is a vreg available containing the result of the compare.  I'm
810   // not sure we can do much, as we've lost the predicate information with
811   // the compare instruction -- we have a 4-bit CR but don't know which bit
812   // to test here.
813   return false;
814 }
815 
816 // Attempt to emit a compare of the two source values.  Signed and unsigned
817 // comparisons are supported.  Return false if we can't handle it.
818 bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
819                              bool IsZExt, unsigned DestReg,
820                              const PPC::Predicate Pred) {
821   Type *Ty = SrcValue1->getType();
822   EVT SrcEVT = TLI.getValueType(DL, Ty, true);
823   if (!SrcEVT.isSimple())
824     return false;
825   MVT SrcVT = SrcEVT.getSimpleVT();
826 
827   if (SrcVT == MVT::i1 && Subtarget->useCRBits())
828     return false;
829 
830   // See if operand 2 is an immediate encodeable in the compare.
831   // FIXME: Operands are not in canonical order at -O0, so an immediate
832   // operand in position 1 is a lost opportunity for now.  We are
833   // similar to ARM in this regard.
834   int64_t Imm = 0;
835   bool UseImm = false;
836   const bool HasSPE = Subtarget->hasSPE();
837 
838   // Only 16-bit integer constants can be represented in compares for
839   // PowerPC.  Others will be materialized into a register.
840   if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
841     if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
842         SrcVT == MVT::i8 || SrcVT == MVT::i1) {
843       const APInt &CIVal = ConstInt->getValue();
844       Imm = (IsZExt) ? (int64_t)CIVal.getZExtValue() :
845                        (int64_t)CIVal.getSExtValue();
846       if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
847         UseImm = true;
848     }
849   }
850 
851   Register SrcReg1 = getRegForValue(SrcValue1);
852   if (SrcReg1 == 0)
853     return false;
854 
855   unsigned SrcReg2 = 0;
856   if (!UseImm) {
857     SrcReg2 = getRegForValue(SrcValue2);
858     if (SrcReg2 == 0)
859       return false;
860   }
861 
862   unsigned CmpOpc;
863   bool NeedsExt = false;
864 
865   auto RC1 = MRI.getRegClass(SrcReg1);
866   auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr;
867 
868   switch (SrcVT.SimpleTy) {
869     default: return false;
870     case MVT::f32:
871       if (HasSPE) {
872         switch (Pred) {
873           default: return false;
874           case PPC::PRED_EQ:
875             CmpOpc = PPC::EFSCMPEQ;
876             break;
877           case PPC::PRED_LT:
878             CmpOpc = PPC::EFSCMPLT;
879             break;
880           case PPC::PRED_GT:
881             CmpOpc = PPC::EFSCMPGT;
882             break;
883         }
884       } else {
885         CmpOpc = PPC::FCMPUS;
886         if (isVSSRCRegClass(RC1))
887           SrcReg1 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg1);
888         if (RC2 && isVSSRCRegClass(RC2))
889           SrcReg2 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg2);
890       }
891       break;
892     case MVT::f64:
893       if (HasSPE) {
894         switch (Pred) {
895           default: return false;
896           case PPC::PRED_EQ:
897             CmpOpc = PPC::EFDCMPEQ;
898             break;
899           case PPC::PRED_LT:
900             CmpOpc = PPC::EFDCMPLT;
901             break;
902           case PPC::PRED_GT:
903             CmpOpc = PPC::EFDCMPGT;
904             break;
905         }
906       } else if (isVSFRCRegClass(RC1) || (RC2 && isVSFRCRegClass(RC2))) {
907         CmpOpc = PPC::XSCMPUDP;
908       } else {
909         CmpOpc = PPC::FCMPUD;
910       }
911       break;
912     case MVT::i1:
913     case MVT::i8:
914     case MVT::i16:
915       NeedsExt = true;
916       LLVM_FALLTHROUGH;
917     case MVT::i32:
918       if (!UseImm)
919         CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
920       else
921         CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
922       break;
923     case MVT::i64:
924       if (!UseImm)
925         CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
926       else
927         CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
928       break;
929   }
930 
931   if (NeedsExt) {
932     Register ExtReg = createResultReg(&PPC::GPRCRegClass);
933     if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
934       return false;
935     SrcReg1 = ExtReg;
936 
937     if (!UseImm) {
938       Register ExtReg = createResultReg(&PPC::GPRCRegClass);
939       if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
940         return false;
941       SrcReg2 = ExtReg;
942     }
943   }
944 
945   if (!UseImm)
946     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
947       .addReg(SrcReg1).addReg(SrcReg2);
948   else
949     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
950       .addReg(SrcReg1).addImm(Imm);
951 
952   return true;
953 }
954 
955 // Attempt to fast-select a floating-point extend instruction.
956 bool PPCFastISel::SelectFPExt(const Instruction *I) {
957   Value *Src  = I->getOperand(0);
958   EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
959   EVT DestVT = TLI.getValueType(DL, I->getType(), true);
960 
961   if (SrcVT != MVT::f32 || DestVT != MVT::f64)
962     return false;
963 
964   Register SrcReg = getRegForValue(Src);
965   if (!SrcReg)
966     return false;
967 
968   // No code is generated for a FP extend.
969   updateValueMap(I, SrcReg);
970   return true;
971 }
972 
973 // Attempt to fast-select a floating-point truncate instruction.
974 bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
975   Value *Src  = I->getOperand(0);
976   EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
977   EVT DestVT = TLI.getValueType(DL, I->getType(), true);
978 
979   if (SrcVT != MVT::f64 || DestVT != MVT::f32)
980     return false;
981 
982   Register SrcReg = getRegForValue(Src);
983   if (!SrcReg)
984     return false;
985 
986   // Round the result to single precision.
987   unsigned DestReg;
988   auto RC = MRI.getRegClass(SrcReg);
989   if (Subtarget->hasSPE()) {
990     DestReg = createResultReg(&PPC::GPRCRegClass);
991     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::EFSCFD),
992             DestReg)
993         .addReg(SrcReg);
994   } else if (Subtarget->hasP8Vector() && isVSFRCRegClass(RC)) {
995     DestReg = createResultReg(&PPC::VSSRCRegClass);
996     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::XSRSP),
997             DestReg)
998         .addReg(SrcReg);
999   } else {
1000     SrcReg = copyRegToRegClass(&PPC::F8RCRegClass, SrcReg);
1001     DestReg = createResultReg(&PPC::F4RCRegClass);
1002     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1003       TII.get(PPC::FRSP), DestReg)
1004       .addReg(SrcReg);
1005   }
1006 
1007   updateValueMap(I, DestReg);
1008   return true;
1009 }
1010 
1011 // Move an i32 or i64 value in a GPR to an f64 value in an FPR.
1012 // FIXME: When direct register moves are implemented (see PowerISA 2.07),
1013 // those should be used instead of moving via a stack slot when the
1014 // subtarget permits.
1015 // FIXME: The code here is sloppy for the 4-byte case.  Can use a 4-byte
1016 // stack slot and 4-byte store/load sequence.  Or just sext the 4-byte
1017 // case to 8 bytes which produces tighter code but wastes stack space.
1018 unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg,
1019                                      bool IsSigned) {
1020 
1021   // If necessary, extend 32-bit int to 64-bit.
1022   if (SrcVT == MVT::i32) {
1023     Register TmpReg = createResultReg(&PPC::G8RCRegClass);
1024     if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
1025       return 0;
1026     SrcReg = TmpReg;
1027   }
1028 
1029   // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
1030   Address Addr;
1031   Addr.BaseType = Address::FrameIndexBase;
1032   Addr.Base.FI = MFI.CreateStackObject(8, Align(8), false);
1033 
1034   // Store the value from the GPR.
1035   if (!PPCEmitStore(MVT::i64, SrcReg, Addr))
1036     return 0;
1037 
1038   // Load the integer value into an FPR.  The kind of load used depends
1039   // on a number of conditions.
1040   unsigned LoadOpc = PPC::LFD;
1041 
1042   if (SrcVT == MVT::i32) {
1043     if (!IsSigned) {
1044       LoadOpc = PPC::LFIWZX;
1045       Addr.Offset = (Subtarget->isLittleEndian()) ? 0 : 4;
1046     } else if (Subtarget->hasLFIWAX()) {
1047       LoadOpc = PPC::LFIWAX;
1048       Addr.Offset = (Subtarget->isLittleEndian()) ? 0 : 4;
1049     }
1050   }
1051 
1052   const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1053   Register ResultReg = 0;
1054   if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
1055     return 0;
1056 
1057   return ResultReg;
1058 }
1059 
1060 // Attempt to fast-select an integer-to-floating-point conversion.
1061 // FIXME: Once fast-isel has better support for VSX, conversions using
1062 //        direct moves should be implemented.
1063 bool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) {
1064   MVT DstVT;
1065   Type *DstTy = I->getType();
1066   if (!isTypeLegal(DstTy, DstVT))
1067     return false;
1068 
1069   if (DstVT != MVT::f32 && DstVT != MVT::f64)
1070     return false;
1071 
1072   Value *Src = I->getOperand(0);
1073   EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true);
1074   if (!SrcEVT.isSimple())
1075     return false;
1076 
1077   MVT SrcVT = SrcEVT.getSimpleVT();
1078 
1079   if (SrcVT != MVT::i8  && SrcVT != MVT::i16 &&
1080       SrcVT != MVT::i32 && SrcVT != MVT::i64)
1081     return false;
1082 
1083   Register SrcReg = getRegForValue(Src);
1084   if (SrcReg == 0)
1085     return false;
1086 
1087   // Shortcut for SPE.  Doesn't need to store/load, since it's all in the GPRs
1088   if (Subtarget->hasSPE()) {
1089     unsigned Opc;
1090     if (DstVT == MVT::f32)
1091       Opc = IsSigned ? PPC::EFSCFSI : PPC::EFSCFUI;
1092     else
1093       Opc = IsSigned ? PPC::EFDCFSI : PPC::EFDCFUI;
1094 
1095     Register DestReg = createResultReg(&PPC::SPERCRegClass);
1096     // Generate the convert.
1097     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1098       .addReg(SrcReg);
1099     updateValueMap(I, DestReg);
1100     return true;
1101   }
1102 
1103   // We can only lower an unsigned convert if we have the newer
1104   // floating-point conversion operations.
1105   if (!IsSigned && !Subtarget->hasFPCVT())
1106     return false;
1107 
1108   // FIXME: For now we require the newer floating-point conversion operations
1109   // (which are present only on P7 and A2 server models) when converting
1110   // to single-precision float.  Otherwise we have to generate a lot of
1111   // fiddly code to avoid double rounding.  If necessary, the fiddly code
1112   // can be found in PPCTargetLowering::LowerINT_TO_FP().
1113   if (DstVT == MVT::f32 && !Subtarget->hasFPCVT())
1114     return false;
1115 
1116   // Extend the input if necessary.
1117   if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
1118     Register TmpReg = createResultReg(&PPC::G8RCRegClass);
1119     if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned))
1120       return false;
1121     SrcVT = MVT::i64;
1122     SrcReg = TmpReg;
1123   }
1124 
1125   // Move the integer value to an FPR.
1126   unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned);
1127   if (FPReg == 0)
1128     return false;
1129 
1130   // Determine the opcode for the conversion.
1131   const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1132   Register DestReg = createResultReg(RC);
1133   unsigned Opc;
1134 
1135   if (DstVT == MVT::f32)
1136     Opc = IsSigned ? PPC::FCFIDS : PPC::FCFIDUS;
1137   else
1138     Opc = IsSigned ? PPC::FCFID : PPC::FCFIDU;
1139 
1140   // Generate the convert.
1141   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1142     .addReg(FPReg);
1143 
1144   updateValueMap(I, DestReg);
1145   return true;
1146 }
1147 
1148 // Move the floating-point value in SrcReg into an integer destination
1149 // register, and return the register (or zero if we can't handle it).
1150 // FIXME: When direct register moves are implemented (see PowerISA 2.07),
1151 // those should be used instead of moving via a stack slot when the
1152 // subtarget permits.
1153 unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT,
1154                                       unsigned SrcReg, bool IsSigned) {
1155   // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
1156   // Note that if have STFIWX available, we could use a 4-byte stack
1157   // slot for i32, but this being fast-isel we'll just go with the
1158   // easiest code gen possible.
1159   Address Addr;
1160   Addr.BaseType = Address::FrameIndexBase;
1161   Addr.Base.FI = MFI.CreateStackObject(8, Align(8), false);
1162 
1163   // Store the value from the FPR.
1164   if (!PPCEmitStore(MVT::f64, SrcReg, Addr))
1165     return 0;
1166 
1167   // Reload it into a GPR.  If we want an i32 on big endian, modify the
1168   // address to have a 4-byte offset so we load from the right place.
1169   if (VT == MVT::i32)
1170     Addr.Offset = (Subtarget->isLittleEndian()) ? 0 : 4;
1171 
1172   // Look at the currently assigned register for this instruction
1173   // to determine the required register class.
1174   Register AssignedReg = FuncInfo.ValueMap[I];
1175   const TargetRegisterClass *RC =
1176     AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
1177 
1178   Register ResultReg = 0;
1179   if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1180     return 0;
1181 
1182   return ResultReg;
1183 }
1184 
1185 // Attempt to fast-select a floating-point-to-integer conversion.
1186 // FIXME: Once fast-isel has better support for VSX, conversions using
1187 //        direct moves should be implemented.
1188 bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
1189   MVT DstVT, SrcVT;
1190   Type *DstTy = I->getType();
1191   if (!isTypeLegal(DstTy, DstVT))
1192     return false;
1193 
1194   if (DstVT != MVT::i32 && DstVT != MVT::i64)
1195     return false;
1196 
1197   // If we don't have FCTIDUZ, or SPE, and we need it, punt to SelectionDAG.
1198   if (DstVT == MVT::i64 && !IsSigned && !Subtarget->hasFPCVT() &&
1199       !Subtarget->hasSPE())
1200     return false;
1201 
1202   Value *Src = I->getOperand(0);
1203   Type *SrcTy = Src->getType();
1204   if (!isTypeLegal(SrcTy, SrcVT))
1205     return false;
1206 
1207   if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1208     return false;
1209 
1210   Register SrcReg = getRegForValue(Src);
1211   if (SrcReg == 0)
1212     return false;
1213 
1214   // Convert f32 to f64 or convert VSSRC to VSFRC if necessary. This is just a
1215   // meaningless copy to get the register class right.
1216   const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
1217   if (InRC == &PPC::F4RCRegClass)
1218     SrcReg = copyRegToRegClass(&PPC::F8RCRegClass, SrcReg);
1219   else if (InRC == &PPC::VSSRCRegClass)
1220     SrcReg = copyRegToRegClass(&PPC::VSFRCRegClass, SrcReg);
1221 
1222   // Determine the opcode for the conversion, which takes place
1223   // entirely within FPRs or VSRs.
1224   unsigned DestReg;
1225   unsigned Opc;
1226   auto RC = MRI.getRegClass(SrcReg);
1227 
1228   if (Subtarget->hasSPE()) {
1229     DestReg = createResultReg(&PPC::GPRCRegClass);
1230     if (IsSigned)
1231       Opc = InRC == &PPC::GPRCRegClass ? PPC::EFSCTSIZ : PPC::EFDCTSIZ;
1232     else
1233       Opc = InRC == &PPC::GPRCRegClass ? PPC::EFSCTUIZ : PPC::EFDCTUIZ;
1234   } else if (isVSFRCRegClass(RC)) {
1235     DestReg = createResultReg(&PPC::VSFRCRegClass);
1236     if (DstVT == MVT::i32)
1237       Opc = IsSigned ? PPC::XSCVDPSXWS : PPC::XSCVDPUXWS;
1238     else
1239       Opc = IsSigned ? PPC::XSCVDPSXDS : PPC::XSCVDPUXDS;
1240   } else {
1241     DestReg = createResultReg(&PPC::F8RCRegClass);
1242     if (DstVT == MVT::i32)
1243       if (IsSigned)
1244         Opc = PPC::FCTIWZ;
1245       else
1246         Opc = Subtarget->hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ;
1247     else
1248       Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ;
1249   }
1250 
1251   // Generate the convert.
1252   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1253     .addReg(SrcReg);
1254 
1255   // Now move the integer value from a float register to an integer register.
1256   unsigned IntReg = Subtarget->hasSPE()
1257                         ? DestReg
1258                         : PPCMoveToIntReg(I, DstVT, DestReg, IsSigned);
1259 
1260   if (IntReg == 0)
1261     return false;
1262 
1263   updateValueMap(I, IntReg);
1264   return true;
1265 }
1266 
1267 // Attempt to fast-select a binary integer operation that isn't already
1268 // handled automatically.
1269 bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1270   EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1271 
1272   // We can get here in the case when we have a binary operation on a non-legal
1273   // type and the target independent selector doesn't know how to handle it.
1274   if (DestVT != MVT::i16 && DestVT != MVT::i8)
1275     return false;
1276 
1277   // Look at the currently assigned register for this instruction
1278   // to determine the required register class.  If there is no register,
1279   // make a conservative choice (don't assign R0).
1280   Register AssignedReg = FuncInfo.ValueMap[I];
1281   const TargetRegisterClass *RC =
1282     (AssignedReg ? MRI.getRegClass(AssignedReg) :
1283      &PPC::GPRC_and_GPRC_NOR0RegClass);
1284   bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1285 
1286   unsigned Opc;
1287   switch (ISDOpcode) {
1288     default: return false;
1289     case ISD::ADD:
1290       Opc = IsGPRC ? PPC::ADD4 : PPC::ADD8;
1291       break;
1292     case ISD::OR:
1293       Opc = IsGPRC ? PPC::OR : PPC::OR8;
1294       break;
1295     case ISD::SUB:
1296       Opc = IsGPRC ? PPC::SUBF : PPC::SUBF8;
1297       break;
1298   }
1299 
1300   Register ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1301   Register SrcReg1 = getRegForValue(I->getOperand(0));
1302   if (SrcReg1 == 0) return false;
1303 
1304   // Handle case of small immediate operand.
1305   if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(1))) {
1306     const APInt &CIVal = ConstInt->getValue();
1307     int Imm = (int)CIVal.getSExtValue();
1308     bool UseImm = true;
1309     if (isInt<16>(Imm)) {
1310       switch (Opc) {
1311         default:
1312           llvm_unreachable("Missing case!");
1313         case PPC::ADD4:
1314           Opc = PPC::ADDI;
1315           MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1316           break;
1317         case PPC::ADD8:
1318           Opc = PPC::ADDI8;
1319           MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1320           break;
1321         case PPC::OR:
1322           Opc = PPC::ORI;
1323           break;
1324         case PPC::OR8:
1325           Opc = PPC::ORI8;
1326           break;
1327         case PPC::SUBF:
1328           if (Imm == -32768)
1329             UseImm = false;
1330           else {
1331             Opc = PPC::ADDI;
1332             MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1333             Imm = -Imm;
1334           }
1335           break;
1336         case PPC::SUBF8:
1337           if (Imm == -32768)
1338             UseImm = false;
1339           else {
1340             Opc = PPC::ADDI8;
1341             MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1342             Imm = -Imm;
1343           }
1344           break;
1345       }
1346 
1347       if (UseImm) {
1348         BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1349                 ResultReg)
1350             .addReg(SrcReg1)
1351             .addImm(Imm);
1352         updateValueMap(I, ResultReg);
1353         return true;
1354       }
1355     }
1356   }
1357 
1358   // Reg-reg case.
1359   Register SrcReg2 = getRegForValue(I->getOperand(1));
1360   if (SrcReg2 == 0) return false;
1361 
1362   // Reverse operands for subtract-from.
1363   if (ISDOpcode == ISD::SUB)
1364     std::swap(SrcReg1, SrcReg2);
1365 
1366   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1367     .addReg(SrcReg1).addReg(SrcReg2);
1368   updateValueMap(I, ResultReg);
1369   return true;
1370 }
1371 
1372 // Handle arguments to a call that we're attempting to fast-select.
1373 // Return false if the arguments are too complex for us at the moment.
1374 bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args,
1375                                   SmallVectorImpl<unsigned> &ArgRegs,
1376                                   SmallVectorImpl<MVT> &ArgVTs,
1377                                   SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1378                                   SmallVectorImpl<unsigned> &RegArgs,
1379                                   CallingConv::ID CC,
1380                                   unsigned &NumBytes,
1381                                   bool IsVarArg) {
1382   SmallVector<CCValAssign, 16> ArgLocs;
1383   CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, *Context);
1384 
1385   // Reserve space for the linkage area on the stack.
1386   unsigned LinkageSize = Subtarget->getFrameLowering()->getLinkageSize();
1387   CCInfo.AllocateStack(LinkageSize, Align(8));
1388 
1389   CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
1390 
1391   // Bail out if we can't handle any of the arguments.
1392   for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1393     CCValAssign &VA = ArgLocs[I];
1394     MVT ArgVT = ArgVTs[VA.getValNo()];
1395 
1396     // Skip vector arguments for now, as well as long double and
1397     // uint128_t, and anything that isn't passed in a register.
1398     if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 || ArgVT == MVT::i1 ||
1399         !VA.isRegLoc() || VA.needsCustom())
1400       return false;
1401 
1402     // Skip bit-converted arguments for now.
1403     if (VA.getLocInfo() == CCValAssign::BCvt)
1404       return false;
1405   }
1406 
1407   // Get a count of how many bytes are to be pushed onto the stack.
1408   NumBytes = CCInfo.getNextStackOffset();
1409 
1410   // The prolog code of the callee may store up to 8 GPR argument registers to
1411   // the stack, allowing va_start to index over them in memory if its varargs.
1412   // Because we cannot tell if this is needed on the caller side, we have to
1413   // conservatively assume that it is needed.  As such, make sure we have at
1414   // least enough stack space for the caller to store the 8 GPRs.
1415   // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
1416   NumBytes = std::max(NumBytes, LinkageSize + 64);
1417 
1418   // Issue CALLSEQ_START.
1419   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1420           TII.get(TII.getCallFrameSetupOpcode()))
1421     .addImm(NumBytes).addImm(0);
1422 
1423   // Prepare to assign register arguments.  Every argument uses up a
1424   // GPR protocol register even if it's passed in a floating-point
1425   // register (unless we're using the fast calling convention).
1426   unsigned NextGPR = PPC::X3;
1427   unsigned NextFPR = PPC::F1;
1428 
1429   // Process arguments.
1430   for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1431     CCValAssign &VA = ArgLocs[I];
1432     unsigned Arg = ArgRegs[VA.getValNo()];
1433     MVT ArgVT = ArgVTs[VA.getValNo()];
1434 
1435     // Handle argument promotion and bitcasts.
1436     switch (VA.getLocInfo()) {
1437       default:
1438         llvm_unreachable("Unknown loc info!");
1439       case CCValAssign::Full:
1440         break;
1441       case CCValAssign::SExt: {
1442         MVT DestVT = VA.getLocVT();
1443         const TargetRegisterClass *RC =
1444           (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1445         Register TmpReg = createResultReg(RC);
1446         if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
1447           llvm_unreachable("Failed to emit a sext!");
1448         ArgVT = DestVT;
1449         Arg = TmpReg;
1450         break;
1451       }
1452       case CCValAssign::AExt:
1453       case CCValAssign::ZExt: {
1454         MVT DestVT = VA.getLocVT();
1455         const TargetRegisterClass *RC =
1456           (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1457         Register TmpReg = createResultReg(RC);
1458         if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
1459           llvm_unreachable("Failed to emit a zext!");
1460         ArgVT = DestVT;
1461         Arg = TmpReg;
1462         break;
1463       }
1464       case CCValAssign::BCvt: {
1465         // FIXME: Not yet handled.
1466         llvm_unreachable("Should have bailed before getting here!");
1467         break;
1468       }
1469     }
1470 
1471     // Copy this argument to the appropriate register.
1472     unsigned ArgReg;
1473     if (ArgVT == MVT::f32 || ArgVT == MVT::f64) {
1474       ArgReg = NextFPR++;
1475       if (CC != CallingConv::Fast)
1476         ++NextGPR;
1477     } else
1478       ArgReg = NextGPR++;
1479 
1480     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1481             TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg);
1482     RegArgs.push_back(ArgReg);
1483   }
1484 
1485   return true;
1486 }
1487 
1488 // For a call that we've determined we can fast-select, finish the
1489 // call sequence and generate a copy to obtain the return value (if any).
1490 bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes) {
1491   CallingConv::ID CC = CLI.CallConv;
1492 
1493   // Issue CallSEQ_END.
1494   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1495           TII.get(TII.getCallFrameDestroyOpcode()))
1496     .addImm(NumBytes).addImm(0);
1497 
1498   // Next, generate a copy to obtain the return value.
1499   // FIXME: No multi-register return values yet, though I don't foresee
1500   // any real difficulties there.
1501   if (RetVT != MVT::isVoid) {
1502     SmallVector<CCValAssign, 16> RVLocs;
1503     CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1504     CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1505     CCValAssign &VA = RVLocs[0];
1506     assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
1507     assert(VA.isRegLoc() && "Can only return in registers!");
1508 
1509     MVT DestVT = VA.getValVT();
1510     MVT CopyVT = DestVT;
1511 
1512     // Ints smaller than a register still arrive in a full 64-bit
1513     // register, so make sure we recognize this.
1514     if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1515       CopyVT = MVT::i64;
1516 
1517     unsigned SourcePhysReg = VA.getLocReg();
1518     unsigned ResultReg = 0;
1519 
1520     if (RetVT == CopyVT) {
1521       const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
1522       ResultReg = copyRegToRegClass(CpyRC, SourcePhysReg);
1523 
1524     // If necessary, round the floating result to single precision.
1525     } else if (CopyVT == MVT::f64) {
1526       ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1527       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP),
1528               ResultReg).addReg(SourcePhysReg);
1529 
1530     // If only the low half of a general register is needed, generate
1531     // a GPRC copy instead of a G8RC copy.  (EXTRACT_SUBREG can't be
1532     // used along the fast-isel path (not lowered), and downstream logic
1533     // also doesn't like a direct subreg copy on a physical reg.)
1534     } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
1535       // Convert physical register from G8RC to GPRC.
1536       SourcePhysReg -= PPC::X0 - PPC::R0;
1537       ResultReg = copyRegToRegClass(&PPC::GPRCRegClass, SourcePhysReg);
1538     }
1539 
1540     assert(ResultReg && "ResultReg unset!");
1541     CLI.InRegs.push_back(SourcePhysReg);
1542     CLI.ResultReg = ResultReg;
1543     CLI.NumResultRegs = 1;
1544   }
1545 
1546   return true;
1547 }
1548 
1549 bool PPCFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1550   CallingConv::ID CC  = CLI.CallConv;
1551   bool IsTailCall     = CLI.IsTailCall;
1552   bool IsVarArg       = CLI.IsVarArg;
1553   const Value *Callee = CLI.Callee;
1554   const MCSymbol *Symbol = CLI.Symbol;
1555 
1556   if (!Callee && !Symbol)
1557     return false;
1558 
1559   // Allow SelectionDAG isel to handle tail calls.
1560   if (IsTailCall)
1561     return false;
1562 
1563   // Let SDISel handle vararg functions.
1564   if (IsVarArg)
1565     return false;
1566 
1567   // If this is a PC-Rel function, let SDISel handle the call.
1568   if (Subtarget->isUsingPCRelativeCalls())
1569     return false;
1570 
1571   // Handle simple calls for now, with legal return types and
1572   // those that can be extended.
1573   Type *RetTy = CLI.RetTy;
1574   MVT RetVT;
1575   if (RetTy->isVoidTy())
1576     RetVT = MVT::isVoid;
1577   else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
1578            RetVT != MVT::i8)
1579     return false;
1580   else if (RetVT == MVT::i1 && Subtarget->useCRBits())
1581     // We can't handle boolean returns when CR bits are in use.
1582     return false;
1583 
1584   // FIXME: No multi-register return values yet.
1585   if (RetVT != MVT::isVoid && RetVT != MVT::i8 && RetVT != MVT::i16 &&
1586       RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 &&
1587       RetVT != MVT::f64) {
1588     SmallVector<CCValAssign, 16> RVLocs;
1589     CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context);
1590     CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1591     if (RVLocs.size() > 1)
1592       return false;
1593   }
1594 
1595   // Bail early if more than 8 arguments, as we only currently
1596   // handle arguments passed in registers.
1597   unsigned NumArgs = CLI.OutVals.size();
1598   if (NumArgs > 8)
1599     return false;
1600 
1601   // Set up the argument vectors.
1602   SmallVector<Value*, 8> Args;
1603   SmallVector<unsigned, 8> ArgRegs;
1604   SmallVector<MVT, 8> ArgVTs;
1605   SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1606 
1607   Args.reserve(NumArgs);
1608   ArgRegs.reserve(NumArgs);
1609   ArgVTs.reserve(NumArgs);
1610   ArgFlags.reserve(NumArgs);
1611 
1612   for (unsigned i = 0, ie = NumArgs; i != ie; ++i) {
1613     // Only handle easy calls for now.  It would be reasonably easy
1614     // to handle <= 8-byte structures passed ByVal in registers, but we
1615     // have to ensure they are right-justified in the register.
1616     ISD::ArgFlagsTy Flags = CLI.OutFlags[i];
1617     if (Flags.isInReg() || Flags.isSRet() || Flags.isNest() || Flags.isByVal())
1618       return false;
1619 
1620     Value *ArgValue = CLI.OutVals[i];
1621     Type *ArgTy = ArgValue->getType();
1622     MVT ArgVT;
1623     if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8)
1624       return false;
1625 
1626     // FIXME: FastISel cannot handle non-simple types yet, including 128-bit FP
1627     // types, which is passed through vector register. Skip these types and
1628     // fallback to default SelectionDAG based selection.
1629     if (ArgVT.isVector() || ArgVT == MVT::f128)
1630       return false;
1631 
1632     Register Arg = getRegForValue(ArgValue);
1633     if (Arg == 0)
1634       return false;
1635 
1636     Args.push_back(ArgValue);
1637     ArgRegs.push_back(Arg);
1638     ArgVTs.push_back(ArgVT);
1639     ArgFlags.push_back(Flags);
1640   }
1641 
1642   // Process the arguments.
1643   SmallVector<unsigned, 8> RegArgs;
1644   unsigned NumBytes;
1645 
1646   if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
1647                        RegArgs, CC, NumBytes, IsVarArg))
1648     return false;
1649 
1650   MachineInstrBuilder MIB;
1651   // FIXME: No handling for function pointers yet.  This requires
1652   // implementing the function descriptor (OPD) setup.
1653   const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1654   if (!GV) {
1655     // patchpoints are a special case; they always dispatch to a pointer value.
1656     // However, we don't actually want to generate the indirect call sequence
1657     // here (that will be generated, as necessary, during asm printing), and
1658     // the call we generate here will be erased by FastISel::selectPatchpoint,
1659     // so don't try very hard...
1660     if (CLI.IsPatchPoint)
1661       MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::NOP));
1662     else
1663       return false;
1664   } else {
1665     // Build direct call with NOP for TOC restore.
1666     // FIXME: We can and should optimize away the NOP for local calls.
1667     MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1668                   TII.get(PPC::BL8_NOP));
1669     // Add callee.
1670     MIB.addGlobalAddress(GV);
1671   }
1672 
1673   // Add implicit physical register uses to the call.
1674   for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II)
1675     MIB.addReg(RegArgs[II], RegState::Implicit);
1676 
1677   // Direct calls, in both the ELF V1 and V2 ABIs, need the TOC register live
1678   // into the call.
1679   PPCFuncInfo->setUsesTOCBasePtr();
1680   MIB.addReg(PPC::X2, RegState::Implicit);
1681 
1682   // Add a register mask with the call-preserved registers.  Proper
1683   // defs for return values will be added by setPhysRegsDeadExcept().
1684   MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1685 
1686   CLI.Call = MIB;
1687 
1688   // Finish off the call including any return values.
1689   return finishCall(RetVT, CLI, NumBytes);
1690 }
1691 
1692 // Attempt to fast-select a return instruction.
1693 bool PPCFastISel::SelectRet(const Instruction *I) {
1694 
1695   if (!FuncInfo.CanLowerReturn)
1696     return false;
1697 
1698   const ReturnInst *Ret = cast<ReturnInst>(I);
1699   const Function &F = *I->getParent()->getParent();
1700 
1701   // Build a list of return value registers.
1702   SmallVector<unsigned, 4> RetRegs;
1703   CallingConv::ID CC = F.getCallingConv();
1704 
1705   if (Ret->getNumOperands() > 0) {
1706     SmallVector<ISD::OutputArg, 4> Outs;
1707     GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1708 
1709     // Analyze operands of the call, assigning locations to each operand.
1710     SmallVector<CCValAssign, 16> ValLocs;
1711     CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, *Context);
1712     CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
1713     const Value *RV = Ret->getOperand(0);
1714 
1715     // FIXME: Only one output register for now.
1716     if (ValLocs.size() > 1)
1717       return false;
1718 
1719     // Special case for returning a constant integer of any size - materialize
1720     // the constant as an i64 and copy it to the return register.
1721     if (const ConstantInt *CI = dyn_cast<ConstantInt>(RV)) {
1722       CCValAssign &VA = ValLocs[0];
1723 
1724       Register RetReg = VA.getLocReg();
1725       // We still need to worry about properly extending the sign. For example,
1726       // we could have only a single bit or a constant that needs zero
1727       // extension rather than sign extension. Make sure we pass the return
1728       // value extension property to integer materialization.
1729       unsigned SrcReg =
1730           PPCMaterializeInt(CI, MVT::i64, VA.getLocInfo() != CCValAssign::ZExt);
1731 
1732       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1733             TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
1734 
1735       RetRegs.push_back(RetReg);
1736 
1737     } else {
1738       Register Reg = getRegForValue(RV);
1739 
1740       if (Reg == 0)
1741         return false;
1742 
1743       // Copy the result values into the output registers.
1744       for (unsigned i = 0; i < ValLocs.size(); ++i) {
1745 
1746         CCValAssign &VA = ValLocs[i];
1747         assert(VA.isRegLoc() && "Can only return in registers!");
1748         RetRegs.push_back(VA.getLocReg());
1749         unsigned SrcReg = Reg + VA.getValNo();
1750 
1751         EVT RVEVT = TLI.getValueType(DL, RV->getType());
1752         if (!RVEVT.isSimple())
1753           return false;
1754         MVT RVVT = RVEVT.getSimpleVT();
1755         MVT DestVT = VA.getLocVT();
1756 
1757         if (RVVT != DestVT && RVVT != MVT::i8 &&
1758             RVVT != MVT::i16 && RVVT != MVT::i32)
1759           return false;
1760 
1761         if (RVVT != DestVT) {
1762           switch (VA.getLocInfo()) {
1763             default:
1764               llvm_unreachable("Unknown loc info!");
1765             case CCValAssign::Full:
1766               llvm_unreachable("Full value assign but types don't match?");
1767             case CCValAssign::AExt:
1768             case CCValAssign::ZExt: {
1769               const TargetRegisterClass *RC =
1770                 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1771               Register TmpReg = createResultReg(RC);
1772               if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, true))
1773                 return false;
1774               SrcReg = TmpReg;
1775               break;
1776             }
1777             case CCValAssign::SExt: {
1778               const TargetRegisterClass *RC =
1779                 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1780               Register TmpReg = createResultReg(RC);
1781               if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, false))
1782                 return false;
1783               SrcReg = TmpReg;
1784               break;
1785             }
1786           }
1787         }
1788 
1789         BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1790                 TII.get(TargetOpcode::COPY), RetRegs[i])
1791           .addReg(SrcReg);
1792       }
1793     }
1794   }
1795 
1796   MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1797                                     TII.get(PPC::BLR8));
1798 
1799   for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1800     MIB.addReg(RetRegs[i], RegState::Implicit);
1801 
1802   return true;
1803 }
1804 
1805 // Attempt to emit an integer extend of SrcReg into DestReg.  Both
1806 // signed and zero extensions are supported.  Return false if we
1807 // can't handle it.
1808 bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1809                                 unsigned DestReg, bool IsZExt) {
1810   if (DestVT != MVT::i32 && DestVT != MVT::i64)
1811     return false;
1812   if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32)
1813     return false;
1814 
1815   // Signed extensions use EXTSB, EXTSH, EXTSW.
1816   if (!IsZExt) {
1817     unsigned Opc;
1818     if (SrcVT == MVT::i8)
1819       Opc = (DestVT == MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64;
1820     else if (SrcVT == MVT::i16)
1821       Opc = (DestVT == MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64;
1822     else {
1823       assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??");
1824       Opc = PPC::EXTSW_32_64;
1825     }
1826     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1827       .addReg(SrcReg);
1828 
1829   // Unsigned 32-bit extensions use RLWINM.
1830   } else if (DestVT == MVT::i32) {
1831     unsigned MB;
1832     if (SrcVT == MVT::i8)
1833       MB = 24;
1834     else {
1835       assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
1836       MB = 16;
1837     }
1838     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLWINM),
1839             DestReg)
1840       .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1841 
1842   // Unsigned 64-bit extensions use RLDICL (with a 32-bit source).
1843   } else {
1844     unsigned MB;
1845     if (SrcVT == MVT::i8)
1846       MB = 56;
1847     else if (SrcVT == MVT::i16)
1848       MB = 48;
1849     else
1850       MB = 32;
1851     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1852             TII.get(PPC::RLDICL_32_64), DestReg)
1853       .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
1854   }
1855 
1856   return true;
1857 }
1858 
1859 // Attempt to fast-select an indirect branch instruction.
1860 bool PPCFastISel::SelectIndirectBr(const Instruction *I) {
1861   Register AddrReg = getRegForValue(I->getOperand(0));
1862   if (AddrReg == 0)
1863     return false;
1864 
1865   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::MTCTR8))
1866     .addReg(AddrReg);
1867   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCTR8));
1868 
1869   const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1870   for (const BasicBlock *SuccBB : IB->successors())
1871     FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[SuccBB]);
1872 
1873   return true;
1874 }
1875 
1876 // Attempt to fast-select an integer truncate instruction.
1877 bool PPCFastISel::SelectTrunc(const Instruction *I) {
1878   Value *Src  = I->getOperand(0);
1879   EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1880   EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1881 
1882   if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16)
1883     return false;
1884 
1885   if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
1886     return false;
1887 
1888   Register SrcReg = getRegForValue(Src);
1889   if (!SrcReg)
1890     return false;
1891 
1892   // The only interesting case is when we need to switch register classes.
1893   if (SrcVT == MVT::i64)
1894     SrcReg = copyRegToRegClass(&PPC::GPRCRegClass, SrcReg, 0, PPC::sub_32);
1895 
1896   updateValueMap(I, SrcReg);
1897   return true;
1898 }
1899 
1900 // Attempt to fast-select an integer extend instruction.
1901 bool PPCFastISel::SelectIntExt(const Instruction *I) {
1902   Type *DestTy = I->getType();
1903   Value *Src = I->getOperand(0);
1904   Type *SrcTy = Src->getType();
1905 
1906   bool IsZExt = isa<ZExtInst>(I);
1907   Register SrcReg = getRegForValue(Src);
1908   if (!SrcReg) return false;
1909 
1910   EVT SrcEVT, DestEVT;
1911   SrcEVT = TLI.getValueType(DL, SrcTy, true);
1912   DestEVT = TLI.getValueType(DL, DestTy, true);
1913   if (!SrcEVT.isSimple())
1914     return false;
1915   if (!DestEVT.isSimple())
1916     return false;
1917 
1918   MVT SrcVT = SrcEVT.getSimpleVT();
1919   MVT DestVT = DestEVT.getSimpleVT();
1920 
1921   // If we know the register class needed for the result of this
1922   // instruction, use it.  Otherwise pick the register class of the
1923   // correct size that does not contain X0/R0, since we don't know
1924   // whether downstream uses permit that assignment.
1925   Register AssignedReg = FuncInfo.ValueMap[I];
1926   const TargetRegisterClass *RC =
1927     (AssignedReg ? MRI.getRegClass(AssignedReg) :
1928      (DestVT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
1929       &PPC::GPRC_and_GPRC_NOR0RegClass));
1930   Register ResultReg = createResultReg(RC);
1931 
1932   if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1933     return false;
1934 
1935   updateValueMap(I, ResultReg);
1936   return true;
1937 }
1938 
1939 // Attempt to fast-select an instruction that wasn't handled by
1940 // the table-generated machinery.
1941 bool PPCFastISel::fastSelectInstruction(const Instruction *I) {
1942 
1943   switch (I->getOpcode()) {
1944     case Instruction::Load:
1945       return SelectLoad(I);
1946     case Instruction::Store:
1947       return SelectStore(I);
1948     case Instruction::Br:
1949       return SelectBranch(I);
1950     case Instruction::IndirectBr:
1951       return SelectIndirectBr(I);
1952     case Instruction::FPExt:
1953       return SelectFPExt(I);
1954     case Instruction::FPTrunc:
1955       return SelectFPTrunc(I);
1956     case Instruction::SIToFP:
1957       return SelectIToFP(I, /*IsSigned*/ true);
1958     case Instruction::UIToFP:
1959       return SelectIToFP(I, /*IsSigned*/ false);
1960     case Instruction::FPToSI:
1961       return SelectFPToI(I, /*IsSigned*/ true);
1962     case Instruction::FPToUI:
1963       return SelectFPToI(I, /*IsSigned*/ false);
1964     case Instruction::Add:
1965       return SelectBinaryIntOp(I, ISD::ADD);
1966     case Instruction::Or:
1967       return SelectBinaryIntOp(I, ISD::OR);
1968     case Instruction::Sub:
1969       return SelectBinaryIntOp(I, ISD::SUB);
1970     case Instruction::Ret:
1971       return SelectRet(I);
1972     case Instruction::Trunc:
1973       return SelectTrunc(I);
1974     case Instruction::ZExt:
1975     case Instruction::SExt:
1976       return SelectIntExt(I);
1977     // Here add other flavors of Instruction::XXX that automated
1978     // cases don't catch.  For example, switches are terminators
1979     // that aren't yet handled.
1980     default:
1981       break;
1982   }
1983   return false;
1984 }
1985 
1986 // Materialize a floating-point constant into a register, and return
1987 // the register number (or zero if we failed to handle it).
1988 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
1989   // If this is a PC-Rel function, let SDISel handle constant pool.
1990   if (Subtarget->isUsingPCRelativeCalls())
1991     return false;
1992 
1993   // No plans to handle long double here.
1994   if (VT != MVT::f32 && VT != MVT::f64)
1995     return 0;
1996 
1997   // All FP constants are loaded from the constant pool.
1998   Align Alignment = DL.getPrefTypeAlign(CFP->getType());
1999   unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Alignment);
2000   const bool HasSPE = Subtarget->hasSPE();
2001   const TargetRegisterClass *RC;
2002   if (HasSPE)
2003     RC = ((VT == MVT::f32) ? &PPC::GPRCRegClass : &PPC::SPERCRegClass);
2004   else
2005     RC = ((VT == MVT::f32) ? &PPC::F4RCRegClass : &PPC::F8RCRegClass);
2006 
2007   Register DestReg = createResultReg(RC);
2008   CodeModel::Model CModel = TM.getCodeModel();
2009 
2010   MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
2011       MachinePointerInfo::getConstantPool(*FuncInfo.MF),
2012       MachineMemOperand::MOLoad, (VT == MVT::f32) ? 4 : 8, Alignment);
2013 
2014   unsigned Opc;
2015 
2016   if (HasSPE)
2017     Opc = ((VT == MVT::f32) ? PPC::SPELWZ : PPC::EVLDD);
2018   else
2019     Opc = ((VT == MVT::f32) ? PPC::LFS : PPC::LFD);
2020 
2021   Register TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2022 
2023   PPCFuncInfo->setUsesTOCBasePtr();
2024   // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
2025   if (CModel == CodeModel::Small) {
2026     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT),
2027             TmpReg)
2028       .addConstantPoolIndex(Idx).addReg(PPC::X2);
2029     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2030       .addImm(0).addReg(TmpReg).addMemOperand(MMO);
2031   } else {
2032     // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA8(X2, Idx)).
2033     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA8),
2034             TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
2035     // But for large code model, we must generate a LDtocL followed
2036     // by the LF[SD].
2037     if (CModel == CodeModel::Large) {
2038       Register TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2039       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
2040               TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg);
2041       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2042           .addImm(0)
2043           .addReg(TmpReg2);
2044     } else
2045       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2046         .addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO)
2047         .addReg(TmpReg)
2048         .addMemOperand(MMO);
2049   }
2050 
2051   return DestReg;
2052 }
2053 
2054 // Materialize the address of a global value into a register, and return
2055 // the register number (or zero if we failed to handle it).
2056 unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
2057   // If this is a PC-Rel function, let SDISel handle GV materialization.
2058   if (Subtarget->isUsingPCRelativeCalls())
2059     return false;
2060 
2061   assert(VT == MVT::i64 && "Non-address!");
2062   const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
2063   Register DestReg = createResultReg(RC);
2064 
2065   // Global values may be plain old object addresses, TLS object
2066   // addresses, constant pool entries, or jump tables.  How we generate
2067   // code for these may depend on small, medium, or large code model.
2068   CodeModel::Model CModel = TM.getCodeModel();
2069 
2070   // FIXME: Jump tables are not yet required because fast-isel doesn't
2071   // handle switches; if that changes, we need them as well.  For now,
2072   // what follows assumes everything's a generic (or TLS) global address.
2073 
2074   // FIXME: We don't yet handle the complexity of TLS.
2075   if (GV->isThreadLocal())
2076     return 0;
2077 
2078   // If the global has the toc-data attribute then fallback to DAG-ISEL.
2079   if (TM.getTargetTriple().isOSAIX())
2080     if (const GlobalVariable *Var = dyn_cast_or_null<GlobalVariable>(GV))
2081       if (Var->hasAttribute("toc-data"))
2082         return false;
2083 
2084   PPCFuncInfo->setUsesTOCBasePtr();
2085   // For small code model, generate a simple TOC load.
2086   if (CModel == CodeModel::Small)
2087     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc),
2088             DestReg)
2089         .addGlobalAddress(GV)
2090         .addReg(PPC::X2);
2091   else {
2092     // If the address is an externally defined symbol, a symbol with common
2093     // or externally available linkage, a non-local function address, or a
2094     // jump table address (not yet needed), or if we are generating code
2095     // for large code model, we generate:
2096     //       LDtocL(GV, ADDIStocHA8(%x2, GV))
2097     // Otherwise we generate:
2098     //       ADDItocL(ADDIStocHA8(%x2, GV), GV)
2099     // Either way, start with the ADDIStocHA8:
2100     Register HighPartReg = createResultReg(RC);
2101     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA8),
2102             HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
2103 
2104     if (Subtarget->isGVIndirectSymbol(GV)) {
2105       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
2106               DestReg).addGlobalAddress(GV).addReg(HighPartReg);
2107     } else {
2108       // Otherwise generate the ADDItocL.
2109       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDItocL),
2110               DestReg).addReg(HighPartReg).addGlobalAddress(GV);
2111     }
2112   }
2113 
2114   return DestReg;
2115 }
2116 
2117 // Materialize a 32-bit integer constant into a register, and return
2118 // the register number (or zero if we failed to handle it).
2119 unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm,
2120                                              const TargetRegisterClass *RC) {
2121   unsigned Lo = Imm & 0xFFFF;
2122   unsigned Hi = (Imm >> 16) & 0xFFFF;
2123 
2124   Register ResultReg = createResultReg(RC);
2125   bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
2126 
2127   if (isInt<16>(Imm))
2128     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2129             TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
2130       .addImm(Imm);
2131   else if (Lo) {
2132     // Both Lo and Hi have nonzero bits.
2133     Register TmpReg = createResultReg(RC);
2134     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2135             TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
2136       .addImm(Hi);
2137     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2138             TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
2139       .addReg(TmpReg).addImm(Lo);
2140   } else
2141     // Just Hi bits.
2142     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2143             TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
2144         .addImm(Hi);
2145 
2146   return ResultReg;
2147 }
2148 
2149 // Materialize a 64-bit integer constant into a register, and return
2150 // the register number (or zero if we failed to handle it).
2151 unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
2152                                              const TargetRegisterClass *RC) {
2153   unsigned Remainder = 0;
2154   unsigned Shift = 0;
2155 
2156   // If the value doesn't fit in 32 bits, see if we can shift it
2157   // so that it fits in 32 bits.
2158   if (!isInt<32>(Imm)) {
2159     Shift = countTrailingZeros<uint64_t>(Imm);
2160     int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
2161 
2162     if (isInt<32>(ImmSh))
2163       Imm = ImmSh;
2164     else {
2165       Remainder = Imm;
2166       Shift = 32;
2167       Imm >>= 32;
2168     }
2169   }
2170 
2171   // Handle the high-order 32 bits (if shifted) or the whole 32 bits
2172   // (if not shifted).
2173   unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
2174   if (!Shift)
2175     return TmpReg1;
2176 
2177   // If upper 32 bits were not zero, we've built them and need to shift
2178   // them into place.
2179   unsigned TmpReg2;
2180   if (Imm) {
2181     TmpReg2 = createResultReg(RC);
2182     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLDICR),
2183             TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
2184   } else
2185     TmpReg2 = TmpReg1;
2186 
2187   unsigned TmpReg3, Hi, Lo;
2188   if ((Hi = (Remainder >> 16) & 0xFFFF)) {
2189     TmpReg3 = createResultReg(RC);
2190     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORIS8),
2191             TmpReg3).addReg(TmpReg2).addImm(Hi);
2192   } else
2193     TmpReg3 = TmpReg2;
2194 
2195   if ((Lo = Remainder & 0xFFFF)) {
2196     Register ResultReg = createResultReg(RC);
2197     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORI8),
2198             ResultReg).addReg(TmpReg3).addImm(Lo);
2199     return ResultReg;
2200   }
2201 
2202   return TmpReg3;
2203 }
2204 
2205 // Materialize an integer constant into a register, and return
2206 // the register number (or zero if we failed to handle it).
2207 unsigned PPCFastISel::PPCMaterializeInt(const ConstantInt *CI, MVT VT,
2208                                         bool UseSExt) {
2209   // If we're using CR bit registers for i1 values, handle that as a special
2210   // case first.
2211   if (VT == MVT::i1 && Subtarget->useCRBits()) {
2212     Register ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2213     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2214             TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2215     return ImmReg;
2216   }
2217 
2218   if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 &&
2219       VT != MVT::i1)
2220     return 0;
2221 
2222   const TargetRegisterClass *RC =
2223       ((VT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass);
2224   int64_t Imm = UseSExt ? CI->getSExtValue() : CI->getZExtValue();
2225 
2226   // If the constant is in range, use a load-immediate.
2227   // Since LI will sign extend the constant we need to make sure that for
2228   // our zeroext constants that the sign extended constant fits into 16-bits -
2229   // a range of 0..0x7fff.
2230   if (isInt<16>(Imm)) {
2231     unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
2232     Register ImmReg = createResultReg(RC);
2233     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
2234         .addImm(Imm);
2235     return ImmReg;
2236   }
2237 
2238   // Construct the constant piecewise.
2239   if (VT == MVT::i64)
2240     return PPCMaterialize64BitInt(Imm, RC);
2241   else if (VT == MVT::i32)
2242     return PPCMaterialize32BitInt(Imm, RC);
2243 
2244   return 0;
2245 }
2246 
2247 // Materialize a constant into a register, and return the register
2248 // number (or zero if we failed to handle it).
2249 unsigned PPCFastISel::fastMaterializeConstant(const Constant *C) {
2250   EVT CEVT = TLI.getValueType(DL, C->getType(), true);
2251 
2252   // Only handle simple types.
2253   if (!CEVT.isSimple()) return 0;
2254   MVT VT = CEVT.getSimpleVT();
2255 
2256   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
2257     return PPCMaterializeFP(CFP, VT);
2258   else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
2259     return PPCMaterializeGV(GV, VT);
2260   else if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
2261     // Note that the code in FunctionLoweringInfo::ComputePHILiveOutRegInfo
2262     // assumes that constant PHI operands will be zero extended, and failure to
2263     // match that assumption will cause problems if we sign extend here but
2264     // some user of a PHI is in a block for which we fall back to full SDAG
2265     // instruction selection.
2266     return PPCMaterializeInt(CI, VT, false);
2267 
2268   return 0;
2269 }
2270 
2271 // Materialize the address created by an alloca into a register, and
2272 // return the register number (or zero if we failed to handle it).
2273 unsigned PPCFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
2274   // Don't handle dynamic allocas.
2275   if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
2276 
2277   MVT VT;
2278   if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
2279 
2280   DenseMap<const AllocaInst*, int>::iterator SI =
2281     FuncInfo.StaticAllocaMap.find(AI);
2282 
2283   if (SI != FuncInfo.StaticAllocaMap.end()) {
2284     Register ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2285     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
2286             ResultReg).addFrameIndex(SI->second).addImm(0);
2287     return ResultReg;
2288   }
2289 
2290   return 0;
2291 }
2292 
2293 // Fold loads into extends when possible.
2294 // FIXME: We can have multiple redundant extend/trunc instructions
2295 // following a load.  The folding only picks up one.  Extend this
2296 // to check subsequent instructions for the same pattern and remove
2297 // them.  Thus ResultReg should be the def reg for the last redundant
2298 // instruction in a chain, and all intervening instructions can be
2299 // removed from parent.  Change test/CodeGen/PowerPC/fast-isel-fold.ll
2300 // to add ELF64-NOT: rldicl to the appropriate tests when this works.
2301 bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2302                                       const LoadInst *LI) {
2303   // Verify we have a legal type before going any further.
2304   MVT VT;
2305   if (!isLoadTypeLegal(LI->getType(), VT))
2306     return false;
2307 
2308   // Combine load followed by zero- or sign-extend.
2309   bool IsZExt = false;
2310   switch(MI->getOpcode()) {
2311     default:
2312       return false;
2313 
2314     case PPC::RLDICL:
2315     case PPC::RLDICL_32_64: {
2316       IsZExt = true;
2317       unsigned MB = MI->getOperand(3).getImm();
2318       if ((VT == MVT::i8 && MB <= 56) ||
2319           (VT == MVT::i16 && MB <= 48) ||
2320           (VT == MVT::i32 && MB <= 32))
2321         break;
2322       return false;
2323     }
2324 
2325     case PPC::RLWINM:
2326     case PPC::RLWINM8: {
2327       IsZExt = true;
2328       unsigned MB = MI->getOperand(3).getImm();
2329       if ((VT == MVT::i8 && MB <= 24) ||
2330           (VT == MVT::i16 && MB <= 16))
2331         break;
2332       return false;
2333     }
2334 
2335     case PPC::EXTSB:
2336     case PPC::EXTSB8:
2337     case PPC::EXTSB8_32_64:
2338       /* There is no sign-extending load-byte instruction. */
2339       return false;
2340 
2341     case PPC::EXTSH:
2342     case PPC::EXTSH8:
2343     case PPC::EXTSH8_32_64: {
2344       if (VT != MVT::i16 && VT != MVT::i8)
2345         return false;
2346       break;
2347     }
2348 
2349     case PPC::EXTSW:
2350     case PPC::EXTSW_32:
2351     case PPC::EXTSW_32_64: {
2352       if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8)
2353         return false;
2354       break;
2355     }
2356   }
2357 
2358   // See if we can handle this address.
2359   Address Addr;
2360   if (!PPCComputeAddress(LI->getOperand(0), Addr))
2361     return false;
2362 
2363   Register ResultReg = MI->getOperand(0).getReg();
2364 
2365   if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt,
2366                    Subtarget->hasSPE() ? PPC::EVLDD : PPC::LFD))
2367     return false;
2368 
2369   MachineBasicBlock::iterator I(MI);
2370   removeDeadCode(I, std::next(I));
2371   return true;
2372 }
2373 
2374 // Attempt to lower call arguments in a faster way than done by
2375 // the selection DAG code.
2376 bool PPCFastISel::fastLowerArguments() {
2377   // Defer to normal argument lowering for now.  It's reasonably
2378   // efficient.  Consider doing something like ARM to handle the
2379   // case where all args fit in registers, no varargs, no float
2380   // or vector args.
2381   return false;
2382 }
2383 
2384 // Handle materializing integer constants into a register.  This is not
2385 // automatically generated for PowerPC, so must be explicitly created here.
2386 unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
2387 
2388   if (Opc != ISD::Constant)
2389     return 0;
2390 
2391   // If we're using CR bit registers for i1 values, handle that as a special
2392   // case first.
2393   if (VT == MVT::i1 && Subtarget->useCRBits()) {
2394     Register ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2395     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2396             TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2397     return ImmReg;
2398   }
2399 
2400   if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 &&
2401       VT != MVT::i1)
2402     return 0;
2403 
2404   const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2405                                    &PPC::GPRCRegClass);
2406   if (VT == MVT::i64)
2407     return PPCMaterialize64BitInt(Imm, RC);
2408   else
2409     return PPCMaterialize32BitInt(Imm, RC);
2410 }
2411 
2412 // Override for ADDI and ADDI8 to set the correct register class
2413 // on RHS operand 0.  The automatic infrastructure naively assumes
2414 // GPRC for i32 and G8RC for i64; the concept of "no R0" is lost
2415 // for these cases.  At the moment, none of the other automatically
2416 // generated RI instructions require special treatment.  However, once
2417 // SelectSelect is implemented, "isel" requires similar handling.
2418 //
2419 // Also be conservative about the output register class.  Avoid
2420 // assigning R0 or X0 to the output register for GPRC and G8RC
2421 // register classes, as any such result could be used in ADDI, etc.,
2422 // where those regs have another meaning.
2423 unsigned PPCFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
2424                                       const TargetRegisterClass *RC,
2425                                       unsigned Op0,
2426                                       uint64_t Imm) {
2427   if (MachineInstOpcode == PPC::ADDI)
2428     MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2429   else if (MachineInstOpcode == PPC::ADDI8)
2430     MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
2431 
2432   const TargetRegisterClass *UseRC =
2433     (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2434      (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2435 
2436   return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC, Op0, Imm);
2437 }
2438 
2439 // Override for instructions with one register operand to avoid use of
2440 // R0/X0.  The automatic infrastructure isn't aware of the context so
2441 // we must be conservative.
2442 unsigned PPCFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
2443                                      const TargetRegisterClass* RC,
2444                                      unsigned Op0) {
2445   const TargetRegisterClass *UseRC =
2446     (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2447      (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2448 
2449   return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0);
2450 }
2451 
2452 // Override for instructions with two register operands to avoid use
2453 // of R0/X0.  The automatic infrastructure isn't aware of the context
2454 // so we must be conservative.
2455 unsigned PPCFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2456                                       const TargetRegisterClass* RC,
2457                                       unsigned Op0, unsigned Op1) {
2458   const TargetRegisterClass *UseRC =
2459     (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2460      (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2461 
2462   return FastISel::fastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op1);
2463 }
2464 
2465 namespace llvm {
2466   // Create the fast instruction selector for PowerPC64 ELF.
2467   FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo,
2468                                 const TargetLibraryInfo *LibInfo) {
2469     // Only available on 64-bit for now.
2470     const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget<PPCSubtarget>();
2471     if (Subtarget.isPPC64())
2472       return new PPCFastISel(FuncInfo, LibInfo);
2473     return nullptr;
2474   }
2475 }
2476