1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the PowerPC 64-bit instructions. These patterns are used 10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// 64-bit operands. 16// 17def s16imm64 : Operand<i64> { 18 let PrintMethod = "printS16ImmOperand"; 19 let EncoderMethod = "getImm16Encoding"; 20 let ParserMatchClass = PPCS16ImmAsmOperand; 21 let DecoderMethod = "decodeSImmOperand<16>"; 22 let OperandType = "OPERAND_IMMEDIATE"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29 let OperandType = "OPERAND_IMMEDIATE"; 30} 31def s17imm64 : Operand<i64> { 32 // This operand type is used for addis/lis to allow the assembler parser 33 // to accept immediates in the range -65536..65535 for compatibility with 34 // the GNU assembler. The operand is treated as 16-bit otherwise. 35 let PrintMethod = "printS16ImmOperand"; 36 let EncoderMethod = "getImm16Encoding"; 37 let ParserMatchClass = PPCS17ImmAsmOperand; 38 let DecoderMethod = "decodeSImmOperand<16>"; 39 let OperandType = "OPERAND_IMMEDIATE"; 40} 41def tocentry : Operand<iPTR> { 42 let MIOperandInfo = (ops i64imm:$imm); 43} 44def tlsreg : Operand<i64> { 45 let EncoderMethod = "getTLSRegEncoding"; 46 let ParserMatchClass = PPCTLSRegOperand; 47} 48def tlsgd : Operand<i64> {} 49def tlscall : Operand<i64> { 50 let PrintMethod = "printTLSCall"; 51 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 52 let EncoderMethod = "getTLSCallEncoding"; 53} 54 55//===----------------------------------------------------------------------===// 56// 64-bit transformation functions. 57// 58 59def SHL64 : SDNodeXForm<imm, [{ 60 // Transformation function: 63 - imm 61 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 62}]>; 63 64def SRL64 : SDNodeXForm<imm, [{ 65 // Transformation function: 64 - imm 66 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 67 : getI32Imm(0, SDLoc(N)); 68}]>; 69 70 71//===----------------------------------------------------------------------===// 72// Calls. 73// 74 75let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 76let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 77 let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in 78 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 79 [(retflag)]>, Requires<[In64BitMode]>; 80 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 81 let isPredicable = 1 in 82 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 83 []>, 84 Requires<[In64BitMode]>; 85 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 86 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 87 []>, 88 Requires<[In64BitMode]>; 89 90 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 91 "bcctr 12, $bi, 0", IIC_BrB, []>, 92 Requires<[In64BitMode]>; 93 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 94 "bcctr 4, $bi, 0", IIC_BrB, []>, 95 Requires<[In64BitMode]>; 96 } 97} 98 99let Defs = [LR8] in 100 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, 101 PPC970_Unit_BRU; 102 103let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 104 let Defs = [CTR8], Uses = [CTR8] in { 105 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 106 "bdz $dst">; 107 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 108 "bdnz $dst">; 109 } 110 111 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 112 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 113 "bdzlr", IIC_BrB, []>; 114 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 115 "bdnzlr", IIC_BrB, []>; 116 } 117} 118 119 120 121let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in { 122 // Convenient aliases for call instructions 123 let Uses = [RM] in { 124 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 125 "bl $func", IIC_BrB, []>; // See Pat patterns below. 126 127 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 128 "bl $func", IIC_BrB, []>; 129 130 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 131 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 132 } 133 let Uses = [RM], isCodeGenOnly = 1 in { 134 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 135 (outs), (ins calltarget:$func), 136 "bl $func\n\tnop", IIC_BrB, []>; 137 138 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 139 (outs), (ins tlscall:$func), 140 "bl $func\n\tnop", IIC_BrB, []>; 141 142 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 143 (outs), (ins abscalltarget:$func), 144 "bla $func\n\tnop", IIC_BrB, 145 [(PPCcall_nop (i64 imm:$func))]>; 146 let Predicates = [PCRelativeMemops] in { 147 // BL8_NOTOC means that the caller does not use the TOC pointer and if 148 // it does use R2 then it is just a caller saved register. Therefore it is 149 // safe to emit only the bl and not the nop for this instruction. The 150 // linker will not try to restore R2 after the call. 151 def BL8_NOTOC : IForm<18, 0, 1, (outs), 152 (ins calltarget:$func), 153 "bl $func", IIC_BrB, []>; 154 def BL8_NOTOC_TLS : IForm<18, 0, 1, (outs), 155 (ins tlscall:$func), 156 "bl $func", IIC_BrB, []>; 157 } 158 } 159 let Uses = [CTR8, RM] in { 160 let isPredicable = 1 in 161 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 162 "bctrl", IIC_BrB, [(PPCbctrl)]>, 163 Requires<[In64BitMode]>; 164 165 let isCodeGenOnly = 1 in { 166 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 167 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 168 []>, 169 Requires<[In64BitMode]>; 170 171 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 172 "bcctrl 12, $bi, 0", IIC_BrB, []>, 173 Requires<[In64BitMode]>; 174 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 175 "bcctrl 4, $bi, 0", IIC_BrB, []>, 176 Requires<[In64BitMode]>; 177 } 178 } 179} 180 181let isCall = 1, PPC970_Unit = 7, Defs = [LR8, RM], hasSideEffects = 0, 182 isCodeGenOnly = 1, Uses = [RM] in { 183 // Convenient aliases for call instructions 184 def BL8_RM : IForm<18, 0, 1, (outs), (ins calltarget:$func), 185 "bl $func", IIC_BrB, []>; // See Pat patterns below. 186 187 def BLA8_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 188 "bla $func", IIC_BrB, [(PPCcall_rm (i64 imm:$func))]>; 189 def BL8_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, 190 (outs), (ins calltarget:$func), 191 "bl $func\n\tnop", IIC_BrB, []>; 192 193 def BLA8_NOP_RM : IForm_and_DForm_4_zero<18, 1, 1, 24, 194 (outs), (ins abscalltarget:$func), 195 "bla $func\n\tnop", IIC_BrB, 196 [(PPCcall_nop_rm (i64 imm:$func))]>; 197 let Predicates = [PCRelativeMemops] in { 198 // BL8_NOTOC means that the caller does not use the TOC pointer and if 199 // it does use R2 then it is just a caller saved register. Therefore it is 200 // safe to emit only the bl and not the nop for this instruction. The 201 // linker will not try to restore R2 after the call. 202 def BL8_NOTOC_RM : IForm<18, 0, 1, (outs), 203 (ins calltarget:$func), 204 "bl $func", IIC_BrB, []>; 205 } 206 let Uses = [CTR8, RM] in { 207 let isPredicable = 1 in 208 def BCTRL8_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 209 "bctrl", IIC_BrB, [(PPCbctrl_rm)]>, 210 Requires<[In64BitMode]>; 211 } 212} 213 214let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 215 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 216 def BCTRL8_LDinto_toc : 217 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 218 (ins memrix:$src), 219 "bctrl\n\tld 2, $src", IIC_BrB, 220 [(PPCbctrl_load_toc iaddrX4:$src)]>, 221 Requires<[In64BitMode]>; 222} 223 224let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 225 Defs = [LR8, X2, RM], Uses = [CTR8, RM], RST = 2 in { 226 def BCTRL8_LDinto_toc_RM : 227 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 228 (ins memrix:$src), 229 "bctrl\n\tld 2, $src", IIC_BrB, 230 [(PPCbctrl_load_toc_rm iaddrX4:$src)]>, 231 Requires<[In64BitMode]>; 232} 233 234} // Interpretation64Bit 235 236// FIXME: Duplicating this for the asm parser should be unnecessary, but the 237// previous definition must be marked as CodeGen only to prevent decoding 238// conflicts. 239let Interpretation64Bit = 1, isAsmParserOnly = 1, hasSideEffects = 0 in 240let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 241def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 242 "bl $func", IIC_BrB, []>; 243 244// Calls 245def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 246 (BL8 tglobaladdr:$dst)>; 247def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 248 (BL8_NOP tglobaladdr:$dst)>; 249 250def : Pat<(PPCcall (i64 texternalsym:$dst)), 251 (BL8 texternalsym:$dst)>; 252def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 253 (BL8_NOP texternalsym:$dst)>; 254 255def : Pat<(PPCcall_notoc (i64 tglobaladdr:$dst)), 256 (BL8_NOTOC tglobaladdr:$dst)>; 257def : Pat<(PPCcall_notoc (i64 texternalsym:$dst)), 258 (BL8_NOTOC texternalsym:$dst)>; 259 260def : Pat<(PPCcall_rm (i64 tglobaladdr:$dst)), 261 (BL8_RM tglobaladdr:$dst)>; 262def : Pat<(PPCcall_nop_rm (i64 tglobaladdr:$dst)), 263 (BL8_NOP_RM tglobaladdr:$dst)>; 264 265def : Pat<(PPCcall_rm (i64 texternalsym:$dst)), 266 (BL8_RM texternalsym:$dst)>; 267def : Pat<(PPCcall_nop_rm (i64 texternalsym:$dst)), 268 (BL8_NOP_RM texternalsym:$dst)>; 269 270def : Pat<(PPCcall_notoc_rm (i64 tglobaladdr:$dst)), 271 (BL8_NOTOC_RM tglobaladdr:$dst)>; 272def : Pat<(PPCcall_notoc_rm (i64 texternalsym:$dst)), 273 (BL8_NOTOC_RM texternalsym:$dst)>; 274 275// Calls for AIX 276def : Pat<(PPCcall (i64 mcsym:$dst)), 277 (BL8 mcsym:$dst)>; 278def : Pat<(PPCcall_nop (i64 mcsym:$dst)), 279 (BL8_NOP mcsym:$dst)>; 280 281def : Pat<(PPCcall_rm (i64 mcsym:$dst)), 282 (BL8_RM mcsym:$dst)>; 283def : Pat<(PPCcall_nop_rm (i64 mcsym:$dst)), 284 (BL8_NOP_RM mcsym:$dst)>; 285 286// Atomic operations 287// FIXME: some of these might be used with constant operands. This will result 288// in constant materialization instructions that may be redundant. We currently 289// clean this up in PPCMIPeephole with calls to 290// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 291// in the first place. 292let Defs = [CR0] in { 293 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo< 294 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 295 [(set i64:$dst, (atomic_load_add_64 ForceXForm:$ptr, i64:$incr))]>; 296 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo< 297 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 298 [(set i64:$dst, (atomic_load_sub_64 ForceXForm:$ptr, i64:$incr))]>; 299 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo< 300 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 301 [(set i64:$dst, (atomic_load_or_64 ForceXForm:$ptr, i64:$incr))]>; 302 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo< 303 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 304 [(set i64:$dst, (atomic_load_xor_64 ForceXForm:$ptr, i64:$incr))]>; 305 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo< 306 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 307 [(set i64:$dst, (atomic_load_and_64 ForceXForm:$ptr, i64:$incr))]>; 308 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo< 309 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 310 [(set i64:$dst, (atomic_load_nand_64 ForceXForm:$ptr, i64:$incr))]>; 311 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo< 312 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 313 [(set i64:$dst, (atomic_load_min_64 ForceXForm:$ptr, i64:$incr))]>; 314 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo< 315 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 316 [(set i64:$dst, (atomic_load_max_64 ForceXForm:$ptr, i64:$incr))]>; 317 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo< 318 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 319 [(set i64:$dst, (atomic_load_umin_64 ForceXForm:$ptr, i64:$incr))]>; 320 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo< 321 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 322 [(set i64:$dst, (atomic_load_umax_64 ForceXForm:$ptr, i64:$incr))]>; 323 324 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo< 325 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 326 [(set i64:$dst, (atomic_cmp_swap_64 ForceXForm:$ptr, i64:$old, i64:$new))]>; 327 328 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< 329 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 330 [(set i64:$dst, (atomic_swap_64 ForceXForm:$ptr, i64:$new))]>; 331} 332 333// Instructions to support atomic operations 334let mayLoad = 1, hasSideEffects = 0 in { 335def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 336 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 337// TODO: Add scheduling info. 338let hasNoSchedulingInfo = 1 in 339def LQARX : XForm_1_memOp<31, 276, (outs g8prc:$RTp), (ins memrr:$ptr), 340 "lqarx $RTp, $ptr", IIC_LdStLQARX, []>, isPPC64; 341 342// Instruction to support lock versions of atomics 343// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 344def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 345 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isRecordForm; 346// TODO: Add scheduling info. 347let hasNoSchedulingInfo = 1 in 348// FIXME: We have to seek a way to remove isRecordForm since 349// LQARXL is not really altering CR0. 350def LQARXL : XForm_1<31, 276, (outs g8prc:$RTp), (ins memrr:$ptr), 351 "lqarx $RTp, $ptr, 1", IIC_LdStLQARX, []>, 352 isPPC64, isRecordForm; 353 354let hasExtraDefRegAllocReq = 1 in 355def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 356 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 357 Requires<[IsISA3_0]>; 358} 359 360let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 361def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 362 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isRecordForm; 363// TODO: Add scheduling info. 364let hasNoSchedulingInfo = 1 in 365def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RSp, memrr:$dst), 366 "stqcx. $RSp, $dst", IIC_LdStSTQCX, []>, 367 isPPC64, isRecordForm; 368} 369 370def SPLIT_QUADWORD : PPCCustomInserterPseudo<(outs g8rc:$lo, g8rc:$hi), 371 (ins g8prc:$src), 372 "#SPLIT_QUADWORD", []>; 373class AtomicRMW128<string asmstr> 374 : PPCPostRAExpPseudo<(outs g8prc:$RTp, g8prc:$scratch), 375 (ins memrr:$ptr, g8rc:$incr_lo, g8rc:$incr_hi), 376 asmstr, []>; 377// We have to keep values in MI's uses during LL/SC looping as they are, 378// so set both $RTp and $scratch earlyclobber. 379let mayStore = 1, mayLoad = 1, 380 Defs = [CR0], 381 Constraints = "@earlyclobber $scratch,@earlyclobber $RTp" in { 382// Atomic pseudo instructions expanded post-ra. 383def ATOMIC_SWAP_I128 : AtomicRMW128<"#ATOMIC_SWAP_I128">; 384def ATOMIC_LOAD_ADD_I128 : AtomicRMW128<"#ATOMIC_LOAD_ADD_I128">; 385def ATOMIC_LOAD_SUB_I128 : AtomicRMW128<"#ATOMIC_LOAD_SUB_I128">; 386def ATOMIC_LOAD_AND_I128 : AtomicRMW128<"#ATOMIC_LOAD_AND_I128">; 387def ATOMIC_LOAD_XOR_I128 : AtomicRMW128<"#ATOMIC_LOAD_XOR_I128">; 388def ATOMIC_LOAD_OR_I128 : AtomicRMW128<"#ATOMIC_LOAD_OR_I128">; 389def ATOMIC_LOAD_NAND_I128 : AtomicRMW128<"#ATOMIC_LOAD_NAND_I128">; 390 391def ATOMIC_CMP_SWAP_I128 : PPCPostRAExpPseudo< 392 (outs g8prc:$RTp, g8prc:$scratch), 393 (ins memrr:$ptr, g8rc:$cmp_lo, g8rc:$cmp_hi, 394 g8rc:$new_lo, g8rc:$new_hi), 395 "#ATOMIC_CMP_SWAP_I128", []>; 396} 397 398def : Pat<(int_ppc_atomicrmw_add_i128 ForceXForm:$ptr, 399 i64:$incr_lo, 400 i64:$incr_hi), 401 (SPLIT_QUADWORD (ATOMIC_LOAD_ADD_I128 memrr:$ptr, 402 g8rc:$incr_lo, 403 g8rc:$incr_hi))>; 404def : Pat<(int_ppc_atomicrmw_sub_i128 ForceXForm:$ptr, 405 i64:$incr_lo, 406 i64:$incr_hi), 407 (SPLIT_QUADWORD (ATOMIC_LOAD_SUB_I128 memrr:$ptr, 408 g8rc:$incr_lo, 409 g8rc:$incr_hi))>; 410def : Pat<(int_ppc_atomicrmw_xor_i128 ForceXForm:$ptr, 411 i64:$incr_lo, 412 i64:$incr_hi), 413 (SPLIT_QUADWORD (ATOMIC_LOAD_XOR_I128 memrr:$ptr, 414 g8rc:$incr_lo, 415 g8rc:$incr_hi))>; 416def : Pat<(int_ppc_atomicrmw_and_i128 ForceXForm:$ptr, 417 i64:$incr_lo, 418 i64:$incr_hi), 419 (SPLIT_QUADWORD (ATOMIC_LOAD_AND_I128 memrr:$ptr, 420 g8rc:$incr_lo, 421 g8rc:$incr_hi))>; 422def : Pat<(int_ppc_atomicrmw_nand_i128 ForceXForm:$ptr, 423 i64:$incr_lo, 424 i64:$incr_hi), 425 (SPLIT_QUADWORD (ATOMIC_LOAD_NAND_I128 memrr:$ptr, 426 g8rc:$incr_lo, 427 g8rc:$incr_hi))>; 428def : Pat<(int_ppc_atomicrmw_or_i128 ForceXForm:$ptr, 429 i64:$incr_lo, 430 i64:$incr_hi), 431 (SPLIT_QUADWORD (ATOMIC_LOAD_OR_I128 memrr:$ptr, 432 g8rc:$incr_lo, 433 g8rc:$incr_hi))>; 434def : Pat<(int_ppc_atomicrmw_xchg_i128 ForceXForm:$ptr, 435 i64:$incr_lo, 436 i64:$incr_hi), 437 (SPLIT_QUADWORD (ATOMIC_SWAP_I128 memrr:$ptr, 438 g8rc:$incr_lo, 439 g8rc:$incr_hi))>; 440def : Pat<(int_ppc_cmpxchg_i128 ForceXForm:$ptr, 441 i64:$cmp_lo, 442 i64:$cmp_hi, 443 i64:$new_lo, 444 i64:$new_hi), 445 (SPLIT_QUADWORD (ATOMIC_CMP_SWAP_I128 446 memrr:$ptr, 447 g8rc:$cmp_lo, 448 g8rc:$cmp_hi, 449 g8rc:$new_lo, 450 g8rc:$new_hi))>; 451 452let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 453def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 454 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 455 Requires<[IsISA3_0]>; 456 457let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 458let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 459def TCRETURNdi8 :PPCEmitTimePseudo< (outs), 460 (ins calltarget:$dst, i32imm:$offset), 461 "#TC_RETURNd8 $dst $offset", 462 []>; 463 464let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 465def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 466 "#TC_RETURNa8 $func $offset", 467 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 468 469let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 470def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 471 "#TC_RETURNr8 $dst $offset", 472 []>; 473 474let hasSideEffects = 0 in { 475let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 476 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 477def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 478 []>, 479 Requires<[In64BitMode]>; 480 481let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 482 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 483def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 484 "b $dst", IIC_BrB, 485 []>; 486 487let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 488 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 489def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 490 "ba $dst", IIC_BrB, 491 []>; 492} 493} // Interpretation64Bit 494 495def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 496 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 497 498def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 499 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 500 501def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 502 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 503 504 505// 64-bit CR instructions 506let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 507let hasSideEffects = 0 in { 508// mtocrf's input needs to be prepared by shifting by an amount dependent 509// on the cr register selected. Thus, post-ra anti-dep breaking must not 510// later change that register assignment. 511let hasExtraDefRegAllocReq = 1 in { 512def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 513 "mtocrf $FXM, $ST", IIC_BrMCRX>, 514 PPC970_DGroup_First, PPC970_Unit_CRU; 515 516// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 517// is dependent on the cr fields being set. 518def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 519 "mtcrf $FXM, $rS", IIC_BrMCRX>, 520 PPC970_MicroCode, PPC970_Unit_CRU; 521} // hasExtraDefRegAllocReq = 1 522 523// mfocrf's input needs to be prepared by shifting by an amount dependent 524// on the cr register selected. Thus, post-ra anti-dep breaking must not 525// later change that register assignment. 526let hasExtraSrcRegAllocReq = 1 in { 527def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 528 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 529 PPC970_DGroup_First, PPC970_Unit_CRU; 530 531// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 532// is dependent on the cr fields being copied. 533def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 534 "mfcr $rT", IIC_SprMFCR>, 535 PPC970_MicroCode, PPC970_Unit_CRU; 536} // hasExtraSrcRegAllocReq = 1 537} // hasSideEffects = 0 538 539// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 540// is not. 541let hasSideEffects = 1 in { 542 let Defs = [CTR8] in 543 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 544 "#EH_SJLJ_SETJMP64", 545 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 546 Requires<[In64BitMode]>; 547} 548 549let hasSideEffects = 1, isBarrier = 1 in { 550 let isTerminator = 1 in 551 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 552 "#EH_SJLJ_LONGJMP64", 553 [(PPCeh_sjlj_longjmp addr:$buf)]>, 554 Requires<[In64BitMode]>; 555} 556 557def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 558 "mfspr $RT, $SPR", IIC_SprMFSPR>; 559def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 560 "mtspr $SPR, $RT", IIC_SprMTSPR>; 561 562 563//===----------------------------------------------------------------------===// 564// 64-bit SPR manipulation instrs. 565 566let Uses = [CTR8] in { 567def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 568 "mfctr $rT", IIC_SprMFSPR>, 569 PPC970_DGroup_First, PPC970_Unit_FXU; 570} 571let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 572def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 573 "mtctr $rS", IIC_SprMTSPR>, 574 PPC970_DGroup_First, PPC970_Unit_FXU; 575} 576let hasSideEffects = 1, Defs = [CTR8] in { 577let Pattern = [(int_set_loop_iterations i64:$rS)] in 578def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 579 "mtctr $rS", IIC_SprMTSPR>, 580 PPC970_DGroup_First, PPC970_Unit_FXU; 581} 582 583 584let hasSideEffects = 1, Defs = [CTR8] in 585def MTCTR8Pseudo : PPCEmitTimePseudo<(outs), (ins g8rc:$rS), "#MTCTR8Pseudo", []>; 586 587let hasSideEffects = 1, Uses = [CTR8], Defs = [CTR8] in 588def DecreaseCTR8Pseudo : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i64imm:$stride), 589 "#DecreaseCTR8Pseudo", []>; 590 591let Pattern = [(set i64:$rT, readcyclecounter)] in 592def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 593 "mfspr $rT, 268", IIC_SprMFTB>, 594 PPC970_DGroup_First, PPC970_Unit_FXU; 595// Note that encoding mftb using mfspr is now the preferred form, 596// and has been since at least ISA v2.03. The mftb instruction has 597// now been phased out. Using mfspr, however, is known not to work on 598// the POWER3. 599 600let Defs = [X1], Uses = [X1] in 601def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 602 [(set i64:$result, 603 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 604def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 605 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 606// Probed alloca to support stack clash protection. 607let Defs = [X1], Uses = [X1], hasNoSchedulingInfo = 1 in { 608def PROBED_ALLOCA_64 : PPCCustomInserterPseudo<(outs g8rc:$result), 609 (ins g8rc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_64", 610 [(set i64:$result, 611 (PPCprobedalloca i64:$negsize, iaddr:$fpsi))]>; 612def PREPARE_PROBED_ALLOCA_64 : PPCEmitTimePseudo<(outs 613 g8rc:$fp, g8rc:$actual_negsize), 614 (ins g8rc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_64", []>; 615def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 : PPCEmitTimePseudo<(outs 616 g8rc:$fp, g8rc:$actual_negsize), 617 (ins g8rc:$negsize, memri:$fpsi), 618 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64", []>, 619 RegConstraint<"$actual_negsize = $negsize">; 620def PROBED_STACKALLOC_64 : PPCEmitTimePseudo<(outs g8rc:$scratch, g8rc:$temp), 621 (ins i64imm:$stacksize), 622 "#PROBED_STACKALLOC_64", []>; 623} 624 625let hasSideEffects = 0 in { 626let Defs = [LR8] in { 627def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 628 "mtlr $rS", IIC_SprMTSPR>, 629 PPC970_DGroup_First, PPC970_Unit_FXU; 630} 631let Uses = [LR8] in { 632def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 633 "mflr $rT", IIC_SprMFSPR>, 634 PPC970_DGroup_First, PPC970_Unit_FXU; 635} 636} // Interpretation64Bit 637} 638 639//===----------------------------------------------------------------------===// 640// Fixed point instructions. 641// 642 643let PPC970_Unit = 1 in { // FXU Operations. 644let Interpretation64Bit = 1 in { 645let hasSideEffects = 0 in { 646let isCodeGenOnly = 1 in { 647 648let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 649def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 650 "li $rD, $imm", IIC_IntSimple, 651 [(set i64:$rD, imm64SExt16:$imm)]>; 652def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 653 "lis $rD, $imm", IIC_IntSimple, 654 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 655} 656 657// Logical ops. 658let isCommutable = 1 in { 659defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 660 "nand", "$rA, $rS, $rB", IIC_IntSimple, 661 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 662defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 663 "and", "$rA, $rS, $rB", IIC_IntSimple, 664 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 665} // isCommutable 666defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 667 "andc", "$rA, $rS, $rB", IIC_IntSimple, 668 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 669let isCommutable = 1 in { 670defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 671 "or", "$rA, $rS, $rB", IIC_IntSimple, 672 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 673defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 674 "nor", "$rA, $rS, $rB", IIC_IntSimple, 675 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 676} // isCommutable 677defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 678 "orc", "$rA, $rS, $rB", IIC_IntSimple, 679 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 680let isCommutable = 1 in { 681defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 682 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 683 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 684defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 685 "xor", "$rA, $rS, $rB", IIC_IntSimple, 686 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 687} // let isCommutable = 1 688 689// Logical ops with immediate. 690let Defs = [CR0] in { 691def ANDI8_rec : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 692 "andi. $dst, $src1, $src2", IIC_IntGeneral, 693 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 694 isRecordForm; 695def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 696 "andis. $dst, $src1, $src2", IIC_IntGeneral, 697 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 698 isRecordForm; 699} 700def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 701 "ori $dst, $src1, $src2", IIC_IntSimple, 702 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 703def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 704 "oris $dst, $src1, $src2", IIC_IntSimple, 705 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 706def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 707 "xori $dst, $src1, $src2", IIC_IntSimple, 708 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 709def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 710 "xoris $dst, $src1, $src2", IIC_IntSimple, 711 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 712 713let isCommutable = 1 in 714defm ADD8 : XOForm_1rx<31, 266, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 715 "add", "$rT, $rA, $rB", IIC_IntSimple, 716 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 717// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 718// initial-exec thread-local storage model. We need to forbid r0 here - 719// while it works for add just fine, the linker can relax this to local-exec 720// addi, which won't work for r0. 721def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 722 "add $rT, $rA, $rB", IIC_IntSimple, 723 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 724let mayLoad = 1 in { 725def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 726 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 727def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 728 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 729def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 730 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 731def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 732 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 733def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 734 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 735def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 736 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 737def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 738 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 739 740} 741 742let mayStore = 1 in { 743def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 744 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 745 PPC970_DGroup_Cracked; 746def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 747 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 748 PPC970_DGroup_Cracked; 749def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 750 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 751 PPC970_DGroup_Cracked; 752def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 753 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 754 PPC970_DGroup_Cracked; 755def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 756 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 757 PPC970_DGroup_Cracked; 758def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 759 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 760 PPC970_DGroup_Cracked; 761def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 762 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 763 PPC970_DGroup_Cracked; 764 765} 766 767let isCommutable = 1 in 768defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 769 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 770 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 771 PPC970_DGroup_Cracked; 772 773let Defs = [CARRY] in 774def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 775 "addic $rD, $rA, $imm", IIC_IntGeneral, 776 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 777def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 778 "addi $rD, $rA, $imm", IIC_IntSimple, 779 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 780def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 781 "addis $rD, $rA, $imm", IIC_IntSimple, 782 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 783 784def LA8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$sym), 785 "la $rD, $sym($rA)", IIC_IntGeneral, 786 [(set i64:$rD, (add i64:$rA, 787 (PPClo tglobaladdr:$sym, 0)))]>; 788 789let Defs = [CARRY] in { 790def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 791 "subfic $rD, $rA, $imm", IIC_IntGeneral, 792 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 793} 794defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 795 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 796 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 797 PPC970_DGroup_Cracked; 798defm SUBF8 : XOForm_1rx<31, 40, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 799 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 800 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 801defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 802 "neg", "$rT, $rA", IIC_IntSimple, 803 [(set i64:$rT, (ineg i64:$rA))]>; 804let Uses = [CARRY] in { 805let isCommutable = 1 in 806defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 807 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 808 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 809defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 810 "addme", "$rT, $rA", IIC_IntGeneral, 811 [(set i64:$rT, (adde i64:$rA, -1))]>; 812defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 813 "addze", "$rT, $rA", IIC_IntGeneral, 814 [(set i64:$rT, (adde i64:$rA, 0))]>; 815defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 816 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 817 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 818defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 819 "subfme", "$rT, $rA", IIC_IntGeneral, 820 [(set i64:$rT, (sube -1, i64:$rA))]>; 821defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 822 "subfze", "$rT, $rA", IIC_IntGeneral, 823 [(set i64:$rT, (sube 0, i64:$rA))]>; 824} 825} // isCodeGenOnly 826 827// FIXME: Duplicating this for the asm parser should be unnecessary, but the 828// previous definition must be marked as CodeGen only to prevent decoding 829// conflicts. 830let isAsmParserOnly = 1 in { 831def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 832 "add $rT, $rA, $rB", IIC_IntSimple, []>; 833 834let mayLoad = 1 in { 835def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 836 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 837def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 838 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 839def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 840 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 841def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 842 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 843} 844 845let mayStore = 1 in { 846def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 847 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 848 PPC970_DGroup_Cracked; 849def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 850 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 851 PPC970_DGroup_Cracked; 852def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 853 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 854 PPC970_DGroup_Cracked; 855def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 856 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 857 PPC970_DGroup_Cracked; 858} 859} 860 861let isCommutable = 1 in { 862defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 863 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 864 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 865defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 866 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 867 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 868} // isCommutable 869} 870} // Interpretation64Bit 871 872let isCompare = 1, hasSideEffects = 0 in { 873 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 874 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 875 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 876 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 877 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 878 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 879 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 880 "cmpldi $dst, $src1, $src2", 881 IIC_IntCompare>, isPPC64; 882 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 883 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), 884 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 885 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 886 Requires<[IsISA3_0]>; 887 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crrc:$BF), 888 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 889 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 890} 891 892let hasSideEffects = 0 in { 893defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 894 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 895 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 896defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 897 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 898 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 899defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 900 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 901 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 902 903let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 904defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 905 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 906defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 907 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 908 Requires<[IsISA3_0]>; 909 910defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 911 "extsb", "$rA, $rS", IIC_IntSimple, 912 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 913defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 914 "extsh", "$rA, $rS", IIC_IntSimple, 915 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 916 917defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 918 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 919defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 920 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 921} // Interpretation64Bit 922 923// For fast-isel: 924let isCodeGenOnly = 1 in { 925def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 926 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 927def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 928 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 929} // isCodeGenOnly for fast-isel 930 931defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 932 "extsw", "$rA, $rS", IIC_IntSimple, 933 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 934let Interpretation64Bit = 1, isCodeGenOnly = 1 in 935defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 936 "extsw", "$rA, $rS", IIC_IntSimple, 937 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 938let isCodeGenOnly = 1 in 939def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), 940 "extsw $rA, $rS", IIC_IntSimple, 941 []>, isPPC64; 942 943defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 944 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 945 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 946 947let Interpretation64Bit = 1, isCodeGenOnly = 1 in 948defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$rA), 949 (ins gprc:$rS, u6imm:$SH), 950 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 951 [(set i64:$rA, 952 (PPCextswsli i32:$rS, (i32 imm:$SH)))]>, 953 isPPC64, Requires<[IsISA3_0]>; 954 955defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 956 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 957 []>, isPPC64, Requires<[IsISA3_0]>; 958 959// For fast-isel: 960let isCodeGenOnly = 1, Defs = [CARRY] in 961def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), 962 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; 963 964defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 965 "cntlzd", "$rA, $rS", IIC_IntGeneral, 966 [(set i64:$rA, (ctlz i64:$rS))]>; 967defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 968 "cnttzd", "$rA, $rS", IIC_IntGeneral, 969 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 970def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 971 "popcntd $rA, $rS", IIC_IntGeneral, 972 [(set i64:$rA, (ctpop i64:$rS))]>; 973def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 974 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 975 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 976 isPPC64, Requires<[HasBPERMD]>; 977 978let isCodeGenOnly = 1, isCommutable = 1 in 979def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 980 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 981 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 982 983// popcntw also does a population count on the high 32 bits (storing the 984// results in the high 32-bits of the output). We'll ignore that here (which is 985// safe because we never separately use the high part of the 64-bit registers). 986def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 987 "popcntw $rA, $rS", IIC_IntGeneral, 988 [(set i32:$rA, (ctpop i32:$rS))]>; 989 990let isCodeGenOnly = 1 in 991def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS), 992 "popcntb $rA, $rS", IIC_IntGeneral, 993 [(set i64:$rA, (int_ppc_popcntb i64:$rS))]>; 994 995defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 996 "divd", "$rT, $rA, $rB", IIC_IntDivD, 997 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 998defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 999 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 1000 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 1001defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 1002 "divde", "$rT, $rA, $rB", IIC_IntDivD, 1003 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 1004 isPPC64, Requires<[HasExtDiv]>; 1005 1006let Predicates = [IsISA3_0] in { 1007def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 1008 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 1009def MADDHDU : VAForm_1a<49, 1010 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 1011 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 1012def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), 1013 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 1014 [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, 1015 isPPC64; 1016let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1017 def MADDLD8 : VAForm_1a<51, 1018 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 1019 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 1020 [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, 1021 isPPC64; 1022 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 1023 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 1024} 1025def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 1026 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 1027def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 1028 "modsd $rT, $rA, $rB", IIC_IntDivW, 1029 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>; 1030def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 1031 "modud $rT, $rA, $rB", IIC_IntDivW, 1032 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>; 1033} 1034 1035defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 1036 "divdeu", "$rT, $rA, $rB", IIC_IntDivD, 1037 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 1038 isPPC64, Requires<[HasExtDiv]>; 1039let isCommutable = 1 in 1040defm MULLD : XOForm_1rx<31, 233, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 1041 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 1042 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 1043let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1044def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 1045 "mulli $rD, $rA, $imm", IIC_IntMulLI, 1046 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 1047} 1048 1049let hasSideEffects = 1 in { 1050def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins u2imm:$L), 1051 "darn $RT, $L", IIC_LdStLD>, isPPC64; 1052} 1053 1054let hasSideEffects = 0 in { 1055defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 1056 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 1057 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1058 []>, isPPC64, RegConstraint<"$rSi = $rA">, 1059 NoEncode<"$rSi">; 1060 1061// Rotate instructions. 1062defm RLDCL : MDSForm_1r<30, 8, 1063 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 1064 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 1065 []>, isPPC64; 1066defm RLDCR : MDSForm_1r<30, 9, 1067 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 1068 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 1069 []>, isPPC64; 1070defm RLDICL : MDForm_1r<30, 0, 1071 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 1072 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1073 []>, isPPC64; 1074// For fast-isel: 1075let isCodeGenOnly = 1 in 1076def RLDICL_32_64 : MDForm_1<30, 0, 1077 (outs g8rc:$rA), 1078 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 1079 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1080 []>, isPPC64; 1081// End fast-isel. 1082let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1083defm RLDICL_32 : MDForm_1r<30, 0, 1084 (outs gprc:$rA), 1085 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 1086 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1087 []>, isPPC64; 1088defm RLDICR : MDForm_1r<30, 1, 1089 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 1090 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1091 []>, isPPC64; 1092let isCodeGenOnly = 1 in 1093def RLDICR_32 : MDForm_1<30, 1, 1094 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 1095 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1096 []>, isPPC64; 1097defm RLDIC : MDForm_1r<30, 2, 1098 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 1099 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1100 []>, isPPC64; 1101 1102let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1103defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 1104 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1105 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 1106 []>; 1107 1108defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 1109 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 1110 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 1111 []>; 1112 1113// RLWIMI can be commuted if the rotate amount is zero. 1114let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1115defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 1116 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 1117 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 1118 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 1119 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 1120 1121let isSelect = 1 in 1122def ISEL8 : AForm_4<31, 15, 1123 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 1124 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 1125 []>; 1126} // Interpretation64Bit 1127} // hasSideEffects = 0 1128} // End FXU Operations. 1129 1130def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>; 1131def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>; 1132 1133def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1134def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1135 1136def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1137def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1138 1139def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 1140 1141def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1142def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1143def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1144def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1145 1146def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 1147def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 1148def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 1149def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 1150def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 1151def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 1152 1153def : InstAlias<"isellt $rT, $rA, $rB", 1154 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>; 1155def : InstAlias<"iselgt $rT, $rA, $rB", 1156 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>; 1157def : InstAlias<"iseleq $rT, $rA, $rB", 1158 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>; 1159 1160def : InstAlias<"nop", (ORI8 X0, X0, 0)>; 1161def : InstAlias<"xnop", (XORI8 X0, X0, 0)>; 1162 1163def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>; 1164def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>; 1165 1166def : InstAlias<"mtxer $Rx", (MTSPR8 1, g8rc:$Rx)>; 1167def : InstAlias<"mfxer $Rx", (MFSPR8 g8rc:$Rx, 1)>; 1168 1169//Disable this alias on AIX for now because as does not support them. 1170let Predicates = [ModernAs] in { 1171 1172def : InstAlias<"mtudscr $Rx", (MTSPR8 3, g8rc:$Rx)>; 1173def : InstAlias<"mfudscr $Rx", (MFSPR8 g8rc:$Rx, 3)>; 1174 1175def : InstAlias<"mfrtcu $Rx", (MFSPR8 g8rc:$Rx, 4)>; 1176def : InstAlias<"mfrtcl $Rx", (MFSPR8 g8rc:$Rx, 5)>; 1177 1178def : InstAlias<"mtlr $Rx", (MTSPR8 8, g8rc:$Rx)>; 1179def : InstAlias<"mflr $Rx", (MFSPR8 g8rc:$Rx, 8)>; 1180 1181def : InstAlias<"mtctr $Rx", (MTSPR8 9, g8rc:$Rx)>; 1182def : InstAlias<"mfctr $Rx", (MFSPR8 g8rc:$Rx, 9)>; 1183 1184def : InstAlias<"mtuamr $Rx", (MTSPR8 13, g8rc:$Rx)>; 1185def : InstAlias<"mfuamr $Rx", (MFSPR8 g8rc:$Rx, 13)>; 1186 1187def : InstAlias<"mtdscr $Rx", (MTSPR8 17, g8rc:$Rx)>; 1188def : InstAlias<"mfdscr $Rx", (MFSPR8 g8rc:$Rx, 17)>; 1189 1190def : InstAlias<"mtdsisr $Rx", (MTSPR8 18, g8rc:$Rx)>; 1191def : InstAlias<"mfdsisr $Rx", (MFSPR8 g8rc:$Rx, 18)>; 1192 1193def : InstAlias<"mtdar $Rx", (MTSPR8 19, g8rc:$Rx)>; 1194def : InstAlias<"mfdar $Rx", (MFSPR8 g8rc:$Rx, 19)>; 1195 1196def : InstAlias<"mtdec $Rx", (MTSPR8 22, g8rc:$Rx)>; 1197def : InstAlias<"mfdec $Rx", (MFSPR8 g8rc:$Rx, 22)>; 1198 1199def : InstAlias<"mtsdr1 $Rx", (MTSPR8 25, g8rc:$Rx)>; 1200def : InstAlias<"mfsdr1 $Rx", (MFSPR8 g8rc:$Rx, 25)>; 1201 1202def : InstAlias<"mtsrr0 $Rx", (MTSPR8 26, g8rc:$Rx)>; 1203def : InstAlias<"mfsrr0 $Rx", (MFSPR8 g8rc:$Rx, 26)>; 1204 1205def : InstAlias<"mtsrr1 $Rx", (MTSPR8 27, g8rc:$Rx)>; 1206def : InstAlias<"mfsrr1 $Rx", (MFSPR8 g8rc:$Rx, 27)>; 1207 1208def : InstAlias<"mtcfar $Rx", (MTSPR8 28, g8rc:$Rx)>; 1209def : InstAlias<"mfcfar $Rx", (MFSPR8 g8rc:$Rx, 28)>; 1210 1211def : InstAlias<"mtamr $Rx", (MTSPR8 29, g8rc:$Rx)>; 1212def : InstAlias<"mfamr $Rx", (MFSPR8 g8rc:$Rx, 29)>; 1213 1214foreach SPRG = 0-3 in { 1215 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1216 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1217 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1218 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1219} 1220 1221def : InstAlias<"mfasr $RT", (MFSPR8 g8rc:$RT, 280)>; 1222def : InstAlias<"mtasr $RT", (MTSPR8 280, g8rc:$RT)>; 1223 1224def : InstAlias<"mttbl $Rx", (MTSPR8 284, g8rc:$Rx)>; 1225def : InstAlias<"mttbu $Rx", (MTSPR8 285, g8rc:$Rx)>; 1226 1227def : InstAlias<"mfpvr $RT", (MFSPR8 g8rc:$RT, 287)>; 1228 1229def : InstAlias<"mfspefscr $Rx", (MFSPR8 g8rc:$Rx, 512)>; 1230def : InstAlias<"mtspefscr $Rx", (MTSPR8 512, g8rc:$Rx)>; 1231 1232} 1233 1234//===----------------------------------------------------------------------===// 1235// Load/Store instructions. 1236// 1237 1238 1239// Sign extending loads. 1240let PPC970_Unit = 2 in { 1241let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1242def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 1243 "lha $rD, $src", IIC_LdStLHA, 1244 [(set i64:$rD, (sextloadi16 DForm:$src))]>, 1245 PPC970_DGroup_Cracked; 1246def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 1247 "lwa $rD, $src", IIC_LdStLWA, 1248 [(set i64:$rD, 1249 (sextloadi32 DSForm:$src))]>, isPPC64, 1250 PPC970_DGroup_Cracked; 1251let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1252def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), 1253 "lhax $rD, $src", IIC_LdStLHA, 1254 [(set i64:$rD, (sextloadi16 XForm:$src))]>, 1255 PPC970_DGroup_Cracked; 1256def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), 1257 "lwax $rD, $src", IIC_LdStLHA, 1258 [(set i64:$rD, (sextloadi32 XForm:$src))]>, isPPC64, 1259 PPC970_DGroup_Cracked; 1260// For fast-isel: 1261let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in { 1262def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 1263 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 1264 PPC970_DGroup_Cracked; 1265def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), 1266 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 1267 PPC970_DGroup_Cracked; 1268} // end fast-isel isCodeGenOnly 1269 1270// Update forms. 1271let mayLoad = 1, hasSideEffects = 0 in { 1272let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1273def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1274 (ins memri:$addr), 1275 "lhau $rD, $addr", IIC_LdStLHAU, 1276 []>, RegConstraint<"$addr.reg = $ea_result">, 1277 NoEncode<"$ea_result">; 1278// NO LWAU! 1279 1280let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1281def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1282 (ins memrr:$addr), 1283 "lhaux $rD, $addr", IIC_LdStLHAUX, 1284 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1285 NoEncode<"$ea_result">; 1286def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1287 (ins memrr:$addr), 1288 "lwaux $rD, $addr", IIC_LdStLHAUX, 1289 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1290 NoEncode<"$ea_result">, isPPC64; 1291} 1292} 1293 1294let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1295// Zero extending loads. 1296let PPC970_Unit = 2 in { 1297def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 1298 "lbz $rD, $src", IIC_LdStLoad, 1299 [(set i64:$rD, (zextloadi8 DForm:$src))]>; 1300def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 1301 "lhz $rD, $src", IIC_LdStLoad, 1302 [(set i64:$rD, (zextloadi16 DForm:$src))]>; 1303def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 1304 "lwz $rD, $src", IIC_LdStLoad, 1305 [(set i64:$rD, (zextloadi32 DForm:$src))]>, isPPC64; 1306 1307def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), 1308 "lbzx $rD, $src", IIC_LdStLoad, 1309 [(set i64:$rD, (zextloadi8 XForm:$src))]>; 1310def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), 1311 "lhzx $rD, $src", IIC_LdStLoad, 1312 [(set i64:$rD, (zextloadi16 XForm:$src))]>; 1313def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), 1314 "lwzx $rD, $src", IIC_LdStLoad, 1315 [(set i64:$rD, (zextloadi32 XForm:$src))]>; 1316 1317 1318// Update forms. 1319let mayLoad = 1, hasSideEffects = 0 in { 1320def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1321 (ins memri:$addr), 1322 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1323 []>, RegConstraint<"$addr.reg = $ea_result">, 1324 NoEncode<"$ea_result">; 1325def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1326 (ins memri:$addr), 1327 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1328 []>, RegConstraint<"$addr.reg = $ea_result">, 1329 NoEncode<"$ea_result">; 1330def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1331 (ins memri:$addr), 1332 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1333 []>, RegConstraint<"$addr.reg = $ea_result">, 1334 NoEncode<"$ea_result">; 1335 1336def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1337 (ins memrr:$addr), 1338 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1339 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1340 NoEncode<"$ea_result">; 1341def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1342 (ins memrr:$addr), 1343 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1344 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1345 NoEncode<"$ea_result">; 1346def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1347 (ins memrr:$addr), 1348 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1349 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1350 NoEncode<"$ea_result">; 1351} 1352} 1353} // Interpretation64Bit 1354 1355 1356// Full 8-byte loads. 1357let PPC970_Unit = 2 in { 1358def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 1359 "ld $rD, $src", IIC_LdStLD, 1360 [(set i64:$rD, (load DSForm:$src))]>, isPPC64; 1361// The following four definitions are selected for small code model only. 1362// Otherwise, we need to create two instructions to form a 32-bit offset, 1363// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 1364def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1365 "#LDtoc", 1366 [(set i64:$rD, 1367 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1368def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1369 "#LDtocJTI", 1370 [(set i64:$rD, 1371 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1372def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1373 "#LDtocCPT", 1374 [(set i64:$rD, 1375 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1376def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1377 "#LDtocCPT", 1378 [(set i64:$rD, 1379 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1380 1381def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), 1382 "ldx $rD, $src", IIC_LdStLD, 1383 [(set i64:$rD, (load XForm:$src))]>, isPPC64; 1384 1385let Predicates = [IsISA2_06] in { 1386def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), 1387 "ldbrx $rD, $src", IIC_LdStLoad, 1388 [(set i64:$rD, (PPClbrx ForceXForm:$src, i64))]>, isPPC64; 1389} 1390 1391let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1392def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), 1393 "lhbrx $rD, $src", IIC_LdStLoad, []>; 1394def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), 1395 "lwbrx $rD, $src", IIC_LdStLoad, []>; 1396} 1397 1398let mayLoad = 1, hasSideEffects = 0 in { 1399def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1400 (ins memrix:$addr), 1401 "ldu $rD, $addr", IIC_LdStLDU, 1402 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1403 NoEncode<"$ea_result">; 1404 1405def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1406 (ins memrr:$addr), 1407 "ldux $rD, $addr", IIC_LdStLDUX, 1408 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1409 NoEncode<"$ea_result">, isPPC64; 1410} 1411 1412let mayLoad = 1, hasNoSchedulingInfo = 1 in { 1413// Full 16-byte load. 1414// Early clobber $RTp to avoid assigned to the same register as RA. 1415// TODO: Add scheduling info. 1416def LQ : DQForm_RTp5_RA17_MEM<56, 0, 1417 (outs g8prc:$RTp), 1418 (ins memrix16:$src), 1419 "lq $RTp, $src", IIC_LdStLQ, 1420 []>, 1421 RegConstraint<"@earlyclobber $RTp">, 1422 isPPC64; 1423// We don't really have LQX in the ISA, make a pseudo one so that we can 1424// handle x-form during isel. Make it pre-ra may expose 1425// oppotunities to some opts(CSE, LICM and etc.) for the result of adding 1426// RA and RB. 1427def LQX_PSEUDO : PPCCustomInserterPseudo<(outs g8prc:$RTp), 1428 (ins memrr:$src), "#LQX_PSEUDO", []>; 1429 1430def RESTORE_QUADWORD : PPCEmitTimePseudo<(outs g8prc:$RTp), (ins memrix:$src), 1431 "#RESTORE_QUADWORD", []>; 1432} 1433 1434} 1435 1436def : Pat<(int_ppc_atomic_load_i128 iaddrX16:$src), 1437 (SPLIT_QUADWORD (LQ memrix16:$src))>; 1438 1439def : Pat<(int_ppc_atomic_load_i128 ForceXForm:$src), 1440 (SPLIT_QUADWORD (LQX_PSEUDO memrr:$src))>; 1441 1442// Support for medium and large code model. 1443let hasSideEffects = 0 in { 1444let isReMaterializable = 1 in { 1445def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1446 "#ADDIStocHA8", []>, isPPC64; 1447def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1448 "#ADDItocL", []>, isPPC64; 1449} 1450 1451// Local Data Transform 1452def ADDItoc8 : PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1453 "#ADDItoc8", 1454 [(set i64:$rD, 1455 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1456 1457let mayLoad = 1 in 1458def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1459 "#LDtocL", []>, isPPC64; 1460} 1461 1462// Support for thread-local storage. 1463def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1464 "#ADDISgotTprelHA", 1465 [(set i64:$rD, 1466 (PPCaddisGotTprelHA i64:$reg, 1467 tglobaltlsaddr:$disp))]>, 1468 isPPC64; 1469def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1470 "#LDgotTprelL", 1471 [(set i64:$rD, 1472 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1473 isPPC64; 1474 1475let Defs = [CR7], Itinerary = IIC_LdStSync in 1476def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1477 1478def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1479 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1480def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1481 "#ADDIStlsgdHA", 1482 [(set i64:$rD, 1483 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1484 isPPC64; 1485def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1486 "#ADDItlsgdL", 1487 [(set i64:$rD, 1488 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1489 isPPC64; 1490 1491class GETtlsADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1492 asmstr, 1493 [(set i64:$rD, 1494 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1495 isPPC64; 1496class GETtlsldADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1497 asmstr, 1498 [(set i64:$rD, 1499 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1500 isPPC64; 1501 1502let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1 in { 1503// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1504// explicitly defined when this op is created, so not mentioned here. 1505// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1506// correct because the branch select pass is relying on it. 1507let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1508def GETtlsADDR : GETtlsADDRPseudo <"#GETtlsADDR">; 1509let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1510def GETtlsADDRPCREL : GETtlsADDRPseudo <"#GETtlsADDRPCREL">; 1511 1512// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1513// explicitly defined when this op is created, so not mentioned here. 1514let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1515def GETtlsldADDR : GETtlsldADDRPseudo <"#GETtlsldADDR">; 1516let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1517def GETtlsldADDRPCREL : GETtlsldADDRPseudo <"#GETtlsldADDRPCREL">; 1518 1519// On AIX, the call to __tls_get_addr needs two inputs in X3/X4 for the 1520// offset and region handle respectively. The call is not followed by a nop 1521// so we don't need to mark it with a size of 8 bytes. Finally, the assembly 1522// manual mentions this exact set of registers as the clobbered set, others 1523// are guaranteed not to be clobbered. 1524let Defs = [X0,X4,X5,X11,LR8,CR0] in 1525def GETtlsADDR64AIX : 1526 PPCEmitTimePseudo<(outs g8rc:$rD),(ins g8rc:$offset, g8rc:$handle), 1527 "GETtlsADDR64AIX", 1528 [(set i64:$rD, 1529 (PPCgetTlsAddr i64:$offset, i64:$handle))]>, isPPC64; 1530} 1531 1532// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1533// are true defines while the rest of the Defs are clobbers. 1534let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1535 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1536 in 1537def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1538 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1539 "#ADDItlsgdLADDR", 1540 [(set i64:$rD, 1541 (PPCaddiTlsgdLAddr i64:$reg, 1542 tglobaltlsaddr:$disp, 1543 tglobaltlsaddr:$sym))]>, 1544 isPPC64; 1545def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1546 "#ADDIStlsldHA", 1547 [(set i64:$rD, 1548 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1549 isPPC64; 1550def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1551 "#ADDItlsldL", 1552 [(set i64:$rD, 1553 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1554 isPPC64; 1555// This pseudo is expanded to two copies to put the variable offset in R4 and 1556// the region handle in R3 and GETtlsADDR64AIX. 1557def TLSGDAIX8 : 1558 PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$offset, g8rc:$handle), 1559 "#TLSGDAIX8", 1560 [(set i64:$rD, 1561 (PPCTlsgdAIX i64:$offset, i64:$handle))]>; 1562// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1563// are true defines, while the rest of the Defs are clobbers. 1564let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1565 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1566 in 1567def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1568 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1569 "#ADDItlsldLADDR", 1570 [(set i64:$rD, 1571 (PPCaddiTlsldLAddr i64:$reg, 1572 tglobaltlsaddr:$disp, 1573 tglobaltlsaddr:$sym))]>, 1574 isPPC64; 1575def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1576 "#ADDISdtprelHA", 1577 [(set i64:$rD, 1578 (PPCaddisDtprelHA i64:$reg, 1579 tglobaltlsaddr:$disp))]>, 1580 isPPC64; 1581def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1582 "#ADDIdtprelL", 1583 [(set i64:$rD, 1584 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1585 isPPC64; 1586def PADDIdtprel : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1587 "#PADDIdtprel", 1588 [(set i64:$rD, 1589 (PPCpaddiDtprel i64:$reg, tglobaltlsaddr:$disp))]>, 1590 isPPC64; 1591 1592let PPC970_Unit = 2 in { 1593let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1594// Truncating stores. 1595def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1596 "stb $rS, $src", IIC_LdStStore, 1597 [(truncstorei8 i64:$rS, DForm:$src)]>; 1598def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1599 "sth $rS, $src", IIC_LdStStore, 1600 [(truncstorei16 i64:$rS, DForm:$src)]>; 1601def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1602 "stw $rS, $src", IIC_LdStStore, 1603 [(truncstorei32 i64:$rS, DForm:$src)]>; 1604def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1605 "stbx $rS, $dst", IIC_LdStStore, 1606 [(truncstorei8 i64:$rS, XForm:$dst)]>, 1607 PPC970_DGroup_Cracked; 1608def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1609 "sthx $rS, $dst", IIC_LdStStore, 1610 [(truncstorei16 i64:$rS, XForm:$dst)]>, 1611 PPC970_DGroup_Cracked; 1612def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1613 "stwx $rS, $dst", IIC_LdStStore, 1614 [(truncstorei32 i64:$rS, XForm:$dst)]>, 1615 PPC970_DGroup_Cracked; 1616} // Interpretation64Bit 1617 1618// Normal 8-byte stores. 1619def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1620 "std $rS, $dst", IIC_LdStSTD, 1621 [(store i64:$rS, DSForm:$dst)]>, isPPC64; 1622def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1623 "stdx $rS, $dst", IIC_LdStSTD, 1624 [(store i64:$rS, XForm:$dst)]>, isPPC64, 1625 PPC970_DGroup_Cracked; 1626 1627let Predicates = [IsISA2_06] in { 1628def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1629 "stdbrx $rS, $dst", IIC_LdStStore, 1630 [(PPCstbrx i64:$rS, ForceXForm:$dst, i64)]>, isPPC64, 1631 PPC970_DGroup_Cracked; 1632} 1633 1634let mayStore = 1, hasNoSchedulingInfo = 1 in { 1635// Normal 16-byte stores. 1636// TODO: Add scheduling info. 1637def STQ : DSForm_1<62, 2, (outs), (ins g8prc:$RSp, memrix:$dst), 1638 "stq $RSp, $dst", IIC_LdStSTQ, 1639 []>, isPPC64; 1640 1641def STQX_PSEUDO : PPCCustomInserterPseudo<(outs), 1642 (ins g8prc:$RSp, memrr:$dst), 1643 "#STQX_PSEUDO", []>; 1644 1645def SPILL_QUADWORD : PPCEmitTimePseudo<(outs), (ins g8prc:$RSp, memrix:$dst), 1646 "#SPILL_QUADWORD", []>; 1647} 1648 1649} 1650 1651def BUILD_QUADWORD : PPCPostRAExpPseudo< 1652 (outs g8prc:$RTp), 1653 (ins g8rc:$lo, g8rc:$hi), 1654 "#BUILD_QUADWORD", []>; 1655 1656def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, DSForm:$dst), 1657 (STQ (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrix:$dst)>; 1658 1659def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, ForceXForm:$dst), 1660 (STQX_PSEUDO (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrr:$dst)>; 1661 1662// Stores with Update (pre-inc). 1663let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1664let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1665def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1666 "stbu $rS, $dst", IIC_LdStSTU, []>, 1667 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1668def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1669 "sthu $rS, $dst", IIC_LdStSTU, []>, 1670 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1671def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1672 "stwu $rS, $dst", IIC_LdStSTU, []>, 1673 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1674 1675def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1676 (ins g8rc:$rS, memrr:$dst), 1677 "stbux $rS, $dst", IIC_LdStSTUX, []>, 1678 RegConstraint<"$dst.ptrreg = $ea_res">, 1679 NoEncode<"$ea_res">, 1680 PPC970_DGroup_Cracked; 1681def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1682 (ins g8rc:$rS, memrr:$dst), 1683 "sthux $rS, $dst", IIC_LdStSTUX, []>, 1684 RegConstraint<"$dst.ptrreg = $ea_res">, 1685 NoEncode<"$ea_res">, 1686 PPC970_DGroup_Cracked; 1687def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1688 (ins g8rc:$rS, memrr:$dst), 1689 "stwux $rS, $dst", IIC_LdStSTUX, []>, 1690 RegConstraint<"$dst.ptrreg = $ea_res">, 1691 NoEncode<"$ea_res">, 1692 PPC970_DGroup_Cracked; 1693} // Interpretation64Bit 1694 1695def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1696 (ins g8rc:$rS, memrix:$dst), 1697 "stdu $rS, $dst", IIC_LdStSTU, []>, 1698 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1699 isPPC64; 1700 1701def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1702 (ins g8rc:$rS, memrr:$dst), 1703 "stdux $rS, $dst", IIC_LdStSTUX, []>, 1704 RegConstraint<"$dst.ptrreg = $ea_res">, 1705 NoEncode<"$ea_res">, 1706 PPC970_DGroup_Cracked, isPPC64; 1707} 1708 1709// Patterns to match the pre-inc stores. We can't put the patterns on 1710// the instruction definitions directly as ISel wants the address base 1711// and offset to be separate operands, not a single complex operand. 1712def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1713 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1714def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1715 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1716def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1717 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1718def : Pat<(DSFormPreStore i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1719 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1720 1721def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1722 (STBUX8 $rS, $ptrreg, $ptroff)>; 1723def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1724 (STHUX8 $rS, $ptrreg, $ptroff)>; 1725def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1726 (STWUX8 $rS, $ptrreg, $ptroff)>; 1727def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1728 (STDUX $rS, $ptrreg, $ptroff)>; 1729 1730 1731//===----------------------------------------------------------------------===// 1732// Floating point instructions. 1733// 1734 1735 1736let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1, 1737 Uses = [RM] in { // FPU Operations. 1738defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1739 "fcfid", "$frD, $frB", IIC_FPGeneral, 1740 [(set f64:$frD, (PPCany_fcfid f64:$frB))]>, isPPC64; 1741defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1742 "fctid", "$frD, $frB", IIC_FPGeneral, 1743 []>, isPPC64; 1744defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), 1745 "fctidu", "$frD, $frB", IIC_FPGeneral, 1746 []>, isPPC64; 1747defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1748 "fctidz", "$frD, $frB", IIC_FPGeneral, 1749 [(set f64:$frD, (PPCany_fctidz f64:$frB))]>, isPPC64; 1750 1751defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1752 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1753 [(set f64:$frD, (PPCany_fcfidu f64:$frB))]>, isPPC64; 1754defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1755 "fcfids", "$frD, $frB", IIC_FPGeneral, 1756 [(set f32:$frD, (PPCany_fcfids f64:$frB))]>, isPPC64; 1757defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1758 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1759 [(set f32:$frD, (PPCany_fcfidus f64:$frB))]>, isPPC64; 1760defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1761 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1762 [(set f64:$frD, (PPCany_fctiduz f64:$frB))]>, isPPC64; 1763defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1764 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1765 [(set f64:$frD, (PPCany_fctiwuz f64:$frB))]>, isPPC64; 1766} 1767 1768// These instructions store a hash computed from the value of the link register 1769// and the value of the stack pointer. 1770let mayStore = 1, Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1771def HASHST8 : XForm_XD6_RA5_RB5<31, 722, (outs), 1772 (ins g8rc:$RB, memrihash:$D_RA_XD), 1773 "hashst $RB, $D_RA_XD", IIC_IntGeneral, []>; 1774def HASHSTP8 : XForm_XD6_RA5_RB5<31, 658, (outs), 1775 (ins g8rc:$RB, memrihash:$D_RA_XD), 1776 "hashstp $RB, $D_RA_XD", IIC_IntGeneral, []>; 1777} 1778 1779// These instructions check a hash computed from the value of the link register 1780// and the value of the stack pointer. The hasSideEffects flag is needed as the 1781// instruction may TRAP if the hash does not match the hash stored at the 1782// specified address. 1783let mayLoad = 1, hasSideEffects = 1, 1784 Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1785def HASHCHK8 : XForm_XD6_RA5_RB5<31, 754, (outs), 1786 (ins g8rc:$RB, memrihash:$D_RA_XD), 1787 "hashchk $RB, $D_RA_XD", IIC_IntGeneral, []>; 1788def HASHCHKP8 : XForm_XD6_RA5_RB5<31, 690, (outs), 1789 (ins g8rc:$RB, memrihash:$D_RA_XD), 1790 "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>; 1791} 1792 1793let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in 1794def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT), 1795 (ins g8rc:$rA, g8rc:$rB, u2imm:$CY), 1796 "addex $rT, $rA, $rB, $CY", IIC_IntGeneral, 1797 [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB, 1798 timm:$CY))]>; 1799 1800//===----------------------------------------------------------------------===// 1801// Instruction Patterns 1802// 1803 1804// Extensions and truncates to/from 32-bit regs. 1805def : Pat<(i64 (zext i32:$in)), 1806 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1807 0, 32)>; 1808def : Pat<(i64 (anyext i32:$in)), 1809 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1810def : Pat<(i32 (trunc i64:$in)), 1811 (EXTRACT_SUBREG $in, sub_32)>; 1812 1813// Implement the 'not' operation with the NOR instruction. 1814// (we could use the default xori pattern, but nor has lower latency on some 1815// cores (such as the A2)). 1816def i64not : OutPatFrag<(ops node:$in), 1817 (NOR8 $in, $in)>; 1818def : Pat<(not i64:$in), 1819 (i64not $in)>; 1820 1821// Extending loads with i64 targets. 1822def : Pat<(zextloadi1 DForm:$src), 1823 (LBZ8 DForm:$src)>; 1824def : Pat<(zextloadi1 XForm:$src), 1825 (LBZX8 XForm:$src)>; 1826def : Pat<(extloadi1 DForm:$src), 1827 (LBZ8 DForm:$src)>; 1828def : Pat<(extloadi1 XForm:$src), 1829 (LBZX8 XForm:$src)>; 1830def : Pat<(extloadi8 DForm:$src), 1831 (LBZ8 DForm:$src)>; 1832def : Pat<(extloadi8 XForm:$src), 1833 (LBZX8 XForm:$src)>; 1834def : Pat<(extloadi16 DForm:$src), 1835 (LHZ8 DForm:$src)>; 1836def : Pat<(extloadi16 XForm:$src), 1837 (LHZX8 XForm:$src)>; 1838def : Pat<(extloadi32 DForm:$src), 1839 (LWZ8 DForm:$src)>; 1840def : Pat<(extloadi32 XForm:$src), 1841 (LWZX8 XForm:$src)>; 1842 1843// Standard shifts. These are represented separately from the real shifts above 1844// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1845// amounts. 1846def : Pat<(sra i64:$rS, i32:$rB), 1847 (SRAD $rS, $rB)>; 1848def : Pat<(srl i64:$rS, i32:$rB), 1849 (SRD $rS, $rB)>; 1850def : Pat<(shl i64:$rS, i32:$rB), 1851 (SLD $rS, $rB)>; 1852 1853// SUBFIC 1854def : Pat<(sub imm64SExt16:$imm, i64:$in), 1855 (SUBFIC8 $in, imm:$imm)>; 1856 1857// SHL/SRL 1858def : Pat<(shl i64:$in, (i32 imm:$imm)), 1859 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1860def : Pat<(srl i64:$in, (i32 imm:$imm)), 1861 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1862 1863// ROTL 1864def : Pat<(rotl i64:$in, i32:$sh), 1865 (RLDCL $in, $sh, 0)>; 1866def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1867 (RLDICL $in, imm:$imm, 0)>; 1868 1869// Hi and Lo for Darwin Global Addresses. 1870def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1871def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1872def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1873def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1874def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1875def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1876def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1877def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1878def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1879 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1880def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1881 (ADDI8 $in, tglobaltlsaddr:$g)>; 1882def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1883 (ADDIS8 $in, tglobaladdr:$g)>; 1884def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1885 (ADDIS8 $in, tconstpool:$g)>; 1886def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1887 (ADDIS8 $in, tjumptable:$g)>; 1888def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1889 (ADDIS8 $in, tblockaddress:$g)>; 1890 1891// AIX 64-bit small code model TLS access. 1892def : Pat<(i64 (PPCtoc_entry tglobaltlsaddr:$disp, i64:$reg)), 1893 (i64 (LDtoc tglobaltlsaddr:$disp, i64:$reg))>; 1894 1895// 64-bits atomic loads and stores 1896def : Pat<(atomic_load_64 DSForm:$src), (LD memrix:$src)>; 1897def : Pat<(atomic_load_64 XForm:$src), (LDX memrr:$src)>; 1898 1899def : Pat<(atomic_store_64 DSForm:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1900def : Pat<(atomic_store_64 XForm:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1901 1902let Predicates = [IsISA3_0, In64BitMode] in { 1903def : Pat<(i64 (int_ppc_cmpeqb g8rc:$a, g8rc:$b)), 1904 (i64 (SETB8 (CMPEQB $a, $b)))>; 1905def : Pat<(i64 (int_ppc_setb g8rc:$a, g8rc:$b)), 1906 (i64 (SETB8 (CMPD $a, $b)))>; 1907def : Pat<(i64 (int_ppc_maddhd g8rc:$a, g8rc:$b, g8rc:$c)), 1908 (i64 (MADDHD $a, $b, $c))>; 1909def : Pat<(i64 (int_ppc_maddhdu g8rc:$a, g8rc:$b, g8rc:$c)), 1910 (i64 (MADDHDU $a, $b, $c))>; 1911def : Pat<(i64 (int_ppc_maddld g8rc:$a, g8rc:$b, g8rc:$c)), 1912 (i64 (MADDLD8 $a, $b, $c))>; 1913} 1914 1915let Predicates = [In64BitMode] in { 1916def : Pat<(i64 (int_ppc_mulhd g8rc:$a, g8rc:$b)), 1917 (i64 (MULHD $a, $b))>; 1918def : Pat<(i64 (int_ppc_mulhdu g8rc:$a, g8rc:$b)), 1919 (i64 (MULHDU $a, $b))>; 1920def : Pat<(int_ppc_load8r ForceXForm:$ptr), 1921 (LDBRX ForceXForm:$ptr)>; 1922def : Pat<(int_ppc_store8r g8rc:$a, ForceXForm:$ptr), 1923 (STDBRX g8rc:$a, ForceXForm:$ptr)>; 1924} 1925 1926def : Pat<(i64 (int_ppc_cmpb g8rc:$a, g8rc:$b)), 1927 (i64 (CMPB8 $a, $b))>; 1928 1929let Predicates = [IsISA3_0] in { 1930// DARN (deliver random number) 1931// L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random 1932def : Pat<(int_ppc_darn32), (EXTRACT_SUBREG (DARN 0), sub_32)>; 1933def : Pat<(int_ppc_darn), (DARN 1)>; 1934def : Pat<(int_ppc_darnraw), (DARN 2)>; 1935 1936class X_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1937 InstrItinClass itin, list<dag> pattern> 1938 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1939 !strconcat(opc, " $rA, $rB"), itin, pattern>{ 1940 let L = 1; 1941} 1942 1943class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1944 InstrItinClass itin, list<dag> pattern> 1945 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1946 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1947 1948let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1949def CP_COPY8 : X_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1950def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm; 1951} 1952 1953// SLB Invalidate Entry Global 1954def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1955 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1956// SLB Synchronize 1957def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1958 1959} // IsISA3_0 1960 1961def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A), 1962 (STDCX g8rc:$A, ForceXForm:$dst)>; 1963 1964// trapd 1965def : Pat<(int_ppc_trapd g8rc:$A), 1966 (TDI 24, $A, 0)>; 1967def : Pat<(i64 (int_ppc_mfspr timm:$SPR)), 1968 (MFSPR8 $SPR)>; 1969def : Pat<(int_ppc_mtspr timm:$SPR, g8rc:$RT), 1970 (MTSPR8 $SPR, $RT)>; 1971