1//===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the Altivec extension to the PowerPC instruction set. 10// 11//===----------------------------------------------------------------------===// 12 13// *********************************** NOTE *********************************** 14// ** For POWER8 Little Endian, the VSX swap optimization relies on knowing ** 15// ** which VMX and VSX instructions are lane-sensitive and which are not. ** 16// ** A lane-sensitive instruction relies, implicitly or explicitly, on ** 17// ** whether lanes are numbered from left to right. An instruction like ** 18// ** VADDFP is not lane-sensitive, because each lane of the result vector ** 19// ** relies only on the corresponding lane of the source vectors. However, ** 20// ** an instruction like VMULESB is lane-sensitive, because "even" and ** 21// ** "odd" lanes are different for big-endian and little-endian numbering. ** 22// ** ** 23// ** When adding new VMX and VSX instructions, please consider whether they ** 24// ** are lane-sensitive. If so, they must be added to a switch statement ** 25// ** in PPCVSXSwapRemoval::gatherVectorInstructions(). ** 26// **************************************************************************** 27 28 29//===----------------------------------------------------------------------===// 30// Altivec transformation functions and pattern fragments. 31// 32 33def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 34 (vector_shuffle node:$lhs, node:$rhs), [{ 35 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 36}]>; 37def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 38 (vector_shuffle node:$lhs, node:$rhs), [{ 39 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 40}]>; 41def vpkudum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 42 (vector_shuffle node:$lhs, node:$rhs), [{ 43 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 44}]>; 45def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 46 (vector_shuffle node:$lhs, node:$rhs), [{ 47 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 48}]>; 49def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 50 (vector_shuffle node:$lhs, node:$rhs), [{ 51 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 52}]>; 53def vpkudum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 54 (vector_shuffle node:$lhs, node:$rhs), [{ 55 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 56}]>; 57 58// These fragments are provided for little-endian, where the inputs must be 59// swapped for correct semantics. 60def vpkuhum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 61 (vector_shuffle node:$lhs, node:$rhs), [{ 62 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 63}]>; 64def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 65 (vector_shuffle node:$lhs, node:$rhs), [{ 66 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 67}]>; 68def vpkudum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 69 (vector_shuffle node:$lhs, node:$rhs), [{ 70 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 71}]>; 72 73def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 74 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 75 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); 76}]>; 77def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 78 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 79 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); 80}]>; 81def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 82 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 83 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); 84}]>; 85def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 86 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 87 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); 88}]>; 89def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 90 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 91 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); 92}]>; 93def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 94 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 95 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); 96}]>; 97 98 99def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 100 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 101 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); 102}]>; 103def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 104 (vector_shuffle node:$lhs, node:$rhs), [{ 105 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); 106}]>; 107def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 108 (vector_shuffle node:$lhs, node:$rhs), [{ 109 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); 110}]>; 111def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 112 (vector_shuffle node:$lhs, node:$rhs), [{ 113 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); 114}]>; 115def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 116 (vector_shuffle node:$lhs, node:$rhs), [{ 117 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); 118}]>; 119def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 120 (vector_shuffle node:$lhs, node:$rhs), [{ 121 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); 122}]>; 123 124 125// These fragments are provided for little-endian, where the inputs must be 126// swapped for correct semantics. 127def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 128 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 129 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); 130}]>; 131def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 132 (vector_shuffle node:$lhs, node:$rhs), [{ 133 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); 134}]>; 135def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 136 (vector_shuffle node:$lhs, node:$rhs), [{ 137 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); 138}]>; 139def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 140 (vector_shuffle node:$lhs, node:$rhs), [{ 141 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); 142}]>; 143def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 144 (vector_shuffle node:$lhs, node:$rhs), [{ 145 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); 146}]>; 147def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 148 (vector_shuffle node:$lhs, node:$rhs), [{ 149 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); 150}]>; 151 152 153def vmrgew_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 154 (vector_shuffle node:$lhs, node:$rhs), [{ 155 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 0, *CurDAG); 156}]>; 157def vmrgow_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 158 (vector_shuffle node:$lhs, node:$rhs), [{ 159 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 0, *CurDAG); 160}]>; 161def vmrgew_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 162 (vector_shuffle node:$lhs, node:$rhs), [{ 163 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 1, *CurDAG); 164}]>; 165def vmrgow_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 166 (vector_shuffle node:$lhs, node:$rhs), [{ 167 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 1, *CurDAG); 168}]>; 169def vmrgew_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 170 (vector_shuffle node:$lhs, node:$rhs), [{ 171 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 2, *CurDAG); 172}]>; 173def vmrgow_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 174 (vector_shuffle node:$lhs, node:$rhs), [{ 175 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 2, *CurDAG); 176}]>; 177 178 179 180def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 181 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG), SDLoc(N)); 182}]>; 183def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 184 (vector_shuffle node:$lhs, node:$rhs), [{ 185 return PPC::isVSLDOIShuffleMask(N, 0, *CurDAG) != -1; 186}], VSLDOI_get_imm>; 187 188 189/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 190/// vector_shuffle(X,undef,mask) by the dag combiner. 191def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 192 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG), SDLoc(N)); 193}]>; 194def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 195 (vector_shuffle node:$lhs, node:$rhs), [{ 196 return PPC::isVSLDOIShuffleMask(N, 1, *CurDAG) != -1; 197}], VSLDOI_unary_get_imm>; 198 199 200/// VSLDOI_swapped* - These fragments are provided for little-endian, where 201/// the inputs must be swapped for correct semantics. 202def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{ 203 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG), SDLoc(N)); 204}]>; 205def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 206 (vector_shuffle node:$lhs, node:$rhs), [{ 207 return PPC::isVSLDOIShuffleMask(N, 2, *CurDAG) != -1; 208}], VSLDOI_get_imm>; 209 210 211// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 212def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 213 return getI32Imm(PPC::getSplatIdxForPPCMnemonics(N, 1, *CurDAG), SDLoc(N)); 214}]>; 215def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 216 (vector_shuffle node:$lhs, node:$rhs), [{ 217 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 218}], VSPLTB_get_imm>; 219def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 220 return getI32Imm(PPC::getSplatIdxForPPCMnemonics(N, 2, *CurDAG), SDLoc(N)); 221}]>; 222def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 223 (vector_shuffle node:$lhs, node:$rhs), [{ 224 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 225}], VSPLTH_get_imm>; 226def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 227 return getI32Imm(PPC::getSplatIdxForPPCMnemonics(N, 4, *CurDAG), SDLoc(N)); 228}]>; 229def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 230 (vector_shuffle node:$lhs, node:$rhs), [{ 231 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 232}], VSPLTW_get_imm>; 233 234 235// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 236def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 237 return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 238}]>; 239def vecspltisb : PatLeaf<(build_vector), [{ 240 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != nullptr; 241}], VSPLTISB_get_imm>; 242 243// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 244def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 245 return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 246}]>; 247def vecspltish : PatLeaf<(build_vector), [{ 248 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != nullptr; 249}], VSPLTISH_get_imm>; 250 251// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 252def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 253 return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 254}]>; 255def vecspltisw : PatLeaf<(build_vector), [{ 256 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != nullptr; 257}], VSPLTISW_get_imm>; 258 259def immEQOneV : PatLeaf<(build_vector), [{ 260 if (ConstantSDNode *C = cast<BuildVectorSDNode>(N)->getConstantSplatNode()) 261 return C->isOne(); 262 return false; 263}]>; 264//===----------------------------------------------------------------------===// 265// Helpers for defining instructions that directly correspond to intrinsics. 266 267// VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type. 268class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty> 269 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 270 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 271 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>; 272 273// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the 274// inputs doesn't match the type of the output. 275class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 276 ValueType InTy> 277 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 278 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 279 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>; 280 281// VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two 282// input types and an output type. 283class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 284 ValueType In1Ty, ValueType In2Ty> 285 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 286 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 287 [(set OutTy:$vD, 288 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>; 289 290// VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type. 291class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 292 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 293 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 294 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>; 295 296// VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the 297// inputs doesn't match the type of the output. 298class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 299 ValueType InTy> 300 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 301 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 302 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>; 303 304// VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two 305// input types and an output type. 306class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 307 ValueType In1Ty, ValueType In2Ty> 308 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 309 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 310 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>; 311 312// VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type. 313class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID> 314 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 315 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 316 [(set v4f32:$vD, (IntID v4f32:$vB))]>; 317 318// VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the 319// inputs doesn't match the type of the output. 320class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 321 ValueType InTy> 322 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 323 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 324 [(set OutTy:$vD, (IntID InTy:$vB))]>; 325 326class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 327 : VXForm_BX<xo, (outs vrrc:$vD), (ins vrrc:$vA), 328 !strconcat(opc, " $vD, $vA"), IIC_VecFP, 329 [(set Ty:$vD, (IntID Ty:$vA))]>; 330 331class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 332 : VXForm_CR<xo, (outs vrrc:$vD), (ins vrrc:$vA, u1imm:$ST, u4imm:$SIX), 333 !strconcat(opc, " $vD, $vA, $ST, $SIX"), IIC_VecFP, 334 [(set Ty:$vD, (IntID Ty:$vA, timm:$ST, timm:$SIX))]>; 335 336//===----------------------------------------------------------------------===// 337// Instruction Definitions. 338 339def HasAltivec : Predicate<"Subtarget->hasAltivec()">; 340let Predicates = [HasAltivec] in { 341 342def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM), 343 "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>, 344 Deprecated<DeprecatedDST> { 345 let A = 0; 346 let B = 0; 347} 348 349def DSSALL : DSS_Form<1, 822, (outs), (ins), 350 "dssall", IIC_LdStLoad /*FIXME*/, []>, 351 Deprecated<DeprecatedDST> { 352 let STRM = 0; 353 let A = 0; 354 let B = 0; 355} 356 357def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 358 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 359 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>, 360 Deprecated<DeprecatedDST>; 361 362def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 363 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 364 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>, 365 Deprecated<DeprecatedDST>; 366 367def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 368 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 369 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>, 370 Deprecated<DeprecatedDST>; 371 372def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 373 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 374 [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>, 375 Deprecated<DeprecatedDST>; 376 377let isCodeGenOnly = 1 in { 378 // The very same instructions as above, but formally matching 64bit registers. 379 def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 380 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 381 [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>, 382 Deprecated<DeprecatedDST>; 383 384 def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 385 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 386 [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>, 387 Deprecated<DeprecatedDST>; 388 389 def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 390 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 391 [(int_ppc_altivec_dstst i64:$rA, i32:$rB, 392 imm:$STRM)]>, 393 Deprecated<DeprecatedDST>; 394 395 def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 396 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 397 [(int_ppc_altivec_dststt i64:$rA, i32:$rB, 398 imm:$STRM)]>, 399 Deprecated<DeprecatedDST>; 400} 401 402let hasSideEffects = 1 in { 403 def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), 404 "mfvscr $vD", IIC_LdStStore, 405 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>; 406 def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB), 407 "mtvscr $vB", IIC_LdStLoad, 408 [(int_ppc_altivec_mtvscr v4i32:$vB)]>; 409} 410 411let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { // Loads. 412def LVEBX: XForm_1_memOp<31, 7, (outs vrrc:$vD), (ins memrr:$src), 413 "lvebx $vD, $src", IIC_LdStLoad, 414 [(set v16i8:$vD, (int_ppc_altivec_lvebx ForceXForm:$src))]>; 415def LVEHX: XForm_1_memOp<31, 39, (outs vrrc:$vD), (ins memrr:$src), 416 "lvehx $vD, $src", IIC_LdStLoad, 417 [(set v8i16:$vD, (int_ppc_altivec_lvehx ForceXForm:$src))]>; 418def LVEWX: XForm_1_memOp<31, 71, (outs vrrc:$vD), (ins memrr:$src), 419 "lvewx $vD, $src", IIC_LdStLoad, 420 [(set v4i32:$vD, (int_ppc_altivec_lvewx ForceXForm:$src))]>; 421def LVX : XForm_1_memOp<31, 103, (outs vrrc:$vD), (ins memrr:$src), 422 "lvx $vD, $src", IIC_LdStLoad, 423 [(set v4i32:$vD, (int_ppc_altivec_lvx ForceXForm:$src))]>; 424def LVXL : XForm_1_memOp<31, 359, (outs vrrc:$vD), (ins memrr:$src), 425 "lvxl $vD, $src", IIC_LdStLoad, 426 [(set v4i32:$vD, (int_ppc_altivec_lvxl ForceXForm:$src))]>; 427} 428 429def LVSL : XForm_1_memOp<31, 6, (outs vrrc:$vD), (ins memrr:$src), 430 "lvsl $vD, $src", IIC_LdStLoad, 431 [(set v16i8:$vD, (int_ppc_altivec_lvsl ForceXForm:$src))]>, 432 PPC970_Unit_LSU; 433def LVSR : XForm_1_memOp<31, 38, (outs vrrc:$vD), (ins memrr:$src), 434 "lvsr $vD, $src", IIC_LdStLoad, 435 [(set v16i8:$vD, (int_ppc_altivec_lvsr ForceXForm:$src))]>, 436 PPC970_Unit_LSU; 437 438let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { // Stores. 439def STVEBX: XForm_8_memOp<31, 135, (outs), (ins vrrc:$rS, memrr:$dst), 440 "stvebx $rS, $dst", IIC_LdStStore, 441 [(int_ppc_altivec_stvebx v16i8:$rS, ForceXForm:$dst)]>; 442def STVEHX: XForm_8_memOp<31, 167, (outs), (ins vrrc:$rS, memrr:$dst), 443 "stvehx $rS, $dst", IIC_LdStStore, 444 [(int_ppc_altivec_stvehx v8i16:$rS, ForceXForm:$dst)]>; 445def STVEWX: XForm_8_memOp<31, 199, (outs), (ins vrrc:$rS, memrr:$dst), 446 "stvewx $rS, $dst", IIC_LdStStore, 447 [(int_ppc_altivec_stvewx v4i32:$rS, ForceXForm:$dst)]>; 448def STVX : XForm_8_memOp<31, 231, (outs), (ins vrrc:$rS, memrr:$dst), 449 "stvx $rS, $dst", IIC_LdStStore, 450 [(int_ppc_altivec_stvx v4i32:$rS, ForceXForm:$dst)]>; 451def STVXL : XForm_8_memOp<31, 487, (outs), (ins vrrc:$rS, memrr:$dst), 452 "stvxl $rS, $dst", IIC_LdStStore, 453 [(int_ppc_altivec_stvxl v4i32:$rS, ForceXForm:$dst)]>; 454} 455 456let PPC970_Unit = 5 in { // VALU Operations. 457// VA-Form instructions. 3-input AltiVec ops. 458let isCommutable = 1 in { 459def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 460 "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP, 461 [(set v4f32:$vD, 462 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>; 463 464// FIXME: The fma+fneg pattern won't match because fneg is not legal. 465def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 466 "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP, 467 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC, 468 (fneg v4f32:$vB))))]>; 469let hasSideEffects = 1 in { 470 def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>; 471 def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs, 472 v8i16>; 473} 474def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>; 475} // isCommutable 476 477def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm, 478 v4i32, v4i32, v16i8>; 479def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>; 480 481// Shuffles. 482def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u4imm:$SH), 483 "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP, 484 [(set v16i8:$vD, 485 (PPCvecshl v16i8:$vA, v16i8:$vB, imm32SExt16:$SH))]>; 486 487// VX-Form instructions. AltiVec arithmetic ops. 488let isCommutable = 1 in { 489def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 490 "vaddfp $vD, $vA, $vB", IIC_VecFP, 491 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; 492 493def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 494 "vaddubm $vD, $vA, $vB", IIC_VecGeneral, 495 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; 496def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 497 "vadduhm $vD, $vA, $vB", IIC_VecGeneral, 498 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>; 499def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 500 "vadduwm $vD, $vA, $vB", IIC_VecGeneral, 501 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; 502 503def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; 504def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>; 505def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>; 506def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>; 507def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>; 508def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>; 509def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>; 510} // isCommutable 511 512let isCommutable = 1 in 513def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 514 "vand $vD, $vA, $vB", IIC_VecFP, 515 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>; 516def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 517 "vandc $vD, $vA, $vB", IIC_VecFP, 518 [(set v4i32:$vD, (and v4i32:$vA, 519 (vnot v4i32:$vB)))]>; 520 521def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 522 "vcfsx $vD, $vB, $UIMM", IIC_VecFP, 523 [(set v4f32:$vD, 524 (int_ppc_altivec_vcfsx v4i32:$vB, timm:$UIMM))]>; 525def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 526 "vcfux $vD, $vB, $UIMM", IIC_VecFP, 527 [(set v4f32:$vD, 528 (int_ppc_altivec_vcfux v4i32:$vB, timm:$UIMM))]>; 529def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 530 "vctsxs $vD, $vB, $UIMM", IIC_VecFP, 531 [(set v4i32:$vD, 532 (int_ppc_altivec_vctsxs v4f32:$vB, timm:$UIMM))]>; 533def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 534 "vctuxs $vD, $vB, $UIMM", IIC_VecFP, 535 [(set v4i32:$vD, 536 (int_ppc_altivec_vctuxs v4f32:$vB, timm:$UIMM))]>; 537 538// Defines with the UIM field set to 0 for floating-point 539// to integer (fp_to_sint/fp_to_uint) conversions and integer 540// to floating-point (sint_to_fp/uint_to_fp) conversions. 541let isCodeGenOnly = 1, VA = 0 in { 542def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB), 543 "vcfsx $vD, $vB, 0", IIC_VecFP, 544 [(set v4f32:$vD, 545 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>; 546def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB), 547 "vctuxs $vD, $vB, 0", IIC_VecFP, 548 [(set v4i32:$vD, 549 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>; 550def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB), 551 "vcfux $vD, $vB, 0", IIC_VecFP, 552 [(set v4f32:$vD, 553 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>; 554def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB), 555 "vctsxs $vD, $vB, 0", IIC_VecFP, 556 [(set v4i32:$vD, 557 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>; 558} 559def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>; 560def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>; 561 562let isCommutable = 1 in { 563def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>; 564def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>; 565def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>; 566def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>; 567def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>; 568def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>; 569 570def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>; 571def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>; 572def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>; 573def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>; 574def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>; 575def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>; 576def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>; 577def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>; 578def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>; 579def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>; 580def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>; 581def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>; 582def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>; 583def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>; 584} // isCommutable 585 586def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 587 "vmrghb $vD, $vA, $vB", IIC_VecFP, 588 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>; 589def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 590 "vmrghh $vD, $vA, $vB", IIC_VecFP, 591 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>; 592def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 593 "vmrghw $vD, $vA, $vB", IIC_VecFP, 594 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>; 595def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 596 "vmrglb $vD, $vA, $vB", IIC_VecFP, 597 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>; 598def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 599 "vmrglh $vD, $vA, $vB", IIC_VecFP, 600 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>; 601def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 602 "vmrglw $vD, $vA, $vB", IIC_VecFP, 603 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>; 604 605def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm, 606 v4i32, v16i8, v4i32>; 607def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm, 608 v4i32, v8i16, v4i32>; 609def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm, 610 v4i32, v16i8, v4i32>; 611def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm, 612 v4i32, v8i16, v4i32>; 613let hasSideEffects = 1 in { 614 def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs, 615 v4i32, v8i16, v4i32>; 616 def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs, 617 v4i32, v8i16, v4i32>; 618} 619 620let isCommutable = 1 in { 621def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb, 622 v8i16, v16i8>; 623def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh, 624 v4i32, v8i16>; 625def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub, 626 v8i16, v16i8>; 627def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh, 628 v4i32, v8i16>; 629def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb, 630 v8i16, v16i8>; 631def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh, 632 v4i32, v8i16>; 633def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub, 634 v8i16, v16i8>; 635def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh, 636 v4i32, v8i16>; 637} // isCommutable 638 639def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>; 640def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>; 641def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>; 642def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>; 643def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>; 644def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 645 646def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>; 647 648def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 649 "vsubfp $vD, $vA, $vB", IIC_VecGeneral, 650 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>; 651def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 652 "vsububm $vD, $vA, $vB", IIC_VecGeneral, 653 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>; 654def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 655 "vsubuhm $vD, $vA, $vB", IIC_VecGeneral, 656 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>; 657def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 658 "vsubuwm $vD, $vA, $vB", IIC_VecGeneral, 659 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; 660 661def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; 662def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>; 663def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>; 664def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>; 665def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>; 666def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>; 667 668let hasSideEffects = 1 in { 669 def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>; 670 def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>; 671 672 def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs, 673 v4i32, v16i8, v4i32>; 674 def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs, 675 v4i32, v8i16, v4i32>; 676 def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs, 677 v4i32, v16i8, v4i32>; 678} 679 680def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 681 "vnor $vD, $vA, $vB", IIC_VecFP, 682 [(set v4i32:$vD, (vnot (or v4i32:$vA, 683 v4i32:$vB)))]>; 684let isCommutable = 1 in { 685def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 686 "vor $vD, $vA, $vB", IIC_VecFP, 687 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>; 688def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 689 "vxor $vD, $vA, $vB", IIC_VecFP, 690 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>; 691} // isCommutable 692 693def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>; 694def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>; 695def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>; 696 697def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >; 698def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>; 699 700def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>; 701def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>; 702def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>; 703 704def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 705 "vspltb $vD, $vB, $UIMM", IIC_VecPerm, 706 [(set v16i8:$vD, 707 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>; 708def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 709 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, 710 [(set v16i8:$vD, 711 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>; 712def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 713 "vspltw $vD, $vB, $UIMM", IIC_VecPerm, 714 [(set v16i8:$vD, 715 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>; 716let isCodeGenOnly = 1, hasSideEffects = 0 in { 717 def VSPLTBs : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB), 718 "vspltb $vD, $vB, $UIMM", IIC_VecPerm, []>; 719 def VSPLTHs : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB), 720 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, []>; 721} 722 723def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>; 724def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>; 725 726def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>; 727def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>; 728def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>; 729def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>; 730def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>; 731def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>; 732 733 734def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM), 735 "vspltisb $vD, $SIMM", IIC_VecPerm, 736 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>; 737def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM), 738 "vspltish $vD, $SIMM", IIC_VecPerm, 739 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>; 740def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM), 741 "vspltisw $vD, $SIMM", IIC_VecPerm, 742 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>; 743 744// Vector Pack. 745def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx, 746 v8i16, v4i32>; 747let hasSideEffects = 1 in { 748 def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss, 749 v16i8, v8i16>; 750 def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus, 751 v16i8, v8i16>; 752 def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss, 753 v8i16, v4i32>; 754 def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus, 755 v8i16, v4i32>; 756 def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus, 757 v16i8, v8i16>; 758 def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus, 759 v8i16, v4i32>; 760} 761def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 762 "vpkuhum $vD, $vA, $vB", IIC_VecFP, 763 [(set v16i8:$vD, 764 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>; 765def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 766 "vpkuwum $vD, $vA, $vB", IIC_VecFP, 767 [(set v16i8:$vD, 768 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>; 769 770// Vector Unpack. 771def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx, 772 v4i32, v8i16>; 773def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb, 774 v8i16, v16i8>; 775def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh, 776 v4i32, v8i16>; 777def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx, 778 v4i32, v8i16>; 779def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb, 780 v8i16, v16i8>; 781def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh, 782 v4i32, v8i16>; 783 784 785// Altivec Comparisons. 786 787class VCMP<bits<10> xo, string asmstr, ValueType Ty> 788 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 789 IIC_VecFPCompare, 790 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>; 791class VCMP_rec<bits<10> xo, string asmstr, ValueType Ty> 792 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 793 IIC_VecFPCompare, 794 [(set Ty:$vD, (Ty (PPCvcmp_rec Ty:$vA, Ty:$vB, xo)))]> { 795 let Defs = [CR6]; 796 let RC = 1; 797} 798 799// f32 element comparisons.0 800def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 801def VCMPBFP_rec : VCMP_rec<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 802def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 803def VCMPEQFP_rec : VCMP_rec<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 804def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 805def VCMPGEFP_rec : VCMP_rec<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 806def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 807def VCMPGTFP_rec : VCMP_rec<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 808 809// i8 element comparisons. 810def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 811def VCMPEQUB_rec : VCMP_rec< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 812def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 813def VCMPGTSB_rec : VCMP_rec<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 814def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 815def VCMPGTUB_rec : VCMP_rec<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 816 817// i16 element comparisons. 818def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 819def VCMPEQUH_rec : VCMP_rec< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 820def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 821def VCMPGTSH_rec : VCMP_rec<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 822def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 823def VCMPGTUH_rec : VCMP_rec<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 824 825// i32 element comparisons. 826def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 827def VCMPEQUW_rec : VCMP_rec<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 828def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 829def VCMPGTSW_rec : VCMP_rec<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 830def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 831def VCMPGTUW_rec : VCMP_rec<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 832 833let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1, 834 isReMaterializable = 1 in { 835 836def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 837 "vxor $vD, $vD, $vD", IIC_VecFP, 838 [(set v16i8:$vD, (v16i8 immAllZerosV))]>; 839def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 840 "vxor $vD, $vD, $vD", IIC_VecFP, 841 [(set v8i16:$vD, (v8i16 immAllZerosV))]>; 842def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 843 "vxor $vD, $vD, $vD", IIC_VecFP, 844 [(set v4i32:$vD, (v4i32 immAllZerosV))]>; 845 846let IMM=-1 in { 847def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins), 848 "vspltisw $vD, -1", IIC_VecFP, 849 [(set v16i8:$vD, (v16i8 immAllOnesV))]>; 850def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins), 851 "vspltisw $vD, -1", IIC_VecFP, 852 [(set v8i16:$vD, (v8i16 immAllOnesV))]>; 853def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), 854 "vspltisw $vD, -1", IIC_VecFP, 855 [(set v4i32:$vD, (v4i32 immAllOnesV))]>; 856} 857} 858} // VALU Operations. 859 860//===----------------------------------------------------------------------===// 861// Additional Altivec Patterns 862// 863 864// Extended mnemonics 865def : InstAlias<"vmr $vD, $vA", (VOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>; 866def : InstAlias<"vnot $vD, $vA", (VNOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>; 867 868// This is a nop on all supported architectures and the AIX assembler 869// doesn't support it (and will not be updated to support it). 870let Predicates = [IsAIX] in 871def : Pat<(int_ppc_altivec_dssall), (NOP)>; 872let Predicates = [NotAIX] in 873def : Pat<(int_ppc_altivec_dssall), (DSSALL)>; 874 875// Rotates. 876def : Pat<(v16i8 (rotl v16i8:$vA, v16i8:$vB)), 877 (v16i8 (VRLB v16i8:$vA, v16i8:$vB))>; 878def : Pat<(v8i16 (rotl v8i16:$vA, v8i16:$vB)), 879 (v8i16 (VRLH v8i16:$vA, v8i16:$vB))>; 880def : Pat<(v4i32 (rotl v4i32:$vA, v4i32:$vB)), 881 (v4i32 (VRLW v4i32:$vA, v4i32:$vB))>; 882 883// Multiply 884def : Pat<(mul v8i16:$vA, v8i16:$vB), (VMLADDUHM $vA, $vB, (v8i16(V_SET0H)))>; 885 886// Add 887def : Pat<(add (mul v8i16:$vA, v8i16:$vB), v8i16:$vC), (VMLADDUHM $vA, $vB, $vC)>; 888 889// Saturating adds/subtracts. 890def : Pat<(v16i8 (saddsat v16i8:$vA, v16i8:$vB)), (v16i8 (VADDSBS $vA, $vB))>; 891def : Pat<(v16i8 (uaddsat v16i8:$vA, v16i8:$vB)), (v16i8 (VADDUBS $vA, $vB))>; 892def : Pat<(v8i16 (saddsat v8i16:$vA, v8i16:$vB)), (v8i16 (VADDSHS $vA, $vB))>; 893def : Pat<(v8i16 (uaddsat v8i16:$vA, v8i16:$vB)), (v8i16 (VADDUHS $vA, $vB))>; 894def : Pat<(v4i32 (saddsat v4i32:$vA, v4i32:$vB)), (v4i32 (VADDSWS $vA, $vB))>; 895def : Pat<(v4i32 (uaddsat v4i32:$vA, v4i32:$vB)), (v4i32 (VADDUWS $vA, $vB))>; 896def : Pat<(v16i8 (ssubsat v16i8:$vA, v16i8:$vB)), (v16i8 (VSUBSBS $vA, $vB))>; 897def : Pat<(v16i8 (usubsat v16i8:$vA, v16i8:$vB)), (v16i8 (VSUBUBS $vA, $vB))>; 898def : Pat<(v8i16 (ssubsat v8i16:$vA, v8i16:$vB)), (v8i16 (VSUBSHS $vA, $vB))>; 899def : Pat<(v8i16 (usubsat v8i16:$vA, v8i16:$vB)), (v8i16 (VSUBUHS $vA, $vB))>; 900def : Pat<(v4i32 (ssubsat v4i32:$vA, v4i32:$vB)), (v4i32 (VSUBSWS $vA, $vB))>; 901def : Pat<(v4i32 (usubsat v4i32:$vA, v4i32:$vB)), (v4i32 (VSUBUWS $vA, $vB))>; 902 903// Loads. 904def : Pat<(v4i32 (load ForceXForm:$src)), (LVX ForceXForm:$src)>; 905 906// Stores. 907def : Pat<(store v4i32:$rS, ForceXForm:$dst), 908 (STVX $rS, ForceXForm:$dst)>; 909 910// Bit conversions. 911def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 912def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 913def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 914def : Pat<(v16i8 (bitconvert (v2i64 VRRC:$src))), (v16i8 VRRC:$src)>; 915def : Pat<(v16i8 (bitconvert (v1i128 VRRC:$src))), (v16i8 VRRC:$src)>; 916 917def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 918def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 919def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 920def : Pat<(v8i16 (bitconvert (v2i64 VRRC:$src))), (v8i16 VRRC:$src)>; 921def : Pat<(v8i16 (bitconvert (v1i128 VRRC:$src))), (v8i16 VRRC:$src)>; 922 923def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 924def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 925def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 926def : Pat<(v4i32 (bitconvert (v2i64 VRRC:$src))), (v4i32 VRRC:$src)>; 927def : Pat<(v4i32 (bitconvert (v1i128 VRRC:$src))), (v4i32 VRRC:$src)>; 928 929def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 930def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 931def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 932def : Pat<(v4f32 (bitconvert (v2i64 VRRC:$src))), (v4f32 VRRC:$src)>; 933def : Pat<(v4f32 (bitconvert (v1i128 VRRC:$src))), (v4f32 VRRC:$src)>; 934 935def : Pat<(v2i64 (bitconvert (v16i8 VRRC:$src))), (v2i64 VRRC:$src)>; 936def : Pat<(v2i64 (bitconvert (v8i16 VRRC:$src))), (v2i64 VRRC:$src)>; 937def : Pat<(v2i64 (bitconvert (v4i32 VRRC:$src))), (v2i64 VRRC:$src)>; 938def : Pat<(v2i64 (bitconvert (v4f32 VRRC:$src))), (v2i64 VRRC:$src)>; 939def : Pat<(v2i64 (bitconvert (v1i128 VRRC:$src))), (v2i64 VRRC:$src)>; 940 941def : Pat<(v1i128 (bitconvert (v16i8 VRRC:$src))), (v1i128 VRRC:$src)>; 942def : Pat<(v1i128 (bitconvert (v8i16 VRRC:$src))), (v1i128 VRRC:$src)>; 943def : Pat<(v1i128 (bitconvert (v4i32 VRRC:$src))), (v1i128 VRRC:$src)>; 944def : Pat<(v1i128 (bitconvert (v4f32 VRRC:$src))), (v1i128 VRRC:$src)>; 945def : Pat<(v1i128 (bitconvert (v2i64 VRRC:$src))), (v1i128 VRRC:$src)>; 946 947def : Pat<(f128 (bitconvert (v16i8 VRRC:$src))), (f128 VRRC:$src)>; 948def : Pat<(f128 (bitconvert (v8i16 VRRC:$src))), (f128 VRRC:$src)>; 949def : Pat<(f128 (bitconvert (v4i32 VRRC:$src))), (f128 VRRC:$src)>; 950def : Pat<(f128 (bitconvert (v4f32 VRRC:$src))), (f128 VRRC:$src)>; 951def : Pat<(f128 (bitconvert (v2f64 VRRC:$src))), (f128 VRRC:$src)>; 952 953def : Pat<(v16i8 (bitconvert (f128 VRRC:$src))), (v16i8 VRRC:$src)>; 954def : Pat<(v8i16 (bitconvert (f128 VRRC:$src))), (v8i16 VRRC:$src)>; 955def : Pat<(v4i32 (bitconvert (f128 VRRC:$src))), (v4i32 VRRC:$src)>; 956def : Pat<(v4f32 (bitconvert (f128 VRRC:$src))), (v4f32 VRRC:$src)>; 957def : Pat<(v2f64 (bitconvert (f128 VRRC:$src))), (v2f64 VRRC:$src)>; 958 959// Max/Min 960def : Pat<(v16i8 (umax v16i8:$src1, v16i8:$src2)), 961 (v16i8 (VMAXUB $src1, $src2))>; 962def : Pat<(v16i8 (smax v16i8:$src1, v16i8:$src2)), 963 (v16i8 (VMAXSB $src1, $src2))>; 964def : Pat<(v8i16 (umax v8i16:$src1, v8i16:$src2)), 965 (v8i16 (VMAXUH $src1, $src2))>; 966def : Pat<(v8i16 (smax v8i16:$src1, v8i16:$src2)), 967 (v8i16 (VMAXSH $src1, $src2))>; 968def : Pat<(v4i32 (umax v4i32:$src1, v4i32:$src2)), 969 (v4i32 (VMAXUW $src1, $src2))>; 970def : Pat<(v4i32 (smax v4i32:$src1, v4i32:$src2)), 971 (v4i32 (VMAXSW $src1, $src2))>; 972def : Pat<(v16i8 (umin v16i8:$src1, v16i8:$src2)), 973 (v16i8 (VMINUB $src1, $src2))>; 974def : Pat<(v16i8 (smin v16i8:$src1, v16i8:$src2)), 975 (v16i8 (VMINSB $src1, $src2))>; 976def : Pat<(v8i16 (umin v8i16:$src1, v8i16:$src2)), 977 (v8i16 (VMINUH $src1, $src2))>; 978def : Pat<(v8i16 (smin v8i16:$src1, v8i16:$src2)), 979 (v8i16 (VMINSH $src1, $src2))>; 980def : Pat<(v4i32 (umin v4i32:$src1, v4i32:$src2)), 981 (v4i32 (VMINUW $src1, $src2))>; 982def : Pat<(v4i32 (smin v4i32:$src1, v4i32:$src2)), 983 (v4i32 (VMINSW $src1, $src2))>; 984 985// Shuffles. 986 987// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 988def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef), 989 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>; 990def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef), 991 (VPKUWUM $vA, $vA)>; 992def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef), 993 (VPKUHUM $vA, $vA)>; 994def:Pat<(vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB), 995 (VSLDOI v16i8:$vA, v16i8:$vB, (VSLDOI_get_imm $SH))>; 996 997 998// Match vsldoi(y,x), vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands. 999// These fragments are matched for little-endian, where the inputs must 1000// be swapped for correct semantics. 1001def:Pat<(vsldoi_swapped_shuffle:$in v16i8:$vA, v16i8:$vB), 1002 (VSLDOI $vB, $vA, (VSLDOI_swapped_get_imm $in))>; 1003def:Pat<(vpkuwum_swapped_shuffle v16i8:$vA, v16i8:$vB), 1004 (VPKUWUM $vB, $vA)>; 1005def:Pat<(vpkuhum_swapped_shuffle v16i8:$vA, v16i8:$vB), 1006 (VPKUHUM $vB, $vA)>; 1007 1008// Match vmrg*(x,x) 1009def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef), 1010 (VMRGLB $vA, $vA)>; 1011def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef), 1012 (VMRGLH $vA, $vA)>; 1013def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef), 1014 (VMRGLW $vA, $vA)>; 1015def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef), 1016 (VMRGHB $vA, $vA)>; 1017def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef), 1018 (VMRGHH $vA, $vA)>; 1019def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef), 1020 (VMRGHW $vA, $vA)>; 1021 1022// Match vmrg*(y,x), i.e., swapped operands. These fragments 1023// are matched for little-endian, where the inputs must be 1024// swapped for correct semantics. 1025def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB), 1026 (VMRGLB $vB, $vA)>; 1027def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB), 1028 (VMRGLH $vB, $vA)>; 1029def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB), 1030 (VMRGLW $vB, $vA)>; 1031def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB), 1032 (VMRGHB $vB, $vA)>; 1033def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB), 1034 (VMRGHH $vB, $vA)>; 1035def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB), 1036 (VMRGHW $vB, $vA)>; 1037 1038// Logical Operations 1039def : Pat<(vnot v4i32:$vA), (VNOR $vA, $vA)>; 1040 1041def : Pat<(vnot (or v4i32:$A, v4i32:$B)), 1042 (VNOR $A, $B)>; 1043def : Pat<(and v4i32:$A, (vnot v4i32:$B)), 1044 (VANDC $A, $B)>; 1045 1046def : Pat<(fmul v4f32:$vA, v4f32:$vB), 1047 (VMADDFP $vA, $vB, 1048 (v4i32 (VSLW (v4i32 (V_SETALLONES)), (v4i32 (V_SETALLONES)))))>; 1049 1050def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C), 1051 (VNMSUBFP $A, $B, $C)>; 1052 1053def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 1054 (VMADDFP $A, $B, $C)>; 1055def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 1056 (VNMSUBFP $A, $B, $C)>; 1057 1058def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC), 1059 (VPERM $vA, $vB, $vC)>; 1060 1061def : Pat<(PPCfre v4f32:$A), (VREFP $A)>; 1062def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>; 1063 1064// Vector shifts 1065def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)), 1066 (v16i8 (VSLB $vA, $vB))>; 1067def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)), 1068 (v8i16 (VSLH $vA, $vB))>; 1069def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)), 1070 (v4i32 (VSLW $vA, $vB))>; 1071def : Pat<(v1i128 (shl v1i128:$vA, v1i128:$vB)), 1072 (v1i128 (VSL (v16i8 (VSLO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1073def : Pat<(v16i8 (PPCshl v16i8:$vA, v16i8:$vB)), 1074 (v16i8 (VSLB $vA, $vB))>; 1075def : Pat<(v8i16 (PPCshl v8i16:$vA, v8i16:$vB)), 1076 (v8i16 (VSLH $vA, $vB))>; 1077def : Pat<(v4i32 (PPCshl v4i32:$vA, v4i32:$vB)), 1078 (v4i32 (VSLW $vA, $vB))>; 1079def : Pat<(v1i128 (PPCshl v1i128:$vA, v1i128:$vB)), 1080 (v1i128 (VSL (v16i8 (VSLO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1081 1082def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)), 1083 (v16i8 (VSRB $vA, $vB))>; 1084def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)), 1085 (v8i16 (VSRH $vA, $vB))>; 1086def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)), 1087 (v4i32 (VSRW $vA, $vB))>; 1088def : Pat<(v1i128 (srl v1i128:$vA, v1i128:$vB)), 1089 (v1i128 (VSR (v16i8 (VSRO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1090def : Pat<(v16i8 (PPCsrl v16i8:$vA, v16i8:$vB)), 1091 (v16i8 (VSRB $vA, $vB))>; 1092def : Pat<(v8i16 (PPCsrl v8i16:$vA, v8i16:$vB)), 1093 (v8i16 (VSRH $vA, $vB))>; 1094def : Pat<(v4i32 (PPCsrl v4i32:$vA, v4i32:$vB)), 1095 (v4i32 (VSRW $vA, $vB))>; 1096def : Pat<(v1i128 (PPCsrl v1i128:$vA, v1i128:$vB)), 1097 (v1i128 (VSR (v16i8 (VSRO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1098 1099def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)), 1100 (v16i8 (VSRAB $vA, $vB))>; 1101def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)), 1102 (v8i16 (VSRAH $vA, $vB))>; 1103def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)), 1104 (v4i32 (VSRAW $vA, $vB))>; 1105def : Pat<(v16i8 (PPCsra v16i8:$vA, v16i8:$vB)), 1106 (v16i8 (VSRAB $vA, $vB))>; 1107def : Pat<(v8i16 (PPCsra v8i16:$vA, v8i16:$vB)), 1108 (v8i16 (VSRAH $vA, $vB))>; 1109def : Pat<(v4i32 (PPCsra v4i32:$vA, v4i32:$vB)), 1110 (v4i32 (VSRAW $vA, $vB))>; 1111 1112// Float to integer and integer to float conversions 1113def : Pat<(v4i32 (fp_to_sint v4f32:$vA)), 1114 (VCTSXS_0 $vA)>; 1115def : Pat<(v4i32 (fp_to_uint v4f32:$vA)), 1116 (VCTUXS_0 $vA)>; 1117def : Pat<(v4f32 (sint_to_fp v4i32:$vA)), 1118 (VCFSX_0 $vA)>; 1119def : Pat<(v4f32 (uint_to_fp v4i32:$vA)), 1120 (VCFUX_0 $vA)>; 1121 1122// Floating-point rounding 1123def : Pat<(v4f32 (ffloor v4f32:$vA)), 1124 (VRFIM $vA)>; 1125def : Pat<(v4f32 (fceil v4f32:$vA)), 1126 (VRFIP $vA)>; 1127def : Pat<(v4f32 (ftrunc v4f32:$vA)), 1128 (VRFIZ $vA)>; 1129def : Pat<(v4f32 (fnearbyint v4f32:$vA)), 1130 (VRFIN $vA)>; 1131 1132// Vector selection 1133def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)), 1134 (VSEL $vC, $vB, $vA)>; 1135def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)), 1136 (VSEL $vC, $vB, $vA)>; 1137def : Pat<(v4i32 (vselect v4i32:$vA, v4i32:$vB, v4i32:$vC)), 1138 (VSEL $vC, $vB, $vA)>; 1139def : Pat<(v2i64 (vselect v2i64:$vA, v2i64:$vB, v2i64:$vC)), 1140 (VSEL $vC, $vB, $vA)>; 1141def : Pat<(v4f32 (vselect v4i32:$vA, v4f32:$vB, v4f32:$vC)), 1142 (VSEL $vC, $vB, $vA)>; 1143def : Pat<(v2f64 (vselect v2i64:$vA, v2f64:$vB, v2f64:$vC)), 1144 (VSEL $vC, $vB, $vA)>; 1145def : Pat<(v1i128 (vselect v1i128:$vA, v1i128:$vB, v1i128:$vC)), 1146 (VSEL $vC, $vB, $vA)>; 1147 1148// Vector Integer Average Instructions 1149def : Pat<(v4i32 (sra (sub v4i32:$vA, (vnot v4i32:$vB)), 1150 (v4i32 (immEQOneV)))), (v4i32 (VAVGSW $vA, $vB))>; 1151def : Pat<(v8i16 (sra (sub v8i16:$vA, (v8i16 (bitconvert(vnot v4i32:$vB)))), 1152 (v8i16 (immEQOneV)))), (v8i16 (VAVGSH $vA, $vB))>; 1153def : Pat<(v16i8 (sra (sub v16i8:$vA, (v16i8 (bitconvert(vnot v4i32:$vB)))), 1154 (v16i8 (immEQOneV)))), (v16i8 (VAVGSB $vA, $vB))>; 1155def : Pat<(v4i32 (srl (sub v4i32:$vA, (vnot v4i32:$vB)), 1156 (v4i32 (immEQOneV)))), (v4i32 (VAVGUW $vA, $vB))>; 1157def : Pat<(v8i16 (srl (sub v8i16:$vA, (v8i16 (bitconvert(vnot v4i32:$vB)))), 1158 (v8i16 (immEQOneV)))), (v8i16 (VAVGUH $vA, $vB))>; 1159def : Pat<(v16i8 (srl (sub v16i8:$vA, (v16i8 (bitconvert(vnot v4i32:$vB)))), 1160 (v16i8 (immEQOneV)))), (v16i8 (VAVGUB $vA, $vB))>; 1161 1162} // end HasAltivec 1163 1164// [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set. 1165class VX_VT5_VA5_VB5_PS1_XO9_o<bits<9> xo, string opc, list<dag> pattern> 1166 : VX_RD5_RSp5_PS1_XO9<xo, 1167 (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u1imm:$PS), 1168 !strconcat(opc, " $vD, $vA, $vB, $PS"), IIC_VecFP, pattern> { 1169 let Defs = [CR6]; 1170} 1171 1172// [PO VRT VRA VRB 1 / XO] 1173class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern> 1174 : VX_RD5_RSp5_PS1_XO9<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1175 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern> { 1176 let Defs = [CR6]; 1177 let PS = 0; 1178} 1179 1180def HasP8Altivec : Predicate<"Subtarget->hasP8Altivec()">; 1181def HasP8Crypto : Predicate<"Subtarget->hasP8Crypto()">; 1182let Predicates = [HasP8Altivec] in { 1183 1184let isCommutable = 1 in { 1185def VMULESW : VX1_Int_Ty2<904, "vmulesw", int_ppc_altivec_vmulesw, 1186 v2i64, v4i32>; 1187def VMULEUW : VX1_Int_Ty2<648, "vmuleuw", int_ppc_altivec_vmuleuw, 1188 v2i64, v4i32>; 1189def VMULOSW : VX1_Int_Ty2<392, "vmulosw", int_ppc_altivec_vmulosw, 1190 v2i64, v4i32>; 1191def VMULOUW : VX1_Int_Ty2<136, "vmulouw", int_ppc_altivec_vmulouw, 1192 v2i64, v4i32>; 1193def VMULUWM : VXForm_1<137, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1194 "vmuluwm $vD, $vA, $vB", IIC_VecGeneral, 1195 [(set v4i32:$vD, (mul v4i32:$vA, v4i32:$vB))]>; 1196def VMAXSD : VX1_Int_Ty<450, "vmaxsd", int_ppc_altivec_vmaxsd, v2i64>; 1197def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>; 1198def VMINSD : VX1_Int_Ty<962, "vminsd", int_ppc_altivec_vminsd, v2i64>; 1199def VMINUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>; 1200} // isCommutable 1201 1202// Vector merge 1203def VMRGEW : VXForm_1<1932, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1204 "vmrgew $vD, $vA, $vB", IIC_VecFP, 1205 [(set v16i8:$vD, 1206 (v16i8 (vmrgew_shuffle v16i8:$vA, v16i8:$vB)))]>; 1207def VMRGOW : VXForm_1<1676, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1208 "vmrgow $vD, $vA, $vB", IIC_VecFP, 1209 [(set v16i8:$vD, 1210 (v16i8 (vmrgow_shuffle v16i8:$vA, v16i8:$vB)))]>; 1211 1212// Match vmrgew(x,x) and vmrgow(x,x) 1213def:Pat<(vmrgew_unary_shuffle v16i8:$vA, undef), 1214 (VMRGEW $vA, $vA)>; 1215def:Pat<(vmrgow_unary_shuffle v16i8:$vA, undef), 1216 (VMRGOW $vA, $vA)>; 1217 1218// Match vmrgew(y,x) and vmrgow(y,x), i.e., swapped operands. These fragments 1219// are matched for little-endian, where the inputs must be swapped for correct 1220// semantics.w 1221def:Pat<(vmrgew_swapped_shuffle v16i8:$vA, v16i8:$vB), 1222 (VMRGEW $vB, $vA)>; 1223def:Pat<(vmrgow_swapped_shuffle v16i8:$vA, v16i8:$vB), 1224 (VMRGOW $vB, $vA)>; 1225 1226// Vector rotates. 1227def VRLD : VX1_Int_Ty<196, "vrld", int_ppc_altivec_vrld, v2i64>; 1228 1229def : Pat<(v2i64 (rotl v2i64:$vA, v2i64:$vB)), 1230 (v2i64 (VRLD v2i64:$vA, v2i64:$vB))>; 1231 1232// Vector shifts 1233def VSLD : VXForm_1<1476, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1234 "vsld $vD, $vA, $vB", IIC_VecGeneral, []>; 1235def VSRD : VXForm_1<1732, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1236 "vsrd $vD, $vA, $vB", IIC_VecGeneral, []>; 1237def VSRAD : VXForm_1<964, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1238 "vsrad $vD, $vA, $vB", IIC_VecGeneral, []>; 1239 1240def : Pat<(v2i64 (shl v2i64:$vA, v2i64:$vB)), 1241 (v2i64 (VSLD $vA, $vB))>; 1242def : Pat<(v2i64 (PPCshl v2i64:$vA, v2i64:$vB)), 1243 (v2i64 (VSLD $vA, $vB))>; 1244def : Pat<(v2i64 (srl v2i64:$vA, v2i64:$vB)), 1245 (v2i64 (VSRD $vA, $vB))>; 1246def : Pat<(v2i64 (PPCsrl v2i64:$vA, v2i64:$vB)), 1247 (v2i64 (VSRD $vA, $vB))>; 1248def : Pat<(v2i64 (sra v2i64:$vA, v2i64:$vB)), 1249 (v2i64 (VSRAD $vA, $vB))>; 1250def : Pat<(v2i64 (PPCsra v2i64:$vA, v2i64:$vB)), 1251 (v2i64 (VSRAD $vA, $vB))>; 1252 1253// Vector Integer Arithmetic Instructions 1254let isCommutable = 1 in { 1255def VADDUDM : VXForm_1<192, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1256 "vaddudm $vD, $vA, $vB", IIC_VecGeneral, 1257 [(set v2i64:$vD, (add v2i64:$vA, v2i64:$vB))]>; 1258def VADDUQM : VXForm_1<256, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1259 "vadduqm $vD, $vA, $vB", IIC_VecGeneral, 1260 [(set v1i128:$vD, (add v1i128:$vA, v1i128:$vB))]>; 1261} // isCommutable 1262 1263// Vector Quadword Add 1264def VADDEUQM : VA1a_Int_Ty<60, "vaddeuqm", int_ppc_altivec_vaddeuqm, v1i128>; 1265def VADDCUQ : VX1_Int_Ty<320, "vaddcuq", int_ppc_altivec_vaddcuq, v1i128>; 1266def VADDECUQ : VA1a_Int_Ty<61, "vaddecuq", int_ppc_altivec_vaddecuq, v1i128>; 1267 1268// Vector Doubleword Subtract 1269def VSUBUDM : VXForm_1<1216, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1270 "vsubudm $vD, $vA, $vB", IIC_VecGeneral, 1271 [(set v2i64:$vD, (sub v2i64:$vA, v2i64:$vB))]>; 1272 1273// Vector Quadword Subtract 1274def VSUBUQM : VXForm_1<1280, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1275 "vsubuqm $vD, $vA, $vB", IIC_VecGeneral, 1276 [(set v1i128:$vD, (sub v1i128:$vA, v1i128:$vB))]>; 1277def VSUBEUQM : VA1a_Int_Ty<62, "vsubeuqm", int_ppc_altivec_vsubeuqm, v1i128>; 1278def VSUBCUQ : VX1_Int_Ty<1344, "vsubcuq", int_ppc_altivec_vsubcuq, v1i128>; 1279def VSUBECUQ : VA1a_Int_Ty<63, "vsubecuq", int_ppc_altivec_vsubecuq, v1i128>; 1280 1281// Count Leading Zeros 1282def VCLZB : VXForm_2<1794, (outs vrrc:$vD), (ins vrrc:$vB), 1283 "vclzb $vD, $vB", IIC_VecGeneral, 1284 [(set v16i8:$vD, (ctlz v16i8:$vB))]>; 1285def VCLZH : VXForm_2<1858, (outs vrrc:$vD), (ins vrrc:$vB), 1286 "vclzh $vD, $vB", IIC_VecGeneral, 1287 [(set v8i16:$vD, (ctlz v8i16:$vB))]>; 1288def VCLZW : VXForm_2<1922, (outs vrrc:$vD), (ins vrrc:$vB), 1289 "vclzw $vD, $vB", IIC_VecGeneral, 1290 [(set v4i32:$vD, (ctlz v4i32:$vB))]>; 1291def VCLZD : VXForm_2<1986, (outs vrrc:$vD), (ins vrrc:$vB), 1292 "vclzd $vD, $vB", IIC_VecGeneral, 1293 [(set v2i64:$vD, (ctlz v2i64:$vB))]>; 1294 1295// Population Count 1296def VPOPCNTB : VXForm_2<1795, (outs vrrc:$vD), (ins vrrc:$vB), 1297 "vpopcntb $vD, $vB", IIC_VecGeneral, 1298 [(set v16i8:$vD, (ctpop v16i8:$vB))]>; 1299def VPOPCNTH : VXForm_2<1859, (outs vrrc:$vD), (ins vrrc:$vB), 1300 "vpopcnth $vD, $vB", IIC_VecGeneral, 1301 [(set v8i16:$vD, (ctpop v8i16:$vB))]>; 1302def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB), 1303 "vpopcntw $vD, $vB", IIC_VecGeneral, 1304 [(set v4i32:$vD, (ctpop v4i32:$vB))]>; 1305def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB), 1306 "vpopcntd $vD, $vB", IIC_VecGeneral, 1307 [(set v2i64:$vD, (ctpop v2i64:$vB))]>; 1308 1309let isCommutable = 1 in { 1310// FIXME: Use AddedComplexity > 400 to ensure these patterns match before the 1311// VSX equivalents. We need to fix this up at some point. Two possible 1312// solutions for this problem: 1313// 1. Disable Altivec patterns that compete with VSX patterns using the 1314// !HasVSX predicate. This essentially favours VSX over Altivec, in 1315// hopes of reducing register pressure (larger register set using VSX 1316// instructions than VMX instructions) 1317// 2. Employ a more disciplined use of AddedComplexity, which would provide 1318// more fine-grained control than option 1. This would be beneficial 1319// if we find situations where Altivec is really preferred over VSX. 1320def VEQV : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1321 "veqv $vD, $vA, $vB", IIC_VecGeneral, 1322 [(set v4i32:$vD, (vnot (xor v4i32:$vA, v4i32:$vB)))]>; 1323def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1324 "vnand $vD, $vA, $vB", IIC_VecGeneral, 1325 [(set v4i32:$vD, (vnot (and v4i32:$vA, v4i32:$vB)))]>; 1326} // isCommutable 1327 1328def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1329 "vorc $vD, $vA, $vB", IIC_VecGeneral, 1330 [(set v4i32:$vD, (or v4i32:$vA, 1331 (vnot v4i32:$vB)))]>; 1332 1333// i64 element comparisons. 1334def VCMPEQUD : VCMP <199, "vcmpequd $vD, $vA, $vB" , v2i64>; 1335def VCMPEQUD_rec : VCMP_rec<199, "vcmpequd. $vD, $vA, $vB", v2i64>; 1336def VCMPGTSD : VCMP <967, "vcmpgtsd $vD, $vA, $vB" , v2i64>; 1337def VCMPGTSD_rec : VCMP_rec<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>; 1338def VCMPGTUD : VCMP <711, "vcmpgtud $vD, $vA, $vB" , v2i64>; 1339def VCMPGTUD_rec : VCMP_rec<711, "vcmpgtud. $vD, $vA, $vB", v2i64>; 1340 1341// The cryptography instructions that do not require Category:Vector.Crypto 1342def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb", 1343 int_ppc_altivec_crypto_vpmsumb, v16i8>; 1344def VPMSUMH : VX1_Int_Ty<1096, "vpmsumh", 1345 int_ppc_altivec_crypto_vpmsumh, v8i16>; 1346def VPMSUMW : VX1_Int_Ty<1160, "vpmsumw", 1347 int_ppc_altivec_crypto_vpmsumw, v4i32>; 1348def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd", 1349 int_ppc_altivec_crypto_vpmsumd, v2i64>; 1350def VPERMXOR : VAForm_1<45, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB, vrrc:$VC), 1351 "vpermxor $VD, $VA, $VB, $VC", IIC_VecFP, []>; 1352 1353// Vector doubleword integer pack and unpack. 1354let hasSideEffects = 1 in { 1355 def VPKSDSS : VX1_Int_Ty2<1486, "vpksdss", int_ppc_altivec_vpksdss, 1356 v4i32, v2i64>; 1357 def VPKSDUS : VX1_Int_Ty2<1358, "vpksdus", int_ppc_altivec_vpksdus, 1358 v4i32, v2i64>; 1359 def VPKUDUS : VX1_Int_Ty2<1230, "vpkudus", int_ppc_altivec_vpkudus, 1360 v4i32, v2i64>; 1361} 1362def VPKUDUM : VXForm_1<1102, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1363 "vpkudum $vD, $vA, $vB", IIC_VecFP, 1364 [(set v16i8:$vD, 1365 (vpkudum_shuffle v16i8:$vA, v16i8:$vB))]>; 1366def VUPKHSW : VX2_Int_Ty2<1614, "vupkhsw", int_ppc_altivec_vupkhsw, 1367 v2i64, v4i32>; 1368def VUPKLSW : VX2_Int_Ty2<1742, "vupklsw", int_ppc_altivec_vupklsw, 1369 v2i64, v4i32>; 1370def BCDADD_rec : VX_VT5_VA5_VB5_PS1_XO9_o<1, "bcdadd." , []>; 1371def BCDSUB_rec : VX_VT5_VA5_VB5_PS1_XO9_o<65, "bcdsub." , []>; 1372 1373def : Pat<(v16i8 (int_ppc_bcdadd v16i8:$vA, v16i8:$vB, timm:$PS)), 1374 (BCDADD_rec $vA, $vB, $PS)>; 1375def : Pat<(v16i8 (int_ppc_bcdsub v16i8:$vA, v16i8:$vB, timm:$PS)), 1376 (BCDSUB_rec $vA, $vB, $PS)>; 1377 1378// Shuffle patterns for unary and swapped (LE) vector pack modulo. 1379def:Pat<(vpkudum_unary_shuffle v16i8:$vA, undef), 1380 (VPKUDUM $vA, $vA)>; 1381def:Pat<(vpkudum_swapped_shuffle v16i8:$vA, v16i8:$vB), 1382 (VPKUDUM $vB, $vA)>; 1383 1384def VGBBD : VX2_Int_Ty2<1292, "vgbbd", int_ppc_altivec_vgbbd, v16i8, v16i8>; 1385def VBPERMQ : VX1_Int_Ty2<1356, "vbpermq", int_ppc_altivec_vbpermq, 1386 v2i64, v16i8>; 1387} // end HasP8Altivec 1388 1389// Crypto instructions (from builtins) 1390let Predicates = [HasP8Crypto] in { 1391def VSHASIGMAW : VXCR_Int_Ty<1666, "vshasigmaw", 1392 int_ppc_altivec_crypto_vshasigmaw, v4i32>; 1393def VSHASIGMAD : VXCR_Int_Ty<1730, "vshasigmad", 1394 int_ppc_altivec_crypto_vshasigmad, v2i64>; 1395def VCIPHER : VX1_Int_Ty<1288, "vcipher", int_ppc_altivec_crypto_vcipher, 1396 v2i64>; 1397def VCIPHERLAST : VX1_Int_Ty<1289, "vcipherlast", 1398 int_ppc_altivec_crypto_vcipherlast, v2i64>; 1399def VNCIPHER : VX1_Int_Ty<1352, "vncipher", 1400 int_ppc_altivec_crypto_vncipher, v2i64>; 1401def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast", 1402 int_ppc_altivec_crypto_vncipherlast, v2i64>; 1403def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>; 1404} // HasP8Crypto 1405 1406// The following altivec instructions were introduced in Power ISA 3.0 1407def HasP9Altivec : Predicate<"Subtarget->hasP9Altivec()">; 1408let Predicates = [HasP9Altivec] in { 1409 1410// Vector Multiply-Sum 1411def VMSUMUDM : VA1a_Int_Ty3<35, "vmsumudm", int_ppc_altivec_vmsumudm, 1412 v1i128, v2i64, v1i128>; 1413 1414// i8 element comparisons. 1415def VCMPNEB : VCMP < 7, "vcmpneb $vD, $vA, $vB" , v16i8>; 1416def VCMPNEB_rec : VCMP_rec < 7, "vcmpneb. $vD, $vA, $vB" , v16i8>; 1417def VCMPNEZB : VCMP <263, "vcmpnezb $vD, $vA, $vB" , v16i8>; 1418def VCMPNEZB_rec : VCMP_rec<263, "vcmpnezb. $vD, $vA, $vB", v16i8>; 1419 1420// i16 element comparisons. 1421def VCMPNEH : VCMP < 71, "vcmpneh $vD, $vA, $vB" , v8i16>; 1422def VCMPNEH_rec : VCMP_rec< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>; 1423def VCMPNEZH : VCMP <327, "vcmpnezh $vD, $vA, $vB" , v8i16>; 1424def VCMPNEZH_rec : VCMP_rec<327, "vcmpnezh. $vD, $vA, $vB", v8i16>; 1425 1426// i32 element comparisons. 1427def VCMPNEW : VCMP <135, "vcmpnew $vD, $vA, $vB" , v4i32>; 1428def VCMPNEW_rec : VCMP_rec<135, "vcmpnew. $vD, $vA, $vB" , v4i32>; 1429def VCMPNEZW : VCMP <391, "vcmpnezw $vD, $vA, $vB" , v4i32>; 1430def VCMPNEZW_rec : VCMP_rec<391, "vcmpnezw. $vD, $vA, $vB", v4i32>; 1431 1432// VX-Form: [PO VRT / UIM VRB XO]. 1433// We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent 1434// "/ UIM" (1 + 4 bit) 1435class VX1_VT5_UIM5_VB5<bits<11> xo, string opc, list<dag> pattern> 1436 : VXForm_1<xo, (outs vrrc:$vD), (ins u4imm:$UIMM, vrrc:$vB), 1437 !strconcat(opc, " $vD, $vB, $UIMM"), IIC_VecGeneral, pattern>; 1438 1439class VX1_RT5_RA5_VB5<bits<11> xo, string opc, list<dag> pattern> 1440 : VXForm_1<xo, (outs g8rc:$rD), (ins g8rc:$rA, vrrc:$vB), 1441 !strconcat(opc, " $rD, $rA, $vB"), IIC_VecGeneral, pattern>; 1442 1443// Vector Extract Unsigned 1444def VEXTRACTUB : VX1_VT5_UIM5_VB5<525, "vextractub", []>; 1445def VEXTRACTUH : VX1_VT5_UIM5_VB5<589, "vextractuh", []>; 1446def VEXTRACTUW : VX1_VT5_UIM5_VB5<653, "vextractuw", []>; 1447def VEXTRACTD : VX1_VT5_UIM5_VB5<717, "vextractd" , []>; 1448 1449// Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed 1450let hasSideEffects = 0 in { 1451def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>; 1452def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>; 1453def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>; 1454def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>; 1455def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>; 1456def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>; 1457} 1458 1459// Vector Insert Element Instructions 1460def VINSERTB : VXForm_1<781, (outs vrrc:$vD), 1461 (ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB), 1462 "vinsertb $vD, $vB, $UIM", IIC_VecGeneral, 1463 [(set v16i8:$vD, (PPCvecinsert v16i8:$vDi, v16i8:$vB, 1464 imm32SExt16:$UIM))]>, 1465 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1466def VINSERTH : VXForm_1<845, (outs vrrc:$vD), 1467 (ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB), 1468 "vinserth $vD, $vB, $UIM", IIC_VecGeneral, 1469 [(set v8i16:$vD, (PPCvecinsert v8i16:$vDi, v8i16:$vB, 1470 imm32SExt16:$UIM))]>, 1471 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1472def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>; 1473def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>; 1474 1475class VX_VT5_EO5_VB5<bits<11> xo, bits<5> eo, string opc, list<dag> pattern> 1476 : VXForm_RD5_XO5_RS5<xo, eo, (outs vrrc:$vD), (ins vrrc:$vB), 1477 !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>; 1478class VX_VT5_EO5_VB5s<bits<11> xo, bits<5> eo, string opc, list<dag> pattern> 1479 : VXForm_RD5_XO5_RS5<xo, eo, (outs vfrc:$vD), (ins vfrc:$vB), 1480 !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>; 1481 1482// Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD] 1483def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs gprc:$rD), (ins vrrc:$vB), 1484 "vclzlsbb $rD, $vB", IIC_VecGeneral, 1485 [(set i32:$rD, (int_ppc_altivec_vclzlsbb 1486 v16i8:$vB))]>; 1487def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs gprc:$rD), (ins vrrc:$vB), 1488 "vctzlsbb $rD, $vB", IIC_VecGeneral, 1489 [(set i32:$rD, (int_ppc_altivec_vctzlsbb 1490 v16i8:$vB))]>; 1491// Vector Count Trailing Zeros 1492def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb", 1493 [(set v16i8:$vD, (cttz v16i8:$vB))]>; 1494def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh", 1495 [(set v8i16:$vD, (cttz v8i16:$vB))]>; 1496def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw", 1497 [(set v4i32:$vD, (cttz v4i32:$vB))]>; 1498def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd", 1499 [(set v2i64:$vD, (cttz v2i64:$vB))]>; 1500 1501// Vector Extend Sign 1502def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", 1503 [(set v4i32:$vD, (int_ppc_altivec_vextsb2w v16i8:$vB))]>; 1504def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w", 1505 [(set v4i32:$vD, (int_ppc_altivec_vextsh2w v8i16:$vB))]>; 1506def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d", 1507 [(set v2i64:$vD, (int_ppc_altivec_vextsb2d v16i8:$vB))]>; 1508def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d", 1509 [(set v2i64:$vD, (int_ppc_altivec_vextsh2d v8i16:$vB))]>; 1510def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d", 1511 [(set v2i64:$vD, (int_ppc_altivec_vextsw2d v4i32:$vB))]>; 1512let isCodeGenOnly = 1 in { 1513 def VEXTSB2Ws : VX_VT5_EO5_VB5s<1538, 16, "vextsb2w", []>; 1514 def VEXTSH2Ws : VX_VT5_EO5_VB5s<1538, 17, "vextsh2w", []>; 1515 def VEXTSB2Ds : VX_VT5_EO5_VB5s<1538, 24, "vextsb2d", []>; 1516 def VEXTSH2Ds : VX_VT5_EO5_VB5s<1538, 25, "vextsh2d", []>; 1517 def VEXTSW2Ds : VX_VT5_EO5_VB5s<1538, 26, "vextsw2d", []>; 1518} 1519 1520def : Pat<(v4i32 (sext_inreg v4i32:$VRB, v4i8)), (v4i32 (VEXTSB2W $VRB))>; 1521def : Pat<(v4i32 (sext_inreg v4i32:$VRB, v4i16)), (v4i32 (VEXTSH2W $VRB))>; 1522def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i8)), (v2i64 (VEXTSB2D $VRB))>; 1523def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i16)), (v2i64 (VEXTSH2D $VRB))>; 1524def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i32)), (v2i64 (VEXTSW2D $VRB))>; 1525 1526// Vector Integer Negate 1527def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw", 1528 [(set v4i32:$vD, 1529 (sub (v4i32 immAllZerosV), v4i32:$vB))]>; 1530 1531def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", 1532 [(set v2i64:$vD, 1533 (sub (v2i64 immAllZerosV), v2i64:$vB))]>; 1534 1535// Vector Parity Byte 1536def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$vD, 1537 (int_ppc_altivec_vprtybw v4i32:$vB))]>; 1538def VPRTYBD : VX_VT5_EO5_VB5<1538, 9, "vprtybd", [(set v2i64:$vD, 1539 (int_ppc_altivec_vprtybd v2i64:$vB))]>; 1540def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", [(set v1i128:$vD, 1541 (int_ppc_altivec_vprtybq v1i128:$vB))]>; 1542 1543// Vector (Bit) Permute (Right-indexed) 1544def VBPERMD : VX1_Int_Ty3<1484, "vbpermd", int_ppc_altivec_vbpermd, 1545 v2i64, v2i64, v16i8>; 1546def VPERMR : VAForm_1a<59, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 1547 "vpermr $vD, $vA, $vB, $vC", IIC_VecFP, []>; 1548 1549class VX1_VT5_VA5_VB5<bits<11> xo, string opc, list<dag> pattern> 1550 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1551 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern>; 1552 1553// Vector Rotate Left Mask/Mask-Insert 1554def VRLWNM : VX1_VT5_VA5_VB5<389, "vrlwnm", 1555 [(set v4i32:$vD, 1556 (int_ppc_altivec_vrlwnm v4i32:$vA, 1557 v4i32:$vB))]>; 1558def VRLWMI : VXForm_1<133, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), 1559 "vrlwmi $vD, $vA, $vB", IIC_VecFP, 1560 [(set v4i32:$vD, 1561 (int_ppc_altivec_vrlwmi v4i32:$vA, v4i32:$vB, 1562 v4i32:$vDi))]>, 1563 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1564def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm", 1565 [(set v2i64:$vD, 1566 (int_ppc_altivec_vrldnm v2i64:$vA, 1567 v2i64:$vB))]>; 1568def VRLDMI : VXForm_1<197, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), 1569 "vrldmi $vD, $vA, $vB", IIC_VecFP, 1570 [(set v2i64:$vD, 1571 (int_ppc_altivec_vrldmi v2i64:$vA, v2i64:$vB, 1572 v2i64:$vDi))]>, 1573 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1574 1575// Vector Shift Left/Right 1576def VSLV : VX1_VT5_VA5_VB5<1860, "vslv", 1577 [(set v16i8 : $vD, (int_ppc_altivec_vslv v16i8 : $vA, v16i8 : $vB))]>; 1578def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv", 1579 [(set v16i8 : $vD, (int_ppc_altivec_vsrv v16i8 : $vA, v16i8 : $vB))]>; 1580 1581// Vector Multiply-by-10 (& Write Carry) Unsigned Quadword 1582def VMUL10UQ : VXForm_BX<513, (outs vrrc:$vD), (ins vrrc:$vA), 1583 "vmul10uq $vD, $vA", IIC_VecFP, []>; 1584def VMUL10CUQ : VXForm_BX< 1, (outs vrrc:$vD), (ins vrrc:$vA), 1585 "vmul10cuq $vD, $vA", IIC_VecFP, []>; 1586 1587// Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword 1588def VMUL10EUQ : VX1_VT5_VA5_VB5<577, "vmul10euq" , []>; 1589def VMUL10ECUQ : VX1_VT5_VA5_VB5< 65, "vmul10ecuq", []>; 1590 1591// Decimal Integer Format Conversion Instructions 1592 1593// [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set. 1594class VX_VT5_EO5_VB5_PS1_XO9_o<bits<5> eo, bits<9> xo, string opc, 1595 list<dag> pattern> 1596 : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB, u1imm:$PS), 1597 !strconcat(opc, " $vD, $vB, $PS"), IIC_VecFP, pattern> { 1598 let Defs = [CR6]; 1599} 1600 1601// [PO VRT EO VRB 1 / XO] 1602class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc, 1603 list<dag> pattern> 1604 : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB), 1605 !strconcat(opc, " $vD, $vB"), IIC_VecFP, pattern> { 1606 let Defs = [CR6]; 1607 let PS = 0; 1608} 1609 1610// Decimal Convert From/to National/Zoned/Signed-QWord 1611def BCDCFN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." , []>; 1612def BCDCFZ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , []>; 1613def BCDCTN_rec : VX_VT5_EO5_VB5_XO9_o <5, 385, "bcdctn." , []>; 1614def BCDCTZ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." , []>; 1615def BCDCFSQ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>; 1616def BCDCTSQ_rec : VX_VT5_EO5_VB5_XO9_o <0, 385, "bcdctsq.", []>; 1617 1618// Decimal Copy-Sign/Set-Sign 1619let Defs = [CR6] in 1620def BCDCPSGN_rec : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>; 1621 1622def BCDSETSGN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", []>; 1623 1624// Decimal Shift/Unsigned-Shift/Shift-and-Round 1625def BCDS_rec : VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>; 1626def BCDUS_rec : VX_VT5_VA5_VB5_XO9_o <129, "bcdus.", []>; 1627def BCDSR_rec : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>; 1628 1629// Decimal (Unsigned) Truncate 1630def BCDTRUNC_rec : VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>; 1631def BCDUTRUNC_rec : VX_VT5_VA5_VB5_XO9_o <321, "bcdutrunc.", []>; 1632 1633// Absolute Difference 1634def VABSDUB : VXForm_1<1027, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1635 "vabsdub $vD, $vA, $vB", IIC_VecGeneral, 1636 [(set v16i8:$vD, (int_ppc_altivec_vabsdub v16i8:$vA, v16i8:$vB))]>; 1637def VABSDUH : VXForm_1<1091, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1638 "vabsduh $vD, $vA, $vB", IIC_VecGeneral, 1639 [(set v8i16:$vD, (int_ppc_altivec_vabsduh v8i16:$vA, v8i16:$vB))]>; 1640def VABSDUW : VXForm_1<1155, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1641 "vabsduw $vD, $vA, $vB", IIC_VecGeneral, 1642 [(set v4i32:$vD, (int_ppc_altivec_vabsduw v4i32:$vA, v4i32:$vB))]>; 1643 1644} // end HasP9Altivec 1645