1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// 11// PowerPC instruction formats 12 13class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 14 : Instruction { 15 field bits<32> Inst; 16 field bits<32> SoftFail = 0; 17 let Size = 4; 18 19 bit PPC64 = 0; // Default value, override with isPPC64 20 21 let Namespace = "PPC"; 22 let Inst{0-5} = opcode; 23 let OutOperandList = OOL; 24 let InOperandList = IOL; 25 let AsmString = asmstr; 26 let Itinerary = itin; 27 28 bits<1> PPC970_First = 0; 29 bits<1> PPC970_Single = 0; 30 bits<1> PPC970_Cracked = 0; 31 bits<3> PPC970_Unit = 0; 32 33 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 34 /// these must be reflected there! See comments there for what these are. 35 let TSFlags{0} = PPC970_First; 36 let TSFlags{1} = PPC970_Single; 37 let TSFlags{2} = PPC970_Cracked; 38 let TSFlags{5-3} = PPC970_Unit; 39 40 // Indicate that this instruction is of type X-Form Load or Store 41 bits<1> XFormMemOp = 0; 42 let TSFlags{6} = XFormMemOp; 43 44 // Indicate that this instruction is prefixed. 45 bits<1> Prefixed = 0; 46 let TSFlags{7} = Prefixed; 47 48 // Fields used for relation models. 49 string BaseName = ""; 50 51 // For cases where multiple instruction definitions really represent the 52 // same underlying instruction but with one definition for 64-bit arguments 53 // and one for 32-bit arguments, this bit breaks the degeneracy between 54 // the two forms and allows TableGen to generate mapping tables. 55 bit Interpretation64Bit = 0; 56} 57 58class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 59class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 60class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 61class PPC970_MicroCode; 62 63class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 64class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 65class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 66class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 67class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 68class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 69class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 70class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 71 72class XFormMemOp { bits<1> XFormMemOp = 1; } 73 74// Two joined instructions; used to emit two adjacent instructions as one. 75// The itinerary from the first instruction is used for scheduling and 76// classification. 77class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 78 InstrItinClass itin> 79 : Instruction { 80 field bits<64> Inst; 81 field bits<64> SoftFail = 0; 82 let Size = 8; 83 84 bit PPC64 = 0; // Default value, override with isPPC64 85 86 let Namespace = "PPC"; 87 let Inst{0-5} = opcode1; 88 let Inst{32-37} = opcode2; 89 let OutOperandList = OOL; 90 let InOperandList = IOL; 91 let AsmString = asmstr; 92 let Itinerary = itin; 93 94 bits<1> PPC970_First = 0; 95 bits<1> PPC970_Single = 0; 96 bits<1> PPC970_Cracked = 0; 97 bits<3> PPC970_Unit = 0; 98 99 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 100 /// these must be reflected there! See comments there for what these are. 101 let TSFlags{0} = PPC970_First; 102 let TSFlags{1} = PPC970_Single; 103 let TSFlags{2} = PPC970_Cracked; 104 let TSFlags{5-3} = PPC970_Unit; 105 106 // Fields used for relation models. 107 string BaseName = ""; 108 bit Interpretation64Bit = 0; 109} 110 111// Base class for all X-Form memory instructions 112class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr, 113 InstrItinClass itin> 114 :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp; 115 116// 1.7.1 I-Form 117class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 118 InstrItinClass itin, list<dag> pattern> 119 : I<opcode, OOL, IOL, asmstr, itin> { 120 let Pattern = pattern; 121 bits<24> LI; 122 123 let Inst{6-29} = LI; 124 let Inst{30} = aa; 125 let Inst{31} = lk; 126} 127 128// 1.7.2 B-Form 129class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 130 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 131 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 132 bits<3> CR; 133 bits<14> BD; 134 135 bits<5> BI; 136 let BI{0-1} = BIBO{5-6}; 137 let BI{2-4} = CR{0-2}; 138 139 let Inst{6-10} = BIBO{4-0}; 140 let Inst{11-15} = BI; 141 let Inst{16-29} = BD; 142 let Inst{30} = aa; 143 let Inst{31} = lk; 144} 145 146class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 147 string asmstr> 148 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 149 let BIBO{4-0} = bo; 150 let BIBO{6-5} = 0; 151 let CR = 0; 152} 153 154class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 155 dag OOL, dag IOL, string asmstr> 156 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 157 bits<14> BD; 158 159 let Inst{6-10} = bo; 160 let Inst{11-15} = bi; 161 let Inst{16-29} = BD; 162 let Inst{30} = aa; 163 let Inst{31} = lk; 164} 165 166class BForm_3<bits<6> opcode, bit aa, bit lk, 167 dag OOL, dag IOL, string asmstr> 168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 169 bits<5> BO; 170 bits<5> BI; 171 bits<14> BD; 172 173 let Inst{6-10} = BO; 174 let Inst{11-15} = BI; 175 let Inst{16-29} = BD; 176 let Inst{30} = aa; 177 let Inst{31} = lk; 178} 179 180class BForm_3_at<bits<6> opcode, bit aa, bit lk, 181 dag OOL, dag IOL, string asmstr> 182 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 183 bits<5> BO; 184 bits<2> at; 185 bits<5> BI; 186 bits<14> BD; 187 188 let Inst{6-8} = BO{4-2}; 189 let Inst{9-10} = at; 190 let Inst{11-15} = BI; 191 let Inst{16-29} = BD; 192 let Inst{30} = aa; 193 let Inst{31} = lk; 194} 195 196class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 197 dag OOL, dag IOL, string asmstr> 198 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 199 bits<5> BI; 200 bits<14> BD; 201 202 let Inst{6-10} = bo; 203 let Inst{11-15} = BI; 204 let Inst{16-29} = BD; 205 let Inst{30} = aa; 206 let Inst{31} = lk; 207} 208 209// 1.7.3 SC-Form 210class SCForm<bits<6> opcode, bits<1> xo, 211 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 212 list<dag> pattern> 213 : I<opcode, OOL, IOL, asmstr, itin> { 214 bits<7> LEV; 215 216 let Pattern = pattern; 217 218 let Inst{20-26} = LEV; 219 let Inst{30} = xo; 220} 221 222// 1.7.4 D-Form 223class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 224 InstrItinClass itin, list<dag> pattern> 225 : I<opcode, OOL, IOL, asmstr, itin> { 226 bits<5> A; 227 bits<5> B; 228 bits<16> C; 229 230 let Pattern = pattern; 231 232 let Inst{6-10} = A; 233 let Inst{11-15} = B; 234 let Inst{16-31} = C; 235} 236 237class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 238 InstrItinClass itin, list<dag> pattern> 239 : I<opcode, OOL, IOL, asmstr, itin> { 240 bits<5> A; 241 bits<21> Addr; 242 243 let Pattern = pattern; 244 245 let Inst{6-10} = A; 246 let Inst{11-15} = Addr{20-16}; // Base Reg 247 let Inst{16-31} = Addr{15-0}; // Displacement 248} 249 250class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 251 InstrItinClass itin, list<dag> pattern> 252 : I<opcode, OOL, IOL, asmstr, itin> { 253 bits<5> A; 254 bits<16> C; 255 bits<5> B; 256 257 let Pattern = pattern; 258 259 let Inst{6-10} = A; 260 let Inst{11-15} = B; 261 let Inst{16-31} = C; 262} 263 264 265class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 266 InstrItinClass itin, list<dag> pattern> 267 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 268 269 // Even though ADDIC_rec does not really have an RC bit, provide 270 // the declaration of one here so that isRecordForm has something to set. 271 bit RC = 0; 272} 273 274class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 275 InstrItinClass itin, list<dag> pattern> 276 : I<opcode, OOL, IOL, asmstr, itin> { 277 bits<5> A; 278 bits<16> B; 279 280 let Pattern = pattern; 281 282 let Inst{6-10} = A; 283 let Inst{11-15} = 0; 284 let Inst{16-31} = B; 285} 286 287class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 288 InstrItinClass itin, list<dag> pattern> 289 : I<opcode, OOL, IOL, asmstr, itin> { 290 bits<5> B; 291 bits<5> A; 292 bits<16> C; 293 294 let Pattern = pattern; 295 296 let Inst{6-10} = A; 297 let Inst{11-15} = B; 298 let Inst{16-31} = C; 299} 300 301class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 302 InstrItinClass itin, list<dag> pattern> 303 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 304 let A = 0; 305 let Addr = 0; 306} 307 308class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 309 string asmstr, InstrItinClass itin, 310 list<dag> pattern> 311 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 312 let A = R; 313 let B = R; 314 let C = 0; 315} 316 317class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 318 dag OOL, dag IOL, string asmstr, 319 InstrItinClass itin, list<dag> pattern> 320 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 321 bits<5> A; 322 bits<21> Addr; 323 324 let Pattern = pattern; 325 bits<24> LI; 326 327 let Inst{6-29} = LI; 328 let Inst{30} = aa; 329 let Inst{31} = lk; 330 331 let Inst{38-42} = A; 332 let Inst{43-47} = Addr{20-16}; // Base Reg 333 let Inst{48-63} = Addr{15-0}; // Displacement 334} 335 336// This is used to emit BL8+NOP. 337class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 338 dag OOL, dag IOL, string asmstr, 339 InstrItinClass itin, list<dag> pattern> 340 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 341 OOL, IOL, asmstr, itin, pattern> { 342 let A = 0; 343 let Addr = 0; 344} 345 346class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 347 InstrItinClass itin> 348 : I<opcode, OOL, IOL, asmstr, itin> { 349 bits<3> BF; 350 bits<1> L; 351 bits<5> RA; 352 bits<16> I; 353 354 let Inst{6-8} = BF; 355 let Inst{9} = 0; 356 let Inst{10} = L; 357 let Inst{11-15} = RA; 358 let Inst{16-31} = I; 359} 360 361class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 362 InstrItinClass itin> 363 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 364 let L = PPC64; 365} 366 367class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 368 InstrItinClass itin> 369 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 370 371class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 372 InstrItinClass itin> 373 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 374 let L = PPC64; 375} 376 377 378// 1.7.5 DS-Form 379class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 380 InstrItinClass itin, list<dag> pattern> 381 : I<opcode, OOL, IOL, asmstr, itin> { 382 bits<5> RST; 383 bits<19> DS_RA; 384 385 let Pattern = pattern; 386 387 let Inst{6-10} = RST; 388 let Inst{11-15} = DS_RA{18-14}; // Register # 389 let Inst{16-29} = DS_RA{13-0}; // Displacement. 390 let Inst{30-31} = xo; 391} 392 393// ISA V3.0B 1.6.6 DX-Form 394class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 395 InstrItinClass itin, list<dag> pattern> 396 : I<opcode, OOL, IOL, asmstr, itin> { 397 bits<5> RT; 398 bits<16> D; 399 400 let Pattern = pattern; 401 402 let Inst{6-10} = RT; 403 let Inst{11-15} = D{5-1}; // d1 404 let Inst{16-25} = D{15-6}; // d0 405 let Inst{26-30} = xo; 406 let Inst{31} = D{0}; // d2 407} 408 409// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO] 410class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 411 string asmstr, InstrItinClass itin, list<dag> pattern> 412 : I<opcode, OOL, IOL, asmstr, itin> { 413 bits<6> XT; 414 bits<17> DS_RA; 415 416 let Pattern = pattern; 417 418 let Inst{6-10} = XT{4-0}; 419 let Inst{11-15} = DS_RA{16-12}; // Register # 420 let Inst{16-27} = DS_RA{11-0}; // Displacement. 421 let Inst{28} = XT{5}; 422 let Inst{29-31} = xo; 423} 424 425class DQForm_RTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 426 string asmstr, InstrItinClass itin, 427 list<dag> pattern> 428 : I<opcode, OOL, IOL, asmstr, itin> { 429 bits<5> RTp; 430 bits<17> DQ_RA; 431 let Pattern = pattern; 432 433 let Inst{6-10} = RTp{4-0}; 434 let Inst{11-15} = DQ_RA{16-12}; // Register # 435 let Inst{16-27} = DQ_RA{11-0}; // Displacement. 436 let Inst{28-31} = xo; 437} 438 439// 1.7.6 X-Form 440class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 441 InstrItinClass itin, list<dag> pattern> 442 : I<opcode, OOL, IOL, asmstr, itin> { 443 bits<5> RST; 444 bits<5> A; 445 bits<5> B; 446 447 let Pattern = pattern; 448 449 bit RC = 0; // set by isRecordForm 450 451 let Inst{6-10} = RST; 452 let Inst{11-15} = A; 453 let Inst{16-20} = B; 454 let Inst{21-30} = xo; 455 let Inst{31} = RC; 456} 457 458class XForm_base_r3xo_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 459 string asmstr, InstrItinClass itin, 460 list<dag> pattern> 461 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 462 463class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 464 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 465 let RST = 0; 466} 467 468class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 469 InstrItinClass itin> 470 : I<opcode, OOL, IOL, asmstr, itin> { 471 let Inst{21-30} = xo; 472} 473 474// This is the same as XForm_base_r3xo, but the first two operands are swapped 475// when code is emitted. 476class XForm_base_r3xo_swapped 477 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 478 InstrItinClass itin> 479 : I<opcode, OOL, IOL, asmstr, itin> { 480 bits<5> A; 481 bits<5> RST; 482 bits<5> B; 483 484 bit RC = 0; // set by isRecordForm 485 486 let Inst{6-10} = RST; 487 let Inst{11-15} = A; 488 let Inst{16-20} = B; 489 let Inst{21-30} = xo; 490 let Inst{31} = RC; 491} 492 493 494class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 495 InstrItinClass itin, list<dag> pattern> 496 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 497 498class XForm_1_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 499 InstrItinClass itin, list<dag> pattern> 500 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 501 502class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 503 InstrItinClass itin, list<dag> pattern> 504 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 505 let RST = 0; 506} 507 508class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 509 InstrItinClass itin, list<dag> pattern> 510 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 511 let A = 0; 512 let B = 0; 513} 514 515class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 516 InstrItinClass itin, list<dag> pattern> 517 : I<opcode, OOL, IOL, asmstr, itin> { 518 bits<5> RST; 519 bits<5> A; 520 bits<1> WS; 521 522 let Pattern = pattern; 523 524 let Inst{6-10} = RST; 525 let Inst{11-15} = A; 526 let Inst{20} = WS; 527 let Inst{21-30} = xo; 528 let Inst{31} = 0; 529} 530 531class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 532 InstrItinClass itin, list<dag> pattern> 533 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 534 let Pattern = pattern; 535} 536 537class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 538 InstrItinClass itin, list<dag> pattern> 539 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 540 541class XForm_8_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 542 InstrItinClass itin, list<dag> pattern> 543 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 544 545class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 546 InstrItinClass itin, list<dag> pattern> 547 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 548 let Pattern = pattern; 549} 550 551class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 552 InstrItinClass itin, list<dag> pattern> 553 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 554 let B = 0; 555 let Pattern = pattern; 556} 557 558class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 559 InstrItinClass itin> 560 : I<opcode, OOL, IOL, asmstr, itin> { 561 bits<3> BF; 562 bits<1> L; 563 bits<5> RA; 564 bits<5> RB; 565 566 let Inst{6-8} = BF; 567 let Inst{9} = 0; 568 let Inst{10} = L; 569 let Inst{11-15} = RA; 570 let Inst{16-20} = RB; 571 let Inst{21-30} = xo; 572 let Inst{31} = 0; 573} 574 575class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 576 InstrItinClass itin> 577 : I<opcode, OOL, IOL, asmstr, itin> { 578 bits<4> CT; 579 bits<5> RA; 580 bits<5> RB; 581 582 let Inst{6} = 0; 583 let Inst{7-10} = CT; 584 let Inst{11-15} = RA; 585 let Inst{16-20} = RB; 586 let Inst{21-30} = xo; 587 let Inst{31} = 0; 588} 589 590class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 591 InstrItinClass itin> 592 : I<opcode, OOL, IOL, asmstr, itin> { 593 bits<5> RS; 594 bits<4> SR; 595 596 let Inst{6-10} = RS; 597 let Inst{12-15} = SR; 598 let Inst{21-30} = xo; 599} 600 601class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 602 InstrItinClass itin> 603 : I<opcode, OOL, IOL, asmstr, itin> { 604 bits<5> MO; 605 606 let Inst{6-10} = MO; 607 let Inst{21-30} = xo; 608} 609 610class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 611 InstrItinClass itin> 612 : I<opcode, OOL, IOL, asmstr, itin> { 613 bits<5> RS; 614 bits<5> RB; 615 616 let Inst{6-10} = RS; 617 let Inst{16-20} = RB; 618 let Inst{21-30} = xo; 619} 620 621class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 622 InstrItinClass itin> 623 : I<opcode, OOL, IOL, asmstr, itin> { 624 bits<5> RS; 625 bits<1> L; 626 627 let Inst{6-10} = RS; 628 let Inst{15} = L; 629 let Inst{21-30} = xo; 630} 631 632class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 633 InstrItinClass itin> 634 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 635 let L = PPC64; 636} 637 638class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 639 InstrItinClass itin> 640 : I<opcode, OOL, IOL, asmstr, itin> { 641 bits<3> BF; 642 bits<5> FRA; 643 bits<5> FRB; 644 645 let Inst{6-8} = BF; 646 let Inst{9-10} = 0; 647 let Inst{11-15} = FRA; 648 let Inst{16-20} = FRB; 649 let Inst{21-30} = xo; 650 let Inst{31} = 0; 651} 652 653class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 654 InstrItinClass itin, list<dag> pattern> 655 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin > { 656 let FRA = 0; 657 let Pattern = pattern; 658} 659 660class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 661 InstrItinClass itin, list<dag> pattern> 662 : I<opcode, OOL, IOL, asmstr, itin> { 663 bits<5> FRT; 664 bits<5> FRA; 665 bits<5> FRB; 666 667 let Pattern = pattern; 668 669 let Inst{6-10} = FRT; 670 let Inst{11-15} = FRA; 671 let Inst{16-20} = FRB; 672 let Inst{21-30} = xo; 673 let Inst{31} = 0; 674} 675 676class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 677 InstrItinClass itin, list<dag> pattern> 678 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 679 let FRA = 0; 680} 681 682class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr, 683 InstrItinClass itin, list<dag> pattern> 684 : I<opcode, OOL, IOL, asmstr, itin> { 685 bits<5> FRT; 686 bits<5> FRA; 687 bits<5> FRB; 688 bits<4> tttt; 689 690 let Pattern = pattern; 691 692 let Inst{6-10} = FRT; 693 let Inst{11-15} = FRA; 694 let Inst{16-20} = FRB; 695 let Inst{21-24} = tttt; 696 let Inst{25-30} = xo; 697 let Inst{31} = 0; 698} 699 700class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 701 InstrItinClass itin, list<dag> pattern> 702 : I<opcode, OOL, IOL, asmstr, itin> { 703 let Pattern = pattern; 704 let Inst{6-10} = 31; 705 let Inst{11-15} = 0; 706 let Inst{16-20} = 0; 707 let Inst{21-30} = xo; 708 let Inst{31} = 0; 709} 710 711class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 712 string asmstr, InstrItinClass itin, list<dag> pattern> 713 : I<opcode, OOL, IOL, asmstr, itin> { 714 bits<2> L; 715 716 let Pattern = pattern; 717 let Inst{6-8} = 0; 718 let Inst{9-10} = L; 719 let Inst{11-15} = 0; 720 let Inst{16-20} = 0; 721 let Inst{21-30} = xo; 722 let Inst{31} = 0; 723} 724 725class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 726 string asmstr, InstrItinClass itin, list<dag> pattern> 727 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 728 let L = 0; 729} 730 731class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 732 InstrItinClass itin, list<dag> pattern> 733 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 734} 735 736class XForm_25_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 737 string asmstr, InstrItinClass itin, list<dag> pattern> 738 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 739} 740 741// [PO RT /// RB XO RC] 742class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 743 InstrItinClass itin, list<dag> pattern> 744 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 745 let A = 0; 746} 747 748class XForm_28_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 749 string asmstr, InstrItinClass itin, list<dag> pattern> 750 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 751} 752 753class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 754 InstrItinClass itin, list<dag> pattern> 755 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 756} 757 758// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 759// numbers presumably relates to some document, but I haven't found it. 760class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 761 InstrItinClass itin, list<dag> pattern> 762 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 763 let Pattern = pattern; 764 765 bit RC = 0; // set by isRecordForm 766 767 let Inst{6-10} = RST; 768 let Inst{11-20} = 0; 769 let Inst{21-30} = xo; 770 let Inst{31} = RC; 771} 772class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 773 InstrItinClass itin, list<dag> pattern> 774 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 775 let Pattern = pattern; 776 bits<5> FM; 777 778 bit RC = 0; // set by isRecordForm 779 780 let Inst{6-10} = FM; 781 let Inst{11-20} = 0; 782 let Inst{21-30} = xo; 783 let Inst{31} = RC; 784} 785 786class XForm_44<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 787 InstrItinClass itin> 788 : I<opcode, OOL, IOL, asmstr, itin> { 789 bits<5> RT; 790 bits<3> BFA; 791 792 let Inst{6-10} = RT; 793 let Inst{11-13} = BFA; 794 let Inst{14-15} = 0; 795 let Inst{16-20} = 0; 796 let Inst{21-30} = xo; 797 let Inst{31} = 0; 798} 799 800class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 801 InstrItinClass itin> 802 : I<opcode, OOL, IOL, asmstr, itin> { 803 bits<5> RT; 804 bits<2> L; 805 806 let Inst{6-10} = RT; 807 let Inst{11-13} = 0; 808 let Inst{14-15} = L; 809 let Inst{16-20} = 0; 810 let Inst{21-30} = xo; 811 let Inst{31} = 0; 812} 813 814class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo, 815 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 816 list<dag> pattern> 817 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 818 let Pattern = pattern; 819 820 let Inst{6-10} = RST; 821 let Inst{11-12} = xo1; 822 let Inst{13-15} = xo2; 823 let Inst{16-20} = 0; 824 let Inst{21-30} = xo; 825 let Inst{31} = 0; 826} 827 828class X_FRT5_XO2_XO3_FRB5_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 829 bits<10> xo, dag OOL, dag IOL, string asmstr, 830 InstrItinClass itin, list<dag> pattern> 831 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 832 let Pattern = pattern; 833 bits<5> FRB; 834 835 let Inst{6-10} = RST; 836 let Inst{11-12} = xo1; 837 let Inst{13-15} = xo2; 838 let Inst{16-20} = FRB; 839 let Inst{21-30} = xo; 840 let Inst{31} = 0; 841} 842 843class X_FRT5_XO2_XO3_DRM3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 844 bits<10> xo, dag OOL, dag IOL, string asmstr, 845 InstrItinClass itin, list<dag> pattern> 846 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 847 let Pattern = pattern; 848 bits<3> DRM; 849 850 let Inst{6-10} = RST; 851 let Inst{11-12} = xo1; 852 let Inst{13-15} = xo2; 853 let Inst{16-17} = 0; 854 let Inst{18-20} = DRM; 855 let Inst{21-30} = xo; 856 let Inst{31} = 0; 857} 858 859class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 860 bits<10> xo, dag OOL, dag IOL, string asmstr, 861 InstrItinClass itin, list<dag> pattern> 862 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 863 let Pattern = pattern; 864 bits<2> RM; 865 866 let Inst{6-10} = RST; 867 let Inst{11-12} = xo1; 868 let Inst{13-15} = xo2; 869 let Inst{16-18} = 0; 870 let Inst{19-20} = RM; 871 let Inst{21-30} = xo; 872 let Inst{31} = 0; 873} 874 875 876class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 877 InstrItinClass itin, list<dag> pattern> 878 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 879 let RST = 0; 880 let A = 0; 881 let B = 0; 882} 883 884class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 885 InstrItinClass itin, list<dag> pattern> 886 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 887 let RST = 0; 888 let A = 0; 889} 890 891class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 892 string asmstr, InstrItinClass itin> 893 : I<opcode, OOL, IOL, asmstr, itin> { 894 bit R; 895 896 bit RC = 1; 897 898 let Inst{6-9} = 0; 899 let Inst{10} = R; 900 let Inst{11-20} = 0; 901 let Inst{21-30} = xo; 902 let Inst{31} = RC; 903} 904 905class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 906 string asmstr, InstrItinClass itin> 907 : I<opcode, OOL, IOL, asmstr, itin> { 908 bit A; 909 910 bit RC = 1; 911 912 let Inst{6} = A; 913 let Inst{7-20} = 0; 914 let Inst{21-30} = xo; 915 let Inst{31} = RC; 916} 917 918class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 919 InstrItinClass itin> 920 : I<opcode, OOL, IOL, asmstr, itin> { 921 bit L; 922 923 bit RC = 0; // set by isRecordForm 924 925 let Inst{7-9} = 0; 926 let Inst{10} = L; 927 let Inst{11-20} = 0; 928 let Inst{21-30} = xo; 929 let Inst{31} = RC; 930} 931 932class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 933 InstrItinClass itin> 934 : I<opcode, OOL, IOL, asmstr, itin> { 935 bits<3> BF; 936 937 bit RC = 0; 938 939 let Inst{6-8} = BF; 940 let Inst{9-20} = 0; 941 let Inst{21-30} = xo; 942 let Inst{31} = RC; 943} 944 945// [PO RT RA RB XO /] 946class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 947 string asmstr, InstrItinClass itin, list<dag> pattern> 948 : I<opcode, OOL, IOL, asmstr, itin> { 949 bits<3> BF; 950 bits<1> L; 951 bits<5> RA; 952 bits<5> RB; 953 954 let Pattern = pattern; 955 956 let Inst{6-8} = BF; 957 let Inst{9} = 0; 958 let Inst{10} = L; 959 let Inst{11-15} = RA; 960 let Inst{16-20} = RB; 961 let Inst{21-30} = xo; 962 let Inst{31} = 0; 963} 964 965// Same as XForm_17 but with GPR's and new naming convention 966class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 967 string asmstr, InstrItinClass itin, list<dag> pattern> 968 : I<opcode, OOL, IOL, asmstr, itin> { 969 bits<3> BF; 970 bits<5> RA; 971 bits<5> RB; 972 973 let Pattern = pattern; 974 975 let Inst{6-8} = BF; 976 let Inst{9-10} = 0; 977 let Inst{11-15} = RA; 978 let Inst{16-20} = RB; 979 let Inst{21-30} = xo; 980 let Inst{31} = 0; 981} 982 983// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO] 984class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 985 string asmstr, InstrItinClass itin, list<dag> pattern> 986 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 987 let A = xo2; 988} 989 990class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 991 string asmstr, InstrItinClass itin, list<dag> pattern> 992 : I<opcode, OOL, IOL, asmstr, itin> { 993 bits<3> BF; 994 bits<7> DCMX; 995 bits<5> VB; 996 997 let Pattern = pattern; 998 999 let Inst{6-8} = BF; 1000 let Inst{9-15} = DCMX; 1001 let Inst{16-20} = VB; 1002 let Inst{21-30} = xo; 1003 let Inst{31} = 0; 1004} 1005 1006class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1007 string asmstr, InstrItinClass itin, list<dag> pattern> 1008 : I<opcode, OOL, IOL, asmstr, itin> { 1009 bits<6> XT; 1010 bits<8> IMM8; 1011 1012 let Pattern = pattern; 1013 1014 let Inst{6-10} = XT{4-0}; 1015 let Inst{11-12} = 0; 1016 let Inst{13-20} = IMM8; 1017 let Inst{21-30} = xo; 1018 let Inst{31} = XT{5}; 1019} 1020 1021// XForm_base_r3xo for instructions such as P9 atomics where we don't want 1022// to specify an SDAG pattern for matching. 1023class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1024 string asmstr, InstrItinClass itin> 1025 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, []> { 1026} 1027 1028class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1029 InstrItinClass itin> 1030 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> { 1031 let FRA = 0; 1032 let FRB = 0; 1033} 1034 1035// [PO /// L RA RB XO /] 1036class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1037 string asmstr, InstrItinClass itin, list<dag> pattern> 1038 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 1039 let BF = 0; 1040 let Pattern = pattern; 1041 1042 bit RC = 0; 1043 let Inst{31} = RC; 1044} 1045 1046// XX*-Form (VSX) 1047class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1048 InstrItinClass itin, list<dag> pattern> 1049 : I<opcode, OOL, IOL, asmstr, itin> { 1050 bits<6> XT; 1051 bits<5> A; 1052 bits<5> B; 1053 1054 let Pattern = pattern; 1055 1056 let Inst{6-10} = XT{4-0}; 1057 let Inst{11-15} = A; 1058 let Inst{16-20} = B; 1059 let Inst{21-30} = xo; 1060 let Inst{31} = XT{5}; 1061} 1062 1063class XX1Form_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1064 string asmstr, InstrItinClass itin, list<dag> pattern> 1065 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 1066 1067class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1068 string asmstr, InstrItinClass itin, list<dag> pattern> 1069 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1070 let B = 0; 1071} 1072 1073class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1074 InstrItinClass itin, list<dag> pattern> 1075 : I<opcode, OOL, IOL, asmstr, itin> { 1076 bits<6> XT; 1077 bits<6> XB; 1078 1079 let Pattern = pattern; 1080 1081 let Inst{6-10} = XT{4-0}; 1082 let Inst{11-15} = 0; 1083 let Inst{16-20} = XB{4-0}; 1084 let Inst{21-29} = xo; 1085 let Inst{30} = XB{5}; 1086 let Inst{31} = XT{5}; 1087} 1088 1089class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1090 InstrItinClass itin, list<dag> pattern> 1091 : I<opcode, OOL, IOL, asmstr, itin> { 1092 bits<3> CR; 1093 bits<6> XB; 1094 1095 let Pattern = pattern; 1096 1097 let Inst{6-8} = CR; 1098 let Inst{9-15} = 0; 1099 let Inst{16-20} = XB{4-0}; 1100 let Inst{21-29} = xo; 1101 let Inst{30} = XB{5}; 1102 let Inst{31} = 0; 1103} 1104 1105class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1106 InstrItinClass itin, list<dag> pattern> 1107 : I<opcode, OOL, IOL, asmstr, itin> { 1108 bits<6> XT; 1109 bits<6> XB; 1110 bits<2> D; 1111 1112 let Pattern = pattern; 1113 1114 let Inst{6-10} = XT{4-0}; 1115 let Inst{11-13} = 0; 1116 let Inst{14-15} = D; 1117 let Inst{16-20} = XB{4-0}; 1118 let Inst{21-29} = xo; 1119 let Inst{30} = XB{5}; 1120 let Inst{31} = XT{5}; 1121} 1122 1123class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1124 string asmstr, InstrItinClass itin, list<dag> pattern> 1125 : I<opcode, OOL, IOL, asmstr, itin> { 1126 bits<6> XT; 1127 bits<6> XB; 1128 bits<5> UIM5; 1129 1130 let Pattern = pattern; 1131 1132 let Inst{6-10} = XT{4-0}; 1133 let Inst{11-15} = UIM5; 1134 let Inst{16-20} = XB{4-0}; 1135 let Inst{21-29} = xo; 1136 let Inst{30} = XB{5}; 1137 let Inst{31} = XT{5}; 1138} 1139 1140// [PO T XO B XO BX /] 1141class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1142 string asmstr, InstrItinClass itin, list<dag> pattern> 1143 : I<opcode, OOL, IOL, asmstr, itin> { 1144 bits<5> RT; 1145 bits<6> XB; 1146 1147 let Pattern = pattern; 1148 1149 let Inst{6-10} = RT; 1150 let Inst{11-15} = xo2; 1151 let Inst{16-20} = XB{4-0}; 1152 let Inst{21-29} = xo; 1153 let Inst{30} = XB{5}; 1154 let Inst{31} = 0; 1155} 1156 1157// [PO T XO B XO BX TX] 1158class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1159 string asmstr, InstrItinClass itin, list<dag> pattern> 1160 : I<opcode, OOL, IOL, asmstr, itin> { 1161 bits<6> XT; 1162 bits<6> XB; 1163 1164 let Pattern = pattern; 1165 1166 let Inst{6-10} = XT{4-0}; 1167 let Inst{11-15} = xo2; 1168 let Inst{16-20} = XB{4-0}; 1169 let Inst{21-29} = xo; 1170 let Inst{30} = XB{5}; 1171 let Inst{31} = XT{5}; 1172} 1173 1174class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1175 string asmstr, InstrItinClass itin, list<dag> pattern> 1176 : I<opcode, OOL, IOL, asmstr, itin> { 1177 bits<3> BF; 1178 bits<7> DCMX; 1179 bits<6> XB; 1180 1181 let Pattern = pattern; 1182 1183 let Inst{6-8} = BF; 1184 let Inst{9-15} = DCMX; 1185 let Inst{16-20} = XB{4-0}; 1186 let Inst{21-29} = xo; 1187 let Inst{30} = XB{5}; 1188 let Inst{31} = 0; 1189} 1190 1191class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2, 1192 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 1193 list<dag> pattern> 1194 : I<opcode, OOL, IOL, asmstr, itin> { 1195 bits<6> XT; 1196 bits<7> DCMX; 1197 bits<6> XB; 1198 1199 let Pattern = pattern; 1200 1201 let Inst{6-10} = XT{4-0}; 1202 let Inst{11-15} = DCMX{4-0}; 1203 let Inst{16-20} = XB{4-0}; 1204 let Inst{21-24} = xo1; 1205 let Inst{25} = DCMX{6}; 1206 let Inst{26-28} = xo2; 1207 let Inst{29} = DCMX{5}; 1208 let Inst{30} = XB{5}; 1209 let Inst{31} = XT{5}; 1210} 1211 1212class XForm_XD6_RA5_RB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1213 string asmstr, InstrItinClass itin, list<dag> pattern> 1214 : I<opcode, OOL, IOL, asmstr, itin> { 1215 bits<11> D_RA_XD; 1216 bits<5> RB; 1217 1218 let Pattern = pattern; 1219 1220 let Inst{6-10} = D_RA_XD{4-0}; // D 1221 let Inst{11-15} = D_RA_XD{10-6}; // RA 1222 let Inst{16-20} = RB; 1223 let Inst{21-30} = xo; 1224 let Inst{31} = D_RA_XD{5}; // DX 1225} 1226 1227class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1228 InstrItinClass itin, list<dag> pattern> 1229 : I<opcode, OOL, IOL, asmstr, itin> { 1230 bits<6> XT; 1231 bits<6> XA; 1232 bits<6> XB; 1233 1234 let Pattern = pattern; 1235 1236 let Inst{6-10} = XT{4-0}; 1237 let Inst{11-15} = XA{4-0}; 1238 let Inst{16-20} = XB{4-0}; 1239 let Inst{21-28} = xo; 1240 let Inst{29} = XA{5}; 1241 let Inst{30} = XB{5}; 1242 let Inst{31} = XT{5}; 1243} 1244 1245class XX3Form_SameOp<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1246 InstrItinClass itin, list<dag> pattern> 1247 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1248 let XA = XT; 1249 let XB = XT; 1250} 1251 1252class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1253 InstrItinClass itin, list<dag> pattern> 1254 : I<opcode, OOL, IOL, asmstr, itin> { 1255 bits<3> CR; 1256 bits<6> XA; 1257 bits<6> XB; 1258 1259 let Pattern = pattern; 1260 1261 let Inst{6-8} = CR; 1262 let Inst{9-10} = 0; 1263 let Inst{11-15} = XA{4-0}; 1264 let Inst{16-20} = XB{4-0}; 1265 let Inst{21-28} = xo; 1266 let Inst{29} = XA{5}; 1267 let Inst{30} = XB{5}; 1268 let Inst{31} = 0; 1269} 1270 1271class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1272 InstrItinClass itin, list<dag> pattern> 1273 : I<opcode, OOL, IOL, asmstr, itin> { 1274 bits<6> XT; 1275 bits<6> XA; 1276 bits<6> XB; 1277 bits<2> D; 1278 1279 let Pattern = pattern; 1280 1281 let Inst{6-10} = XT{4-0}; 1282 let Inst{11-15} = XA{4-0}; 1283 let Inst{16-20} = XB{4-0}; 1284 let Inst{21} = 0; 1285 let Inst{22-23} = D; 1286 let Inst{24-28} = xo; 1287 let Inst{29} = XA{5}; 1288 let Inst{30} = XB{5}; 1289 let Inst{31} = XT{5}; 1290} 1291 1292class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 1293 InstrItinClass itin, list<dag> pattern> 1294 : I<opcode, OOL, IOL, asmstr, itin> { 1295 bits<6> XT; 1296 bits<6> XA; 1297 bits<6> XB; 1298 1299 let Pattern = pattern; 1300 1301 bit RC = 0; // set by isRecordForm 1302 1303 let Inst{6-10} = XT{4-0}; 1304 let Inst{11-15} = XA{4-0}; 1305 let Inst{16-20} = XB{4-0}; 1306 let Inst{21} = RC; 1307 let Inst{22-28} = xo; 1308 let Inst{29} = XA{5}; 1309 let Inst{30} = XB{5}; 1310 let Inst{31} = XT{5}; 1311} 1312 1313class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 1314 InstrItinClass itin, list<dag> pattern> 1315 : I<opcode, OOL, IOL, asmstr, itin> { 1316 bits<6> XT; 1317 bits<6> XA; 1318 bits<6> XB; 1319 bits<6> XC; 1320 1321 let Pattern = pattern; 1322 1323 let Inst{6-10} = XT{4-0}; 1324 let Inst{11-15} = XA{4-0}; 1325 let Inst{16-20} = XB{4-0}; 1326 let Inst{21-25} = XC{4-0}; 1327 let Inst{26-27} = xo; 1328 let Inst{28} = XC{5}; 1329 let Inst{29} = XA{5}; 1330 let Inst{30} = XB{5}; 1331 let Inst{31} = XT{5}; 1332} 1333 1334// DCB_Form - Form X instruction, used for dcb* instructions. 1335class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 1336 InstrItinClass itin, list<dag> pattern> 1337 : I<31, OOL, IOL, asmstr, itin> { 1338 bits<5> A; 1339 bits<5> B; 1340 1341 let Pattern = pattern; 1342 1343 let Inst{6-10} = immfield; 1344 let Inst{11-15} = A; 1345 let Inst{16-20} = B; 1346 let Inst{21-30} = xo; 1347 let Inst{31} = 0; 1348} 1349 1350class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr, 1351 InstrItinClass itin, list<dag> pattern> 1352 : I<31, OOL, IOL, asmstr, itin> { 1353 bits<5> TH; 1354 bits<5> A; 1355 bits<5> B; 1356 1357 let Pattern = pattern; 1358 1359 let Inst{6-10} = TH; 1360 let Inst{11-15} = A; 1361 let Inst{16-20} = B; 1362 let Inst{21-30} = xo; 1363 let Inst{31} = 0; 1364} 1365 1366// DSS_Form - Form X instruction, used for altivec dss* instructions. 1367class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 1368 InstrItinClass itin, list<dag> pattern> 1369 : I<31, OOL, IOL, asmstr, itin> { 1370 bits<2> STRM; 1371 bits<5> A; 1372 bits<5> B; 1373 1374 let Pattern = pattern; 1375 1376 let Inst{6} = T; 1377 let Inst{7-8} = 0; 1378 let Inst{9-10} = STRM; 1379 let Inst{11-15} = A; 1380 let Inst{16-20} = B; 1381 let Inst{21-30} = xo; 1382 let Inst{31} = 0; 1383} 1384 1385// 1.7.7 XL-Form 1386class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1387 InstrItinClass itin, list<dag> pattern> 1388 : I<opcode, OOL, IOL, asmstr, itin> { 1389 bits<5> CRD; 1390 bits<5> CRA; 1391 bits<5> CRB; 1392 1393 let Pattern = pattern; 1394 1395 let Inst{6-10} = CRD; 1396 let Inst{11-15} = CRA; 1397 let Inst{16-20} = CRB; 1398 let Inst{21-30} = xo; 1399 let Inst{31} = 0; 1400} 1401 1402class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1403 InstrItinClass itin, list<dag> pattern> 1404 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1405 let CRD = 0; 1406 let CRA = 0; 1407 let CRB = 0; 1408} 1409 1410class XLForm_1_gen<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1411 InstrItinClass itin, list<dag> pattern> 1412 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1413 bits<5> RT; 1414 bits<5> RB; 1415 1416 let CRD = RT; 1417 let CRA = 0; 1418 let CRB = RB; 1419} 1420 1421class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1422 InstrItinClass itin, list<dag> pattern> 1423 : I<opcode, OOL, IOL, asmstr, itin> { 1424 bits<5> CRD; 1425 1426 let Pattern = pattern; 1427 1428 let Inst{6-10} = CRD; 1429 let Inst{11-15} = CRD; 1430 let Inst{16-20} = CRD; 1431 let Inst{21-30} = xo; 1432 let Inst{31} = 0; 1433} 1434 1435class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 1436 InstrItinClass itin, list<dag> pattern> 1437 : I<opcode, OOL, IOL, asmstr, itin> { 1438 bits<5> BO; 1439 bits<5> BI; 1440 bits<2> BH; 1441 1442 let Pattern = pattern; 1443 1444 let Inst{6-10} = BO; 1445 let Inst{11-15} = BI; 1446 let Inst{16-18} = 0; 1447 let Inst{19-20} = BH; 1448 let Inst{21-30} = xo; 1449 let Inst{31} = lk; 1450} 1451 1452class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 1453 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1454 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1455 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 1456 bits<3> CR; 1457 1458 let BO = BIBO{4-0}; 1459 let BI{0-1} = BIBO{5-6}; 1460 let BI{2-4} = CR{0-2}; 1461 let BH = 0; 1462} 1463 1464class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 1465 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1466 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1467 let BO = bo; 1468 let BH = 0; 1469} 1470 1471class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 1472 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1473 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1474 let BO = bo; 1475 let BI = bi; 1476 let BH = 0; 1477} 1478 1479class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1480 InstrItinClass itin> 1481 : I<opcode, OOL, IOL, asmstr, itin> { 1482 bits<3> BF; 1483 bits<3> BFA; 1484 1485 let Inst{6-8} = BF; 1486 let Inst{9-10} = 0; 1487 let Inst{11-13} = BFA; 1488 let Inst{14-15} = 0; 1489 let Inst{16-20} = 0; 1490 let Inst{21-30} = xo; 1491 let Inst{31} = 0; 1492} 1493 1494class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1495 InstrItinClass itin> 1496 : I<opcode, OOL, IOL, asmstr, itin> { 1497 bits<3> BF; 1498 bit W; 1499 bits<4> U; 1500 1501 bit RC = 0; 1502 1503 let Inst{6-8} = BF; 1504 let Inst{9-10} = 0; 1505 let Inst{11-14} = 0; 1506 let Inst{15} = W; 1507 let Inst{16-19} = U; 1508 let Inst{20} = 0; 1509 let Inst{21-30} = xo; 1510 let Inst{31} = RC; 1511} 1512 1513class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1514 InstrItinClass itin, list<dag> pattern> 1515 : I<opcode, OOL, IOL, asmstr, itin> { 1516 bits<1> S; 1517 1518 let Pattern = pattern; 1519 1520 let Inst{6-19} = 0; 1521 let Inst{20} = S; 1522 let Inst{21-30} = xo; 1523 let Inst{31} = 0; 1524} 1525 1526class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk, 1527 bits<6> opcode2, bits<2> xo2, 1528 dag OOL, dag IOL, string asmstr, 1529 InstrItinClass itin, list<dag> pattern> 1530 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1531 bits<5> BO; 1532 bits<5> BI; 1533 bits<2> BH; 1534 1535 bits<5> RST; 1536 bits<19> DS_RA; 1537 1538 let Pattern = pattern; 1539 1540 let Inst{6-10} = BO; 1541 let Inst{11-15} = BI; 1542 let Inst{16-18} = 0; 1543 let Inst{19-20} = BH; 1544 let Inst{21-30} = xo1; 1545 let Inst{31} = lk; 1546 1547 let Inst{38-42} = RST; 1548 let Inst{43-47} = DS_RA{18-14}; // Register # 1549 let Inst{48-61} = DS_RA{13-0}; // Displacement. 1550 let Inst{62-63} = xo2; 1551} 1552 1553class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1, 1554 bits<5> bo, bits<5> bi, bit lk, 1555 bits<6> opcode2, bits<2> xo2, 1556 dag OOL, dag IOL, string asmstr, 1557 InstrItinClass itin, list<dag> pattern> 1558 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2, 1559 OOL, IOL, asmstr, itin, pattern> { 1560 let BO = bo; 1561 let BI = bi; 1562 let BH = 0; 1563} 1564 1565class XLForm_2_ext_and_DForm_1<bits<6> opcode1, bits<10> xo1, bits<5> bo, 1566 bits<5> bi, bit lk, bits<6> opcode2, dag OOL, 1567 dag IOL, string asmstr, InstrItinClass itin, 1568 list<dag> pattern> 1569 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1570 1571 bits<5> RST; 1572 bits<21> D_RA; 1573 1574 let Pattern = pattern; 1575 1576 let Inst{6-10} = bo; 1577 let Inst{11-15} = bi; 1578 let Inst{16-18} = 0; 1579 let Inst{19-20} = 0; // Unused (BH) 1580 let Inst{21-30} = xo1; 1581 let Inst{31} = lk; 1582 1583 let Inst{38-42} = RST; 1584 let Inst{43-47} = D_RA{20-16}; // Base Register 1585 let Inst{48-63} = D_RA{15-0}; // Displacement 1586} 1587 1588// 1.7.8 XFX-Form 1589class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1590 InstrItinClass itin> 1591 : I<opcode, OOL, IOL, asmstr, itin> { 1592 bits<5> RT; 1593 bits<10> SPR; 1594 1595 let Inst{6-10} = RT; 1596 let Inst{11} = SPR{4}; 1597 let Inst{12} = SPR{3}; 1598 let Inst{13} = SPR{2}; 1599 let Inst{14} = SPR{1}; 1600 let Inst{15} = SPR{0}; 1601 let Inst{16} = SPR{9}; 1602 let Inst{17} = SPR{8}; 1603 let Inst{18} = SPR{7}; 1604 let Inst{19} = SPR{6}; 1605 let Inst{20} = SPR{5}; 1606 let Inst{21-30} = xo; 1607 let Inst{31} = 0; 1608} 1609 1610class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1611 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1612 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 1613 let SPR = spr; 1614} 1615 1616class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1617 InstrItinClass itin> 1618 : I<opcode, OOL, IOL, asmstr, itin> { 1619 bits<5> RT; 1620 1621 let Inst{6-10} = RT; 1622 let Inst{11-20} = 0; 1623 let Inst{21-30} = xo; 1624 let Inst{31} = 0; 1625} 1626 1627class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1628 InstrItinClass itin, list<dag> pattern> 1629 : I<opcode, OOL, IOL, asmstr, itin> { 1630 bits<5> RT; 1631 bits<10> Entry; 1632 let Pattern = pattern; 1633 1634 let Inst{6-10} = RT; 1635 let Inst{11-20} = Entry; 1636 let Inst{21-30} = xo; 1637 let Inst{31} = 0; 1638} 1639 1640class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1641 InstrItinClass itin> 1642 : I<opcode, OOL, IOL, asmstr, itin> { 1643 bits<8> FXM; 1644 bits<5> rS; 1645 1646 let Inst{6-10} = rS; 1647 let Inst{11} = 0; 1648 let Inst{12-19} = FXM; 1649 let Inst{20} = 0; 1650 let Inst{21-30} = xo; 1651 let Inst{31} = 0; 1652} 1653 1654class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1655 InstrItinClass itin> 1656 : I<opcode, OOL, IOL, asmstr, itin> { 1657 bits<5> ST; 1658 bits<8> FXM; 1659 1660 let Inst{6-10} = ST; 1661 let Inst{11} = 1; 1662 let Inst{12-19} = FXM; 1663 let Inst{20} = 0; 1664 let Inst{21-30} = xo; 1665 let Inst{31} = 0; 1666} 1667 1668class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1669 InstrItinClass itin> 1670 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 1671 1672class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1673 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1674 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 1675 let SPR = spr; 1676} 1677 1678// XFL-Form - MTFSF 1679// This is probably 1.7.9, but I don't have the reference that uses this 1680// numbering scheme... 1681class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1682 InstrItinClass itin, list<dag>pattern> 1683 : I<opcode, OOL, IOL, asmstr, itin> { 1684 bits<8> FM; 1685 bits<5> rT; 1686 1687 bit RC = 0; // set by isRecordForm 1688 let Pattern = pattern; 1689 1690 let Inst{6} = 0; 1691 let Inst{7-14} = FM; 1692 let Inst{15} = 0; 1693 let Inst{16-20} = rT; 1694 let Inst{21-30} = xo; 1695 let Inst{31} = RC; 1696} 1697 1698class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1699 InstrItinClass itin, list<dag>pattern> 1700 : I<opcode, OOL, IOL, asmstr, itin> { 1701 bit L; 1702 bits<8> FLM; 1703 bit W; 1704 bits<5> FRB; 1705 1706 bit RC = 0; // set by isRecordForm 1707 let Pattern = pattern; 1708 1709 let Inst{6} = L; 1710 let Inst{7-14} = FLM; 1711 let Inst{15} = W; 1712 let Inst{16-20} = FRB; 1713 let Inst{21-30} = xo; 1714 let Inst{31} = RC; 1715} 1716 1717// 1.7.10 XS-Form - SRADI. 1718class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1719 InstrItinClass itin, list<dag> pattern> 1720 : I<opcode, OOL, IOL, asmstr, itin> { 1721 bits<5> A; 1722 bits<5> RS; 1723 bits<6> SH; 1724 1725 bit RC = 0; // set by isRecordForm 1726 let Pattern = pattern; 1727 1728 let Inst{6-10} = RS; 1729 let Inst{11-15} = A; 1730 let Inst{16-20} = SH{4,3,2,1,0}; 1731 let Inst{21-29} = xo; 1732 let Inst{30} = SH{5}; 1733 let Inst{31} = RC; 1734} 1735 1736// 1.7.11 XO-Form 1737class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1738 InstrItinClass itin, list<dag> pattern> 1739 : I<opcode, OOL, IOL, asmstr, itin> { 1740 bits<5> RT; 1741 bits<5> RA; 1742 bits<5> RB; 1743 1744 let Pattern = pattern; 1745 1746 bit RC = 0; // set by isRecordForm 1747 1748 let Inst{6-10} = RT; 1749 let Inst{11-15} = RA; 1750 let Inst{16-20} = RB; 1751 let Inst{21} = oe; 1752 let Inst{22-30} = xo; 1753 let Inst{31} = RC; 1754} 1755 1756class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1757 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1758 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1759 let RB = 0; 1760} 1761 1762// 1.7.12 A-Form 1763class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1764 InstrItinClass itin, list<dag> pattern> 1765 : I<opcode, OOL, IOL, asmstr, itin> { 1766 bits<5> FRT; 1767 bits<5> FRA; 1768 bits<5> FRC; 1769 bits<5> FRB; 1770 1771 let Pattern = pattern; 1772 1773 bit RC = 0; // set by isRecordForm 1774 1775 let Inst{6-10} = FRT; 1776 let Inst{11-15} = FRA; 1777 let Inst{16-20} = FRB; 1778 let Inst{21-25} = FRC; 1779 let Inst{26-30} = xo; 1780 let Inst{31} = RC; 1781} 1782 1783class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1784 InstrItinClass itin, list<dag> pattern> 1785 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1786 let FRC = 0; 1787} 1788 1789class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1790 InstrItinClass itin, list<dag> pattern> 1791 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1792 let FRB = 0; 1793} 1794 1795class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1796 InstrItinClass itin, list<dag> pattern> 1797 : I<opcode, OOL, IOL, asmstr, itin> { 1798 bits<5> RT; 1799 bits<5> RA; 1800 bits<5> RB; 1801 bits<5> COND; 1802 1803 let Pattern = pattern; 1804 1805 let Inst{6-10} = RT; 1806 let Inst{11-15} = RA; 1807 let Inst{16-20} = RB; 1808 let Inst{21-25} = COND; 1809 let Inst{26-30} = xo; 1810 let Inst{31} = 0; 1811} 1812 1813// 1.7.13 M-Form 1814class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1815 InstrItinClass itin, list<dag> pattern> 1816 : I<opcode, OOL, IOL, asmstr, itin> { 1817 bits<5> RA; 1818 bits<5> RS; 1819 bits<5> RB; 1820 bits<5> MB; 1821 bits<5> ME; 1822 1823 let Pattern = pattern; 1824 1825 bit RC = 0; // set by isRecordForm 1826 1827 let Inst{6-10} = RS; 1828 let Inst{11-15} = RA; 1829 let Inst{16-20} = RB; 1830 let Inst{21-25} = MB; 1831 let Inst{26-30} = ME; 1832 let Inst{31} = RC; 1833} 1834 1835class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1836 InstrItinClass itin, list<dag> pattern> 1837 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 1838} 1839 1840// 1.7.14 MD-Form 1841class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1842 InstrItinClass itin, list<dag> pattern> 1843 : I<opcode, OOL, IOL, asmstr, itin> { 1844 bits<5> RA; 1845 bits<5> RS; 1846 bits<6> SH; 1847 bits<6> MBE; 1848 1849 let Pattern = pattern; 1850 1851 bit RC = 0; // set by isRecordForm 1852 1853 let Inst{6-10} = RS; 1854 let Inst{11-15} = RA; 1855 let Inst{16-20} = SH{4,3,2,1,0}; 1856 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1857 let Inst{27-29} = xo; 1858 let Inst{30} = SH{5}; 1859 let Inst{31} = RC; 1860} 1861 1862class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1863 InstrItinClass itin, list<dag> pattern> 1864 : I<opcode, OOL, IOL, asmstr, itin> { 1865 bits<5> RA; 1866 bits<5> RS; 1867 bits<5> RB; 1868 bits<6> MBE; 1869 1870 let Pattern = pattern; 1871 1872 bit RC = 0; // set by isRecordForm 1873 1874 let Inst{6-10} = RS; 1875 let Inst{11-15} = RA; 1876 let Inst{16-20} = RB; 1877 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1878 let Inst{27-30} = xo; 1879 let Inst{31} = RC; 1880} 1881 1882 1883// E-1 VA-Form 1884 1885// VAForm_1 - DACB ordering. 1886class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1887 InstrItinClass itin, list<dag> pattern> 1888 : I<4, OOL, IOL, asmstr, itin> { 1889 bits<5> VD; 1890 bits<5> VA; 1891 bits<5> VC; 1892 bits<5> VB; 1893 1894 let Pattern = pattern; 1895 1896 let Inst{6-10} = VD; 1897 let Inst{11-15} = VA; 1898 let Inst{16-20} = VB; 1899 let Inst{21-25} = VC; 1900 let Inst{26-31} = xo; 1901} 1902 1903// VAForm_1a - DABC ordering. 1904class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1905 InstrItinClass itin, list<dag> pattern> 1906 : I<4, OOL, IOL, asmstr, itin> { 1907 bits<5> VD; 1908 bits<5> VA; 1909 bits<5> VB; 1910 bits<5> VC; 1911 1912 let Pattern = pattern; 1913 1914 let Inst{6-10} = VD; 1915 let Inst{11-15} = VA; 1916 let Inst{16-20} = VB; 1917 let Inst{21-25} = VC; 1918 let Inst{26-31} = xo; 1919} 1920 1921class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1922 InstrItinClass itin, list<dag> pattern> 1923 : I<4, OOL, IOL, asmstr, itin> { 1924 bits<5> VD; 1925 bits<5> VA; 1926 bits<5> VB; 1927 bits<4> SH; 1928 1929 let Pattern = pattern; 1930 1931 let Inst{6-10} = VD; 1932 let Inst{11-15} = VA; 1933 let Inst{16-20} = VB; 1934 let Inst{21} = 0; 1935 let Inst{22-25} = SH; 1936 let Inst{26-31} = xo; 1937} 1938 1939// E-2 VX-Form 1940class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1941 InstrItinClass itin, list<dag> pattern> 1942 : I<4, OOL, IOL, asmstr, itin> { 1943 bits<5> VD; 1944 bits<5> VA; 1945 bits<5> VB; 1946 1947 let Pattern = pattern; 1948 1949 let Inst{6-10} = VD; 1950 let Inst{11-15} = VA; 1951 let Inst{16-20} = VB; 1952 let Inst{21-31} = xo; 1953} 1954 1955class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1956 InstrItinClass itin, list<dag> pattern> 1957 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1958 let VA = VD; 1959 let VB = VD; 1960} 1961 1962 1963class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1964 InstrItinClass itin, list<dag> pattern> 1965 : I<4, OOL, IOL, asmstr, itin> { 1966 bits<5> VD; 1967 bits<5> VB; 1968 1969 let Pattern = pattern; 1970 1971 let Inst{6-10} = VD; 1972 let Inst{11-15} = 0; 1973 let Inst{16-20} = VB; 1974 let Inst{21-31} = xo; 1975} 1976 1977class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1978 InstrItinClass itin, list<dag> pattern> 1979 : I<4, OOL, IOL, asmstr, itin> { 1980 bits<5> VD; 1981 bits<5> IMM; 1982 1983 let Pattern = pattern; 1984 1985 let Inst{6-10} = VD; 1986 let Inst{11-15} = IMM; 1987 let Inst{16-20} = 0; 1988 let Inst{21-31} = xo; 1989} 1990 1991/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1992class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1993 InstrItinClass itin, list<dag> pattern> 1994 : I<4, OOL, IOL, asmstr, itin> { 1995 bits<5> VD; 1996 1997 let Pattern = pattern; 1998 1999 let Inst{6-10} = VD; 2000 let Inst{11-15} = 0; 2001 let Inst{16-20} = 0; 2002 let Inst{21-31} = xo; 2003} 2004 2005/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 2006class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 2007 InstrItinClass itin, list<dag> pattern> 2008 : I<4, OOL, IOL, asmstr, itin> { 2009 bits<5> VB; 2010 2011 let Pattern = pattern; 2012 2013 let Inst{6-10} = 0; 2014 let Inst{11-15} = 0; 2015 let Inst{16-20} = VB; 2016 let Inst{21-31} = xo; 2017} 2018 2019// e.g. [PO VRT EO VRB XO] 2020class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL, 2021 string asmstr, InstrItinClass itin, list<dag> pattern> 2022 : I<4, OOL, IOL, asmstr, itin> { 2023 bits<5> RD; 2024 bits<5> VB; 2025 2026 let Pattern = pattern; 2027 2028 let Inst{6-10} = RD; 2029 let Inst{11-15} = eo; 2030 let Inst{16-20} = VB; 2031 let Inst{21-31} = xo; 2032} 2033 2034/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX" 2035class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr, 2036 InstrItinClass itin, list<dag> pattern> 2037 : I<4, OOL, IOL, asmstr, itin> { 2038 bits<5> VD; 2039 bits<5> VA; 2040 bits<1> ST; 2041 bits<4> SIX; 2042 2043 let Pattern = pattern; 2044 2045 let Inst{6-10} = VD; 2046 let Inst{11-15} = VA; 2047 let Inst{16} = ST; 2048 let Inst{17-20} = SIX; 2049 let Inst{21-31} = xo; 2050} 2051 2052/// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox" 2053class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr, 2054 InstrItinClass itin, list<dag> pattern> 2055 : I<4, OOL, IOL, asmstr, itin> { 2056 bits<5> VD; 2057 bits<5> VA; 2058 2059 let Pattern = pattern; 2060 2061 let Inst{6-10} = VD; 2062 let Inst{11-15} = VA; 2063 let Inst{16-20} = 0; 2064 let Inst{21-31} = xo; 2065} 2066 2067// E-4 VXR-Form 2068class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 2069 InstrItinClass itin, list<dag> pattern> 2070 : I<4, OOL, IOL, asmstr, itin> { 2071 bits<5> VD; 2072 bits<5> VA; 2073 bits<5> VB; 2074 bit RC = 0; 2075 2076 let Pattern = pattern; 2077 2078 let Inst{6-10} = VD; 2079 let Inst{11-15} = VA; 2080 let Inst{16-20} = VB; 2081 let Inst{21} = RC; 2082 let Inst{22-31} = xo; 2083} 2084 2085// VX-Form: [PO VRT EO VRB 1 PS XO] 2086class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo, 2087 dag OOL, dag IOL, string asmstr, 2088 InstrItinClass itin, list<dag> pattern> 2089 : I<4, OOL, IOL, asmstr, itin> { 2090 bits<5> VD; 2091 bits<5> VB; 2092 bit PS; 2093 2094 let Pattern = pattern; 2095 2096 let Inst{6-10} = VD; 2097 let Inst{11-15} = eo; 2098 let Inst{16-20} = VB; 2099 let Inst{21} = 1; 2100 let Inst{22} = PS; 2101 let Inst{23-31} = xo; 2102} 2103 2104// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO] 2105class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr, 2106 InstrItinClass itin, list<dag> pattern> 2107 : I<4, OOL, IOL, asmstr, itin> { 2108 bits<5> VD; 2109 bits<5> VA; 2110 bits<5> VB; 2111 bit PS; 2112 2113 let Pattern = pattern; 2114 2115 let Inst{6-10} = VD; 2116 let Inst{11-15} = VA; 2117 let Inst{16-20} = VB; 2118 let Inst{21} = 1; 2119 let Inst{22} = PS; 2120 let Inst{23-31} = xo; 2121} 2122 2123class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2124 InstrItinClass itin, list<dag> pattern> 2125 : I<opcode, OOL, IOL, asmstr, itin> { 2126 bits<5> VRT; 2127 bit R; 2128 bits<5> VRB; 2129 bits<2> idx; 2130 2131 let Pattern = pattern; 2132 2133 bit RC = 0; // set by isRecordForm 2134 2135 let Inst{6-10} = VRT; 2136 let Inst{11-14} = 0; 2137 let Inst{15} = R; 2138 let Inst{16-20} = VRB; 2139 let Inst{21-22} = idx; 2140 let Inst{23-30} = xo; 2141 let Inst{31} = RC; 2142} 2143 2144class Z23Form_RTAB5_CY2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 2145 string asmstr, InstrItinClass itin, list<dag> pattern> 2146 : I<opcode, OOL, IOL, asmstr, itin> { 2147 bits<5> RT; 2148 bits<5> RA; 2149 bits<5> RB; 2150 bits<2> CY; 2151 2152 let Pattern = pattern; 2153 2154 let Inst{6-10} = RT; 2155 let Inst{11-15} = RA; 2156 let Inst{16-20} = RB; 2157 let Inst{21-22} = CY; 2158 let Inst{23-30} = xo; 2159 let Inst{31} = 0; 2160} 2161 2162//===----------------------------------------------------------------------===// 2163// EmitTimePseudo won't have encoding information for the [MC]CodeEmitter 2164// stuff 2165class PPCEmitTimePseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2166 : I<0, OOL, IOL, asmstr, NoItinerary> { 2167 let isCodeGenOnly = 1; 2168 let PPC64 = 0; 2169 let Pattern = pattern; 2170 let Inst{31-0} = 0; 2171 let hasNoSchedulingInfo = 1; 2172} 2173 2174// Instruction that require custom insertion support 2175// a.k.a. ISelPseudos, however, these won't have isPseudo set 2176class PPCCustomInserterPseudo<dag OOL, dag IOL, string asmstr, 2177 list<dag> pattern> 2178 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2179 let usesCustomInserter = 1; 2180} 2181 2182// PostRAPseudo will be expanded in expandPostRAPseudo, isPseudo flag in td 2183// files is set only for PostRAPseudo 2184class PPCPostRAExpPseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2185 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2186 let isPseudo = 1; 2187} 2188 2189class PseudoXFormMemOp<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2190 : PPCPostRAExpPseudo<OOL, IOL, asmstr, pattern>, XFormMemOp; 2191 2192