10b57cec5SDimitry Andric//===-- PPCInstrHTM.td - The PowerPC Hardware Transactional Memory -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file describes the Hardware Transactional Memory extension to the 100b57cec5SDimitry Andric// PowerPC instruction set. 110b57cec5SDimitry Andric// 120b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric 150b57cec5SDimitry Andric 165ffd83dbSDimitry Andricdef HasHTM : Predicate<"Subtarget->hasHTM()">; 170b57cec5SDimitry Andric 180b57cec5SDimitry Andricdef HTM_get_imm : SDNodeXForm<imm, [{ 190b57cec5SDimitry Andric return getI32Imm (N->getZExtValue(), SDLoc(N)); 200b57cec5SDimitry Andric}]>; 210b57cec5SDimitry Andric 220b57cec5SDimitry Andriclet hasSideEffects = 1 in { 230b57cec5SDimitry Andricdef TCHECK_RET : PPCCustomInserterPseudo<(outs gprc:$out), (ins), "#TCHECK_RET", []>; 240b57cec5SDimitry Andricdef TBEGIN_RET : PPCCustomInserterPseudo<(outs gprc:$out), (ins u1imm:$R), "#TBEGIN_RET", []>; 250b57cec5SDimitry Andric} 260b57cec5SDimitry Andric 270b57cec5SDimitry Andric 280b57cec5SDimitry Andriclet Predicates = [HasHTM] in { 290b57cec5SDimitry Andric 300b57cec5SDimitry Andriclet Defs = [CR0] in { 310b57cec5SDimitry Andricdef TBEGIN : XForm_htm0 <31, 654, 32349cc55cSDimitry Andric (outs), (ins u1imm:$R), "tbegin. $R", IIC_SprMTSPR>; 330b57cec5SDimitry Andric 340b57cec5SDimitry Andricdef TEND : XForm_htm1 <31, 686, 35349cc55cSDimitry Andric (outs), (ins u1imm:$A), "tend. $A", IIC_SprMTSPR>; 360b57cec5SDimitry Andric 370b57cec5SDimitry Andricdef TABORT : XForm_base_r3xo <31, 910, 3806c3fb27SDimitry Andric (outs), (ins gprc:$RA), "tabort. $RA", IIC_SprMTSPR, 39480093f4SDimitry Andric []>, isRecordForm { 400b57cec5SDimitry Andric let RST = 0; 4106c3fb27SDimitry Andric let RB = 0; 420b57cec5SDimitry Andric} 430b57cec5SDimitry Andric 440b57cec5SDimitry Andricdef TABORTWC : XForm_base_r3xo <31, 782, 4506c3fb27SDimitry Andric (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB), 4606c3fb27SDimitry Andric "tabortwc. $RST, $RA, $RB", IIC_SprMTSPR, []>, 47480093f4SDimitry Andric isRecordForm; 480b57cec5SDimitry Andric 490b57cec5SDimitry Andricdef TABORTWCI : XForm_base_r3xo <31, 846, 5006c3fb27SDimitry Andric (outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB), 5106c3fb27SDimitry Andric "tabortwci. $RST, $RA, $RB", IIC_SprMTSPR, []>, 52480093f4SDimitry Andric isRecordForm; 530b57cec5SDimitry Andric 540b57cec5SDimitry Andricdef TABORTDC : XForm_base_r3xo <31, 814, 5506c3fb27SDimitry Andric (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB), 5606c3fb27SDimitry Andric "tabortdc. $RST, $RA, $RB", IIC_SprMTSPR, []>, 57480093f4SDimitry Andric isRecordForm; 580b57cec5SDimitry Andric 590b57cec5SDimitry Andricdef TABORTDCI : XForm_base_r3xo <31, 878, 6006c3fb27SDimitry Andric (outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB), 6106c3fb27SDimitry Andric "tabortdci. $RST, $RA, $RB", IIC_SprMTSPR, []>, 62480093f4SDimitry Andric isRecordForm; 630b57cec5SDimitry Andric 640b57cec5SDimitry Andricdef TSR : XForm_htm2 <31, 750, 65349cc55cSDimitry Andric (outs), (ins u1imm:$L), "tsr. $L", IIC_SprMTSPR>, 66480093f4SDimitry Andric isRecordForm; 670b57cec5SDimitry Andric 680b57cec5SDimitry Andricdef TRECLAIM : XForm_base_r3xo <31, 942, 6906c3fb27SDimitry Andric (outs), (ins gprc:$RA), "treclaim. $RA", 700b57cec5SDimitry Andric IIC_SprMTSPR, []>, 71480093f4SDimitry Andric isRecordForm { 720b57cec5SDimitry Andric let RST = 0; 7306c3fb27SDimitry Andric let RB = 0; 740b57cec5SDimitry Andric} 750b57cec5SDimitry Andric 760b57cec5SDimitry Andricdef TRECHKPT : XForm_base_r3xo <31, 1006, 770b57cec5SDimitry Andric (outs), (ins), "trechkpt.", IIC_SprMTSPR, []>, 78480093f4SDimitry Andric isRecordForm { 790b57cec5SDimitry Andric let RST = 0; 8006c3fb27SDimitry Andric let RA = 0; 8106c3fb27SDimitry Andric let RB = 0; 820b57cec5SDimitry Andric} 830b57cec5SDimitry Andric 840b57cec5SDimitry Andric} 850b57cec5SDimitry Andric 860b57cec5SDimitry Andricdef TCHECK : XForm_htm3 <31, 718, 87349cc55cSDimitry Andric (outs crrc:$BF), (ins), "tcheck $BF", IIC_SprMTSPR>; 880b57cec5SDimitry Andric// Builtins 890b57cec5SDimitry Andric 900b57cec5SDimitry Andric// All HTM instructions, with the exception of tcheck, set CR0 with the 910b57cec5SDimitry Andric// value of the MSR Transaction State (TS) bits that exist before the 920b57cec5SDimitry Andric// instruction is executed. For tbegin., the EQ bit in CR0 can be used 930b57cec5SDimitry Andric// to determine whether the transaction was successfully started (0) or 940b57cec5SDimitry Andric// failed (1). We use an XORI pattern to 'flip' the bit to match the 950b57cec5SDimitry Andric// tbegin builtin API which defines a return value of 1 as success. 960b57cec5SDimitry Andric 970b57cec5SDimitry Andricdef : Pat<(int_ppc_tbegin i32:$R), 980b57cec5SDimitry Andric (XORI (TBEGIN_RET(HTM_get_imm imm:$R)), 1)>; 990b57cec5SDimitry Andric 1000b57cec5SDimitry Andricdef : Pat<(int_ppc_tend i32:$R), 1010b57cec5SDimitry Andric (TEND (HTM_get_imm imm:$R))>; 1020b57cec5SDimitry Andric 1030b57cec5SDimitry Andricdef : Pat<(int_ppc_tabort i32:$R), 1040b57cec5SDimitry Andric (TABORT $R)>; 1050b57cec5SDimitry Andric 1060b57cec5SDimitry Andricdef : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB), 1070b57cec5SDimitry Andric (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>; 1080b57cec5SDimitry Andric 1090b57cec5SDimitry Andricdef : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI), 1100b57cec5SDimitry Andric (TABORTWCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>; 1110b57cec5SDimitry Andric 1120b57cec5SDimitry Andricdef : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB), 1130b57cec5SDimitry Andric (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>; 1140b57cec5SDimitry Andric 1150b57cec5SDimitry Andricdef : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI), 1160b57cec5SDimitry Andric (TABORTDCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>; 1170b57cec5SDimitry Andric 1180b57cec5SDimitry Andricdef : Pat<(int_ppc_tcheck), 1190b57cec5SDimitry Andric (TCHECK_RET)>; 1200b57cec5SDimitry Andric 1210b57cec5SDimitry Andricdef : Pat<(int_ppc_treclaim i32:$RA), 1220b57cec5SDimitry Andric (TRECLAIM $RA)>; 1230b57cec5SDimitry Andric 1240b57cec5SDimitry Andricdef : Pat<(int_ppc_trechkpt), 1250b57cec5SDimitry Andric (TRECHKPT)>; 1260b57cec5SDimitry Andric 1270b57cec5SDimitry Andricdef : Pat<(int_ppc_tsr i32:$L), 1280b57cec5SDimitry Andric (TSR (HTM_get_imm imm:$L))>; 1290b57cec5SDimitry Andric 1300b57cec5SDimitry Andricdef : Pat<(int_ppc_get_texasr), 1310b57cec5SDimitry Andric (MFSPR8 130)>; 1320b57cec5SDimitry Andric 1330b57cec5SDimitry Andricdef : Pat<(int_ppc_get_texasru), 1340b57cec5SDimitry Andric (MFSPR8 131)>; 1350b57cec5SDimitry Andric 1360b57cec5SDimitry Andricdef : Pat<(int_ppc_get_tfhar), 1370b57cec5SDimitry Andric (MFSPR8 128)>; 1380b57cec5SDimitry Andric 1390b57cec5SDimitry Andricdef : Pat<(int_ppc_get_tfiar), 1400b57cec5SDimitry Andric (MFSPR8 129)>; 1410b57cec5SDimitry Andric 1420b57cec5SDimitry Andric 1430b57cec5SDimitry Andricdef : Pat<(int_ppc_set_texasr i64:$V), 1440b57cec5SDimitry Andric (MTSPR8 130, $V)>; 1450b57cec5SDimitry Andric 1460b57cec5SDimitry Andricdef : Pat<(int_ppc_set_texasru i64:$V), 1470b57cec5SDimitry Andric (MTSPR8 131, $V)>; 1480b57cec5SDimitry Andric 1490b57cec5SDimitry Andricdef : Pat<(int_ppc_set_tfhar i64:$V), 1500b57cec5SDimitry Andric (MTSPR8 128, $V)>; 1510b57cec5SDimitry Andric 1520b57cec5SDimitry Andricdef : Pat<(int_ppc_set_tfiar i64:$V), 1530b57cec5SDimitry Andric (MTSPR8 129, $V)>; 1540b57cec5SDimitry Andric 1550b57cec5SDimitry Andric 1560b57cec5SDimitry Andric// Extended mnemonics 1570b57cec5SDimitry Andricdef : Pat<(int_ppc_tendall), 1580b57cec5SDimitry Andric (TEND 1)>; 1590b57cec5SDimitry Andric 1600b57cec5SDimitry Andricdef : Pat<(int_ppc_tresume), 1610b57cec5SDimitry Andric (TSR 1)>; 1620b57cec5SDimitry Andric 1630b57cec5SDimitry Andricdef : Pat<(int_ppc_tsuspend), 1640b57cec5SDimitry Andric (TSR 0)>; 1650b57cec5SDimitry Andric 1660b57cec5SDimitry Andricdef : Pat<(i64 (int_ppc_ttest)), 167e8d8bef9SDimitry Andric (i64 (INSERT_SUBREG 168e8d8bef9SDimitry Andric (i64 (IMPLICIT_DEF)), (TABORTWCI 0, (LI 0), 0), sub_32))>; 1690b57cec5SDimitry Andric 1700b57cec5SDimitry Andric} // [HasHTM] 1715ffd83dbSDimitry Andric 1725ffd83dbSDimitry Andricdef : InstAlias<"tend.", (TEND 0)>, Requires<[HasHTM]>; 1735ffd83dbSDimitry Andricdef : InstAlias<"tendall.", (TEND 1)>, Requires<[HasHTM]>; 1745ffd83dbSDimitry Andricdef : InstAlias<"tsuspend.", (TSR 0)>, Requires<[HasHTM]>; 1755ffd83dbSDimitry Andricdef : InstAlias<"tresume.", (TSR 1)>, Requires<[HasHTM]>; 176