1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the subset of the 32-bit PowerPC instruction set, as used 10// by the PowerPC instruction selector. 11// 12//===----------------------------------------------------------------------===// 13 14include "PPCInstrFormats.td" 15 16//===----------------------------------------------------------------------===// 17// PowerPC specific type constraints. 18// 19def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 20 SDTCisVT<0, f64>, SDTCisPtrTy<1> 21]>; 22def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 23 SDTCisVT<0, f64>, SDTCisPtrTy<1> 24]>; 25def SDT_PPCLxsizx : SDTypeProfile<1, 2, [ 26 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 27]>; 28def SDT_PPCstxsix : SDTypeProfile<0, 3, [ 29 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 30]>; 31def SDT_PPCcv_fp_to_int : SDTypeProfile<1, 1, [ 32 SDTCisFP<0>, SDTCisFP<1> 33 ]>; 34def SDT_PPCstore_scal_int_from_vsr : SDTypeProfile<0, 3, [ 35 SDTCisFP<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 36]>; 37def SDT_PPCVexts : SDTypeProfile<1, 2, [ 38 SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2> 39]>; 40 41def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 42 SDTCisVT<1, i32> ]>; 43def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 44 SDTCisVT<1, i32> ]>; 45def SDT_PPCvperm : SDTypeProfile<1, 3, [ 46 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 47]>; 48 49def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>, 50 SDTCisVec<1>, SDTCisInt<2> 51]>; 52 53def SDT_PPCSpToDp : SDTypeProfile<1, 1, [ SDTCisVT<0, v2f64>, 54 SDTCisInt<1> 55]>; 56 57def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>, 58 SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3> 59]>; 60 61def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>, 62 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 63]>; 64 65def SDT_PPCxxpermdi: SDTypeProfile<1, 3, [ SDTCisVec<0>, 66 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 67]>; 68 69def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 70 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 71]>; 72 73def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 74 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 75]>; 76 77def SDT_PPCFtsqrt : SDTypeProfile<1, 1, [ 78 SDTCisVT<0, i32>]>; 79 80def SDT_PPClbrx : SDTypeProfile<1, 2, [ 81 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 82]>; 83def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 84 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 85]>; 86def SDT_StoreCond : SDTypeProfile<0, 3, [ 87 SDTCisPtrTy<0>, SDTCisInt<1>, SDTCisPtrTy<2> 88]>; 89 90def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 91 SDTCisPtrTy<0>, SDTCisVT<1, i32> 92]>; 93 94def tocentry32 : Operand<iPTR> { 95 let MIOperandInfo = (ops i32imm:$imm); 96} 97 98def SDT_PPCqvfperm : SDTypeProfile<1, 3, [ 99 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3> 100]>; 101def SDT_PPCqvgpci : SDTypeProfile<1, 1, [ 102 SDTCisVec<0>, SDTCisInt<1> 103]>; 104def SDT_PPCqvaligni : SDTypeProfile<1, 3, [ 105 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3> 106]>; 107def SDT_PPCqvesplati : SDTypeProfile<1, 2, [ 108 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2> 109]>; 110 111def SDT_PPCqbflt : SDTypeProfile<1, 1, [ 112 SDTCisVec<0>, SDTCisVec<1> 113]>; 114 115def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [ 116 SDTCisVec<0>, SDTCisPtrTy<1> 117]>; 118 119def SDT_PPCextswsli : SDTypeProfile<1, 2, [ // extswsli 120 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisInt<2> 121]>; 122 123def SDT_PPCFPMinMax : SDTypeProfile<1, 2, [ 124 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 125]>; 126 127//===----------------------------------------------------------------------===// 128// PowerPC specific DAG Nodes. 129// 130 131def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 132def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 133def PPCfsqrt : SDNode<"PPCISD::FSQRT", SDTFPUnaryOp, []>; 134def PPCftsqrt : SDNode<"PPCISD::FTSQRT", SDT_PPCFtsqrt,[]>; 135 136def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 137def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 138def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 139def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 140def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 141def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 142def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 143def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 144 145def PPCstrict_fcfid : SDNode<"PPCISD::STRICT_FCFID", 146 SDTFPUnaryOp, [SDNPHasChain]>; 147def PPCstrict_fcfidu : SDNode<"PPCISD::STRICT_FCFIDU", 148 SDTFPUnaryOp, [SDNPHasChain]>; 149def PPCstrict_fcfids : SDNode<"PPCISD::STRICT_FCFIDS", 150 SDTFPRoundOp, [SDNPHasChain]>; 151def PPCstrict_fcfidus : SDNode<"PPCISD::STRICT_FCFIDUS", 152 SDTFPRoundOp, [SDNPHasChain]>; 153 154def PPCany_fcfid : PatFrags<(ops node:$op), 155 [(PPCfcfid node:$op), 156 (PPCstrict_fcfid node:$op)]>; 157def PPCany_fcfidu : PatFrags<(ops node:$op), 158 [(PPCfcfidu node:$op), 159 (PPCstrict_fcfidu node:$op)]>; 160def PPCany_fcfids : PatFrags<(ops node:$op), 161 [(PPCfcfids node:$op), 162 (PPCstrict_fcfids node:$op)]>; 163def PPCany_fcfidus : PatFrags<(ops node:$op), 164 [(PPCfcfidus node:$op), 165 (PPCstrict_fcfidus node:$op)]>; 166 167def PPCstore_scal_int_from_vsr: 168 SDNode<"PPCISD::ST_VSR_SCAL_INT", SDT_PPCstore_scal_int_from_vsr, 169 [SDNPHasChain, SDNPMayStore]>; 170def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 171 [SDNPHasChain, SDNPMayStore]>; 172def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 173 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 174def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 175 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 176def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx, 177 [SDNPHasChain, SDNPMayLoad]>; 178def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix, 179 [SDNPHasChain, SDNPMayStore]>; 180def PPCVexts : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>; 181 182// Extract FPSCR (not modeled at the DAG level). 183def PPCmffs : SDNode<"PPCISD::MFFS", 184 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 185 [SDNPHasChain]>; 186 187// Perform FADD in round-to-zero mode. 188def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 189def PPCstrict_faddrtz: SDNode<"PPCISD::STRICT_FADDRTZ", SDTFPBinOp, 190 [SDNPHasChain]>; 191 192def PPCany_faddrtz: PatFrags<(ops node:$lhs, node:$rhs), 193 [(PPCfaddrtz node:$lhs, node:$rhs), 194 (PPCstrict_faddrtz node:$lhs, node:$rhs)]>; 195 196def PPCfsel : SDNode<"PPCISD::FSEL", 197 // Type constraint for fsel. 198 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 199 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 200def PPCxsmaxc : SDNode<"PPCISD::XSMAXC", SDT_PPCFPMinMax, []>; 201def PPCxsminc : SDNode<"PPCISD::XSMINC", SDT_PPCFPMinMax, []>; 202def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 203def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 204def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, 205 [SDNPMayLoad, SDNPMemOperand]>; 206 207def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>; 208 209def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 210def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 211 [SDNPMayLoad]>; 212def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 213def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 214def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 215def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 216def PPCgetTpointer : SDNode<"PPCISD::GET_TPOINTER", SDTIntLeaf, []>; 217def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR", 218 SDTypeProfile<1, 3, [ 219 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 220 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 221def PPCTlsgdAIX : SDNode<"PPCISD::TLSGD_AIX", SDTIntBinOp>; 222def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 223def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 224def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 225def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR", 226 SDTypeProfile<1, 3, [ 227 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 228 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 229def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>; 230def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 231def PPCpaddiDtprel : SDNode<"PPCISD::PADDI_DTPREL", SDTIntBinOp>; 232 233def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 234def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>; 235def PPCxxspltidp : SDNode<"PPCISD::XXSPLTI_SP_TO_DP", SDT_PPCSpToDp, []>; 236def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>; 237def PPCxxpermdi : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>; 238def PPCvecshl : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>; 239 240def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>; 241 242// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 243// amounts. These nodes are generated by the multi-precision shift code. 244def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 245def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 246def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 247 248def PPCfnmsub : SDNode<"PPCISD::FNMSUB" , SDTFPTernaryOp>; 249 250def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>; 251 252def PPCstrict_fctidz : SDNode<"PPCISD::STRICT_FCTIDZ", 253 SDTFPUnaryOp, [SDNPHasChain]>; 254def PPCstrict_fctiwz : SDNode<"PPCISD::STRICT_FCTIWZ", 255 SDTFPUnaryOp, [SDNPHasChain]>; 256def PPCstrict_fctiduz : SDNode<"PPCISD::STRICT_FCTIDUZ", 257 SDTFPUnaryOp, [SDNPHasChain]>; 258def PPCstrict_fctiwuz : SDNode<"PPCISD::STRICT_FCTIWUZ", 259 SDTFPUnaryOp, [SDNPHasChain]>; 260 261def PPCany_fctidz : PatFrags<(ops node:$op), 262 [(PPCstrict_fctidz node:$op), 263 (PPCfctidz node:$op)]>; 264def PPCany_fctiwz : PatFrags<(ops node:$op), 265 [(PPCstrict_fctiwz node:$op), 266 (PPCfctiwz node:$op)]>; 267def PPCany_fctiduz : PatFrags<(ops node:$op), 268 [(PPCstrict_fctiduz node:$op), 269 (PPCfctiduz node:$op)]>; 270def PPCany_fctiwuz : PatFrags<(ops node:$op), 271 [(PPCstrict_fctiwuz node:$op), 272 (PPCfctiwuz node:$op)]>; 273 274// Move 2 i64 values into a VSX register 275def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128", 276 SDTypeProfile<1, 2, 277 [SDTCisFP<0>, SDTCisSameSizeAs<1,2>, 278 SDTCisSameAs<1,2>]>, 279 []>; 280 281def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64", 282 SDTypeProfile<1, 2, 283 [SDTCisVT<0, f64>, SDTCisVT<1,i32>, 284 SDTCisVT<1,i32>]>, 285 []>; 286 287def PPCextract_spe : SDNode<"PPCISD::EXTRACT_SPE", 288 SDTypeProfile<1, 2, 289 [SDTCisVT<0, i32>, SDTCisVT<1, f64>, 290 SDTCisPtrTy<2>]>, 291 []>; 292 293// These are target-independent nodes, but have target-specific formats. 294def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 295 [SDNPHasChain, SDNPOutGlue]>; 296def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 297 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 298 299def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 300def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 301 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 302 SDNPVariadic]>; 303def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 304 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 305 SDNPVariadic]>; 306def PPCcall_notoc : SDNode<"PPCISD::CALL_NOTOC", SDT_PPCCall, 307 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 308 SDNPVariadic]>; 309def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 310 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 311def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 312 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 313 SDNPVariadic]>; 314def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC", 315 SDTypeProfile<0, 1, []>, 316 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 317 SDNPVariadic]>; 318 319// Call nodes for strictfp calls (that define RM). 320def PPCcall_rm : SDNode<"PPCISD::CALL_RM", SDT_PPCCall, 321 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 322 SDNPVariadic]>; 323def PPCcall_nop_rm : SDNode<"PPCISD::CALL_NOP_RM", SDT_PPCCall, 324 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 325 SDNPVariadic]>; 326def PPCcall_notoc_rm : SDNode<"PPCISD::CALL_NOTOC_RM", SDT_PPCCall, 327 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 328 SDNPVariadic]>; 329def PPCbctrl_rm : SDNode<"PPCISD::BCTRL_RM", SDTNone, 330 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 331 SDNPVariadic]>; 332def PPCbctrl_load_toc_rm : SDNode<"PPCISD::BCTRL_LOAD_TOC_RM", 333 SDTypeProfile<0, 1, []>, 334 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 335 SDNPVariadic]>; 336 337def retglue : SDNode<"PPCISD::RET_GLUE", SDTNone, 338 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 339 340def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 341 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 342 343def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 344 SDTypeProfile<1, 1, [SDTCisInt<0>, 345 SDTCisPtrTy<1>]>, 346 [SDNPHasChain, SDNPSideEffect]>; 347def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 348 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 349 [SDNPHasChain, SDNPSideEffect]>; 350 351def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 352def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, 353 [SDNPHasChain, SDNPSideEffect]>; 354 355def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone, 356 [SDNPHasChain, SDNPSideEffect]>; 357def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>; 358def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc, 359 [SDNPHasChain, SDNPSideEffect]>; 360 361def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 362def PPCvcmp_rec : SDNode<"PPCISD::VCMP_rec", SDT_PPCvcmp, [SDNPOutGlue]>; 363 364def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 365 [SDNPHasChain, SDNPOptInGlue]>; 366 367// PPC-specific atomic operations. 368def PPCatomicCmpSwap_8 : 369 SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3, 370 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 371def PPCatomicCmpSwap_16 : 372 SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3, 373 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 374def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 375 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 376def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 377 [SDNPHasChain, SDNPMayStore]>; 378def PPCStoreCond : SDNode<"PPCISD::STORE_COND", SDT_StoreCond, 379 [SDNPHasChain, SDNPMayStore, 380 SDNPMemOperand, SDNPOutGlue]>; 381 382// Instructions to set/unset CR bit 6 for SVR4 vararg calls 383def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 384 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 385def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 386 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 387 388// Instructions to support dynamic alloca. 389def SDTDynOp : SDTypeProfile<1, 2, []>; 390def SDTDynAreaOp : SDTypeProfile<1, 1, []>; 391def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 392def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>; 393def PPCprobedalloca : SDNode<"PPCISD::PROBED_ALLOCA", SDTDynOp, [SDNPHasChain]>; 394 395// PC Relative Specific Nodes 396def PPCmatpcreladdr : SDNode<"PPCISD::MAT_PCREL_ADDR", SDTIntUnaryOp, []>; 397def PPCtlsdynamatpcreladdr : SDNode<"PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR", 398 SDTIntUnaryOp, []>; 399def PPCtlslocalexecmataddr : SDNode<"PPCISD::TLS_LOCAL_EXEC_MAT_ADDR", 400 SDTIntUnaryOp, []>; 401 402//===----------------------------------------------------------------------===// 403// PowerPC specific transformation functions and pattern fragments. 404// 405 406// A floating point immediate that is not a positive zero and can be converted 407// to a single precision floating point non-denormal immediate without loss of 408// information. 409def nzFPImmAsi32 : PatLeaf<(fpimm), [{ 410 APFloat APFloatOfN = N->getValueAPF(); 411 return convertToNonDenormSingle(APFloatOfN) && !N->isExactlyValue(+0.0); 412}]>; 413 414// A floating point immediate that is exactly an integer (for example 3.0, -5.0) 415// and can be represented in 5 bits (range of [-16, 15]). 416def nzFPImmExactInti5 : PatLeaf<(fpimm), [{ 417 APFloat FloatValue = N->getValueAPF(); 418 bool IsExact; 419 APSInt IntResult(16, false); 420 FloatValue.convertToInteger(IntResult, APFloat::rmTowardZero, &IsExact); 421 return IsExact && IntResult <= 15 && IntResult >= -16 && !FloatValue.isZero(); 422}]>; 423 424def getFPAs5BitExactInt : SDNodeXForm<fpimm, [{ 425 APFloat FloatValue = N->getValueAPF(); 426 bool IsExact; 427 APSInt IntResult(32, false); 428 FloatValue.convertToInteger(IntResult, APFloat::rmTowardZero, &IsExact); 429 return CurDAG->getTargetConstant(IntResult, SDLoc(N), MVT::i32); 430}]>; 431 432// Convert the floating point immediate into a 32 bit floating point immediate 433// and get a i32 with the resulting bits. 434def getFPAs32BitInt : SDNodeXForm<fpimm, [{ 435 APFloat APFloatOfN = N->getValueAPF(); 436 convertToNonDenormSingle(APFloatOfN); 437 return CurDAG->getTargetConstant(APFloatOfN.bitcastToAPInt().getZExtValue(), 438 SDLoc(N), MVT::i32); 439}]>; 440 441// Check if the value can be converted to be single precision immediate, which 442// can be exploited by XXSPLTIDP. Ensure that it cannot be converted to single 443// precision before exploiting with XXSPLTI32DX. 444def nzFPImmAsi64 : PatLeaf<(fpimm), [{ 445 APFloat APFloatOfN = N->getValueAPF(); 446 return !N->isExactlyValue(+0.0) && !checkConvertToNonDenormSingle(APFloatOfN); 447}]>; 448 449// Get the Hi bits of a 64 bit immediate. 450def getFPAs64BitIntHi : SDNodeXForm<fpimm, [{ 451 APFloat APFloatOfN = N->getValueAPF(); 452 bool Unused; 453 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 454 &Unused); 455 uint32_t Hi = (uint32_t)((APFloatOfN.bitcastToAPInt().getZExtValue() & 456 0xFFFFFFFF00000000LL) >> 32); 457 return CurDAG->getTargetConstant(Hi, SDLoc(N), MVT::i32); 458}]>; 459 460// Get the Lo bits of a 64 bit immediate. 461def getFPAs64BitIntLo : SDNodeXForm<fpimm, [{ 462 APFloat APFloatOfN = N->getValueAPF(); 463 bool Unused; 464 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 465 &Unused); 466 uint32_t Lo = (uint32_t)(APFloatOfN.bitcastToAPInt().getZExtValue() & 467 0xFFFFFFFF); 468 return CurDAG->getTargetConstant(Lo, SDLoc(N), MVT::i32); 469}]>; 470 471def imm34 : PatLeaf<(imm), [{ 472 return isInt<34>(N->getSExtValue()); 473}]>; 474 475def getImmAs64BitInt : SDNodeXForm<imm, [{ 476 return getI64Imm(N->getSExtValue(), SDLoc(N)); 477}]>; 478 479def SHL32 : SDNodeXForm<imm, [{ 480 // Transformation function: 31 - imm 481 return getI32Imm(31 - N->getZExtValue(), SDLoc(N)); 482}]>; 483 484def SRL32 : SDNodeXForm<imm, [{ 485 // Transformation function: 32 - imm 486 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N)) 487 : getI32Imm(0, SDLoc(N)); 488}]>; 489 490def LO16 : SDNodeXForm<imm, [{ 491 // Transformation function: get the low 16 bits. 492 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N)); 493}]>; 494 495def HI16 : SDNodeXForm<imm, [{ 496 // Transformation function: shift the immediate value down into the low bits. 497 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N)); 498}]>; 499 500def HA16 : SDNodeXForm<imm, [{ 501 // Transformation function: shift the immediate value down into the low bits. 502 int64_t Val = N->getZExtValue(); 503 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); 504}]>; 505def MB : SDNodeXForm<imm, [{ 506 // Transformation function: get the start bit of a mask 507 unsigned mb = 0, me; 508 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 509 return getI32Imm(mb, SDLoc(N)); 510}]>; 511 512def ME : SDNodeXForm<imm, [{ 513 // Transformation function: get the end bit of a mask 514 unsigned mb, me = 0; 515 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 516 return getI32Imm(me, SDLoc(N)); 517}]>; 518def maskimm32 : PatLeaf<(imm), [{ 519 // maskImm predicate - True if immediate is a run of ones. 520 unsigned mb, me; 521 if (N->getValueType(0) == MVT::i32) 522 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 523 else 524 return false; 525}]>; 526 527def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ 528 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 529 // sign extended field. Used by instructions like 'addi'. 530 return (int32_t)Imm == (short)Imm; 531}]>; 532def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ 533 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 534 // sign extended field. Used by instructions like 'addi'. 535 return (int64_t)Imm == (short)Imm; 536}]>; 537def immZExt16 : PatLeaf<(imm), [{ 538 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 539 // field. Used by instructions like 'ori'. 540 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 541}], LO16>; 542def immNonAllOneAnyExt8 : ImmLeaf<i32, [{ 543 return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF)); 544}]>; 545def i32immNonAllOneNonZero : ImmLeaf<i32, [{ return Imm && (Imm != -1); }]>; 546def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>; 547 548// imm16Shifted* - These match immediates where the low 16-bits are zero. There 549// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 550// identical in 32-bit mode, but in 64-bit mode, they return true if the 551// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 552// clear). 553def imm16ShiftedZExt : PatLeaf<(imm), [{ 554 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 555 // immediate are set. Used by instructions like 'xoris'. 556 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 557}], HI16>; 558 559def imm16ShiftedSExt : PatLeaf<(imm), [{ 560 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 561 // immediate are set. Used by instructions like 'addis'. Identical to 562 // imm16ShiftedZExt in 32-bit mode. 563 if (N->getZExtValue() & 0xFFFF) return false; 564 if (N->getValueType(0) == MVT::i32) 565 return true; 566 // For 64-bit, make sure it is sext right. 567 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 568}], HI16>; 569 570def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{ 571 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit 572 // zero extended field. 573 return isUInt<32>(Imm); 574}]>; 575 576// This is a somewhat weaker condition than actually checking for 4-byte 577// alignment. It is simply checking that the displacement can be represented 578// as an immediate that is a multiple of 4 (i.e. the requirements for DS-Form 579// instructions). 580// But some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 581// restricted memrix (4-aligned) constants are alignment sensitive. If these 582// offsets are hidden behind TOC entries than the values of the lower-order 583// bits cannot be checked directly. As a result, we need to also incorporate 584// an alignment check into the relevant patterns. 585 586def DSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 587 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlign() >= 4; 588}]>; 589def DSFormStore : PatFrag<(ops node:$val, node:$ptr), 590 (store node:$val, node:$ptr), [{ 591 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlign() >= 4; 592}]>; 593def DSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 594 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlign() >= 4; 595}]>; 596def DSFormPreStore : PatFrag< 597 (ops node:$val, node:$base, node:$offset), 598 (pre_store node:$val, node:$base, node:$offset), [{ 599 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlign() >= 4; 600}]>; 601 602def NonDSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 603 return cast<LoadSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4); 604}]>; 605def NonDSFormStore : PatFrag<(ops node:$val, node:$ptr), 606 (store node:$val, node:$ptr), [{ 607 return cast<StoreSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4); 608}]>; 609def NonDSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 610 return cast<LoadSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4); 611}]>; 612 613// This is a somewhat weaker condition than actually checking for 16-byte 614// alignment. It is simply checking that the displacement can be represented 615// as an immediate that is a multiple of 16 (i.e. the requirements for DQ-Form 616// instructions). 617def quadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 618 return isOffsetMultipleOf(N, 16); 619}]>; 620def quadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 621 (store node:$val, node:$ptr), [{ 622 return isOffsetMultipleOf(N, 16); 623}]>; 624def nonQuadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 625 return !isOffsetMultipleOf(N, 16); 626}]>; 627def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 628 (store node:$val, node:$ptr), [{ 629 return !isOffsetMultipleOf(N, 16); 630}]>; 631 632// PatFrag for binary operation whose operands are both non-constant 633class BinOpWithoutSImm16Operand<SDNode opcode> : 634 PatFrag<(ops node:$left, node:$right), (opcode node:$left, node:$right), [{ 635 int16_t Imm; 636 return !isIntS16Immediate(N->getOperand(0), Imm) 637 && !isIntS16Immediate(N->getOperand(1), Imm); 638}]>; 639 640def add_without_simm16 : BinOpWithoutSImm16Operand<add>; 641def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>; 642 643//===----------------------------------------------------------------------===// 644// PowerPC Flag Definitions. 645 646class isPPC64 { bit PPC64 = 1; } 647class isRecordForm { bit RC = 1; } 648 649class RegConstraint<string C> { 650 string Constraints = C; 651} 652class NoEncode<string E> { 653 string DisableEncoding = E; 654} 655 656 657// Define PowerPC specific addressing mode. 658 659// d-form 660def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; // "stb" 661// ds-form 662def iaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" 663// dq-form 664def iaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrImmX16", [], []>; // "stxv" 665// 8LS:d-form 666def iaddrX34 : ComplexPattern<iPTR, 2, "SelectAddrImmX34", [], []>; // "pstxvp" 667 668// Below forms are all x-form addressing mode, use three different ones so we 669// can make a accurate check for x-form instructions in ISEL. 670// x-form addressing mode whose associated displacement form is D. 671def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; // "stbx" 672// x-form addressing mode whose associated displacement form is DS. 673def xaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrIdxX4", [], []>; // "stdx" 674// x-form addressing mode whose associated displacement form is DQ. 675def xaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrIdxX16", [], []>; // "stxvx" 676 677def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 678 679// The address in a single register. This is used with the SjLj 680// pseudo-instructions. 681def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 682 683/// This is just the offset part of iaddr, used for preinc. 684def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 685 686// Load and Store Instruction Selection addressing modes. 687def DForm : ComplexPattern<iPTR, 2, "SelectDForm", [], [SDNPWantParent]>; 688def DSForm : ComplexPattern<iPTR, 2, "SelectDSForm", [], [SDNPWantParent]>; 689def DQForm : ComplexPattern<iPTR, 2, "SelectDQForm", [], [SDNPWantParent]>; 690def XForm : ComplexPattern<iPTR, 2, "SelectXForm", [], [SDNPWantParent]>; 691def ForceXForm : ComplexPattern<iPTR, 2, "SelectForceXForm", [], [SDNPWantParent]>; 692def PCRelForm : ComplexPattern<iPTR, 2, "SelectPCRelForm", [], [SDNPWantParent]>; 693def PDForm : ComplexPattern<iPTR, 2, "SelectPDForm", [], [SDNPWantParent]>; 694 695//===----------------------------------------------------------------------===// 696// PowerPC Instruction Predicate Definitions. 697def In32BitMode : Predicate<"!Subtarget->isPPC64()">; 698def In64BitMode : Predicate<"Subtarget->isPPC64()">; 699def IsBookE : Predicate<"Subtarget->isBookE()">; 700def IsNotBookE : Predicate<"!Subtarget->isBookE()">; 701def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">; 702def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">; 703def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">; 704def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">; 705def IsE500 : Predicate<"Subtarget->isE500()">; 706def HasSPE : Predicate<"Subtarget->hasSPE()">; 707def HasICBT : Predicate<"Subtarget->hasICBT()">; 708def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">; 709def HasQuadwordAtomics : Predicate<"Subtarget->hasQuadwordAtomics()">; 710def NoNaNsFPMath 711 : Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 712def NaNsFPMath 713 : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 714def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; 715def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; 716def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">; 717def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">; 718def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">; 719def HasFPU : Predicate<"Subtarget->hasFPU()">; 720def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">; 721def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">; 722 723// AIX assembler may not be modern enough to support some extended mne. 724def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">, 725 AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>; 726def IsAIX : Predicate<"Subtarget->isAIXABI()">; 727def NotAIX : Predicate<"!Subtarget->isAIXABI()">; 728def IsISAFuture : Predicate<"Subtarget->isISAFuture()">; 729def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">; 730 731//===----------------------------------------------------------------------===// 732// PowerPC Multiclass Definitions. 733multiclass XForm_base_r3xo_r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 734 string asmbase, string asmstr, list<dag> pattern> { 735 let BaseName = asmbase in { 736 def NAME : XForm_base_r3xo<opcode, xo, OOL, IOL, 737 !strconcat(asmbase, !strconcat(" ", asmstr)), 738 NoItinerary, pattern>, RecFormRel; 739 let Defs = [CR1] in 740 def _rec : XForm_base_r3xo<opcode, xo, OOL, IOL, 741 !strconcat(asmbase, !strconcat(". ", asmstr)), 742 NoItinerary, []>, isRecordForm, RecFormRel; 743 } 744} 745 746multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 747 string asmbase, string asmstr, InstrItinClass itin, 748 list<dag> pattern> { 749 let BaseName = asmbase in { 750 def NAME : XForm_6<opcode, xo, OOL, IOL, 751 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 752 pattern>, RecFormRel; 753 let Defs = [CR0] in 754 def _rec : XForm_6<opcode, xo, OOL, IOL, 755 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 756 []>, isRecordForm, RecFormRel; 757 } 758} 759 760multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 761 string asmbase, string asmstr, InstrItinClass itin, 762 list<dag> pattern> { 763 let BaseName = asmbase in { 764 let Defs = [CARRY] in 765 def NAME : XForm_6<opcode, xo, OOL, IOL, 766 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 767 pattern>, RecFormRel; 768 let Defs = [CARRY, CR0] in 769 def _rec : XForm_6<opcode, xo, OOL, IOL, 770 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 771 []>, isRecordForm, RecFormRel; 772 } 773} 774 775multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 776 string asmbase, string asmstr, InstrItinClass itin, 777 list<dag> pattern> { 778 let BaseName = asmbase in { 779 let Defs = [CARRY] in 780 def NAME : XForm_10<opcode, xo, OOL, IOL, 781 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 782 pattern>, RecFormRel; 783 let Defs = [CARRY, CR0] in 784 def _rec : XForm_10<opcode, xo, OOL, IOL, 785 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 786 []>, isRecordForm, RecFormRel; 787 } 788} 789 790multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 791 string asmbase, string asmstr, InstrItinClass itin, 792 list<dag> pattern> { 793 let BaseName = asmbase in { 794 def NAME : XForm_11<opcode, xo, OOL, IOL, 795 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 796 pattern>, RecFormRel; 797 let Defs = [CR0] in 798 def _rec : XForm_11<opcode, xo, OOL, IOL, 799 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 800 []>, isRecordForm, RecFormRel; 801 } 802} 803 804multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 805 string asmbase, string asmstr, InstrItinClass itin, 806 list<dag> pattern> { 807 let BaseName = asmbase in { 808 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 809 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 810 pattern>, RecFormRel; 811 let Defs = [CR0] in 812 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 813 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 814 []>, isRecordForm, RecFormRel; 815 } 816} 817 818// Multiclass for instructions which have a record overflow form as well 819// as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.) 820multiclass XOForm_1rx<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 821 string asmbase, string asmstr, InstrItinClass itin, 822 list<dag> pattern> { 823 let BaseName = asmbase in { 824 def NAME : XOForm_1<opcode, xo, 0, OOL, IOL, 825 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 826 pattern>, RecFormRel; 827 let Defs = [CR0] in 828 def _rec : XOForm_1<opcode, xo, 0, OOL, IOL, 829 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 830 []>, isRecordForm, RecFormRel; 831 } 832 let BaseName = !strconcat(asmbase, "O") in { 833 let Defs = [XER] in 834 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 835 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 836 []>, RecFormRel; 837 let Defs = [XER, CR0] in 838 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 839 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 840 []>, isRecordForm, RecFormRel; 841 } 842} 843 844// Multiclass for instructions for which the non record form is not cracked 845// and the record form is cracked (i.e. divw, mullw, etc.) 846multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 847 string asmbase, string asmstr, InstrItinClass itin, 848 list<dag> pattern> { 849 let BaseName = asmbase in { 850 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 851 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 852 pattern>, RecFormRel; 853 let Defs = [CR0] in 854 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 855 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 856 []>, isRecordForm, RecFormRel, PPC970_DGroup_First, 857 PPC970_DGroup_Cracked; 858 } 859 let BaseName = !strconcat(asmbase, "O") in { 860 let Defs = [XER] in 861 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 862 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 863 []>, RecFormRel; 864 let Defs = [XER, CR0] in 865 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 866 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 867 []>, isRecordForm, RecFormRel; 868 } 869} 870 871multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 872 string asmbase, string asmstr, InstrItinClass itin, 873 list<dag> pattern> { 874 let BaseName = asmbase in { 875 let Defs = [CARRY] in 876 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 877 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 878 pattern>, RecFormRel; 879 let Defs = [CARRY, CR0] in 880 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 881 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 882 []>, isRecordForm, RecFormRel; 883 } 884 let BaseName = !strconcat(asmbase, "O") in { 885 let Defs = [CARRY, XER] in 886 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 887 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 888 []>, RecFormRel; 889 let Defs = [CARRY, XER, CR0] in 890 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 891 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 892 []>, isRecordForm, RecFormRel; 893 } 894} 895 896multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 897 string asmbase, string asmstr, InstrItinClass itin, 898 list<dag> pattern> { 899 let BaseName = asmbase in { 900 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 901 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 902 pattern>, RecFormRel; 903 let Defs = [CR0] in 904 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 905 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 906 []>, isRecordForm, RecFormRel; 907 } 908 let BaseName = !strconcat(asmbase, "O") in { 909 let Defs = [XER] in 910 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 911 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 912 []>, RecFormRel; 913 let Defs = [XER, CR0] in 914 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 915 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 916 []>, isRecordForm, RecFormRel; 917 } 918} 919 920multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 921 string asmbase, string asmstr, InstrItinClass itin, 922 list<dag> pattern> { 923 let BaseName = asmbase in { 924 let Defs = [CARRY] in 925 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 926 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 927 pattern>, RecFormRel; 928 let Defs = [CARRY, CR0] in 929 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 930 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 931 []>, isRecordForm, RecFormRel; 932 } 933 let BaseName = !strconcat(asmbase, "O") in { 934 let Defs = [CARRY, XER] in 935 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 936 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 937 []>, RecFormRel; 938 let Defs = [CARRY, XER, CR0] in 939 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 940 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 941 []>, isRecordForm, RecFormRel; 942 } 943} 944 945multiclass MForm_1r<bits<6> opcode, dag OOL, dag IOL, 946 string asmbase, string asmstr, InstrItinClass itin, 947 list<dag> pattern> { 948 let BaseName = asmbase in { 949 def NAME : MForm_1<opcode, OOL, IOL, 950 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 951 pattern>, RecFormRel; 952 let Defs = [CR0] in 953 def _rec : MForm_1<opcode, OOL, IOL, 954 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 955 []>, isRecordForm, RecFormRel; 956 } 957} 958 959multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 960 string asmbase, string asmstr, InstrItinClass itin, 961 list<dag> pattern> { 962 let BaseName = asmbase in { 963 def NAME : MForm_2<opcode, OOL, IOL, 964 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 965 pattern>, RecFormRel; 966 let Defs = [CR0] in 967 def _rec : MForm_2<opcode, OOL, IOL, 968 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 969 []>, isRecordForm, RecFormRel; 970 } 971} 972 973multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 974 string asmbase, string asmstr, InstrItinClass itin, 975 list<dag> pattern> { 976 let BaseName = asmbase in { 977 def NAME : MDForm_1<opcode, xo, OOL, IOL, 978 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 979 pattern>, RecFormRel; 980 let Defs = [CR0] in 981 def _rec : MDForm_1<opcode, xo, OOL, IOL, 982 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 983 []>, isRecordForm, RecFormRel; 984 } 985} 986 987multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 988 string asmbase, string asmstr, InstrItinClass itin, 989 list<dag> pattern> { 990 let BaseName = asmbase in { 991 def NAME : MDSForm_1<opcode, xo, OOL, IOL, 992 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 993 pattern>, RecFormRel; 994 let Defs = [CR0] in 995 def _rec : MDSForm_1<opcode, xo, OOL, IOL, 996 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 997 []>, isRecordForm, RecFormRel; 998 } 999} 1000 1001multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1002 string asmbase, string asmstr, InstrItinClass itin, 1003 list<dag> pattern> { 1004 let BaseName = asmbase in { 1005 let Defs = [CARRY] in 1006 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1007 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1008 pattern>, RecFormRel; 1009 let Defs = [CARRY, CR0] in 1010 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1011 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1012 []>, isRecordForm, RecFormRel; 1013 } 1014} 1015 1016multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1017 string asmbase, string asmstr, InstrItinClass itin, 1018 list<dag> pattern> { 1019 let BaseName = asmbase in { 1020 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1021 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1022 pattern>, RecFormRel; 1023 let Defs = [CR0] in 1024 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1025 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1026 []>, isRecordForm, RecFormRel; 1027 } 1028} 1029 1030multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1031 string asmbase, string asmstr, InstrItinClass itin, 1032 list<dag> pattern> { 1033 let BaseName = asmbase in { 1034 def NAME : XForm_26<opcode, xo, OOL, IOL, 1035 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1036 pattern>, RecFormRel; 1037 let Defs = [CR1] in 1038 def _rec : XForm_26<opcode, xo, OOL, IOL, 1039 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1040 []>, isRecordForm, RecFormRel; 1041 } 1042} 1043 1044multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1045 string asmbase, string asmstr, InstrItinClass itin, 1046 list<dag> pattern> { 1047 let BaseName = asmbase in { 1048 def NAME : XForm_28<opcode, xo, OOL, IOL, 1049 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1050 pattern>, RecFormRel; 1051 let Defs = [CR1] in 1052 def _rec : XForm_28<opcode, xo, OOL, IOL, 1053 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1054 []>, isRecordForm, RecFormRel; 1055 } 1056} 1057 1058multiclass XForm_SP2_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1059 string asmbase, string asmstr, list<dag> pattern> { 1060 let BaseName = asmbase in { 1061 def NAME : XForm_SP2_FRTB5<opcode, xo, OOL, IOL, 1062 !strconcat(asmbase, !strconcat(" ", asmstr)), 1063 pattern, NoItinerary>, RecFormRel; 1064 let Defs = [CR1] in 1065 def _rec : XForm_SP2_FRTB5<opcode, xo, OOL, IOL, 1066 !strconcat(asmbase, !strconcat(". ", asmstr)), 1067 [], NoItinerary>, isRecordForm, RecFormRel; 1068 } 1069} 1070 1071multiclass XForm_S1_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1072 string asmbase, string asmstr, list<dag> pattern> { 1073 let BaseName = asmbase in { 1074 def NAME : XForm_S1_FRTB5<opcode, xo, OOL, IOL, 1075 !strconcat(asmbase, !strconcat(" ", asmstr)), 1076 pattern, NoItinerary>, RecFormRel; 1077 let Defs = [CR1] in 1078 def _rec : XForm_S1_FRTB5<opcode, xo, OOL, IOL, 1079 !strconcat(asmbase, !strconcat(". ", asmstr)), [], 1080 NoItinerary>, isRecordForm, RecFormRel; 1081 } 1082} 1083 1084multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1085 string asmbase, string asmstr, InstrItinClass itin, 1086 list<dag> pattern> { 1087 let BaseName = asmbase in { 1088 def NAME : AForm_1<opcode, xo, OOL, IOL, 1089 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1090 pattern>, RecFormRel; 1091 let Defs = [CR1] in 1092 def _rec : AForm_1<opcode, xo, OOL, IOL, 1093 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1094 []>, isRecordForm, RecFormRel; 1095 } 1096} 1097 1098multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1099 string asmbase, string asmstr, InstrItinClass itin, 1100 list<dag> pattern> { 1101 let BaseName = asmbase in { 1102 def NAME : AForm_2<opcode, xo, OOL, IOL, 1103 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1104 pattern>, RecFormRel; 1105 let Defs = [CR1] in 1106 def _rec : AForm_2<opcode, xo, OOL, IOL, 1107 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1108 []>, isRecordForm, RecFormRel; 1109 } 1110} 1111 1112multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1113 string asmbase, string asmstr, InstrItinClass itin, 1114 list<dag> pattern> { 1115 let BaseName = asmbase in { 1116 def NAME : AForm_3<opcode, xo, OOL, IOL, 1117 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1118 pattern>, RecFormRel; 1119 let Defs = [CR1] in 1120 def _rec : AForm_3<opcode, xo, OOL, IOL, 1121 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1122 []>, isRecordForm, RecFormRel; 1123 } 1124} 1125 1126multiclass 1127 Z23Form_TE5_FRTB5_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1128 string asmbase, string asmstr, list<dag> pattern> { 1129 let BaseName = asmbase in { 1130 def NAME 1131 : Z23Form_TE5_FRTB5_RMC2<opcode, xo, OOL, IOL, 1132 !strconcat(asmbase, !strconcat(" ", asmstr)), 1133 pattern>, RecFormRel; 1134 let Defs = [CR0] in 1135 def _rec : Z23Form_TE5_FRTB5_RMC2<opcode, xo, OOL, IOL, 1136 !strconcat(asmbase, !strconcat(". ", asmstr)), 1137 []>, isRecordForm, RecFormRel; 1138 } 1139} 1140 1141multiclass 1142 Z23Form_FRTAB5_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1143 string asmbase, string asmstr, list<dag> pattern> { 1144 let BaseName = asmbase in { 1145 def NAME : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL, 1146 !strconcat(asmbase, !strconcat(" ", asmstr)), 1147 pattern>, RecFormRel; 1148 let Defs = [CR1] in 1149 def _rec : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL, 1150 !strconcat(asmbase, !strconcat(". ", asmstr)), 1151 []>, isRecordForm, RecFormRel; 1152 } 1153} 1154 1155multiclass 1156 Z23Form_FRTB5_R1_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1157 string asmbase, string asmstr, list<dag> pattern> { 1158 let BaseName = asmbase in { 1159 def NAME : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL, 1160 !strconcat(asmbase, !strconcat(" ", asmstr)), 1161 pattern>, RecFormRel; 1162 let Defs = [CR1] in 1163 def _rec : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL, 1164 !strconcat(asmbase, !strconcat(". ", asmstr)), 1165 []>, isRecordForm, RecFormRel; 1166 } 1167} 1168 1169multiclass Z22Form_FRTA5_SH6r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1170 string asmbase, string asmstr, list<dag> pattern> { 1171 let BaseName = asmbase in { 1172 def NAME : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL, 1173 !strconcat(asmbase, !strconcat(" ", asmstr)), 1174 pattern, NoItinerary>, RecFormRel; 1175 let Defs = [CR1] in 1176 def _rec : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL, 1177 !strconcat(asmbase, !strconcat(". ", asmstr)), 1178 [], NoItinerary>, isRecordForm, RecFormRel; 1179 } 1180} 1181 1182//===----------------------------------------------------------------------===// 1183// END OF MULTICLASS DEFINITIONS 1184//===----------------------------------------------------------------------===// 1185 1186//===----------------------------------------------------------------------===// 1187// PowerPC Instruction Definitions. 1188 1189// Pseudo instructions: 1190 1191let hasCtrlDep = 1 in { 1192let Defs = [R1], Uses = [R1] in { 1193def ADJCALLSTACKDOWN : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1194 "#ADJCALLSTACKDOWN $amt1 $amt2", 1195 [(callseq_start timm:$amt1, timm:$amt2)]>; 1196def ADJCALLSTACKUP : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1197 "#ADJCALLSTACKUP $amt1 $amt2", 1198 [(callseq_end timm:$amt1, timm:$amt2)]>; 1199} 1200} // hasCtrlDep 1201 1202let Defs = [R1], Uses = [R1] in 1203def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", 1204 [(set i32:$result, 1205 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 1206def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET", 1207 [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 1208// Probed alloca to support stack clash protection. 1209let Defs = [R1], Uses = [R1], hasNoSchedulingInfo = 1 in { 1210def PROBED_ALLOCA_32 : PPCCustomInserterPseudo<(outs gprc:$result), 1211 (ins gprc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_32", 1212 [(set i32:$result, 1213 (PPCprobedalloca i32:$negsize, iaddr:$fpsi))]>; 1214def PREPARE_PROBED_ALLOCA_32 : PPCEmitTimePseudo<(outs 1215 gprc:$fp, gprc:$actual_negsize), 1216 (ins gprc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_32", []>; 1217def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 : PPCEmitTimePseudo<(outs 1218 gprc:$fp, gprc:$actual_negsize), 1219 (ins gprc:$negsize, memri:$fpsi), 1220 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32", []>, 1221 RegConstraint<"$actual_negsize = $negsize">; 1222def PROBED_STACKALLOC_32 : PPCEmitTimePseudo<(outs gprc:$scratch, gprc:$temp), 1223 (ins i64imm:$stacksize), 1224 "#PROBED_STACKALLOC_32", []>; 1225} 1226 1227// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 1228// instruction selection into a branch sequence. 1229let PPC970_Single = 1 in { 1230 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 1231 // because either operand might become the first operand in an isel, and 1232 // that operand cannot be r0. 1233 def SELECT_CC_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crrc:$cond, 1234 gprc_nor0:$T, gprc_nor0:$F, 1235 i32imm:$BROPC), "#SELECT_CC_I4", 1236 []>; 1237 def SELECT_CC_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crrc:$cond, 1238 g8rc_nox0:$T, g8rc_nox0:$F, 1239 i32imm:$BROPC), "#SELECT_CC_I8", 1240 []>; 1241 def SELECT_CC_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, 1242 i32imm:$BROPC), "#SELECT_CC_F4", 1243 []>; 1244 def SELECT_CC_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, 1245 i32imm:$BROPC), "#SELECT_CC_F8", 1246 []>; 1247 def SELECT_CC_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1248 i32imm:$BROPC), "#SELECT_CC_F16", 1249 []>; 1250 def SELECT_CC_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1251 i32imm:$BROPC), "#SELECT_CC_VRRC", 1252 []>; 1253 1254 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition 1255 // register bit directly. 1256 def SELECT_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crbitrc:$cond, 1257 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", 1258 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; 1259 def SELECT_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crbitrc:$cond, 1260 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", 1261 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; 1262let Predicates = [HasFPU] in { 1263 def SELECT_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crbitrc:$cond, 1264 f4rc:$T, f4rc:$F), "#SELECT_F4", 1265 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; 1266 def SELECT_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crbitrc:$cond, 1267 f8rc:$T, f8rc:$F), "#SELECT_F8", 1268 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; 1269 def SELECT_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1270 vrrc:$T, vrrc:$F), "#SELECT_F16", 1271 [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>; 1272} 1273 def SELECT_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1274 vrrc:$T, vrrc:$F), "#SELECT_VRRC", 1275 [(set v4i32:$dst, 1276 (select i1:$cond, v4i32:$T, v4i32:$F))]>; 1277} 1278 1279// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 1280// scavenge a register for it. 1281let mayStore = 1 in { 1282def SPILL_CR : PPCEmitTimePseudo<(outs), (ins crrc:$cond, memri:$F), 1283 "#SPILL_CR", []>; 1284def SPILL_CRBIT : PPCEmitTimePseudo<(outs), (ins crbitrc:$cond, memri:$F), 1285 "#SPILL_CRBIT", []>; 1286} 1287 1288// RESTORE_CR - Indicate that we're restoring the CR register (previously 1289// spilled), so we'll need to scavenge a register for it. 1290let mayLoad = 1 in { 1291def RESTORE_CR : PPCEmitTimePseudo<(outs crrc:$cond), (ins memri:$F), 1292 "#RESTORE_CR", []>; 1293def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F), 1294 "#RESTORE_CRBIT", []>; 1295} 1296 1297let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 1298 let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in 1299 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 1300 [(retglue)]>, Requires<[In32BitMode]>; 1301 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 1302 let isPredicable = 1 in 1303 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1304 []>; 1305 1306 let isCodeGenOnly = 1 in { 1307 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond), 1308 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 1309 []>; 1310 1311 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI), 1312 "bcctr 12, $BI, 0", IIC_BrB, []>; 1313 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI), 1314 "bcctr 4, $BI, 0", IIC_BrB, []>; 1315 } 1316 } 1317} 1318 1319// Set the float rounding mode. 1320let Uses = [RM], Defs = [RM] in { 1321def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND), 1322 "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>; 1323 1324def SETRND : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins gprc:$in), 1325 "#SETRND", [(set f64:$FRT, (int_ppc_setrnd gprc :$in))]>; 1326 1327def SETFLM : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FLM), 1328 "#SETFLM", [(set f64:$FRT, (int_ppc_setflm f8rc:$FLM))]>; 1329} 1330 1331let isBarrier = 1, hasSideEffects = 1, Defs = [RM] in 1332def FENCE : PPCEmitTimePseudo<(outs), (ins), "#FENCE", []>; 1333 1334let Defs = [LR] in 1335 def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>, 1336 PPC970_Unit_BRU; 1337let Defs = [LR] in 1338 def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>, 1339 PPC970_Unit_BRU; 1340 1341let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1342 hasSideEffects = 0 in { 1343 let isBarrier = 1 in { 1344 let isPredicable = 1 in 1345 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$LI), 1346 "b $LI", IIC_BrB, 1347 [(br bb:$LI)]>; 1348 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$LI), 1349 "ba $LI", IIC_BrB, []>; 1350 } 1351 1352 // BCC represents an arbitrary conditional branch on a predicate. 1353 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 1354 // a two-value operand where a dag node expects two operands. :( 1355 let isCodeGenOnly = 1 in { 1356 class BCC_class : BForm<16, 0, 0, (outs), (ins (pred $BIBO, $CR):$cond, condbrtarget:$BD), 1357 "b${cond:cc}${cond:pm} ${cond:reg}, $BD" 1358 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$BD)]*/>; 1359 def BCC : BCC_class; 1360 1361 // The same as BCC, except that it's not a terminator. Used for introducing 1362 // control flow dependency without creating new blocks. 1363 let isTerminator = 0 in def CTRL_DEP : BCC_class; 1364 1365 def BCCA : BForm<16, 1, 0, (outs), (ins (pred $BIBO, $CR):$cond, abscondbrtarget:$BD), 1366 "b${cond:cc}a${cond:pm} ${cond:reg}, $BD">; 1367 1368 let isReturn = 1, Uses = [LR, RM] in 1369 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins (pred $BIBO, $CR):$cond), 1370 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; 1371 } 1372 1373 let isCodeGenOnly = 1 in { 1374 let Pattern = [(brcond i1:$BI, bb:$BD)] in 1375 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD), 1376 "bc 12, $BI, $BD">; 1377 1378 let Pattern = [(brcond (not i1:$BI), bb:$BD)] in 1379 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD), 1380 "bc 4, $BI, $BD">; 1381 1382 let isReturn = 1, Uses = [LR, RM] in { 1383 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$BI), 1384 "bclr 12, $BI, 0", IIC_BrB, []>; 1385 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$BI), 1386 "bclr 4, $BI, 0", IIC_BrB, []>; 1387 } 1388 } 1389 1390 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 1391 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 1392 "bdzlr", IIC_BrB, []>; 1393 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 1394 "bdnzlr", IIC_BrB, []>; 1395 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), 1396 "bdzlr+", IIC_BrB, []>; 1397 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), 1398 "bdnzlr+", IIC_BrB, []>; 1399 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), 1400 "bdzlr-", IIC_BrB, []>; 1401 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), 1402 "bdnzlr-", IIC_BrB, []>; 1403 } 1404 1405 let Defs = [CTR], Uses = [CTR] in { 1406 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$BD), 1407 "bdz $BD">; 1408 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$BD), 1409 "bdnz $BD">; 1410 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$BD), 1411 "bdza $BD">; 1412 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$BD), 1413 "bdnza $BD">; 1414 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$BD), 1415 "bdz+ $BD">; 1416 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$BD), 1417 "bdnz+ $BD">; 1418 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$BD), 1419 "bdza+ $BD">; 1420 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$BD), 1421 "bdnza+ $BD">; 1422 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$BD), 1423 "bdz- $BD">; 1424 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$BD), 1425 "bdnz- $BD">; 1426 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$BD), 1427 "bdza- $BD">; 1428 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$BD), 1429 "bdnza- $BD">; 1430 } 1431} 1432 1433// The unconditional BCL used by the SjLj setjmp code. 1434let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7, 1435 hasSideEffects = 0 in { 1436 let Defs = [LR], Uses = [RM] in { 1437 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$BD), 1438 "bcl 20, 31, $BD">; 1439 } 1440} 1441 1442let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 1443 // Convenient aliases for call instructions 1444 let Uses = [RM] in { 1445 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$LI), 1446 "bl $LI", IIC_BrB, []>; // See Pat patterns below. 1447 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), 1448 "bla $LI", IIC_BrB, [(PPCcall (i32 imm:$LI))]>; 1449 1450 let isCodeGenOnly = 1 in { 1451 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$LI), 1452 "bl $LI", IIC_BrB, []>; 1453 def BCCL : BForm<16, 0, 1, (outs), (ins (pred $BIBO, $CR):$cond, condbrtarget:$BD), 1454 "b${cond:cc}l${cond:pm} ${cond:reg}, $BD">; 1455 def BCCLA : BForm<16, 1, 1, (outs), (ins (pred $BIBO, $CR):$cond, abscondbrtarget:$BD), 1456 "b${cond:cc}la${cond:pm} ${cond:reg}, $BD">; 1457 1458 def BCL : BForm_4<16, 12, 0, 1, (outs), 1459 (ins crbitrc:$BI, condbrtarget:$BD), 1460 "bcl 12, $BI, $BD">; 1461 def BCLn : BForm_4<16, 4, 0, 1, (outs), 1462 (ins crbitrc:$BI, condbrtarget:$BD), 1463 "bcl 4, $BI, $BD">; 1464 def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 1465 (outs), (ins calltarget:$LI), 1466 "bl $LI\n\tnop", IIC_BrB, []>; 1467 } 1468 } 1469 let Uses = [CTR, RM] in { 1470 let isPredicable = 1 in 1471 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1472 "bctrl", IIC_BrB, [(PPCbctrl)]>, 1473 Requires<[In32BitMode]>; 1474 1475 let isCodeGenOnly = 1 in { 1476 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond), 1477 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 1478 []>; 1479 1480 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI), 1481 "bcctrl 12, $BI, 0", IIC_BrB, []>; 1482 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI), 1483 "bcctrl 4, $BI, 0", IIC_BrB, []>; 1484 } 1485 } 1486 let Uses = [LR, RM] in { 1487 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), 1488 "blrl", IIC_BrB, []>; 1489 1490 let isCodeGenOnly = 1 in { 1491 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins (pred $BIBO, $CR):$cond), 1492 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, 1493 []>; 1494 1495 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$BI), 1496 "bclrl 12, $BI, 0", IIC_BrB, []>; 1497 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$BI), 1498 "bclrl 4, $BI, 0", IIC_BrB, []>; 1499 } 1500 } 1501 let Defs = [CTR], Uses = [CTR, RM] in { 1502 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$BD), 1503 "bdzl $BD">; 1504 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$BD), 1505 "bdnzl $BD">; 1506 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$BD), 1507 "bdzla $BD">; 1508 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$BD), 1509 "bdnzla $BD">; 1510 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$BD), 1511 "bdzl+ $BD">; 1512 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$BD), 1513 "bdnzl+ $BD">; 1514 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$BD), 1515 "bdzla+ $BD">; 1516 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$BD), 1517 "bdnzla+ $BD">; 1518 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$BD), 1519 "bdzl- $BD">; 1520 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$BD), 1521 "bdnzl- $BD">; 1522 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$BD), 1523 "bdzla- $BD">; 1524 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$BD), 1525 "bdnzla- $BD">; 1526 } 1527 let Defs = [CTR], Uses = [CTR, LR, RM] in { 1528 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), 1529 "bdzlrl", IIC_BrB, []>; 1530 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), 1531 "bdnzlrl", IIC_BrB, []>; 1532 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), 1533 "bdzlrl+", IIC_BrB, []>; 1534 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), 1535 "bdnzlrl+", IIC_BrB, []>; 1536 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), 1537 "bdzlrl-", IIC_BrB, []>; 1538 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), 1539 "bdnzlrl-", IIC_BrB, []>; 1540 } 1541} 1542 1543let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in { 1544 // Convenient aliases for call instructions 1545 let Uses = [RM] in { 1546 def BL_RM : IForm<18, 0, 1, (outs), (ins calltarget:$LI), 1547 "bl $LI", IIC_BrB, []>; // See Pat patterns below. 1548 def BLA_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), 1549 "bla $LI", IIC_BrB, [(PPCcall_rm (i32 imm:$LI))]>; 1550 1551 def BL_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, 1552 (outs), (ins calltarget:$LI), 1553 "bl $LI\n\tnop", IIC_BrB, []>; 1554 } 1555 let Uses = [CTR, RM] in { 1556 let isPredicable = 1 in 1557 def BCTRL_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1558 "bctrl", IIC_BrB, [(PPCbctrl_rm)]>, 1559 Requires<[In32BitMode]>; 1560 } 1561} 1562 1563let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1564def TCRETURNdi :PPCEmitTimePseudo< (outs), 1565 (ins calltarget:$dst, i32imm:$offset), 1566 "#TC_RETURNd $dst $offset", 1567 []>; 1568 1569 1570let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1571def TCRETURNai :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 1572 "#TC_RETURNa $func $offset", 1573 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 1574 1575let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1576def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 1577 "#TC_RETURNr $dst $offset", 1578 []>; 1579 1580let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1581 Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in { 1582 def BCTRL_LWZinto_toc: 1583 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1584 (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB, 1585 [(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[In32BitMode]>; 1586 1587} 1588 1589let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1590 Defs = [LR, R2, RM], Uses = [CTR, RM], RST = 2 in { 1591 def BCTRL_LWZinto_toc_RM: 1592 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1593 (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB, 1594 [(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[In32BitMode]>; 1595 1596} 1597 1598let isCodeGenOnly = 1, hasSideEffects = 0 in { 1599 1600let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 1601 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 1602def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1603 []>, Requires<[In32BitMode]>; 1604 1605let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1606 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1607def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$LI), 1608 "b $LI", IIC_BrB, 1609 []>; 1610 1611let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1612 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1613def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$LI), 1614 "ba $LI", IIC_BrB, 1615 []>; 1616 1617} 1618 1619// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 1620// is not. 1621let hasSideEffects = 1 in { 1622 let Defs = [CTR] in 1623 def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 1624 "#EH_SJLJ_SETJMP32", 1625 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 1626 Requires<[In32BitMode]>; 1627} 1628 1629let hasSideEffects = 1, isBarrier = 1 in { 1630 let isTerminator = 1 in 1631 def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 1632 "#EH_SJLJ_LONGJMP32", 1633 [(PPCeh_sjlj_longjmp addr:$buf)]>, 1634 Requires<[In32BitMode]>; 1635} 1636 1637// This pseudo is never removed from the function, as it serves as 1638// a terminator. Size is set to 0 to prevent the builtin assembler 1639// from emitting it. 1640let isBranch = 1, isTerminator = 1, Size = 0 in { 1641 def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst), 1642 "#EH_SjLj_Setup\t$dst", []>; 1643} 1644 1645// System call. 1646let PPC970_Unit = 7 in { 1647 def SC : SCForm<17, 1, 0, (outs), (ins i32imm:$LEV), 1648 "sc $LEV", IIC_BrB, [(PPCsc (i32 imm:$LEV))]>; 1649} 1650 1651// We mark SCV as having no scheduling model since it is only meant to be used 1652// as inline assembly. If we implement a builtin pattern for it we will need to 1653// add it to the P9 and P10 scheduling models. 1654let Predicates = [IsISA3_0], hasNoSchedulingInfo = 1 in { 1655 def SCV : SCForm<17, 0, 1, (outs), (ins i32imm:$LEV), 1656 "scv $LEV", IIC_BrB, []>; 1657} 1658 1659// Branch history rolling buffer. 1660def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, 1661 [(PPCclrbhrb)]>, 1662 PPC970_DGroup_Single; 1663// The $dmy argument used for MFBHRBE is not needed; however, including 1664// it avoids automatic generation of PPCFastISel::fastEmit_i(), which 1665// interferes with necessary special handling (see PPCFastISel.cpp). 1666def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$RT), 1667 (ins u10imm:$imm, u10imm:$dmy), 1668 "mfbhrbe $RT, $imm", IIC_BrB, 1669 [(set i32:$RT, 1670 (PPCmfbhrbe imm:$imm, imm:$dmy))]>, 1671 PPC970_DGroup_First; 1672 1673def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$S), "rfebb $S", 1674 IIC_BrB, [(PPCrfebb (i32 imm:$S))]>, 1675 PPC970_DGroup_Single; 1676 1677def : InstAlias<"rfebb", (RFEBB 1)>; 1678 1679// DCB* instructions. 1680def DCBA : DCB_Form<758, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcba $addr", 1681 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$addr)]>, 1682 PPC970_DGroup_Single; 1683def DCBI : DCB_Form<470, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbi $addr", 1684 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$addr)]>, 1685 PPC970_DGroup_Single; 1686def DCBST : DCB_Form<54, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbst $addr", 1687 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$addr)]>, 1688 PPC970_DGroup_Single; 1689def DCBZ : DCB_Form<1014, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbz $addr", 1690 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$addr)]>, 1691 PPC970_DGroup_Single; 1692def DCBZL : DCB_Form<1014, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzl $addr", 1693 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$addr)]>, 1694 PPC970_DGroup_Single; 1695 1696def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, (memrr $RA, $RB):$addr), 1697 "dcbf $addr, $TH", IIC_LdStDCBF, []>, 1698 PPC970_DGroup_Single; 1699 1700let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { 1701def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr), 1702 "dcbt $addr, $TH", IIC_LdStDCBF, []>, 1703 PPC970_DGroup_Single; 1704def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr), 1705 "dcbtst $addr, $TH", IIC_LdStDCBF, []>, 1706 PPC970_DGroup_Single; 1707} // hasSideEffects = 0 1708 1709def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1710 "icblc $CT, $addr", IIC_LdStStore>, Requires<[HasICBT]>; 1711def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1712 "icblq. $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; 1713def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1714 "icbt $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; 1715def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1716 "icbtls $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; 1717 1718def : Pat<(int_ppc_dcbt xoaddr:$dst), 1719 (DCBT 0, xoaddr:$dst)>; 1720def : Pat<(int_ppc_dcbtst xoaddr:$dst), 1721 (DCBTST 0, xoaddr:$dst)>; 1722def : Pat<(int_ppc_dcbf xoaddr:$dst), 1723 (DCBF 0, xoaddr:$dst)>; 1724def : Pat<(int_ppc_icbt xoaddr:$dst), 1725 (ICBT 0, xoaddr:$dst)>; 1726 1727def : Pat<(prefetch xoaddr:$dst, (i32 0), timm, (i32 1)), 1728 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads 1729def : Pat<(prefetch xoaddr:$dst, (i32 1), timm, (i32 1)), 1730 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores 1731def : Pat<(prefetch xoaddr:$dst, (i32 0), timm, (i32 0)), 1732 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read) 1733 1734def : Pat<(int_ppc_dcbt_with_hint xoaddr:$dst, i32:$TH), 1735 (DCBT i32:$TH, xoaddr:$dst)>; 1736def : Pat<(int_ppc_dcbtst_with_hint xoaddr:$dst, i32:$TH), 1737 (DCBTST i32:$TH, xoaddr:$dst)>; 1738 1739// Atomic operations 1740// FIXME: some of these might be used with constant operands. This will result 1741// in constant materialization instructions that may be redundant. We currently 1742// clean this up in PPCMIPeephole with calls to 1743// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 1744// in the first place. 1745let Defs = [CR0] in { 1746 def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo< 1747 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", 1748 [(set i32:$dst, (atomic_load_add_8 ForceXForm:$ptr, i32:$incr))]>; 1749 def ATOMIC_LOAD_SUB_I8 : PPCCustomInserterPseudo< 1750 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", 1751 [(set i32:$dst, (atomic_load_sub_8 ForceXForm:$ptr, i32:$incr))]>; 1752 def ATOMIC_LOAD_AND_I8 : PPCCustomInserterPseudo< 1753 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", 1754 [(set i32:$dst, (atomic_load_and_8 ForceXForm:$ptr, i32:$incr))]>; 1755 def ATOMIC_LOAD_OR_I8 : PPCCustomInserterPseudo< 1756 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", 1757 [(set i32:$dst, (atomic_load_or_8 ForceXForm:$ptr, i32:$incr))]>; 1758 def ATOMIC_LOAD_XOR_I8 : PPCCustomInserterPseudo< 1759 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", 1760 [(set i32:$dst, (atomic_load_xor_8 ForceXForm:$ptr, i32:$incr))]>; 1761 def ATOMIC_LOAD_NAND_I8 : PPCCustomInserterPseudo< 1762 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", 1763 [(set i32:$dst, (atomic_load_nand_8 ForceXForm:$ptr, i32:$incr))]>; 1764 def ATOMIC_LOAD_MIN_I8 : PPCCustomInserterPseudo< 1765 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8", 1766 [(set i32:$dst, (atomic_load_min_8 ForceXForm:$ptr, i32:$incr))]>; 1767 def ATOMIC_LOAD_MAX_I8 : PPCCustomInserterPseudo< 1768 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8", 1769 [(set i32:$dst, (atomic_load_max_8 ForceXForm:$ptr, i32:$incr))]>; 1770 def ATOMIC_LOAD_UMIN_I8 : PPCCustomInserterPseudo< 1771 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8", 1772 [(set i32:$dst, (atomic_load_umin_8 ForceXForm:$ptr, i32:$incr))]>; 1773 def ATOMIC_LOAD_UMAX_I8 : PPCCustomInserterPseudo< 1774 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8", 1775 [(set i32:$dst, (atomic_load_umax_8 ForceXForm:$ptr, i32:$incr))]>; 1776 def ATOMIC_LOAD_ADD_I16 : PPCCustomInserterPseudo< 1777 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", 1778 [(set i32:$dst, (atomic_load_add_16 ForceXForm:$ptr, i32:$incr))]>; 1779 def ATOMIC_LOAD_SUB_I16 : PPCCustomInserterPseudo< 1780 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", 1781 [(set i32:$dst, (atomic_load_sub_16 ForceXForm:$ptr, i32:$incr))]>; 1782 def ATOMIC_LOAD_AND_I16 : PPCCustomInserterPseudo< 1783 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", 1784 [(set i32:$dst, (atomic_load_and_16 ForceXForm:$ptr, i32:$incr))]>; 1785 def ATOMIC_LOAD_OR_I16 : PPCCustomInserterPseudo< 1786 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", 1787 [(set i32:$dst, (atomic_load_or_16 ForceXForm:$ptr, i32:$incr))]>; 1788 def ATOMIC_LOAD_XOR_I16 : PPCCustomInserterPseudo< 1789 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", 1790 [(set i32:$dst, (atomic_load_xor_16 ForceXForm:$ptr, i32:$incr))]>; 1791 def ATOMIC_LOAD_NAND_I16 : PPCCustomInserterPseudo< 1792 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", 1793 [(set i32:$dst, (atomic_load_nand_16 ForceXForm:$ptr, i32:$incr))]>; 1794 def ATOMIC_LOAD_MIN_I16 : PPCCustomInserterPseudo< 1795 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16", 1796 [(set i32:$dst, (atomic_load_min_16 ForceXForm:$ptr, i32:$incr))]>; 1797 def ATOMIC_LOAD_MAX_I16 : PPCCustomInserterPseudo< 1798 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16", 1799 [(set i32:$dst, (atomic_load_max_16 ForceXForm:$ptr, i32:$incr))]>; 1800 def ATOMIC_LOAD_UMIN_I16 : PPCCustomInserterPseudo< 1801 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16", 1802 [(set i32:$dst, (atomic_load_umin_16 ForceXForm:$ptr, i32:$incr))]>; 1803 def ATOMIC_LOAD_UMAX_I16 : PPCCustomInserterPseudo< 1804 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16", 1805 [(set i32:$dst, (atomic_load_umax_16 ForceXForm:$ptr, i32:$incr))]>; 1806 def ATOMIC_LOAD_ADD_I32 : PPCCustomInserterPseudo< 1807 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", 1808 [(set i32:$dst, (atomic_load_add_32 ForceXForm:$ptr, i32:$incr))]>; 1809 def ATOMIC_LOAD_SUB_I32 : PPCCustomInserterPseudo< 1810 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", 1811 [(set i32:$dst, (atomic_load_sub_32 ForceXForm:$ptr, i32:$incr))]>; 1812 def ATOMIC_LOAD_AND_I32 : PPCCustomInserterPseudo< 1813 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", 1814 [(set i32:$dst, (atomic_load_and_32 ForceXForm:$ptr, i32:$incr))]>; 1815 def ATOMIC_LOAD_OR_I32 : PPCCustomInserterPseudo< 1816 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", 1817 [(set i32:$dst, (atomic_load_or_32 ForceXForm:$ptr, i32:$incr))]>; 1818 def ATOMIC_LOAD_XOR_I32 : PPCCustomInserterPseudo< 1819 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", 1820 [(set i32:$dst, (atomic_load_xor_32 ForceXForm:$ptr, i32:$incr))]>; 1821 def ATOMIC_LOAD_NAND_I32 : PPCCustomInserterPseudo< 1822 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", 1823 [(set i32:$dst, (atomic_load_nand_32 ForceXForm:$ptr, i32:$incr))]>; 1824 def ATOMIC_LOAD_MIN_I32 : PPCCustomInserterPseudo< 1825 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32", 1826 [(set i32:$dst, (atomic_load_min_32 ForceXForm:$ptr, i32:$incr))]>; 1827 def ATOMIC_LOAD_MAX_I32 : PPCCustomInserterPseudo< 1828 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32", 1829 [(set i32:$dst, (atomic_load_max_32 ForceXForm:$ptr, i32:$incr))]>; 1830 def ATOMIC_LOAD_UMIN_I32 : PPCCustomInserterPseudo< 1831 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32", 1832 [(set i32:$dst, (atomic_load_umin_32 ForceXForm:$ptr, i32:$incr))]>; 1833 def ATOMIC_LOAD_UMAX_I32 : PPCCustomInserterPseudo< 1834 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32", 1835 [(set i32:$dst, (atomic_load_umax_32 ForceXForm:$ptr, i32:$incr))]>; 1836 1837 def ATOMIC_CMP_SWAP_I8 : PPCCustomInserterPseudo< 1838 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", 1839 [(set i32:$dst, (atomic_cmp_swap_8 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1840 def ATOMIC_CMP_SWAP_I16 : PPCCustomInserterPseudo< 1841 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 1842 [(set i32:$dst, (atomic_cmp_swap_16 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1843 def ATOMIC_CMP_SWAP_I32 : PPCCustomInserterPseudo< 1844 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 1845 [(set i32:$dst, (atomic_cmp_swap_32 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1846 1847 def ATOMIC_SWAP_I8 : PPCCustomInserterPseudo< 1848 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", 1849 [(set i32:$dst, (atomic_swap_8 ForceXForm:$ptr, i32:$new))]>; 1850 def ATOMIC_SWAP_I16 : PPCCustomInserterPseudo< 1851 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", 1852 [(set i32:$dst, (atomic_swap_16 ForceXForm:$ptr, i32:$new))]>; 1853 def ATOMIC_SWAP_I32 : PPCCustomInserterPseudo< 1854 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", 1855 [(set i32:$dst, (atomic_swap_32 ForceXForm:$ptr, i32:$new))]>; 1856} 1857 1858def : Pat<(PPCatomicCmpSwap_8 ForceXForm:$ptr, i32:$old, i32:$new), 1859 (ATOMIC_CMP_SWAP_I8 ForceXForm:$ptr, i32:$old, i32:$new)>; 1860def : Pat<(PPCatomicCmpSwap_16 ForceXForm:$ptr, i32:$old, i32:$new), 1861 (ATOMIC_CMP_SWAP_I16 ForceXForm:$ptr, i32:$old, i32:$new)>; 1862 1863// Instructions to support atomic operations 1864let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 1865def LBARX : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1866 "lbarx $RST, $addr", IIC_LdStLWARX, []>, 1867 Requires<[HasPartwordAtomics]>; 1868 1869def LHARX : XForm_1_memOp<31, 116, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1870 "lharx $RST, $addr", IIC_LdStLWARX, []>, 1871 Requires<[HasPartwordAtomics]>; 1872 1873def LWARX : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1874 "lwarx $RST, $addr", IIC_LdStLWARX, []>; 1875 1876// Instructions to support lock versions of atomics 1877// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 1878def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1879 "lbarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm, 1880 Requires<[HasPartwordAtomics]>; 1881 1882def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1883 "lharx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm, 1884 Requires<[HasPartwordAtomics]>; 1885 1886def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1887 "lwarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm; 1888 1889// The atomic instructions use the destination register as well as the next one 1890// or two registers in order (modulo 31). 1891let hasExtraSrcRegAllocReq = 1 in 1892def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$RST), (ins gprc:$RA, u5imm:$RB), 1893 "lwat $RST, $RA, $RB", IIC_LdStLoad>, 1894 Requires<[IsISA3_0]>; 1895} 1896 1897let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 1898def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 1899 "stbcx. $RST, $addr", IIC_LdStSTWCX, []>, 1900 isRecordForm, Requires<[HasPartwordAtomics]>; 1901 1902def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 1903 "sthcx. $RST, $addr", IIC_LdStSTWCX, []>, 1904 isRecordForm, Requires<[HasPartwordAtomics]>; 1905 1906def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 1907 "stwcx. $RST, $addr", IIC_LdStSTWCX, []>, isRecordForm; 1908} 1909 1910let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 1911def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$RST, gprc:$RA, u5imm:$RB), 1912 "stwat $RST, $RA, $RB", IIC_LdStStore>, 1913 Requires<[IsISA3_0]>; 1914 1915let isTrap = 1, hasCtrlDep = 1 in 1916def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; 1917 1918def TWI : DForm_base<3, (outs), (ins u5imm:$RST, gprc:$RA, s16imm:$D, variable_ops), 1919 "twi $RST, $RA, $D", IIC_IntTrapW, []>; 1920def TW : XForm_1<31, 4, (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB, variable_ops), 1921 "tw $RST, $RA, $RB", IIC_IntTrapW, []>; 1922def TDI : DForm_base<2, (outs), (ins u5imm:$RST, g8rc:$RA, s16imm:$D, variable_ops), 1923 "tdi $RST, $RA, $D", IIC_IntTrapD, []>; 1924def TD : XForm_1<31, 68, (outs), (ins u5imm:$RST, g8rc:$RA, g8rc:$RB, variable_ops), 1925 "td $RST, $RA, $RB", IIC_IntTrapD, []>; 1926 1927def POPCNTB : XForm_11<31, 122, (outs gprc:$RA), (ins gprc:$RST), 1928 "popcntb $RA, $RST", IIC_IntGeneral, 1929 [(set i32:$RA, (int_ppc_popcntb i32:$RST))]>; 1930 1931def CDTBCD : XForm_11<31, 282, (outs gprc:$RA), (ins gprc:$RST), 1932 "cdtbcd $RA, $RST", IIC_IntGeneral, []>; 1933def CBCDTD : XForm_11<31, 314, (outs gprc:$RA), (ins gprc:$RST), 1934 "cbcdtd $RA, $RST", IIC_IntGeneral, []>; 1935 1936def ADDG6S : XOForm_1<31, 74, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 1937 "addg6s $RT, $RA, $RB", IIC_IntGeneral, []>; 1938 1939//===----------------------------------------------------------------------===// 1940// PPC32 Load Instructions. 1941// 1942 1943// Unindexed (r+i) Loads. 1944let PPC970_Unit = 2 in { 1945def LBZ : DForm_1<34, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1946 "lbz $RST, $addr", IIC_LdStLoad, 1947 [(set i32:$RST, (zextloadi8 DForm:$addr))]>, ZExt32To64, 1948 SExt32To64; 1949def LHA : DForm_1<42, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1950 "lha $RST, $addr", IIC_LdStLHA, 1951 [(set i32:$RST, (sextloadi16 DForm:$addr))]>, 1952 PPC970_DGroup_Cracked, SExt32To64; 1953def LHZ : DForm_1<40, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1954 "lhz $RST, $addr", IIC_LdStLoad, 1955 [(set i32:$RST, (zextloadi16 DForm:$addr))]>, ZExt32To64, 1956 SExt32To64; 1957def LWZ : DForm_1<32, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1958 "lwz $RST, $addr", IIC_LdStLoad, 1959 [(set i32:$RST, (load DForm:$addr))]>, ZExt32To64; 1960 1961let Predicates = [HasFPU] in { 1962def LFS : DForm_1<48, (outs f4rc:$RST), (ins (memri $D, $RA):$addr), 1963 "lfs $RST, $addr", IIC_LdStLFD, 1964 [(set f32:$RST, (load DForm:$addr))]>; 1965def LFD : DForm_1<50, (outs f8rc:$RST), (ins (memri $D, $RA):$addr), 1966 "lfd $RST, $addr", IIC_LdStLFD, 1967 [(set f64:$RST, (load DForm:$addr))]>; 1968} 1969 1970 1971// Unindexed (r+i) Loads with Update (preinc). 1972let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 1973def LBZU : DForm_1<35, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1974 "lbzu $RST, $addr", IIC_LdStLoadUpd, 1975 []>, RegConstraint<"$RA = $ea_result">; 1976 1977def LHAU : DForm_1<43, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1978 "lhau $RST, $addr", IIC_LdStLHAU, 1979 []>, RegConstraint<"$addr.reg = $ea_result">, 1980 NoEncode<"$ea_result">; 1981 1982def LHZU : DForm_1<41, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1983 "lhzu $RST, $addr", IIC_LdStLoadUpd, 1984 []>, RegConstraint<"$addr.reg = $ea_result">, 1985 NoEncode<"$ea_result">; 1986 1987def LWZU : DForm_1<33, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1988 "lwzu $RST, $addr", IIC_LdStLoadUpd, 1989 []>, RegConstraint<"$addr.reg = $ea_result">, 1990 NoEncode<"$ea_result">; 1991 1992let Predicates = [HasFPU] in { 1993def LFSU : DForm_1<49, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1994 "lfsu $RST, $addr", IIC_LdStLFDU, 1995 []>, RegConstraint<"$addr.reg = $ea_result">, 1996 NoEncode<"$ea_result">; 1997 1998def LFDU : DForm_1<51, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1999 "lfdu $RST, $addr", IIC_LdStLFDU, 2000 []>, RegConstraint<"$addr.reg = $ea_result">, 2001 NoEncode<"$ea_result">; 2002} 2003 2004 2005// Indexed (r+r) Loads with Update (preinc). 2006def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2007 (ins (memrr $RA, $RB):$addr), 2008 "lbzux $RST, $addr", IIC_LdStLoadUpdX, 2009 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2010 NoEncode<"$ea_result">; 2011 2012def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2013 (ins (memrr $RA, $RB):$addr), 2014 "lhaux $RST, $addr", IIC_LdStLHAUX, 2015 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2016 NoEncode<"$ea_result">; 2017 2018def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2019 (ins (memrr $RA, $RB):$addr), 2020 "lhzux $RST, $addr", IIC_LdStLoadUpdX, 2021 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2022 NoEncode<"$ea_result">; 2023 2024def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2025 (ins (memrr $RA, $RB):$addr), 2026 "lwzux $RST, $addr", IIC_LdStLoadUpdX, 2027 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2028 NoEncode<"$ea_result">; 2029 2030let Predicates = [HasFPU] in { 2031def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), 2032 (ins (memrr $RA, $RB):$addr), 2033 "lfsux $RST, $addr", IIC_LdStLFDUX, 2034 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2035 NoEncode<"$ea_result">; 2036 2037def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), 2038 (ins (memrr $RA, $RB):$addr), 2039 "lfdux $RST, $addr", IIC_LdStLFDUX, 2040 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2041 NoEncode<"$ea_result">; 2042} 2043} 2044} 2045 2046// Indexed (r+r) Loads. 2047// 2048let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { 2049def LBZX : XForm_1_memOp<31, 87, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2050 "lbzx $RST, $addr", IIC_LdStLoad, 2051 [(set i32:$RST, (zextloadi8 XForm:$addr))]>, ZExt32To64, 2052 SExt32To64; 2053def LHAX : XForm_1_memOp<31, 343, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2054 "lhax $RST, $addr", IIC_LdStLHA, 2055 [(set i32:$RST, (sextloadi16 XForm:$addr))]>, 2056 PPC970_DGroup_Cracked, SExt32To64; 2057def LHZX : XForm_1_memOp<31, 279, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2058 "lhzx $RST, $addr", IIC_LdStLoad, 2059 [(set i32:$RST, (zextloadi16 XForm:$addr))]>, ZExt32To64, 2060 SExt32To64; 2061def LWZX : XForm_1_memOp<31, 23, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2062 "lwzx $RST, $addr", IIC_LdStLoad, 2063 [(set i32:$RST, (load XForm:$addr))]>, ZExt32To64; 2064def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2065 "lhbrx $RST, $addr", IIC_LdStLoad, 2066 [(set i32:$RST, (PPClbrx ForceXForm:$addr, i16))]>, ZExt32To64; 2067def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2068 "lwbrx $RST, $addr", IIC_LdStLoad, 2069 [(set i32:$RST, (PPClbrx ForceXForm:$addr, i32))]>, ZExt32To64; 2070 2071let Predicates = [HasFPU] in { 2072def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$RST), (ins (memrr $RA, $RB):$addr), 2073 "lfsx $RST, $addr", IIC_LdStLFD, 2074 [(set f32:$RST, (load XForm:$addr))]>; 2075def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 2076 "lfdx $RST, $addr", IIC_LdStLFD, 2077 [(set f64:$RST, (load XForm:$addr))]>; 2078 2079def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 2080 "lfiwax $RST, $addr", IIC_LdStLFD, 2081 [(set f64:$RST, (PPClfiwax ForceXForm:$addr))]>; 2082def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 2083 "lfiwzx $RST, $addr", IIC_LdStLFD, 2084 [(set f64:$RST, (PPClfiwzx ForceXForm:$addr))]>; 2085} 2086} 2087 2088// Load Multiple 2089let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in 2090def LMW : DForm_1<46, (outs gprc:$RST), (ins (memri $D, $RA):$src), 2091 "lmw $RST, $src", IIC_LdStLMW, []>; 2092 2093//===----------------------------------------------------------------------===// 2094// PPC32 Store Instructions. 2095// 2096 2097// Unindexed (r+i) Stores. 2098let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2099def STB : DForm_1<38, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2100 "stb $RST, $dst", IIC_LdStStore, 2101 [(truncstorei8 i32:$RST, DForm:$dst)]>; 2102def STH : DForm_1<44, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2103 "sth $RST, $dst", IIC_LdStStore, 2104 [(truncstorei16 i32:$RST, DForm:$dst)]>; 2105def STW : DForm_1<36, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2106 "stw $RST, $dst", IIC_LdStStore, 2107 [(store i32:$RST, DForm:$dst)]>; 2108let Predicates = [HasFPU] in { 2109def STFS : DForm_1<52, (outs), (ins f4rc:$RST, (memri $D, $RA):$dst), 2110 "stfs $RST, $dst", IIC_LdStSTFD, 2111 [(store f32:$RST, DForm:$dst)]>; 2112def STFD : DForm_1<54, (outs), (ins f8rc:$RST, (memri $D, $RA):$dst), 2113 "stfd $RST, $dst", IIC_LdStSTFD, 2114 [(store f64:$RST, DForm:$dst)]>; 2115} 2116} 2117 2118// Unindexed (r+i) Stores with Update (preinc). 2119let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2120def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), 2121 "stbu $RST, $dst", IIC_LdStSTU, []>, 2122 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2123def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), 2124 "sthu $RST, $dst", IIC_LdStSTU, []>, 2125 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2126def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), 2127 "stwu $RST, $dst", IIC_LdStSTU, []>, 2128 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2129let Predicates = [HasFPU] in { 2130def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$RST, (memri $D, $RA):$dst), 2131 "stfsu $RST, $dst", IIC_LdStSTFDU, []>, 2132 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2133def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$RST, (memri $D, $RA):$dst), 2134 "stfdu $RST, $dst", IIC_LdStSTFDU, []>, 2135 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2136} 2137} 2138 2139// Patterns to match the pre-inc stores. We can't put the patterns on 2140// the instruction definitions directly as ISel wants the address base 2141// and offset to be separate operands, not a single complex operand. 2142def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2143 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 2144def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2145 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 2146def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2147 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 2148def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2149 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 2150def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2151 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 2152 2153// Indexed (r+r) Stores. 2154let PPC970_Unit = 2 in { 2155def STBX : XForm_8_memOp<31, 215, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2156 "stbx $RST, $addr", IIC_LdStStore, 2157 [(truncstorei8 i32:$RST, XForm:$addr)]>, 2158 PPC970_DGroup_Cracked; 2159def STHX : XForm_8_memOp<31, 407, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2160 "sthx $RST, $addr", IIC_LdStStore, 2161 [(truncstorei16 i32:$RST, XForm:$addr)]>, 2162 PPC970_DGroup_Cracked; 2163def STWX : XForm_8_memOp<31, 151, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2164 "stwx $RST, $addr", IIC_LdStStore, 2165 [(store i32:$RST, XForm:$addr)]>, 2166 PPC970_DGroup_Cracked; 2167 2168def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2169 "sthbrx $RST, $addr", IIC_LdStStore, 2170 [(PPCstbrx i32:$RST, ForceXForm:$addr, i16)]>, 2171 PPC970_DGroup_Cracked; 2172def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2173 "stwbrx $RST, $addr", IIC_LdStStore, 2174 [(PPCstbrx i32:$RST, ForceXForm:$addr, i32)]>, 2175 PPC970_DGroup_Cracked; 2176 2177let Predicates = [HasFPU] in { 2178def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), 2179 "stfiwx $RST, $addr", IIC_LdStSTFD, 2180 [(PPCstfiwx f64:$RST, ForceXForm:$addr)]>; 2181 2182def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$RST, (memrr $RA, $RB):$addr), 2183 "stfsx $RST, $addr", IIC_LdStSTFD, 2184 [(store f32:$RST, XForm:$addr)]>; 2185def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), 2186 "stfdx $RST, $addr", IIC_LdStSTFD, 2187 [(store f64:$RST, XForm:$addr)]>; 2188} 2189} 2190 2191// Indexed (r+r) Stores with Update (preinc). 2192let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2193def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 2194 (ins gprc:$RST, (memrr $RA, $RB):$addr), 2195 "stbux $RST, $addr", IIC_LdStSTUX, []>, 2196 RegConstraint<"$addr.ptrreg = $ea_res">, 2197 NoEncode<"$ea_res">, 2198 PPC970_DGroup_Cracked; 2199def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 2200 (ins gprc:$RST, (memrr $RA, $RB):$addr), 2201 "sthux $RST, $addr", IIC_LdStSTUX, []>, 2202 RegConstraint<"$addr.ptrreg = $ea_res">, 2203 NoEncode<"$ea_res">, 2204 PPC970_DGroup_Cracked; 2205def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 2206 (ins gprc:$RST, (memrr $RA, $RB):$addr), 2207 "stwux $RST, $addr", IIC_LdStSTUX, []>, 2208 RegConstraint<"$addr.ptrreg = $ea_res">, 2209 NoEncode<"$ea_res">, 2210 PPC970_DGroup_Cracked; 2211let Predicates = [HasFPU] in { 2212def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res), 2213 (ins f4rc:$RST, (memrr $RA, $RB):$addr), 2214 "stfsux $RST, $addr", IIC_LdStSTFDU, []>, 2215 RegConstraint<"$addr.ptrreg = $ea_res">, 2216 NoEncode<"$ea_res">, 2217 PPC970_DGroup_Cracked; 2218def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res), 2219 (ins f8rc:$RST, (memrr $RA, $RB):$addr), 2220 "stfdux $RST, $addr", IIC_LdStSTFDU, []>, 2221 RegConstraint<"$addr.ptrreg = $ea_res">, 2222 NoEncode<"$ea_res">, 2223 PPC970_DGroup_Cracked; 2224} 2225} 2226 2227// Patterns to match the pre-inc stores. We can't put the patterns on 2228// the instruction definitions directly as ISel wants the address base 2229// and offset to be separate operands, not a single complex operand. 2230def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2231 (STBUX $rS, $ptrreg, $ptroff)>; 2232def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2233 (STHUX $rS, $ptrreg, $ptroff)>; 2234def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2235 (STWUX $rS, $ptrreg, $ptroff)>; 2236let Predicates = [HasFPU] in { 2237def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2238 (STFSUX $rS, $ptrreg, $ptroff)>; 2239def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2240 (STFDUX $rS, $ptrreg, $ptroff)>; 2241} 2242 2243// Store Multiple 2244let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 2245def STMW : DForm_1<47, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2246 "stmw $RST, $dst", IIC_LdStLMW, []>; 2247 2248def SYNC : XForm_24_sync<31, 598, (outs), (ins u2imm:$L), 2249 "sync $L", IIC_LdStSync, []>; 2250 2251let isCodeGenOnly = 1 in { 2252 def MSYNC : XForm_24_sync<31, 598, (outs), (ins), 2253 "msync", IIC_LdStSync, []> { 2254 let L = 0; 2255 } 2256} 2257 2258// We used to have EIEIO as value but E[0-9A-Z] is a reserved name 2259def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins), 2260 "eieio", IIC_LdStLoad, []>; 2261 2262def PseudoEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCEIEIO", 2263 [(int_ppc_eieio)]>; 2264 2265def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2266def : Pat<(int_ppc_iospace_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2267def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2268def : Pat<(int_ppc_iospace_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2269def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2270def : Pat<(int_ppc_iospace_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2271def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2272def : Pat<(int_ppc_iospace_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2273def : Pat<(int_ppc_eieio), (PseudoEIEIO)>; 2274def : Pat<(int_ppc_iospace_eieio), (PseudoEIEIO)>; 2275 2276//===----------------------------------------------------------------------===// 2277// PPC32 Arithmetic Instructions. 2278// 2279 2280let PPC970_Unit = 1 in { // FXU Operations. 2281def ADDI : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D), 2282 "addi $RST, $RA, $D", IIC_IntSimple, 2283 [(set i32:$RST, (add i32:$RA, imm32SExt16:$D))]>; 2284let BaseName = "addic" in { 2285let Defs = [CARRY] in 2286def ADDIC : DForm_2<12, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2287 "addic $RST, $RA, $D", IIC_IntGeneral, 2288 [(set i32:$RST, (addc i32:$RA, imm32SExt16:$D))]>, 2289 RecFormRel, PPC970_DGroup_Cracked; 2290let Defs = [CARRY, CR0] in 2291def ADDIC_rec : DForm_2<13, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2292 "addic. $RST, $RA, $D", IIC_IntGeneral, 2293 []>, isRecordForm, RecFormRel; 2294} 2295def ADDIS : DForm_2<15, (outs gprc:$RST), (ins gprc_nor0:$RA, s17imm:$D), 2296 "addis $RST, $RA, $D", IIC_IntSimple, 2297 [(set i32:$RST, (add i32:$RA, imm16ShiftedSExt:$D))]>; 2298let isCodeGenOnly = 1 in 2299def LA : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D), 2300 "la $RST, $D($RA)", IIC_IntGeneral, 2301 [(set i32:$RST, (add i32:$RA, 2302 (PPClo tglobaladdr:$D, 0)))]>; 2303def MULLI : DForm_2< 7, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2304 "mulli $RST, $RA, $D", IIC_IntMulLI, 2305 [(set i32:$RST, (mul i32:$RA, imm32SExt16:$D))]>; 2306let Defs = [CARRY] in 2307def SUBFIC : DForm_2< 8, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2308 "subfic $RST, $RA, $D", IIC_IntGeneral, 2309 [(set i32:$RST, (subc imm32SExt16:$D, i32:$RA))]>; 2310 2311let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 2312 def LI : DForm_2_r0<14, (outs gprc:$RST), (ins s16imm:$D), 2313 "li $RST, $D", IIC_IntSimple, 2314 [(set i32:$RST, imm32SExt16:$D)]>, SExt32To64; 2315 def LIS : DForm_2_r0<15, (outs gprc:$RST), (ins s17imm:$D), 2316 "lis $RST, $D", IIC_IntSimple, 2317 [(set i32:$RST, imm16ShiftedSExt:$D)]>, SExt32To64; 2318} 2319} 2320 2321def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>; 2322def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>; 2323 2324let PPC970_Unit = 1 in { // FXU Operations. 2325let Defs = [CR0] in { 2326def ANDI_rec : DForm_4<28, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2327 "andi. $RA, $RST, $D", IIC_IntGeneral, 2328 [(set i32:$RA, (and i32:$RST, immZExt16:$D))]>, 2329 isRecordForm, ZExt32To64, SExt32To64; 2330def ANDIS_rec : DForm_4<29, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2331 "andis. $RA, $RST, $D", IIC_IntGeneral, 2332 [(set i32:$RA, (and i32:$RST, imm16ShiftedZExt:$D))]>, 2333 isRecordForm, ZExt32To64; 2334} 2335def ORI : DForm_4<24, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2336 "ori $RA, $RST, $D", IIC_IntSimple, 2337 [(set i32:$RA, (or i32:$RST, immZExt16:$D))]>; 2338def ORIS : DForm_4<25, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2339 "oris $RA, $RST, $D", IIC_IntSimple, 2340 [(set i32:$RA, (or i32:$RST, imm16ShiftedZExt:$D))]>; 2341def XORI : DForm_4<26, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2342 "xori $RA, $RST, $D", IIC_IntSimple, 2343 [(set i32:$RA, (xor i32:$RST, immZExt16:$D))]>; 2344def XORIS : DForm_4<27, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2345 "xoris $RA, $RST, $D", IIC_IntSimple, 2346 [(set i32:$RA, (xor i32:$RST, imm16ShiftedZExt:$D))]>; 2347 2348def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, 2349 []>; 2350let isCodeGenOnly = 1 in { 2351// The POWER6 and POWER7 have special group-terminating nops. 2352def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins), 2353 "ori 1, 1, 0", IIC_IntSimple, []>; 2354def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins), 2355 "ori 2, 2, 0", IIC_IntSimple, []>; 2356} 2357 2358let isCompare = 1, hasSideEffects = 0 in { 2359 def CMPWI : DForm_5_ext<11, (outs crrc:$BF), (ins gprc:$RA, s16imm:$D), 2360 "cmpwi $BF, $RA, $D", IIC_IntCompare>; 2361 def CMPLWI : DForm_6_ext<10, (outs crrc:$BF), (ins gprc:$RA, u16imm:$D), 2362 "cmplwi $BF, $RA, $D", IIC_IntCompare>; 2363 def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), 2364 (ins u1imm:$L, gprc:$RA, gprc:$RB), 2365 "cmprb $BF, $L, $RA, $RB", IIC_IntCompare, []>, 2366 Requires<[IsISA3_0]>; 2367} 2368} 2369 2370let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2371let isCommutable = 1 in { 2372defm NAND : XForm_6r<31, 476, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2373 "nand", "$RA, $RST, $RB", IIC_IntSimple, 2374 [(set i32:$RA, (not (and i32:$RST, i32:$RB)))]>; 2375defm AND : XForm_6r<31, 28, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2376 "and", "$RA, $RST, $RB", IIC_IntSimple, 2377 [(set i32:$RA, (and i32:$RST, i32:$RB))]>; 2378} // isCommutable 2379defm ANDC : XForm_6r<31, 60, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2380 "andc", "$RA, $RST, $RB", IIC_IntSimple, 2381 [(set i32:$RA, (and i32:$RST, (not i32:$RB)))]>; 2382let isCommutable = 1 in { 2383defm OR : XForm_6r<31, 444, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2384 "or", "$RA, $RST, $RB", IIC_IntSimple, 2385 [(set i32:$RA, (or i32:$RST, i32:$RB))]>; 2386defm NOR : XForm_6r<31, 124, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2387 "nor", "$RA, $RST, $RB", IIC_IntSimple, 2388 [(set i32:$RA, (not (or i32:$RST, i32:$RB)))]>; 2389} // isCommutable 2390defm ORC : XForm_6r<31, 412, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2391 "orc", "$RA, $RST, $RB", IIC_IntSimple, 2392 [(set i32:$RA, (or i32:$RST, (not i32:$RB)))]>; 2393let isCommutable = 1 in { 2394defm EQV : XForm_6r<31, 284, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2395 "eqv", "$RA, $RST, $RB", IIC_IntSimple, 2396 [(set i32:$RA, (not (xor i32:$RST, i32:$RB)))]>; 2397defm XOR : XForm_6r<31, 316, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2398 "xor", "$RA, $RST, $RB", IIC_IntSimple, 2399 [(set i32:$RA, (xor i32:$RST, i32:$RB))]>; 2400} // isCommutable 2401defm SLW : XForm_6r<31, 24, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2402 "slw", "$RA, $RST, $RB", IIC_IntGeneral, 2403 [(set i32:$RA, (PPCshl i32:$RST, i32:$RB))]>, ZExt32To64; 2404defm SRW : XForm_6r<31, 536, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2405 "srw", "$RA, $RST, $RB", IIC_IntGeneral, 2406 [(set i32:$RA, (PPCsrl i32:$RST, i32:$RB))]>, ZExt32To64; 2407defm SRAW : XForm_6rc<31, 792, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2408 "sraw", "$RA, $RST, $RB", IIC_IntShift, 2409 [(set i32:$RA, (PPCsra i32:$RST, i32:$RB))]>, SExt32To64; 2410} 2411 2412def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>; 2413def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>; 2414 2415def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>; 2416def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>; 2417 2418def : InstAlias<"nop", (ORI R0, R0, 0)>; 2419 2420let PPC970_Unit = 1 in { // FXU Operations. 2421let hasSideEffects = 0 in { 2422defm SRAWI : XForm_10rc<31, 824, (outs gprc:$RA), (ins gprc:$RST, u5imm:$RB), 2423 "srawi", "$RA, $RST, $RB", IIC_IntShift, 2424 [(set i32:$RA, (sra i32:$RST, (i32 imm:$RB)))]>, 2425 SExt32To64; 2426defm CNTLZW : XForm_11r<31, 26, (outs gprc:$RA), (ins gprc:$RST), 2427 "cntlzw", "$RA, $RST", IIC_IntGeneral, 2428 [(set i32:$RA, (ctlz i32:$RST))]>, ZExt32To64; 2429defm CNTTZW : XForm_11r<31, 538, (outs gprc:$RA), (ins gprc:$RST), 2430 "cnttzw", "$RA, $RST", IIC_IntGeneral, 2431 [(set i32:$RA, (cttz i32:$RST))]>, Requires<[IsISA3_0]>, 2432 ZExt32To64; 2433defm EXTSB : XForm_11r<31, 954, (outs gprc:$RA), (ins gprc:$RST), 2434 "extsb", "$RA, $RST", IIC_IntSimple, 2435 [(set i32:$RA, (sext_inreg i32:$RST, i8))]>, SExt32To64; 2436defm EXTSH : XForm_11r<31, 922, (outs gprc:$RA), (ins gprc:$RST), 2437 "extsh", "$RA, $RST", IIC_IntSimple, 2438 [(set i32:$RA, (sext_inreg i32:$RST, i16))]>, SExt32To64; 2439 2440let isCommutable = 1 in 2441def CMPB : XForm_6<31, 508, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2442 "cmpb $RA, $RST, $RB", IIC_IntGeneral, 2443 [(set i32:$RA, (PPCcmpb i32:$RST, i32:$RB))]>; 2444} 2445let isCompare = 1, hasSideEffects = 0 in { 2446 def CMPW : XForm_16_ext<31, 0, (outs crrc:$BF), (ins gprc:$RA, gprc:$RB), 2447 "cmpw $BF, $RA, $RB", IIC_IntCompare>; 2448 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$BF), (ins gprc:$RA, gprc:$RB), 2449 "cmplw $BF, $RA, $RB", IIC_IntCompare>; 2450} 2451} 2452let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations. 2453let isCompare = 1, mayRaiseFPException = 1, hasSideEffects = 0 in { 2454 def FCMPUS : XForm_17<63, 0, (outs crrc:$BF), (ins f4rc:$RA, f4rc:$RB), 2455 "fcmpu $BF, $RA, $RB", IIC_FPCompare>; 2456 def FCMPOS : XForm_17<63, 32, (outs crrc:$BF), (ins f4rc:$RA, f4rc:$RB), 2457 "fcmpo $BF, $RA, $RB", IIC_FPCompare>; 2458 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 2459 def FCMPUD : XForm_17<63, 0, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), 2460 "fcmpu $BF, $RA, $RB", IIC_FPCompare>; 2461 def FCMPOD : XForm_17<63, 32, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), 2462 "fcmpo $BF, $RA, $RB", IIC_FPCompare>; 2463 } 2464} 2465 2466def FTDIV: XForm_17<63, 128, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), 2467 "ftdiv $BF, $RA, $RB", IIC_FPCompare>; 2468def FTSQRT: XForm_17a<63, 160, (outs crrc:$BF), (ins f8rc:$RB), 2469 "ftsqrt $BF, $RB", IIC_FPCompare, 2470 [(set i32:$BF, (PPCftsqrt f64:$RB))]>; 2471 2472let mayRaiseFPException = 1, hasSideEffects = 0 in { 2473 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2474 defm FRIND : XForm_26r<63, 392, (outs f8rc:$RST), (ins f8rc:$RB), 2475 "frin", "$RST, $RB", IIC_FPGeneral, 2476 [(set f64:$RST, (any_fround f64:$RB))]>; 2477 defm FRINS : XForm_26r<63, 392, (outs f4rc:$RST), (ins f4rc:$RB), 2478 "frin", "$RST, $RB", IIC_FPGeneral, 2479 [(set f32:$RST, (any_fround f32:$RB))]>; 2480 2481 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2482 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$RST), (ins f8rc:$RB), 2483 "frip", "$RST, $RB", IIC_FPGeneral, 2484 [(set f64:$RST, (any_fceil f64:$RB))]>; 2485 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$RST), (ins f4rc:$RB), 2486 "frip", "$RST, $RB", IIC_FPGeneral, 2487 [(set f32:$RST, (any_fceil f32:$RB))]>; 2488 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2489 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$RST), (ins f8rc:$RB), 2490 "friz", "$RST, $RB", IIC_FPGeneral, 2491 [(set f64:$RST, (any_ftrunc f64:$RB))]>; 2492 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$RST), (ins f4rc:$RB), 2493 "friz", "$RST, $RB", IIC_FPGeneral, 2494 [(set f32:$RST, (any_ftrunc f32:$RB))]>; 2495 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2496 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$RST), (ins f8rc:$RB), 2497 "frim", "$RST, $RB", IIC_FPGeneral, 2498 [(set f64:$RST, (any_ffloor f64:$RB))]>; 2499 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$RST), (ins f4rc:$RB), 2500 "frim", "$RST, $RB", IIC_FPGeneral, 2501 [(set f32:$RST, (any_ffloor f32:$RB))]>; 2502} 2503 2504let Uses = [RM], mayRaiseFPException = 1, hasSideEffects = 0 in { 2505 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$RST), (ins f8rc:$RB), 2506 "fctiw", "$RST, $RB", IIC_FPGeneral, 2507 []>; 2508 defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$RST), (ins f8rc:$RB), 2509 "fctiwu", "$RST, $RB", IIC_FPGeneral, 2510 []>; 2511 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$RST), (ins f8rc:$RB), 2512 "fctiwz", "$RST, $RB", IIC_FPGeneral, 2513 [(set f64:$RST, (PPCany_fctiwz f64:$RB))]>; 2514 2515 defm FRSP : XForm_26r<63, 12, (outs f4rc:$RST), (ins f8rc:$RB), 2516 "frsp", "$RST, $RB", IIC_FPGeneral, 2517 [(set f32:$RST, (any_fpround f64:$RB))]>; 2518 2519 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$RST), (ins f8rc:$RB), 2520 "fsqrt", "$RST, $RB", IIC_FPSqrtD, 2521 [(set f64:$RST, (any_fsqrt f64:$RB))]>; 2522 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$RST), (ins f4rc:$RB), 2523 "fsqrts", "$RST, $RB", IIC_FPSqrtS, 2524 [(set f32:$RST, (any_fsqrt f32:$RB))]>; 2525} 2526} 2527 2528def : Pat<(PPCfsqrt f64:$frA), (FSQRT $frA)>; 2529 2530/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 2531/// often coalesced away and we don't want the dispatch group builder to think 2532/// that they will fill slots (which could cause the load of a LSU reject to 2533/// sneak into a d-group with a store). 2534let hasSideEffects = 0, Predicates = [HasFPU] in 2535defm FMR : XForm_26r<63, 72, (outs f4rc:$RST), (ins f4rc:$RB), 2536 "fmr", "$RST, $RB", IIC_FPGeneral, 2537 []>, // (set f32:$RST, f32:$RB) 2538 PPC970_Unit_Pseudo; 2539 2540let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2541// These are artificially split into two different forms, for 4/8 byte FP. 2542defm FABSS : XForm_26r<63, 264, (outs f4rc:$RST), (ins f4rc:$RB), 2543 "fabs", "$RST, $RB", IIC_FPGeneral, 2544 [(set f32:$RST, (fabs f32:$RB))]>; 2545let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2546defm FABSD : XForm_26r<63, 264, (outs f8rc:$RST), (ins f8rc:$RB), 2547 "fabs", "$RST, $RB", IIC_FPGeneral, 2548 [(set f64:$RST, (fabs f64:$RB))]>; 2549defm FNABSS : XForm_26r<63, 136, (outs f4rc:$RST), (ins f4rc:$RB), 2550 "fnabs", "$RST, $RB", IIC_FPGeneral, 2551 [(set f32:$RST, (fneg (fabs f32:$RB)))]>; 2552let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2553defm FNABSD : XForm_26r<63, 136, (outs f8rc:$RST), (ins f8rc:$RB), 2554 "fnabs", "$RST, $RB", IIC_FPGeneral, 2555 [(set f64:$RST, (fneg (fabs f64:$RB)))]>; 2556defm FNEGS : XForm_26r<63, 40, (outs f4rc:$RST), (ins f4rc:$RB), 2557 "fneg", "$RST, $RB", IIC_FPGeneral, 2558 [(set f32:$RST, (fneg f32:$RB))]>; 2559let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2560defm FNEGD : XForm_26r<63, 40, (outs f8rc:$RST), (ins f8rc:$RB), 2561 "fneg", "$RST, $RB", IIC_FPGeneral, 2562 [(set f64:$RST, (fneg f64:$RB))]>; 2563 2564defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$RST), (ins f4rc:$RA, f4rc:$RB), 2565 "fcpsgn", "$RST, $RA, $RB", IIC_FPGeneral, 2566 [(set f32:$RST, (fcopysign f32:$RB, f32:$RA))]>; 2567let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2568defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB), 2569 "fcpsgn", "$RST, $RA, $RB", IIC_FPGeneral, 2570 [(set f64:$RST, (fcopysign f64:$RB, f64:$RA))]>; 2571 2572// Reciprocal estimates. 2573let mayRaiseFPException = 1 in { 2574defm FRE : XForm_26r<63, 24, (outs f8rc:$RST), (ins f8rc:$RB), 2575 "fre", "$RST, $RB", IIC_FPGeneral, 2576 [(set f64:$RST, (PPCfre f64:$RB))]>; 2577defm FRES : XForm_26r<59, 24, (outs f4rc:$RST), (ins f4rc:$RB), 2578 "fres", "$RST, $RB", IIC_FPGeneral, 2579 [(set f32:$RST, (PPCfre f32:$RB))]>; 2580defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$RST), (ins f8rc:$RB), 2581 "frsqrte", "$RST, $RB", IIC_FPGeneral, 2582 [(set f64:$RST, (PPCfrsqrte f64:$RB))]>; 2583defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$RST), (ins f4rc:$RB), 2584 "frsqrtes", "$RST, $RB", IIC_FPGeneral, 2585 [(set f32:$RST, (PPCfrsqrte f32:$RB))]>; 2586} 2587} 2588 2589// XL-Form instructions. condition register logical ops. 2590// 2591let hasSideEffects = 0 in 2592def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), 2593 "mcrf $BF, $BFA", IIC_BrMCR>, 2594 PPC970_DGroup_First, PPC970_Unit_CRU; 2595 2596// FIXME: According to the ISA (section 2.5.1 of version 2.06), the 2597// condition-register logical instructions have preferred forms. Specifically, 2598// it is preferred that the bit specified by the BT field be in the same 2599// condition register as that specified by the bit BB. We might want to account 2600// for this via hinting the register allocator and anti-dep breakers, or we 2601// could constrain the register class to force this constraint and then loosen 2602// it during register allocation via convertToThreeAddress or some similar 2603// mechanism. 2604 2605let isCommutable = 1 in { 2606def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD), 2607 (ins crbitrc:$CRA, crbitrc:$CRB), 2608 "crand $CRD, $CRA, $CRB", IIC_BrCR, 2609 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>; 2610 2611def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD), 2612 (ins crbitrc:$CRA, crbitrc:$CRB), 2613 "crnand $CRD, $CRA, $CRB", IIC_BrCR, 2614 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>; 2615 2616def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD), 2617 (ins crbitrc:$CRA, crbitrc:$CRB), 2618 "cror $CRD, $CRA, $CRB", IIC_BrCR, 2619 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>; 2620 2621def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD), 2622 (ins crbitrc:$CRA, crbitrc:$CRB), 2623 "crxor $CRD, $CRA, $CRB", IIC_BrCR, 2624 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>; 2625 2626def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD), 2627 (ins crbitrc:$CRA, crbitrc:$CRB), 2628 "crnor $CRD, $CRA, $CRB", IIC_BrCR, 2629 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>; 2630def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD), 2631 (ins crbitrc:$CRA, crbitrc:$CRB), 2632 "creqv $CRD, $CRA, $CRB", IIC_BrCR, 2633 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>; 2634} // isCommutable 2635 2636let isCodeGenOnly = 1 in 2637def CRNOT : XLForm_1s<19, 33, (outs crbitrc:$CRD), (ins crbitrc:$CRA), 2638 "crnot $CRD, $CRA", IIC_BrCR, 2639 [(set i1:$CRD, (not i1:$CRA))]>; 2640 2641def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD), 2642 (ins crbitrc:$CRA, crbitrc:$CRB), 2643 "crandc $CRD, $CRA, $CRB", IIC_BrCR, 2644 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>; 2645 2646def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), 2647 (ins crbitrc:$CRA, crbitrc:$CRB), 2648 "crorc $CRD, $CRA, $CRB", IIC_BrCR, 2649 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>; 2650 2651let isCodeGenOnly = 1 in { 2652let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 2653def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$CRD), (ins), 2654 "creqv $CRD, $CRD, $CRD", IIC_BrCR, 2655 [(set i1:$CRD, 1)]>; 2656 2657def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$CRD), (ins), 2658 "crxor $CRD, $CRD, $CRD", IIC_BrCR, 2659 [(set i1:$CRD, 0)]>; 2660} 2661 2662let Defs = [CR1EQ], CRD = 6 in { 2663def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 2664 "creqv 6, 6, 6", IIC_BrCR, 2665 [(PPCcr6set)]>; 2666 2667def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 2668 "crxor 6, 6, 6", IIC_BrCR, 2669 [(PPCcr6unset)]>; 2670} 2671} 2672 2673// XFX-Form instructions. Instructions that deal with SPRs. 2674// 2675 2676def MFSPR : XFXForm_1<31, 339, (outs gprc:$RST), (ins i32imm:$SPR), 2677 "mfspr $RST, $SPR", IIC_SprMFSPR>; 2678def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RST), 2679 "mtspr $SPR, $RST", IIC_SprMTSPR>; 2680 2681def MFTB : XFXForm_1<31, 371, (outs gprc:$RST), (ins i32imm:$SPR), 2682 "mftb $RST, $SPR", IIC_SprMFTB>; 2683 2684def MFPMR : XFXForm_1<31, 334, (outs gprc:$RST), (ins i32imm:$SPR), 2685 "mfpmr $RST, $SPR", IIC_SprMFPMR>; 2686 2687def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RST), 2688 "mtpmr $SPR, $RST", IIC_SprMTPMR>; 2689 2690 2691// A pseudo-instruction used to implement the read of the 64-bit cycle counter 2692// on a 32-bit target. 2693let hasSideEffects = 1 in 2694def ReadTB : PPCCustomInserterPseudo<(outs gprc:$lo, gprc:$hi), (ins), 2695 "#ReadTB", []>; 2696 2697let Uses = [CTR] in { 2698def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$RST), (ins), 2699 "mfctr $RST", IIC_SprMFSPR>, 2700 PPC970_DGroup_First, PPC970_Unit_FXU; 2701} 2702let Defs = [CTR], Pattern = [(PPCmtctr i32:$RST)] in { 2703def MTCTR : XFXForm_1_ext<31, 467, 9, (outs), (ins gprc:$RST), 2704 "mtctr $RST", IIC_SprMTSPR>, 2705 PPC970_DGroup_First, PPC970_Unit_FXU; 2706} 2707let hasSideEffects = 1, isCodeGenOnly = 1, isNotDuplicable = 1, Defs = [CTR] in { 2708let Pattern = [(int_set_loop_iterations i32:$RST)] in 2709def MTCTRloop : XFXForm_1_ext<31, 467, 9, (outs), (ins gprc:$RST), 2710 "mtctr $RST", IIC_SprMTSPR>, 2711 PPC970_DGroup_First, PPC970_Unit_FXU; 2712} 2713 2714let hasSideEffects = 1, hasNoSchedulingInfo = 1, isNotDuplicable = 1, Uses = [CTR], Defs = [CTR] in 2715def DecreaseCTRloop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i32imm:$stride), 2716 "#DecreaseCTRloop", [(set i1:$rT, (int_loop_decrement (i32 imm:$stride)))]>; 2717 2718let hasSideEffects = 0 in { 2719let Defs = [LR] in { 2720def MTLR : XFXForm_1_ext<31, 467, 8, (outs), (ins gprc:$RST), 2721 "mtlr $RST", IIC_SprMTSPR>, 2722 PPC970_DGroup_First, PPC970_Unit_FXU; 2723} 2724let Uses = [LR] in { 2725def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$RST), (ins), 2726 "mflr $RST", IIC_SprMFSPR>, 2727 PPC970_DGroup_First, PPC970_Unit_FXU; 2728} 2729} 2730 2731let hasSideEffects = 1 in { 2732 def MTUDSCR : XFXForm_1_ext<31, 467, 3, (outs), (ins gprc:$RST), 2733 "mtspr 3, $RST", IIC_SprMTSPR>, 2734 PPC970_DGroup_Single, PPC970_Unit_FXU; 2735 def MFUDSCR : XFXForm_1_ext<31, 339, 3, (outs gprc:$RST), (ins), 2736 "mfspr $RST, 3", IIC_SprMFSPR>, 2737 PPC970_DGroup_First, PPC970_Unit_FXU; 2738} 2739 2740// Disable these alias on AIX since they are not supported. 2741let Predicates = [ModernAs] in { 2742// Aliases for moving to/from dscr to mtspr/mfspr 2743def : InstAlias<"mtudscr $Rx", (MTUDSCR gprc:$Rx)>; 2744def : InstAlias<"mfudscr $Rx", (MFUDSCR gprc:$Rx)>; 2745} 2746 2747let isCodeGenOnly = 1 in { 2748 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 2749 // like a GPR on the PPC970. As such, copies in and out have the same 2750 // performance characteristics as an OR instruction. 2751 def MTVRSAVE : XFXForm_1_ext<31, 467, 256, (outs), (ins gprc:$RST), 2752 "mtspr 256, $RST", IIC_IntGeneral>, 2753 PPC970_DGroup_Single, PPC970_Unit_FXU; 2754 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$RST), (ins), 2755 "mfspr $RST, 256", IIC_IntGeneral>, 2756 PPC970_DGroup_First, PPC970_Unit_FXU; 2757 2758 def MTVRSAVEv : XFXForm_1_ext<31, 467, 256, 2759 (outs VRSAVERC:$SPR), (ins gprc:$RST), 2760 "mtspr 256, $RST", IIC_IntGeneral>, 2761 PPC970_DGroup_Single, PPC970_Unit_FXU; 2762 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$RST), 2763 (ins VRSAVERC:$SPR), 2764 "mfspr $RST, 256", IIC_IntGeneral>, 2765 PPC970_DGroup_First, PPC970_Unit_FXU; 2766} 2767 2768// Aliases for mtvrsave/mfvrsave to mfspr/mtspr. 2769def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>; 2770def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>; 2771 2772let hasSideEffects = 0 in { 2773// mtocrf's input needs to be prepared by shifting by an amount dependent 2774// on the cr register selected. Thus, post-ra anti-dep breaking must not 2775// later change that register assignment. 2776let hasExtraDefRegAllocReq = 1 in { 2777def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$RST), 2778 "mtocrf $FXM, $RST", IIC_BrMCRX>, 2779 PPC970_DGroup_First, PPC970_Unit_CRU; 2780 2781// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 2782// is dependent on the cr fields being set. 2783def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$RST), 2784 "mtcrf $FXM, $RST", IIC_BrMCRX>, 2785 PPC970_MicroCode, PPC970_Unit_CRU; 2786} // hasExtraDefRegAllocReq = 1 2787 2788// mfocrf's input needs to be prepared by shifting by an amount dependent 2789// on the cr register selected. Thus, post-ra anti-dep breaking must not 2790// later change that register assignment. 2791let hasExtraSrcRegAllocReq = 1 in { 2792def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$RST), (ins crbitm:$FXM), 2793 "mfocrf $RST, $FXM", IIC_SprMFCRF>, 2794 PPC970_DGroup_First, PPC970_Unit_CRU; 2795 2796// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 2797// is dependent on the cr fields being copied. 2798def MFCR : XFXForm_3<31, 19, (outs gprc:$RT), (ins), 2799 "mfcr $RT", IIC_SprMFCR>, 2800 PPC970_MicroCode, PPC970_Unit_CRU; 2801} // hasExtraSrcRegAllocReq = 1 2802 2803def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins), 2804 "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>; 2805} // hasSideEffects = 0 2806 2807def : InstAlias<"mtcr $rA", (MTCRF 255, gprc:$rA)>; 2808 2809let Predicates = [HasFPU] in { 2810// Custom inserter instruction to perform FADD in round-to-zero mode. 2811let Uses = [RM], mayRaiseFPException = 1 in { 2812 def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", 2813 [(set f64:$FRT, (PPCany_faddrtz f64:$FRA, f64:$FRB))]>; 2814} 2815 2816// The above pseudo gets expanded to make use of the following instructions 2817// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 2818 2819// When FM is 30/31, we are setting the 62/63 bit of FPSCR, the implicit-def 2820// RM should be set. 2821let hasSideEffects = 1, Defs = [RM] in { 2822def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 2823 "mtfsb0 $FM", IIC_IntMTFSB0, 2824 [(int_ppc_mtfsb0 timm:$FM)]>, 2825 PPC970_DGroup_Single, PPC970_Unit_FPU; 2826def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 2827 "mtfsb1 $FM", IIC_IntMTFSB0, 2828 [(int_ppc_mtfsb1 timm:$FM)]>, 2829 PPC970_DGroup_Single, PPC970_Unit_FPU; 2830} 2831 2832let Defs = [RM], hasSideEffects = 1 in { 2833 let isCodeGenOnly = 1 in 2834 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$RT), 2835 "mtfsf $FM, $RT", IIC_IntMTFSB0, 2836 [(int_ppc_mtfsf timm:$FM, f64:$RT)]>, 2837 PPC970_DGroup_Single, PPC970_Unit_FPU; 2838} 2839let Uses = [RM], hasSideEffects = 1 in { 2840 def MFFS : XForm_42<63, 583, (outs f8rc:$RST), (ins), 2841 "mffs $RST", IIC_IntMFFS, 2842 [(set f64:$RST, (PPCmffs))]>, 2843 PPC970_DGroup_Single, PPC970_Unit_FPU; 2844 2845 let Defs = [CR1] in 2846 def MFFS_rec : XForm_42<63, 583, (outs f8rc:$RST), (ins), 2847 "mffs. $RST", IIC_IntMFFS, []>, isRecordForm; 2848 2849 def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$RST), (ins), 2850 "mffsce $RST", IIC_IntMFFS, []>, 2851 PPC970_DGroup_Single, PPC970_Unit_FPU; 2852 2853 def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$RST), 2854 (ins f8rc:$FRB), "mffscdrn $RST, $FRB", 2855 IIC_IntMFFS, []>, 2856 PPC970_DGroup_Single, PPC970_Unit_FPU; 2857 2858 def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$RST), 2859 (ins u3imm:$DRM), 2860 "mffscdrni $RST, $DRM", 2861 IIC_IntMFFS, []>, 2862 PPC970_DGroup_Single, PPC970_Unit_FPU; 2863 2864 def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$RST), 2865 (ins f8rc:$FRB), "mffscrn $RST, $FRB", 2866 IIC_IntMFFS, []>, 2867 PPC970_DGroup_Single, PPC970_Unit_FPU; 2868 2869 def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$RST), 2870 (ins u2imm:$RM), "mffscrni $RST, $RM", 2871 IIC_IntMFFS, []>, 2872 PPC970_DGroup_Single, PPC970_Unit_FPU; 2873 2874 def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$RST), (ins), 2875 "mffsl $RST", IIC_IntMFFS, []>, 2876 PPC970_DGroup_Single, PPC970_Unit_FPU; 2877} 2878} 2879 2880let Predicates = [IsISA3_0] in { 2881def MODSW : XForm_8<31, 779, (outs gprc:$RST), (ins gprc:$RA, gprc:$RB), 2882 "modsw $RST, $RA, $RB", IIC_IntDivW, 2883 [(set i32:$RST, (srem i32:$RA, i32:$RB))]>; 2884def MODUW : XForm_8<31, 267, (outs gprc:$RST), (ins gprc:$RA, gprc:$RB), 2885 "moduw $RST, $RA, $RB", IIC_IntDivW, 2886 [(set i32:$RST, (urem i32:$RA, i32:$RB))]>; 2887let hasSideEffects = 1 in 2888def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$RT), 2889 (ins gprc:$RA, gprc:$RB, u2imm:$CY), 2890 "addex $RT, $RA, $RB, $CY", IIC_IntGeneral, []>; 2891} 2892 2893let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2894// XO-Form instructions. Arithmetic instructions that can set overflow bit 2895let isCommutable = 1 in 2896defm ADD4 : XOForm_1rx<31, 266, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2897 "add", "$RT, $RA, $RB", IIC_IntSimple, 2898 [(set i32:$RT, (add i32:$RA, i32:$RB))]>; 2899let isCodeGenOnly = 1 in 2900def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$RT), (ins gprc:$RA, tlsreg32:$RB), 2901 "add $RT, $RA, $RB", IIC_IntSimple, 2902 [(set i32:$RT, (add i32:$RA, tglobaltlsaddr:$RB))]>; 2903let isCommutable = 1 in 2904defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2905 "addc", "$RT, $RA, $RB", IIC_IntGeneral, 2906 [(set i32:$RT, (addc i32:$RA, i32:$RB))]>, 2907 PPC970_DGroup_Cracked; 2908 2909defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2910 "divw", "$RT, $RA, $RB", IIC_IntDivW, 2911 [(set i32:$RT, (sdiv i32:$RA, i32:$RB))]>; 2912defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2913 "divwu", "$RT, $RA, $RB", IIC_IntDivW, 2914 [(set i32:$RT, (udiv i32:$RA, i32:$RB))]>; 2915defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2916 "divwe", "$RT, $RA, $RB", IIC_IntDivW, 2917 [(set i32:$RT, (int_ppc_divwe gprc:$RA, gprc:$RB))]>, 2918 Requires<[HasExtDiv]>; 2919defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2920 "divweu", "$RT, $RA, $RB", IIC_IntDivW, 2921 [(set i32:$RT, (int_ppc_divweu gprc:$RA, gprc:$RB))]>, 2922 Requires<[HasExtDiv]>; 2923let isCommutable = 1 in { 2924defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2925 "mulhw", "$RT, $RA, $RB", IIC_IntMulHW, 2926 [(set i32:$RT, (mulhs i32:$RA, i32:$RB))]>; 2927defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2928 "mulhwu", "$RT, $RA, $RB", IIC_IntMulHWU, 2929 [(set i32:$RT, (mulhu i32:$RA, i32:$RB))]>; 2930defm MULLW : XOForm_1rx<31, 235, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2931 "mullw", "$RT, $RA, $RB", IIC_IntMulHW, 2932 [(set i32:$RT, (mul i32:$RA, i32:$RB))]>; 2933} // isCommutable 2934defm SUBF : XOForm_1rx<31, 40, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2935 "subf", "$RT, $RA, $RB", IIC_IntGeneral, 2936 [(set i32:$RT, (sub i32:$RB, i32:$RA))]>; 2937defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2938 "subfc", "$RT, $RA, $RB", IIC_IntGeneral, 2939 [(set i32:$RT, (subc i32:$RB, i32:$RA))]>, 2940 PPC970_DGroup_Cracked; 2941defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$RT), (ins gprc:$RA), 2942 "neg", "$RT, $RA", IIC_IntSimple, 2943 [(set i32:$RT, (ineg i32:$RA))]>; 2944let Uses = [CARRY] in { 2945let isCommutable = 1 in 2946defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2947 "adde", "$RT, $RA, $RB", IIC_IntGeneral, 2948 [(set i32:$RT, (adde i32:$RA, i32:$RB))]>; 2949defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$RT), (ins gprc:$RA), 2950 "addme", "$RT, $RA", IIC_IntGeneral, 2951 [(set i32:$RT, (adde i32:$RA, -1))]>; 2952defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$RT), (ins gprc:$RA), 2953 "addze", "$RT, $RA", IIC_IntGeneral, 2954 [(set i32:$RT, (adde i32:$RA, 0))]>; 2955defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2956 "subfe", "$RT, $RA, $RB", IIC_IntGeneral, 2957 [(set i32:$RT, (sube i32:$RB, i32:$RA))]>; 2958defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$RT), (ins gprc:$RA), 2959 "subfme", "$RT, $RA", IIC_IntGeneral, 2960 [(set i32:$RT, (sube -1, i32:$RA))]>; 2961defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$RT), (ins gprc:$RA), 2962 "subfze", "$RT, $RA", IIC_IntGeneral, 2963 [(set i32:$RT, (sube 0, i32:$RA))]>; 2964} 2965} 2966 2967def : InstAlias<"sub $rA, $rB, $rC", (SUBF gprc:$rA, gprc:$rC, gprc:$rB)>; 2968def : InstAlias<"sub. $rA, $rB, $rC", (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 2969def : InstAlias<"subc $rA, $rB, $rC", (SUBFC gprc:$rA, gprc:$rC, gprc:$rB)>; 2970def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 2971 2972// A-Form instructions. Most of the instructions executed in the FPU are of 2973// this type. 2974// 2975let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2976let mayRaiseFPException = 1, Uses = [RM] in { 2977let isCommutable = 1 in { 2978 defm FMADD : AForm_1r<63, 29, 2979 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2980 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2981 [(set f64:$FRT, (any_fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 2982 defm FMADDS : AForm_1r<59, 29, 2983 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2984 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2985 [(set f32:$FRT, (any_fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 2986 defm FMSUB : AForm_1r<63, 28, 2987 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2988 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2989 [(set f64:$FRT, 2990 (any_fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 2991 defm FMSUBS : AForm_1r<59, 28, 2992 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2993 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2994 [(set f32:$FRT, 2995 (any_fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 2996 defm FNMADD : AForm_1r<63, 31, 2997 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2998 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2999 [(set f64:$FRT, 3000 (fneg (any_fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 3001 defm FNMADDS : AForm_1r<59, 31, 3002 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3003 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3004 [(set f32:$FRT, 3005 (fneg (any_fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 3006 defm FNMSUB : AForm_1r<63, 30, 3007 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3008 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3009 [(set f64:$FRT, (fneg (any_fma f64:$FRA, f64:$FRC, 3010 (fneg f64:$FRB))))]>; 3011 defm FNMSUBS : AForm_1r<59, 30, 3012 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3013 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3014 [(set f32:$FRT, (fneg (any_fma f32:$FRA, f32:$FRC, 3015 (fneg f32:$FRB))))]>; 3016} // isCommutable 3017} 3018// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 3019// having 4 of these, force the comparison to always be an 8-byte double (code 3020// should use an FMRSD if the input comparison value really wants to be a float) 3021// and 4/8 byte forms for the result and operand type.. 3022let Interpretation64Bit = 1, isCodeGenOnly = 1 in 3023defm FSELD : AForm_1r<63, 23, 3024 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3025 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3026 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 3027defm FSELS : AForm_1r<63, 23, 3028 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3029 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3030 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 3031let Uses = [RM], mayRaiseFPException = 1 in { 3032 let isCommutable = 1 in { 3033 defm FADD : AForm_2r<63, 21, 3034 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3035 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3036 [(set f64:$FRT, (any_fadd f64:$FRA, f64:$FRB))]>; 3037 defm FADDS : AForm_2r<59, 21, 3038 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3039 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3040 [(set f32:$FRT, (any_fadd f32:$FRA, f32:$FRB))]>; 3041 } // isCommutable 3042 defm FDIV : AForm_2r<63, 18, 3043 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3044 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD, 3045 [(set f64:$FRT, (any_fdiv f64:$FRA, f64:$FRB))]>; 3046 defm FDIVS : AForm_2r<59, 18, 3047 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3048 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS, 3049 [(set f32:$FRT, (any_fdiv f32:$FRA, f32:$FRB))]>; 3050 let isCommutable = 1 in { 3051 defm FMUL : AForm_3r<63, 25, 3052 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC), 3053 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused, 3054 [(set f64:$FRT, (any_fmul f64:$FRA, f64:$FRC))]>; 3055 defm FMULS : AForm_3r<59, 25, 3056 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC), 3057 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral, 3058 [(set f32:$FRT, (any_fmul f32:$FRA, f32:$FRC))]>; 3059 } // isCommutable 3060 defm FSUB : AForm_2r<63, 20, 3061 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3062 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3063 [(set f64:$FRT, (any_fsub f64:$FRA, f64:$FRB))]>; 3064 defm FSUBS : AForm_2r<59, 20, 3065 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3066 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3067 [(set f32:$FRT, (any_fsub f32:$FRA, f32:$FRB))]>; 3068 } 3069} 3070 3071let hasSideEffects = 0 in { 3072let PPC970_Unit = 1 in { // FXU Operations. 3073 let isSelect = 1 in 3074 def ISEL : AForm_4<31, 15, 3075 (outs gprc:$RT), (ins gprc_nor0:$RA, gprc:$RB, crbitrc:$COND), 3076 "isel $RT, $RA, $RB, $COND", IIC_IntISEL, 3077 []>; 3078} 3079 3080let PPC970_Unit = 1 in { // FXU Operations. 3081// M-Form instructions. rotate and mask instructions. 3082// 3083let isCommutable = 1 in { 3084// RLWIMI can be commuted if the rotate amount is zero. 3085defm RLWIMI : MForm_2r<20, (outs gprc:$RA), 3086 (ins gprc:$RAi, gprc:$RS, u5imm:$SH, u5imm:$MB, 3087 u5imm:$ME), "rlwimi", "$RA, $RS, $SH, $MB, $ME", 3088 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 3089 RegConstraint<"$RAi = $RA">, NoEncode<"$RAi">; 3090} 3091let BaseName = "rlwinm" in { 3092def RLWINM : MForm_2<21, 3093 (outs gprc:$RA), (ins gprc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3094 "rlwinm $RA, $RS, $SH, $MB, $ME", IIC_IntGeneral, 3095 []>, RecFormRel; 3096let Defs = [CR0] in 3097def RLWINM_rec : MForm_2<21, 3098 (outs gprc:$RA), (ins gprc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3099 "rlwinm. $RA, $RS, $SH, $MB, $ME", IIC_IntGeneral, 3100 []>, isRecordForm, RecFormRel, PPC970_DGroup_Cracked; 3101} 3102defm RLWNM : MForm_1r<23, (outs gprc:$RA), 3103 (ins gprc:$RS, gprc:$RB, u5imm:$MB, u5imm:$ME), 3104 "rlwnm", "$RA, $RS, $RB, $MB, $ME", IIC_IntGeneral, 3105 []>; 3106} 3107} // hasSideEffects = 0 3108 3109//===----------------------------------------------------------------------===// 3110// PowerPC Instruction Patterns 3111// 3112 3113// Arbitrary immediate support. Implement in terms of LIS/ORI. 3114def : Pat<(i32 imm:$imm), 3115 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 3116 3117// Implement the 'not' operation with the NOR instruction. 3118def i32not : OutPatFrag<(ops node:$in), 3119 (NOR $in, $in)>; 3120def : Pat<(not i32:$in), 3121 (i32not $in)>; 3122 3123// ADD an arbitrary immediate. 3124def : Pat<(add i32:$in, imm:$imm), 3125 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 3126// OR an arbitrary immediate. 3127def : Pat<(or i32:$in, imm:$imm), 3128 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3129// XOR an arbitrary immediate. 3130def : Pat<(xor i32:$in, imm:$imm), 3131 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3132// SUBFIC 3133def : Pat<(sub imm32SExt16:$imm, i32:$in), 3134 (SUBFIC $in, imm:$imm)>; 3135 3136// SHL/SRL 3137def : Pat<(shl i32:$in, (i32 imm:$imm)), 3138 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 3139def : Pat<(srl i32:$in, (i32 imm:$imm)), 3140 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 3141 3142// ROTL 3143def : Pat<(rotl i32:$in, i32:$sh), 3144 (RLWNM $in, $sh, 0, 31)>; 3145def : Pat<(rotl i32:$in, (i32 imm:$imm)), 3146 (RLWINM $in, imm:$imm, 0, 31)>; 3147 3148// RLWNM 3149def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 3150 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 3151 3152// Calls 3153def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 3154 (BL tglobaladdr:$dst)>; 3155 3156def : Pat<(PPCcall (i32 texternalsym:$dst)), 3157 (BL texternalsym:$dst)>; 3158 3159def : Pat<(PPCcall_rm (i32 tglobaladdr:$dst)), 3160 (BL_RM tglobaladdr:$dst)>; 3161 3162def : Pat<(PPCcall_rm (i32 texternalsym:$dst)), 3163 (BL_RM texternalsym:$dst)>; 3164 3165// Calls for AIX only 3166def : Pat<(PPCcall (i32 mcsym:$dst)), 3167 (BL mcsym:$dst)>; 3168 3169def : Pat<(PPCcall_nop (i32 mcsym:$dst)), 3170 (BL_NOP mcsym:$dst)>; 3171 3172def : Pat<(PPCcall_nop (i32 texternalsym:$dst)), 3173 (BL_NOP texternalsym:$dst)>; 3174 3175def : Pat<(PPCcall_rm (i32 mcsym:$dst)), 3176 (BL_RM mcsym:$dst)>; 3177 3178def : Pat<(PPCcall_nop_rm (i32 mcsym:$dst)), 3179 (BL_NOP_RM mcsym:$dst)>; 3180 3181def : Pat<(PPCcall_nop_rm (i32 texternalsym:$dst)), 3182 (BL_NOP_RM texternalsym:$dst)>; 3183 3184def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 3185 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 3186 3187def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 3188 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 3189 3190def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 3191 (TCRETURNri CTRRC:$dst, imm:$imm)>; 3192 3193def : Pat<(int_ppc_fence), (FENCE)>; 3194def : Pat<(int_ppc_readflm), (MFFS)>; 3195def : Pat<(int_ppc_mffsl), (MFFSL)>; 3196 3197// Hi and Lo for Darwin Global Addresses. 3198def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 3199def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 3200def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 3201def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 3202def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 3203def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 3204def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 3205def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 3206def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 3207 (ADDIS $in, tglobaltlsaddr:$g)>; 3208def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 3209 (ADDI $in, tglobaltlsaddr:$g)>; 3210def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 3211 (ADDIS $in, tglobaladdr:$g)>; 3212def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 3213 (ADDIS $in, tconstpool:$g)>; 3214def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 3215 (ADDIS $in, tjumptable:$g)>; 3216def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 3217 (ADDIS $in, tblockaddress:$g)>; 3218 3219// Support for thread-local storage. 3220def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT", 3221 [(set i32:$rD, (PPCppc32GOT))]>; 3222 3223// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode. 3224// This uses two output registers, the first as the real output, the second as a 3225// temporary register, used internally in code generation. 3226def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", 3227 []>, NoEncode<"$rT">; 3228 3229def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg), 3230 "#LDgotTprelL32", 3231 [(set i32:$rD, 3232 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; 3233def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), 3234 (ADD4TLS $in, tglobaltlsaddr:$g)>; 3235 3236def ADDItlsgdL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3237 "#ADDItlsgdL32", 3238 [(set i32:$rD, 3239 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>; 3240// LR is a true define, while the rest of the Defs are clobbers. R3 is 3241// explicitly defined when this op is created, so not mentioned here. 3242let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3243 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3244def GETtlsADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3245 "GETtlsADDR32", 3246 [(set i32:$rD, 3247 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>; 3248// R3 is explicitly defined when this op is created, so not mentioned here. 3249// The rest of the Defs are the exact set of registers that will be clobbered by 3250// the call. 3251let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3252 Defs = [R0,R4,R5,R11,LR,CR0] in 3253def GETtlsADDR32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3254 "GETtlsADDR32AIX", 3255 [(set i32:$rD, 3256 (PPCgetTlsAddr i32:$offset, i32:$handle))]>; 3257 3258// For local-exec accesses on 32-bit AIX, a call to .__get_tpointer is 3259// generated to retrieve the thread pointer. GETtlsTpointer32AIX clobbers both 3260// R3 and the LR (link register). 3261let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3262 Defs = [R3,LR] in 3263def GETtlsTpointer32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins), 3264 "GETtlsTpointer32AIX", 3265 [(set i32:$rD, (PPCgetTpointer))]>; 3266 3267// The following pattern matches local- and initial-exec TLS accesses on 32-bit AIX. 3268// PPCaddTls is used in local- and initial-exec accesses in order to: 3269// - Get the address of a variable (add the variable offset to the thread 3270// pointer, retrieved by calling .__get_tpointer). 3271// - Create an opportunity to optimize the user of the loaded address. 3272def : Pat<(PPCaddTls i32:$in, i32:$addr), 3273 (ADD4TLS $in, $addr)>; 3274 3275// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR 3276// are true defines while the rest of the Defs are clobbers. 3277let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3278 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3279def ADDItlsgdLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3280 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3281 "#ADDItlsgdLADDR32", 3282 [(set i32:$rD, 3283 (PPCaddiTlsgdLAddr i32:$reg, 3284 tglobaltlsaddr:$disp, 3285 tglobaltlsaddr:$sym))]>; 3286def ADDItlsldL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3287 "#ADDItlsldL32", 3288 [(set i32:$rD, 3289 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>; 3290// This pseudo is expanded to two copies to put the variable offset in R4 and 3291// the region handle in R3 and GETtlsADDR32AIX. 3292def TLSGDAIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3293 "#TLSGDAIX", 3294 [(set i32:$rD, 3295 (PPCTlsgdAIX i32:$offset, i32:$handle))]>; 3296// LR is a true define, while the rest of the Defs are clobbers. R3 is 3297// explicitly defined when this op is created, so not mentioned here. 3298let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3299 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3300def GETtlsldADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3301 "GETtlsldADDR32", 3302 [(set i32:$rD, 3303 (PPCgetTlsldAddr i32:$reg, 3304 tglobaltlsaddr:$sym))]>; 3305// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR 3306// are true defines while the rest of the Defs are clobbers. 3307let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3308 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3309def ADDItlsldLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3310 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3311 "#ADDItlsldLADDR32", 3312 [(set i32:$rD, 3313 (PPCaddiTlsldLAddr i32:$reg, 3314 tglobaltlsaddr:$disp, 3315 tglobaltlsaddr:$sym))]>; 3316def ADDIdtprelL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3317 "#ADDIdtprelL32", 3318 [(set i32:$rD, 3319 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>; 3320def ADDISdtprelHA32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3321 "#ADDISdtprelHA32", 3322 [(set i32:$rD, 3323 (PPCaddisDtprelHA i32:$reg, 3324 tglobaltlsaddr:$disp))]>; 3325 3326// Support for Position-independent code 3327def LWZtoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3328 "#LWZtoc", 3329 [(set i32:$rD, 3330 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3331def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor0:$reg), 3332 "#LWZtocL", 3333 [(set i32:$rD, 3334 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3335def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp), 3336 "#ADDIStocHA", 3337 [(set i32:$rD, 3338 (PPCtoc_entry i32:$reg, tglobaladdr:$disp))]>; 3339// Local Data Transform 3340def ADDItoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3341 "#ADDItoc", 3342 [(set i32:$rD, 3343 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3344 3345// Get Global (GOT) Base Register offset, from the word immediately preceding 3346// the function label. 3347def UpdateGBR : PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>; 3348 3349// Pseudo-instruction marked for deletion. When deleting the instruction would 3350// cause iterator invalidation in MIR transformation passes, this pseudo can be 3351// used instead. It will be removed unconditionally at pre-emit time (prior to 3352// branch selection). 3353def UNENCODED_NOP: PPCEmitTimePseudo<(outs), (ins), "#UNENCODED_NOP", []>; 3354 3355// Standard shifts. These are represented separately from the real shifts above 3356// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 3357// amounts. 3358def : Pat<(sra i32:$rS, i32:$rB), 3359 (SRAW $rS, $rB)>; 3360def : Pat<(srl i32:$rS, i32:$rB), 3361 (SRW $rS, $rB)>; 3362def : Pat<(shl i32:$rS, i32:$rB), 3363 (SLW $rS, $rB)>; 3364 3365def : Pat<(i32 (zextloadi1 DForm:$src)), 3366 (LBZ DForm:$src)>; 3367def : Pat<(i32 (zextloadi1 XForm:$src)), 3368 (LBZX XForm:$src)>; 3369def : Pat<(i32 (extloadi1 DForm:$src)), 3370 (LBZ DForm:$src)>; 3371def : Pat<(i32 (extloadi1 XForm:$src)), 3372 (LBZX XForm:$src)>; 3373def : Pat<(i32 (extloadi8 DForm:$src)), 3374 (LBZ DForm:$src)>; 3375def : Pat<(i32 (extloadi8 XForm:$src)), 3376 (LBZX XForm:$src)>; 3377def : Pat<(i32 (extloadi16 DForm:$src)), 3378 (LHZ DForm:$src)>; 3379def : Pat<(i32 (extloadi16 XForm:$src)), 3380 (LHZX XForm:$src)>; 3381let Predicates = [HasFPU] in { 3382def : Pat<(f64 (extloadf32 DForm:$src)), 3383 (COPY_TO_REGCLASS (LFS DForm:$src), F8RC)>; 3384def : Pat<(f64 (extloadf32 XForm:$src)), 3385 (COPY_TO_REGCLASS (LFSX XForm:$src), F8RC)>; 3386 3387def : Pat<(f64 (any_fpextend f32:$src)), 3388 (COPY_TO_REGCLASS $src, F8RC)>; 3389} 3390 3391// Only seq_cst fences require the heavyweight sync (SYNC 0). 3392// All others can use the lightweight sync (SYNC 1). 3393// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html 3394// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits 3395// versions of Power. 3396def : Pat<(atomic_fence (i64 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3397def : Pat<(atomic_fence (i32 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3398def : Pat<(atomic_fence (timm), (timm)), (SYNC 1)>, Requires<[HasSYNC]>; 3399def : Pat<(atomic_fence (timm), (timm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 3400 3401let Predicates = [HasFPU] in { 3402// Additional fnmsub patterns for custom node 3403def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C), 3404 (FNMSUB $A, $B, $C)>; 3405def : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C), 3406 (FNMSUBS $A, $B, $C)>; 3407def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)), 3408 (FMSUB $A, $B, $C)>; 3409def : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)), 3410 (FMSUBS $A, $B, $C)>; 3411def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)), 3412 (FNMADD $A, $B, $C)>; 3413def : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)), 3414 (FNMADDS $A, $B, $C)>; 3415 3416// FCOPYSIGN's operand types need not agree. 3417def : Pat<(fcopysign f64:$frB, f32:$frA), 3418 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>; 3419def : Pat<(fcopysign f32:$frB, f64:$frA), 3420 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>; 3421} 3422 3423// XL Compat intrinsics. 3424def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (FMSUB $A, $B, $C)>; 3425def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (FMSUBS $A, $B, $C)>; 3426def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (FNMADD $A, $B, $C)>; 3427def : Pat<(int_ppc_fnmadds f32:$A, f32:$B, f32:$C), (FNMADDS $A, $B, $C)>; 3428def : Pat<(int_ppc_fre f64:$A), (FRE $A)>; 3429def : Pat<(int_ppc_fres f32:$A), (FRES $A)>; 3430def : Pat<(int_ppc_fnabs f64:$A), (FNABSD $A)>; 3431def : Pat<(int_ppc_fnabss f32:$A), (FNABSS $A)>; 3432 3433include "PPCInstrAltivec.td" 3434include "PPCInstrSPE.td" 3435include "PPCInstr64Bit.td" 3436include "PPCInstrVSX.td" 3437include "PPCInstrHTM.td" 3438 3439def crnot : OutPatFrag<(ops node:$in), 3440 (CRNOT $in)>; 3441def : Pat<(not i1:$in), 3442 (crnot $in)>; 3443 3444// Pseudo-instructions for alternate assembly syntax (never used by codegen). 3445// These are aliases that require C++ handling to convert to the target 3446// instruction, while InstAliases can be handled directly by tblgen. 3447class PPCAsmPseudo<string asm, dag iops> 3448 : Instruction { 3449 let Namespace = "PPC"; 3450 bit PPC64 = 0; // Default value, override with isPPC64 3451 3452 let OutOperandList = (outs); 3453 let InOperandList = iops; 3454 let Pattern = []; 3455 let AsmString = asm; 3456 let isAsmParserOnly = 1; 3457 let isPseudo = 1; 3458 let hasNoSchedulingInfo = 1; 3459} 3460 3461// Prefixed instructions may require access to the above defs at a later 3462// time so we include this after the def. 3463include "PPCInstrP10.td" 3464include "PPCInstrFutureMMA.td" 3465include "PPCInstrFuture.td" 3466include "PPCInstrMMA.td" 3467include "PPCInstrDFP.td" 3468 3469// Patterns for arithmetic i1 operations. 3470def : Pat<(add i1:$a, i1:$b), 3471 (CRXOR $a, $b)>; 3472def : Pat<(sub i1:$a, i1:$b), 3473 (CRXOR $a, $b)>; 3474def : Pat<(mul i1:$a, i1:$b), 3475 (CRAND $a, $b)>; 3476 3477// We're sometimes asked to materialize i1 -1, which is just 1 in this case 3478// (-1 is used to mean all bits set). 3479def : Pat<(i1 -1), (CRSET)>; 3480 3481// i1 extensions, implemented in terms of isel. 3482def : Pat<(i32 (zext i1:$in)), 3483 (SELECT_I4 $in, (LI 1), (LI 0))>; 3484def : Pat<(i32 (sext i1:$in)), 3485 (SELECT_I4 $in, (LI -1), (LI 0))>; 3486 3487def : Pat<(i64 (zext i1:$in)), 3488 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3489def : Pat<(i64 (sext i1:$in)), 3490 (SELECT_I8 $in, (LI8 -1), (LI8 0))>; 3491 3492// FIXME: We should choose either a zext or a sext based on other constants 3493// already around. 3494def : Pat<(i32 (anyext i1:$in)), 3495 (SELECT_I4 $in, (LI 1), (LI 0))>; 3496def : Pat<(i64 (anyext i1:$in)), 3497 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3498 3499// match setcc on i1 variables. 3500// CRANDC is: 3501// 1 1 : F 3502// 1 0 : T 3503// 0 1 : F 3504// 0 0 : F 3505// 3506// LT is: 3507// -1 -1 : F 3508// -1 0 : T 3509// 0 -1 : F 3510// 0 0 : F 3511// 3512// ULT is: 3513// 1 1 : F 3514// 1 0 : F 3515// 0 1 : T 3516// 0 0 : F 3517def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 3518 (CRANDC $s1, $s2)>; 3519def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 3520 (CRANDC $s2, $s1)>; 3521// CRORC is: 3522// 1 1 : T 3523// 1 0 : T 3524// 0 1 : F 3525// 0 0 : T 3526// 3527// LE is: 3528// -1 -1 : T 3529// -1 0 : T 3530// 0 -1 : F 3531// 0 0 : T 3532// 3533// ULE is: 3534// 1 1 : T 3535// 1 0 : F 3536// 0 1 : T 3537// 0 0 : T 3538def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 3539 (CRORC $s1, $s2)>; 3540def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 3541 (CRORC $s2, $s1)>; 3542 3543def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 3544 (CREQV $s1, $s2)>; 3545 3546// GE is: 3547// -1 -1 : T 3548// -1 0 : F 3549// 0 -1 : T 3550// 0 0 : T 3551// 3552// UGE is: 3553// 1 1 : T 3554// 1 0 : T 3555// 0 1 : F 3556// 0 0 : T 3557def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 3558 (CRORC $s2, $s1)>; 3559def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 3560 (CRORC $s1, $s2)>; 3561 3562// GT is: 3563// -1 -1 : F 3564// -1 0 : F 3565// 0 -1 : T 3566// 0 0 : F 3567// 3568// UGT is: 3569// 1 1 : F 3570// 1 0 : T 3571// 0 1 : F 3572// 0 0 : F 3573def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 3574 (CRANDC $s2, $s1)>; 3575def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), 3576 (CRANDC $s1, $s2)>; 3577 3578def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)), 3579 (CRXOR $s1, $s2)>; 3580 3581// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE, 3582// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for 3583// floating-point types. 3584 3585multiclass CRNotPat<dag pattern, dag result> { 3586 def : Pat<pattern, (crnot result)>; 3587 def : Pat<(not pattern), result>; 3588 3589 // We can also fold the crnot into an extension: 3590 def : Pat<(i32 (zext pattern)), 3591 (SELECT_I4 result, (LI 0), (LI 1))>; 3592 def : Pat<(i32 (sext pattern)), 3593 (SELECT_I4 result, (LI 0), (LI -1))>; 3594 3595 // We can also fold the crnot into an extension: 3596 def : Pat<(i64 (zext pattern)), 3597 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3598 def : Pat<(i64 (sext pattern)), 3599 (SELECT_I8 result, (LI8 0), (LI8 -1))>; 3600 3601 // FIXME: We should choose either a zext or a sext based on other constants 3602 // already around. 3603 def : Pat<(i32 (anyext pattern)), 3604 (SELECT_I4 result, (LI 0), (LI 1))>; 3605 3606 def : Pat<(i64 (anyext pattern)), 3607 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3608} 3609 3610// FIXME: Because of what seems like a bug in TableGen's type-inference code, 3611// we need to write imm:$imm in the output patterns below, not just $imm, or 3612// else the resulting matcher will not correctly add the immediate operand 3613// (making it a register operand instead). 3614 3615// extended SETCC. 3616multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag, 3617 OutPatFrag rfrag, OutPatFrag rfrag8> { 3618 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))), 3619 (rfrag $s1)>; 3620 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))), 3621 (rfrag8 $s1)>; 3622 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))), 3623 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3624 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))), 3625 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3626 3627 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))), 3628 (rfrag $s1)>; 3629 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))), 3630 (rfrag8 $s1)>; 3631 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))), 3632 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3633 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))), 3634 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3635} 3636 3637// Note that we do all inversions below with i(32|64)not, instead of using 3638// (xori x, 1) because on the A2 nor has single-cycle latency while xori 3639// has 2-cycle latency. 3640 3641defm : ExtSetCCPat<SETEQ, 3642 PatFrag<(ops node:$in, node:$cc), 3643 (setcc $in, 0, $cc)>, 3644 OutPatFrag<(ops node:$in), 3645 (RLWINM (CNTLZW $in), 27, 31, 31)>, 3646 OutPatFrag<(ops node:$in), 3647 (RLDICL (CNTLZD $in), 58, 63)> >; 3648 3649defm : ExtSetCCPat<SETNE, 3650 PatFrag<(ops node:$in, node:$cc), 3651 (setcc $in, 0, $cc)>, 3652 OutPatFrag<(ops node:$in), 3653 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>, 3654 OutPatFrag<(ops node:$in), 3655 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >; 3656 3657defm : ExtSetCCPat<SETLT, 3658 PatFrag<(ops node:$in, node:$cc), 3659 (setcc $in, 0, $cc)>, 3660 OutPatFrag<(ops node:$in), 3661 (RLWINM $in, 1, 31, 31)>, 3662 OutPatFrag<(ops node:$in), 3663 (RLDICL $in, 1, 63)> >; 3664 3665defm : ExtSetCCPat<SETGE, 3666 PatFrag<(ops node:$in, node:$cc), 3667 (setcc $in, 0, $cc)>, 3668 OutPatFrag<(ops node:$in), 3669 (RLWINM (i32not $in), 1, 31, 31)>, 3670 OutPatFrag<(ops node:$in), 3671 (RLDICL (i64not $in), 1, 63)> >; 3672 3673defm : ExtSetCCPat<SETGT, 3674 PatFrag<(ops node:$in, node:$cc), 3675 (setcc $in, 0, $cc)>, 3676 OutPatFrag<(ops node:$in), 3677 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>, 3678 OutPatFrag<(ops node:$in), 3679 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >; 3680 3681defm : ExtSetCCPat<SETLE, 3682 PatFrag<(ops node:$in, node:$cc), 3683 (setcc $in, 0, $cc)>, 3684 OutPatFrag<(ops node:$in), 3685 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>, 3686 OutPatFrag<(ops node:$in), 3687 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >; 3688 3689defm : ExtSetCCPat<SETLT, 3690 PatFrag<(ops node:$in, node:$cc), 3691 (setcc $in, -1, $cc)>, 3692 OutPatFrag<(ops node:$in), 3693 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>, 3694 OutPatFrag<(ops node:$in), 3695 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3696 3697defm : ExtSetCCPat<SETGE, 3698 PatFrag<(ops node:$in, node:$cc), 3699 (setcc $in, -1, $cc)>, 3700 OutPatFrag<(ops node:$in), 3701 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>, 3702 OutPatFrag<(ops node:$in), 3703 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3704 3705defm : ExtSetCCPat<SETGT, 3706 PatFrag<(ops node:$in, node:$cc), 3707 (setcc $in, -1, $cc)>, 3708 OutPatFrag<(ops node:$in), 3709 (RLWINM (i32not $in), 1, 31, 31)>, 3710 OutPatFrag<(ops node:$in), 3711 (RLDICL (i64not $in), 1, 63)> >; 3712 3713defm : ExtSetCCPat<SETLE, 3714 PatFrag<(ops node:$in, node:$cc), 3715 (setcc $in, -1, $cc)>, 3716 OutPatFrag<(ops node:$in), 3717 (RLWINM $in, 1, 31, 31)>, 3718 OutPatFrag<(ops node:$in), 3719 (RLDICL $in, 1, 63)> >; 3720 3721// An extended SETCC with shift amount. 3722multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag, 3723 OutPatFrag rfrag, OutPatFrag rfrag8> { 3724 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3725 (rfrag $s1, $sa)>; 3726 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3727 (rfrag8 $s1, $sa)>; 3728 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3729 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3730 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3731 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3732 3733 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3734 (rfrag $s1, $sa)>; 3735 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3736 (rfrag8 $s1, $sa)>; 3737 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3738 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3739 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3740 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3741} 3742 3743defm : ExtSetCCShiftPat<SETNE, 3744 PatFrag<(ops node:$in, node:$sa, node:$cc), 3745 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3746 OutPatFrag<(ops node:$in, node:$sa), 3747 (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>, 3748 OutPatFrag<(ops node:$in, node:$sa), 3749 (RLDCL $in, (SUBFIC $sa, 64), 63)> >; 3750 3751defm : ExtSetCCShiftPat<SETEQ, 3752 PatFrag<(ops node:$in, node:$sa, node:$cc), 3753 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3754 OutPatFrag<(ops node:$in, node:$sa), 3755 (RLWNM (i32not $in), 3756 (SUBFIC $sa, 32), 31, 31)>, 3757 OutPatFrag<(ops node:$in, node:$sa), 3758 (RLDCL (i64not $in), 3759 (SUBFIC $sa, 64), 63)> >; 3760 3761// SETCC for i32. 3762def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)), 3763 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3764def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)), 3765 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3766def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)), 3767 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3768def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)), 3769 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3770def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)), 3771 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3772def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)), 3773 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3774 3775// For non-equality comparisons, the default code would materialize the 3776// constant, then compare against it, like this: 3777// lis r2, 4660 3778// ori r2, r2, 22136 3779// cmpw cr0, r3, r2 3780// beq cr0,L6 3781// Since we are just comparing for equality, we can emit this instead: 3782// xoris r0,r3,0x1234 3783// cmplwi cr0,r0,0x5678 3784// beq cr0,L6 3785 3786def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)), 3787 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3788 (LO16 imm:$imm)), sub_eq)>; 3789 3790def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)), 3791 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3792def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)), 3793 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3794def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)), 3795 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3796def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)), 3797 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3798def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)), 3799 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3800 3801// SETCC for i64. 3802def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)), 3803 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3804def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)), 3805 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3806def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)), 3807 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3808def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)), 3809 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3810def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)), 3811 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3812def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)), 3813 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3814 3815// For non-equality comparisons, the default code would materialize the 3816// constant, then compare against it, like this: 3817// lis r2, 4660 3818// ori r2, r2, 22136 3819// cmpd cr0, r3, r2 3820// beq cr0,L6 3821// Since we are just comparing for equality, we can emit this instead: 3822// xoris r0,r3,0x1234 3823// cmpldi cr0,r0,0x5678 3824// beq cr0,L6 3825 3826def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)), 3827 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3828 (LO16 imm:$imm)), sub_eq)>; 3829 3830def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)), 3831 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3832def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)), 3833 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3834def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)), 3835 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3836def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)), 3837 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3838def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)), 3839 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3840 3841let Predicates = [IsNotISA3_1] in { 3842// Instantiations of CRNotPat for i32. 3843defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)), 3844 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3845defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)), 3846 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3847defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)), 3848 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3849defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)), 3850 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3851defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)), 3852 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3853defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)), 3854 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3855 3856defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 3857 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3858 (LO16 imm:$imm)), sub_eq)>; 3859 3860defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)), 3861 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3862defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)), 3863 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3864defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)), 3865 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3866defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)), 3867 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3868defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)), 3869 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3870 3871// Instantiations of CRNotPat for i64. 3872defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)), 3873 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3874defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)), 3875 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3876defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)), 3877 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3878defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)), 3879 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3880defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)), 3881 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3882defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)), 3883 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3884 3885defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 3886 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3887 (LO16 imm:$imm)), sub_eq)>; 3888 3889defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)), 3890 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3891defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)), 3892 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3893defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), 3894 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3895defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)), 3896 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3897defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)), 3898 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3899} 3900 3901multiclass FSetCCPat<SDPatternOperator SetCC, ValueType Ty, I FCmp> { 3902 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 3903 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3904 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 3905 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3906 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 3907 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3908 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 3909 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3910 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)), 3911 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3912 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 3913 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3914 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)), 3915 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 3916 3917 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)), 3918 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3919 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)), 3920 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3921 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOGT)), 3922 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3923 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGT)), 3924 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3925 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOEQ)), 3926 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3927 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETEQ)), 3928 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3929 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUO)), 3930 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 3931} 3932 3933let Predicates = [HasFPU] in { 3934// FCMPU: If either of the operands is a Signaling NaN, then VXSNAN is set. 3935// SETCC for f32. 3936defm : FSetCCPat<any_fsetcc, f32, FCMPUS>; 3937 3938// SETCC for f64. 3939defm : FSetCCPat<any_fsetcc, f64, FCMPUD>; 3940 3941// SETCC for f128. 3942defm : FSetCCPat<any_fsetcc, f128, XSCMPUQP>; 3943 3944// FCMPO: If either of the operands is a Signaling NaN, then VXSNAN is set and, 3945// if neither operand is a Signaling NaN but at least one operand is a Quiet NaN, 3946// then VXVC is set. 3947// SETCCS for f32. 3948defm : FSetCCPat<strict_fsetccs, f32, FCMPOS>; 3949 3950// SETCCS for f64. 3951defm : FSetCCPat<strict_fsetccs, f64, FCMPOD>; 3952 3953// SETCCS for f128. 3954defm : FSetCCPat<strict_fsetccs, f128, XSCMPOQP>; 3955} 3956 3957// This must be in this file because it relies on patterns defined in this file 3958// after the inclusion of the instruction sets. 3959let Predicates = [HasSPE] in { 3960// SETCC for f32. 3961def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOLT)), 3962 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3963def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLT)), 3964 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3965def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOGT)), 3966 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3967def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGT)), 3968 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3969def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOEQ)), 3970 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3971def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETEQ)), 3972 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3973 3974defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUGE)), 3975 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3976defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGE)), 3977 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3978defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETULE)), 3979 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3980defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLE)), 3981 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3982defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUNE)), 3983 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3984defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETNE)), 3985 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3986 3987// SETCC for f64. 3988def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOLT)), 3989 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3990def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLT)), 3991 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3992def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOGT)), 3993 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3994def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGT)), 3995 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3996def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOEQ)), 3997 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3998def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETEQ)), 3999 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4000 4001defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUGE)), 4002 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4003defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGE)), 4004 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4005defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETULE)), 4006 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4007defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLE)), 4008 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4009defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUNE)), 4010 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4011defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETNE)), 4012 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4013} 4014// match select on i1 variables: 4015def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), 4016 (CROR (CRAND $cond , $tval), 4017 (CRAND (crnot $cond), $fval))>; 4018 4019// match selectcc on i1 variables: 4020// select (lhs == rhs), tval, fval is: 4021// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) 4022def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), 4023 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 4024 (CRAND (CRORC $rhs, $lhs), $fval))>; 4025def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)), 4026 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4027 (CRAND (CRORC $lhs, $rhs), $fval))>; 4028def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)), 4029 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4030 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4031def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)), 4032 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4033 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4034def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)), 4035 (CROR (CRAND (CREQV $lhs, $rhs), $tval), 4036 (CRAND (CRXOR $lhs, $rhs), $fval))>; 4037def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), 4038 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4039 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4040def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)), 4041 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4042 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4043def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)), 4044 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4045 (CRAND (CRORC $lhs, $rhs), $fval))>; 4046def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)), 4047 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 4048 (CRAND (CRORC $rhs, $lhs), $fval))>; 4049def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), 4050 (CROR (CRAND (CREQV $lhs, $rhs), $fval), 4051 (CRAND (CRXOR $lhs, $rhs), $tval))>; 4052 4053// match selectcc on i1 variables with non-i1 output. 4054def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)), 4055 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4056def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)), 4057 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4058def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)), 4059 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4060def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)), 4061 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4062def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)), 4063 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>; 4064def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)), 4065 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4066def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)), 4067 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4068def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)), 4069 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4070def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)), 4071 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4072def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)), 4073 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4074 4075def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)), 4076 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4077def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)), 4078 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4079def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)), 4080 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4081def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)), 4082 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4083def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)), 4084 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>; 4085def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)), 4086 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4087def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)), 4088 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4089def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), 4090 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4091def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)), 4092 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4093def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), 4094 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4095 4096let Predicates = [HasFPU] in { 4097def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 4098 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4099def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 4100 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4101def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 4102 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4103def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 4104 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4105def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 4106 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>; 4107def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 4108 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4109def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 4110 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4111def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 4112 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4113def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 4114 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4115def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 4116 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4117 4118def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 4119 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4120def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 4121 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4122def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 4123 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4124def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 4125 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4126def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 4127 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>; 4128def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 4129 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4130def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 4131 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4132def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 4133 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4134def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 4135 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4136def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 4137 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4138} 4139 4140def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)), 4141 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4142def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)), 4143 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4144def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)), 4145 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4146def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)), 4147 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4148def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETEQ)), 4149 (SELECT_F16 (CREQV $lhs, $rhs), $tval, $fval)>; 4150def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGE)), 4151 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4152def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGE)), 4153 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4154def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGT)), 4155 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4156def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGT)), 4157 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4158def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETNE)), 4159 (SELECT_F16 (CRXOR $lhs, $rhs), $tval, $fval)>; 4160 4161def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)), 4162 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4163def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)), 4164 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4165def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)), 4166 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4167def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)), 4168 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4169def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)), 4170 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>; 4171def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)), 4172 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4173def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)), 4174 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4175def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)), 4176 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4177def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)), 4178 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4179def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), 4180 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; 4181 4182def ANDI_rec_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4183 "#ANDI_rec_1_EQ_BIT", 4184 [(set i1:$dst, (trunc (not i32:$in)))]>; 4185def ANDI_rec_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4186 "#ANDI_rec_1_GT_BIT", 4187 [(set i1:$dst, (trunc i32:$in))]>; 4188 4189def ANDI_rec_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4190 "#ANDI_rec_1_EQ_BIT8", 4191 [(set i1:$dst, (trunc (not i64:$in)))]>; 4192def ANDI_rec_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4193 "#ANDI_rec_1_GT_BIT8", 4194 [(set i1:$dst, (trunc i64:$in))]>; 4195 4196def : Pat<(i1 (not (trunc i32:$in))), 4197 (ANDI_rec_1_EQ_BIT $in)>; 4198def : Pat<(i1 (not (trunc i64:$in))), 4199 (ANDI_rec_1_EQ_BIT8 $in)>; 4200 4201def : Pat<(int_ppc_fsel f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), (FSELD $FRA, $FRC, $FRB)>; 4202def : Pat<(int_ppc_frsqrte f8rc:$frB), (FRSQRTE $frB)>; 4203def : Pat<(int_ppc_frsqrtes f4rc:$frB), (FRSQRTES $frB)>; 4204 4205//===----------------------------------------------------------------------===// 4206// PowerPC Instructions used for assembler/disassembler only 4207// 4208 4209// FIXME: For B=0 or B > 8, the registers following RT are used. 4210// WARNING: Do not add patterns for this instruction without fixing this. 4211def LSWI : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RST), 4212 (ins gprc:$RA, u5imm:$RB), 4213 "lswi $RST, $RA, $RB", IIC_LdStLoad, []>; 4214 4215// FIXME: For B=0 or B > 8, the registers following RT are used. 4216// WARNING: Do not add patterns for this instruction without fixing this. 4217def STSWI : XForm_base_r3xo_memOp<31, 725, (outs), 4218 (ins gprc:$RST, gprc:$RA, u5imm:$RB), 4219 "stswi $RST, $RA, $RB", IIC_LdStLoad, []>; 4220 4221def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), 4222 "isync", IIC_SprISYNC, []>; 4223 4224def ICBI : XForm_1a<31, 982, (outs), (ins (memrr $RA, $RB):$addr), 4225 "icbi $addr", IIC_LdStICBI, []>; 4226 4227def WAIT : XForm_24_sync<31, 30, (outs), (ins u2imm:$L), 4228 "wait $L", IIC_LdStLoad, []>; 4229 4230def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO), 4231 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>; 4232 4233def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR), 4234 "mtsr $SR, $RS", IIC_SprMTSR>; 4235 4236def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR), 4237 "mfsr $RS, $SR", IIC_SprMFSR>; 4238 4239def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB), 4240 "mtsrin $RS, $RB", IIC_SprMTSR>; 4241 4242def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB), 4243 "mfsrin $RS, $RB", IIC_SprMFSR>; 4244 4245def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, u1imm:$L), 4246 "mtmsr $RS, $L", IIC_SprMTMSR>; 4247 4248def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS), 4249 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> { 4250 let L = 0; 4251} 4252 4253def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>, 4254 Requires<[IsBookE]> { 4255 bits<1> E; 4256 4257 let Inst{16} = E; 4258 let Inst{21-30} = 163; 4259} 4260 4261def DCCCI : XForm_tlb<454, (outs), (ins gprc:$RA, gprc:$RB), 4262 "dccci $RA, $RB", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4263def ICCCI : XForm_tlb<966, (outs), (ins gprc:$RA, gprc:$RB), 4264 "iccci $RA, $RB", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4265 4266def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4267def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4268def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4269def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4270 4271def MFMSR : XForm_rs<31, 83, (outs gprc:$RST), (ins), 4272 "mfmsr $RST", IIC_SprMFMSR, []>; 4273 4274def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, u1imm:$L), 4275 "mtmsrd $RS, $L", IIC_SprMTMSRD>; 4276 4277def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA), 4278 "mcrfs $BF, $BFA", IIC_BrMCR>; 4279 4280// All MTFSF variants may change the rounding mode so conservatively set it 4281// as an implicit def for all of them. 4282let Predicates = [HasFPU] in { 4283let Defs = [RM], hasSideEffects = 1 in { 4284let isCodeGenOnly = 1, 4285 Pattern = [(int_ppc_mtfsfi timm:$BF, timm:$U)], W = 0 in 4286def MTFSFIb : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U), 4287 "mtfsfi $BF, $U", IIC_IntMFFS>; 4288def MTFSFI : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, i32imm:$W), 4289 "mtfsfi $BF, $U, $W", IIC_IntMFFS>; 4290let Defs = [CR1] in 4291def MTFSFI_rec : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, u1imm:$W), 4292 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm; 4293 4294def MTFSF : XFLForm_1<63, 711, (outs), 4295 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4296 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>; 4297let Defs = [CR1] in 4298def MTFSF_rec : XFLForm_1<63, 711, (outs), 4299 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4300 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm; 4301} 4302 4303def : InstAlias<"mtfsfi $BF, $U", (MTFSFI u3imm:$BF, u4imm:$U, 0)>; 4304def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec u3imm:$BF, u4imm:$U, 0)>; 4305def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4306def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4307} 4308 4309def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), 4310 "slbie $RB", IIC_SprSLBIE, []>; 4311 4312def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RST, gprc:$RB), 4313 "slbmte $RST, $RB", IIC_SprSLBMTE, []>; 4314 4315def SLBMFEE : XForm_26<31, 915, (outs gprc:$RST), (ins gprc:$RB), 4316 "slbmfee $RST, $RB", IIC_SprSLBMFEE, []>; 4317 4318def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB), 4319 "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>; 4320 4321def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; 4322 4323let Defs = [CR0] in 4324def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RST), (ins gprc:$RB), 4325 "slbfee. $RST, $RB", IIC_SprSLBFEE, []>, isRecordForm; 4326 4327def TLBIA : XForm_0<31, 370, (outs), (ins), 4328 "tlbia", IIC_SprTLBIA, []>; 4329 4330def TLBSYNC : XForm_0<31, 566, (outs), (ins), 4331 "tlbsync", IIC_SprTLBSYNC, []>; 4332 4333def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), 4334 "tlbiel $RB", IIC_SprTLBIEL, []>; 4335 4336def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB), 4337 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4338def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB), 4339 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4340 4341def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RST, gprc:$RB), 4342 "tlbie $RB,$RST", IIC_SprTLBIE, []>; 4343 4344def TLBSX : XForm_tlb<914, (outs), (ins gprc:$RA, gprc:$RB), "tlbsx $RA, $RB", 4345 IIC_LdStLoad>, Requires<[IsBookE]>; 4346 4347def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$RA, gprc:$RB), "tlbivax $RA, $RB", 4348 IIC_LdStLoad>, Requires<[IsBookE]>; 4349 4350def TLBILX : XForm_tlbilx<18, (outs), (ins u2imm:$T, gprc:$RA, gprc:$RB), 4351 "tlbilx $T, $RA, $RB", IIC_LdStLoad>, Requires<[IsBookE]>; 4352 4353def TLBRE : XForm_24_eieio<31, 946, (outs), (ins), 4354 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4355 4356def TLBWE : XForm_24_eieio<31, 978, (outs), (ins), 4357 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4358 4359def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RST), (ins gprc:$RA, i1imm:$WS), 4360 "tlbre $RST, $RA, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4361 4362def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RST, gprc:$RA, i1imm:$WS), 4363 "tlbwe $RST, $RA, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4364 4365def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$RA, gprc:$RB), 4366 "tlbsx $RST, $RA, $RB", IIC_LdStLoad, []>, 4367 Requires<[IsPPC4xx]>; 4368def TLBSX2D : XForm_base_r3xo<31, 914, (outs), 4369 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4370 "tlbsx. $RST, $RA, $RB", IIC_LdStLoad, []>, 4371 Requires<[IsPPC4xx]>, isRecordForm; 4372 4373def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>; 4374 4375def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>, 4376 Requires<[IsBookE]>; 4377def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>, 4378 Requires<[IsBookE]>; 4379 4380def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>, 4381 Requires<[IsE500]>; 4382def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>, 4383 Requires<[IsE500]>; 4384 4385def MFDCR : XFXForm_1<31, 323, (outs gprc:$RST), (ins i32imm:$SPR), 4386 "mfdcr $RST, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; 4387def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RST, i32imm:$SPR), 4388 "mtdcr $SPR, $RST", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; 4389 4390def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>; 4391def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>; 4392 4393def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; 4394 4395def LBZCIX : XForm_base_r3xo_memOp<31, 853, (outs gprc:$RST), 4396 (ins gprc:$RA, gprc:$RB), 4397 "lbzcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4398def LHZCIX : XForm_base_r3xo_memOp<31, 821, (outs gprc:$RST), 4399 (ins gprc:$RA, gprc:$RB), 4400 "lhzcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4401def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST), 4402 (ins gprc:$RA, gprc:$RB), 4403 "lwzcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4404def LDCIX : XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST), 4405 (ins gprc:$RA, gprc:$RB), 4406 "ldcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4407 4408def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs), 4409 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4410 "stbcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4411def STHCIX : XForm_base_r3xo_memOp<31, 949, (outs), 4412 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4413 "sthcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4414def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs), 4415 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4416 "stwcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4417def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs), 4418 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4419 "stdcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4420 4421// External PID Load Store Instructions 4422 4423def LBEPX : XForm_1<31, 95, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 4424 "lbepx $RST, $addr", IIC_LdStLoad, []>, 4425 Requires<[IsE500]>; 4426 4427def LFDEPX : XForm_25<31, 607, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 4428 "lfdepx $RST, $addr", IIC_LdStLFD, []>, 4429 Requires<[IsE500]>; 4430 4431def LHEPX : XForm_1<31, 287, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 4432 "lhepx $RST, $addr", IIC_LdStLoad, []>, 4433 Requires<[IsE500]>; 4434 4435def LWEPX : XForm_1<31, 31, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 4436 "lwepx $RST, $addr", IIC_LdStLoad, []>, 4437 Requires<[IsE500]>; 4438 4439def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 4440 "stbepx $RST, $addr", IIC_LdStStore, []>, 4441 Requires<[IsE500]>; 4442 4443def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), 4444 "stfdepx $RST, $addr", IIC_LdStSTFD, []>, 4445 Requires<[IsE500]>; 4446 4447def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 4448 "sthepx $RST, $addr", IIC_LdStStore, []>, 4449 Requires<[IsE500]>; 4450 4451def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 4452 "stwepx $RST, $addr", IIC_LdStStore, []>, 4453 Requires<[IsE500]>; 4454 4455def DCBFEP : DCB_Form<127, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbfep $addr", 4456 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4457 4458def DCBSTEP : DCB_Form<63, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbstep $addr", 4459 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4460 4461def DCBTEP : DCB_Form_hint<319, (outs), (ins (memrr $RA, $RB):$addr, u5imm:$TH), 4462 "dcbtep $TH, $addr", IIC_LdStDCBF, []>, 4463 Requires<[IsE500]>; 4464 4465def DCBTSTEP : DCB_Form_hint<255, (outs), (ins (memrr $RA, $RB):$addr, u5imm:$TH), 4466 "dcbtstep $TH, $addr", IIC_LdStDCBF, []>, 4467 Requires<[IsE500]>; 4468 4469def DCBZEP : DCB_Form<1023, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbzep $addr", 4470 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4471 4472def DCBZLEP : DCB_Form<1023, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzlep $addr", 4473 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4474 4475def ICBIEP : XForm_1a<31, 991, (outs), (ins (memrr $RA, $RB):$addr), "icbiep $addr", 4476 IIC_LdStICBI, []>, Requires<[IsE500]>; 4477 4478//===----------------------------------------------------------------------===// 4479// PowerPC Assembler Instruction Aliases 4480// 4481 4482def : InstAlias<"sc", (SC 0)>; 4483 4484def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>; 4485def : InstAlias<"hwsync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4486def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4487def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>; 4488def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>; 4489 4490def : InstAlias<"wait", (WAIT 0)>; 4491def : InstAlias<"waitrsv", (WAIT 1)>; 4492def : InstAlias<"waitimpl", (WAIT 2)>; 4493 4494def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>; 4495 4496def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>; 4497def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>; 4498 4499def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4500def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4501def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>; 4502 4503def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4504def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4505def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>; 4506 4507def DCBFx : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>; 4508def DCBFL : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>; 4509def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>; 4510 4511def : Pat<(int_ppc_isync), (ISYNC)>; 4512def : Pat<(int_ppc_dcbfl xoaddr:$dst), 4513 (DCBF 1, xoaddr:$dst)>; 4514def : Pat<(int_ppc_dcbflp xoaddr:$dst), 4515 (DCBF 3, xoaddr:$dst)>; 4516 4517let Predicates = [IsISA3_1] in { 4518 def DCBFPS : PPCAsmPseudo<"dcbfps $dst", (ins memrr:$dst)>; 4519 def DCBSTPS : PPCAsmPseudo<"dcbstps $dst", (ins memrr:$dst)>; 4520 4521 def : Pat<(int_ppc_dcbfps xoaddr:$dst), 4522 (DCBF 4, xoaddr:$dst)>; 4523 def : Pat<(int_ppc_dcbstps xoaddr:$dst), 4524 (DCBF 6, xoaddr:$dst)>; 4525} 4526 4527def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4528def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4529def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4530def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4531 4532def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 4533def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>; 4534def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 4535 4536def : InstAlias<"xnop", (XORI R0, R0, 0)>; 4537 4538def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 4539def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 4540 4541//Disable this alias on AIX for now because as does not support them. 4542let Predicates = [ModernAs] in { 4543 4544foreach BR = 0-7 in { 4545 def : InstAlias<"mfbr"#BR#" $Rx", 4546 (MFDCR gprc:$Rx, !add(BR, 0x80))>, 4547 Requires<[IsPPC4xx]>; 4548 def : InstAlias<"mtbr"#BR#" $Rx", 4549 (MTDCR gprc:$Rx, !add(BR, 0x80))>, 4550 Requires<[IsPPC4xx]>; 4551} 4552 4553def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>; 4554def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>; 4555def : InstAlias<"mtudscr $Rx", (MTSPR 3, gprc:$Rx)>; 4556def : InstAlias<"mfudscr $Rx", (MFSPR gprc:$Rx, 3)>; 4557 4558def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>; 4559def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>; 4560 4561def : InstAlias<"mtlr $Rx", (MTSPR 8, gprc:$Rx)>; 4562def : InstAlias<"mflr $Rx", (MFSPR gprc:$Rx, 8)>; 4563 4564def : InstAlias<"mtctr $Rx", (MTSPR 9, gprc:$Rx)>; 4565def : InstAlias<"mfctr $Rx", (MFSPR gprc:$Rx, 9)>; 4566 4567def : InstAlias<"mtuamr $Rx", (MTSPR 13, gprc:$Rx)>; 4568def : InstAlias<"mfuamr $Rx", (MFSPR gprc:$Rx, 13)>; 4569 4570def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>; 4571def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>; 4572 4573def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>; 4574def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>; 4575 4576def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>; 4577def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>; 4578 4579def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>; 4580def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>; 4581 4582def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>; 4583def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>; 4584 4585def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>; 4586def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>; 4587 4588def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>; 4589def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>; 4590 4591def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>; 4592def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>; 4593 4594def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>; 4595def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>; 4596 4597def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>; 4598def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>; 4599 4600foreach SPRG = 4-7 in { 4601 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>, 4602 Requires<[IsBookE]>; 4603 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>, 4604 Requires<[IsBookE]>; 4605 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4606 Requires<[IsBookE]>; 4607 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4608 Requires<[IsBookE]>; 4609} 4610 4611foreach SPRG = 0-3 in { 4612 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>; 4613 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>; 4614 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4615 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4616} 4617 4618def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>; 4619def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>; 4620 4621def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>; 4622def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>; 4623 4624def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>; 4625 4626def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>; 4627def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>; 4628 4629foreach BATR = 0-3 in { 4630 def : InstAlias<"mtdbatu "#BATR#", $Rx", 4631 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>, 4632 Requires<[IsPPC6xx]>; 4633 def : InstAlias<"mfdbatu $Rx, "#BATR, 4634 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>, 4635 Requires<[IsPPC6xx]>; 4636 def : InstAlias<"mtdbatl "#BATR#", $Rx", 4637 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>, 4638 Requires<[IsPPC6xx]>; 4639 def : InstAlias<"mfdbatl $Rx, "#BATR, 4640 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>, 4641 Requires<[IsPPC6xx]>; 4642 def : InstAlias<"mtibatu "#BATR#", $Rx", 4643 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>, 4644 Requires<[IsPPC6xx]>; 4645 def : InstAlias<"mfibatu $Rx, "#BATR, 4646 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>, 4647 Requires<[IsPPC6xx]>; 4648 def : InstAlias<"mtibatl "#BATR#", $Rx", 4649 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>, 4650 Requires<[IsPPC6xx]>; 4651 def : InstAlias<"mfibatl $Rx, "#BATR, 4652 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>, 4653 Requires<[IsPPC6xx]>; 4654} 4655 4656def : InstAlias<"mtppr $RT", (MTSPR 896, gprc:$RT)>; 4657def : InstAlias<"mfppr $RT", (MFSPR gprc:$RT, 896)>; 4658 4659def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4660def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>; 4661 4662def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4663def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>; 4664 4665def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4666def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>; 4667 4668def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>; 4669def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4670 4671def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>; 4672def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4673 4674def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4675def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>; 4676 4677def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4678def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>; 4679 4680def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4681def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>; 4682 4683def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4684def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>; 4685 4686} 4687 4688def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>; 4689 4690def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>, 4691 Requires<[IsPPC4xx]>; 4692def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>, 4693 Requires<[IsPPC4xx]>; 4694def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>, 4695 Requires<[IsPPC4xx]>; 4696def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>, 4697 Requires<[IsPPC4xx]>; 4698 4699def : InstAlias<"tlbilxlpid", (TLBILX 0, R0, R0)>, Requires<[IsBookE]>; 4700def : InstAlias<"tlbilxpid", (TLBILX 1, R0, R0)>, Requires<[IsBookE]>; 4701def : InstAlias<"tlbilxva $RA, $RB", (TLBILX 3, gprc:$RA, gprc:$RB)>, 4702 Requires<[IsBookE]>; 4703def : InstAlias<"tlbilxva $RB", (TLBILX 3, R0, gprc:$RB)>, Requires<[IsBookE]>; 4704 4705def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>; 4706 4707def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", 4708 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4709def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm", 4710 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4711def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm", 4712 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4713def SUBIC_rec : PPCAsmPseudo<"subic. $rA, $rB, $imm", 4714 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4715 4716def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", 4717 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>, 4718 ZExt32To64; 4719def EXTLWI_rec : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", 4720 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>, 4721 ZExt32To64; 4722def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", 4723 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4724def EXTRWI_rec : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", 4725 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4726def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", 4727 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4728def INSLWI_rec : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", 4729 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4730def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", 4731 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4732def INSRWI_rec : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", 4733 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4734def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", 4735 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4736def ROTRWI_rec : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", 4737 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4738def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", 4739 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4740def SLWI_rec : PPCAsmPseudo<"slwi. $rA, $rS, $n", 4741 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4742def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", 4743 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4744def SRWI_rec : PPCAsmPseudo<"srwi. $rA, $rS, $n", 4745 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4746def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", 4747 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4748def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", 4749 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4750def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", 4751 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4752def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", 4753 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4754 4755def : InstAlias<"isellt $rT, $rA, $rB", 4756 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT)>; 4757def : InstAlias<"iselgt $rT, $rA, $rB", 4758 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT)>; 4759def : InstAlias<"iseleq $rT, $rA, $rB", 4760 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ)>; 4761 4762def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4763def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4764def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4765def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4766def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4767def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4768 4769def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>; 4770def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW_rec gprc:$rA, gprc:$rS)>; 4771// The POWER variant 4772def : MnemonicAlias<"cntlz", "cntlzw">; 4773def : MnemonicAlias<"cntlz.", "cntlzw.">; 4774 4775def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", 4776 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4777def EXTLDI_rec : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", 4778 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4779def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", 4780 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4781def EXTRDI_rec : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", 4782 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4783def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", 4784 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4785def INSRDI_rec : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", 4786 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4787def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", 4788 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4789def ROTRDI_rec : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", 4790 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4791def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", 4792 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4793def SLDI_rec : PPCAsmPseudo<"sldi. $rA, $rS, $n", 4794 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4795def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", 4796 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4797def SRDI_rec : PPCAsmPseudo<"srdi. $rA, $rS, $n", 4798 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4799def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", 4800 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4801def CLRRDI_rec : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", 4802 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4803def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", 4804 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4805def CLRLSLDI_rec : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", 4806 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4807def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>; 4808 4809def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4810def : InstAlias<"rotldi $rA, $rS, $n", 4811 (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0)>; 4812def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4813def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4814def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4815def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4816def : InstAlias<"clrldi $rA, $rS, $n", 4817 (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>; 4818def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4819def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>; 4820 4821def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b", 4822 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4823def RLWINMbm_rec : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b", 4824 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4825def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b", 4826 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4827def RLWIMIbm_rec : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b", 4828 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4829def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b", 4830 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4831def RLWNMbm_rec : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b", 4832 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4833 4834// These generic branch instruction forms are used for the assembler parser only. 4835// Defs and Uses are conservative, since we don't know the BO value. 4836let PPC970_Unit = 7, isBranch = 1, hasSideEffects = 0 in { 4837 let Defs = [CTR], Uses = [CTR, RM] in { 4838 def gBC : BForm_3<16, 0, 0, (outs), 4839 (ins u5imm:$BO, crbitrc:$BI, condbrtarget:$BD), 4840 "bc $BO, $BI, $BD">; 4841 def gBCA : BForm_3<16, 1, 0, (outs), 4842 (ins u5imm:$BO, crbitrc:$BI, abscondbrtarget:$BD), 4843 "bca $BO, $BI, $BD">; 4844 let isAsmParserOnly = 1 in { 4845 def gBCat : BForm_3_at<16, 0, 0, (outs), 4846 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4847 condbrtarget:$BD), 4848 "bc$at $BO, $BI, $BD">; 4849 def gBCAat : BForm_3_at<16, 1, 0, (outs), 4850 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4851 abscondbrtarget:$BD), 4852 "bca$at $BO, $BI, $BD">; 4853 } // isAsmParserOnly = 1 4854 } 4855 let Defs = [LR, CTR], Uses = [CTR, RM] in { 4856 def gBCL : BForm_3<16, 0, 1, (outs), 4857 (ins u5imm:$BO, crbitrc:$BI, condbrtarget:$BD), 4858 "bcl $BO, $BI, $BD">; 4859 def gBCLA : BForm_3<16, 1, 1, (outs), 4860 (ins u5imm:$BO, crbitrc:$BI, abscondbrtarget:$BD), 4861 "bcla $BO, $BI, $BD">; 4862 let isAsmParserOnly = 1 in { 4863 def gBCLat : BForm_3_at<16, 0, 1, (outs), 4864 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4865 condbrtarget:$BD), 4866 "bcl$at $BO, $BI, $BD">; 4867 def gBCLAat : BForm_3_at<16, 1, 1, (outs), 4868 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4869 abscondbrtarget:$BD), 4870 "bcla$at $BO, $BI, $BD">; 4871 } // // isAsmParserOnly = 1 4872 } 4873 let Defs = [CTR], Uses = [CTR, LR, RM] in 4874 def gBCLR : XLForm_2<19, 16, 0, (outs), 4875 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4876 "bclr $BO, $BI, $BH", IIC_BrB, []>; 4877 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4878 def gBCLRL : XLForm_2<19, 16, 1, (outs), 4879 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4880 "bclrl $BO, $BI, $BH", IIC_BrB, []>; 4881 let Defs = [CTR], Uses = [CTR, LR, RM] in 4882 def gBCCTR : XLForm_2<19, 528, 0, (outs), 4883 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4884 "bcctr $BO, $BI, $BH", IIC_BrB, []>; 4885 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4886 def gBCCTRL : XLForm_2<19, 528, 1, (outs), 4887 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4888 "bcctrl $BO, $BI, $BH", IIC_BrB, []>; 4889} 4890 4891multiclass BranchSimpleMnemonicAT<string pm, int at> { 4892 def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi, 4893 condbrtarget:$dst)>; 4894 def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi, 4895 condbrtarget:$dst)>; 4896 def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi, 4897 condbrtarget:$dst)>; 4898 def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi, 4899 condbrtarget:$dst)>; 4900} 4901defm : BranchSimpleMnemonicAT<"+", 3>; 4902defm : BranchSimpleMnemonicAT<"-", 2>; 4903 4904def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; 4905def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; 4906def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; 4907def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; 4908 4909multiclass BranchSimpleMnemonic1<string name, string pm, int bo> { 4910 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>; 4911 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4912 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>; 4913 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>; 4914 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4915 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>; 4916} 4917multiclass BranchSimpleMnemonic2<string name, string pm, int bo> 4918 : BranchSimpleMnemonic1<name, pm, bo> { 4919 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>; 4920 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>; 4921} 4922defm : BranchSimpleMnemonic2<"t", "", 12>; 4923defm : BranchSimpleMnemonic2<"f", "", 4>; 4924defm : BranchSimpleMnemonic2<"t", "-", 14>; 4925defm : BranchSimpleMnemonic2<"f", "-", 6>; 4926defm : BranchSimpleMnemonic2<"t", "+", 15>; 4927defm : BranchSimpleMnemonic2<"f", "+", 7>; 4928defm : BranchSimpleMnemonic1<"dnzt", "", 8>; 4929defm : BranchSimpleMnemonic1<"dnzf", "", 0>; 4930defm : BranchSimpleMnemonic1<"dzt", "", 10>; 4931defm : BranchSimpleMnemonic1<"dzf", "", 2>; 4932 4933multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> { 4934 def : InstAlias<"b"#name#pm#" $cc, $dst", 4935 (BCC bibo, crrc:$cc, condbrtarget:$dst)>; 4936 def : InstAlias<"b"#name#pm#" $dst", 4937 (BCC bibo, CR0, condbrtarget:$dst)>; 4938 4939 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst", 4940 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4941 def : InstAlias<"b"#name#"a"#pm#" $dst", 4942 (BCCA bibo, CR0, abscondbrtarget:$dst)>; 4943 4944 def : InstAlias<"b"#name#"lr"#pm#" $cc", 4945 (BCCLR bibo, crrc:$cc)>; 4946 def : InstAlias<"b"#name#"lr"#pm, 4947 (BCCLR bibo, CR0)>; 4948 4949 def : InstAlias<"b"#name#"ctr"#pm#" $cc", 4950 (BCCCTR bibo, crrc:$cc)>; 4951 def : InstAlias<"b"#name#"ctr"#pm, 4952 (BCCCTR bibo, CR0)>; 4953 4954 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst", 4955 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>; 4956 def : InstAlias<"b"#name#"l"#pm#" $dst", 4957 (BCCL bibo, CR0, condbrtarget:$dst)>; 4958 4959 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst", 4960 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4961 def : InstAlias<"b"#name#"la"#pm#" $dst", 4962 (BCCLA bibo, CR0, abscondbrtarget:$dst)>; 4963 4964 def : InstAlias<"b"#name#"lrl"#pm#" $cc", 4965 (BCCLRL bibo, crrc:$cc)>; 4966 def : InstAlias<"b"#name#"lrl"#pm, 4967 (BCCLRL bibo, CR0)>; 4968 4969 def : InstAlias<"b"#name#"ctrl"#pm#" $cc", 4970 (BCCCTRL bibo, crrc:$cc)>; 4971 def : InstAlias<"b"#name#"ctrl"#pm, 4972 (BCCCTRL bibo, CR0)>; 4973} 4974multiclass BranchExtendedMnemonic<string name, int bibo> { 4975 defm : BranchExtendedMnemonicPM<name, "", bibo>; 4976 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>; 4977 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>; 4978} 4979defm : BranchExtendedMnemonic<"lt", 12>; 4980defm : BranchExtendedMnemonic<"gt", 44>; 4981defm : BranchExtendedMnemonic<"eq", 76>; 4982defm : BranchExtendedMnemonic<"un", 108>; 4983defm : BranchExtendedMnemonic<"so", 108>; 4984defm : BranchExtendedMnemonic<"ge", 4>; 4985defm : BranchExtendedMnemonic<"nl", 4>; 4986defm : BranchExtendedMnemonic<"le", 36>; 4987defm : BranchExtendedMnemonic<"ng", 36>; 4988defm : BranchExtendedMnemonic<"ne", 68>; 4989defm : BranchExtendedMnemonic<"nu", 100>; 4990defm : BranchExtendedMnemonic<"ns", 100>; 4991 4992def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; 4993def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; 4994def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; 4995def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; 4996def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>; 4997def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; 4998def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>; 4999def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; 5000 5001def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>; 5002def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>; 5003def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>; 5004def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>; 5005def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>; 5006def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 5007def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>; 5008def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 5009 5010def : InstAlias<"trap", (TW 31, R0, R0)>; 5011 5012multiclass TrapExtendedMnemonic<string name, int to> { 5013 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>; 5014 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>; 5015 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>; 5016 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>; 5017} 5018defm : TrapExtendedMnemonic<"lt", 16>; 5019defm : TrapExtendedMnemonic<"le", 20>; 5020defm : TrapExtendedMnemonic<"eq", 4>; 5021defm : TrapExtendedMnemonic<"ge", 12>; 5022defm : TrapExtendedMnemonic<"gt", 8>; 5023defm : TrapExtendedMnemonic<"nl", 12>; 5024defm : TrapExtendedMnemonic<"ne", 24>; 5025defm : TrapExtendedMnemonic<"ng", 20>; 5026defm : TrapExtendedMnemonic<"llt", 2>; 5027defm : TrapExtendedMnemonic<"lle", 6>; 5028defm : TrapExtendedMnemonic<"lge", 5>; 5029defm : TrapExtendedMnemonic<"lgt", 1>; 5030defm : TrapExtendedMnemonic<"lnl", 5>; 5031defm : TrapExtendedMnemonic<"lng", 6>; 5032defm : TrapExtendedMnemonic<"u", 31>; 5033 5034// Atomic loads 5035def : Pat<(atomic_load_8 DForm:$src), (LBZ memri:$src)>; 5036def : Pat<(atomic_load_16 DForm:$src), (LHZ memri:$src)>; 5037def : Pat<(atomic_load_32 DForm:$src), (LWZ memri:$src)>; 5038def : Pat<(atomic_load_8 XForm:$src), (LBZX memrr:$src)>; 5039def : Pat<(atomic_load_16 XForm:$src), (LHZX memrr:$src)>; 5040def : Pat<(atomic_load_32 XForm:$src), (LWZX memrr:$src)>; 5041 5042// Atomic stores 5043def : Pat<(atomic_store_8 i32:$val, DForm:$ptr), (STB gprc:$val, memri:$ptr)>; 5044def : Pat<(atomic_store_16 i32:$val, DForm:$ptr), (STH gprc:$val, memri:$ptr)>; 5045def : Pat<(atomic_store_32 i32:$val, DForm:$ptr), (STW gprc:$val, memri:$ptr)>; 5046def : Pat<(atomic_store_8 i32:$val, XForm:$ptr), (STBX gprc:$val, memrr:$ptr)>; 5047def : Pat<(atomic_store_16 i32:$val, XForm:$ptr), (STHX gprc:$val, memrr:$ptr)>; 5048def : Pat<(atomic_store_32 i32:$val, XForm:$ptr), (STWX gprc:$val, memrr:$ptr)>; 5049 5050let Predicates = [IsISA3_0] in { 5051 5052// Copy-Paste Facility 5053// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to 5054// PASTE for naming consistency. 5055let mayLoad = 1 in 5056def CP_COPY : X_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>; 5057 5058let mayStore = 1, Defs = [CR0] in 5059def CP_PASTE_rec : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isRecordForm; 5060 5061def : InstAlias<"paste. $RA, $RB", (CP_PASTE_rec gprc:$RA, gprc:$RB, 1)>; 5062def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cpabort", IIC_SprABORT, []>; 5063 5064// Message Synchronize 5065def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>; 5066 5067// Power-Saving Mode Instruction: 5068def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>; 5069 5070def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 5071 "setb $RT, $BFA", IIC_IntGeneral>, SExt32To64; 5072} // IsISA3_0 5073 5074let Predicates = [IsISA3_0] in { 5075def : Pat<(i32 (int_ppc_cmprb i32:$a, gprc:$b, gprc:$c)), 5076 (i32 (SETB (CMPRB u1imm:$a, $b, $c)))>; 5077} 5078def : Pat<(i32 (int_ppc_mulhw gprc:$a, gprc:$b)), 5079 (i32 (MULHW $a, $b))>; 5080def : Pat<(i32 (int_ppc_mulhwu gprc:$a, gprc:$b)), 5081 (i32 (MULHWU $a, $b))>; 5082def : Pat<(i32 (int_ppc_cmpb gprc:$a, gprc:$b)), 5083 (i32 (CMPB $a, $b))>; 5084 5085def : Pat<(int_ppc_load2r ForceXForm:$ptr), 5086 (LHBRX ForceXForm:$ptr)>; 5087def : Pat<(int_ppc_load4r ForceXForm:$ptr), 5088 (LWBRX ForceXForm:$ptr)>; 5089def : Pat<(int_ppc_store2r gprc:$a, ForceXForm:$ptr), 5090 (STHBRX gprc:$a, ForceXForm:$ptr)>; 5091def : Pat<(int_ppc_store4r gprc:$a, ForceXForm:$ptr), 5092 (STWBRX gprc:$a, ForceXForm:$ptr)>; 5093 5094 5095// Fast 32-bit reverse bits algorithm: 5096// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5097// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA); 5098// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5099// n = ((n >> 2) & 0x33333333) | ((n << 2) & 0xCCCCCCCC); 5100// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5101// n = ((n >> 4) & 0x0F0F0F0F) | ((n << 4) & 0xF0F0F0F0); 5102// Step 4: byte reverse (Suppose n = [B1,B2,B3,B4]): 5103// Step 4.1: Put B4,B2 in the right position (rotate left 3 bytes): 5104// n' = (n rotl 24); After which n' = [B4, B1, B2, B3] 5105// Step 4.2: Insert B3 to the right position: 5106// n' = rlwimi n', n, 8, 8, 15; After which n' = [B4, B3, B2, B3] 5107// Step 4.3: Insert B1 to the right position: 5108// n' = rlwimi n', n, 8, 24, 31; After which n' = [B4, B3, B2, B1] 5109def MaskValues { 5110 dag Lo1 = (ORI (LIS 0x5555), 0x5555); 5111 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA); 5112 dag Lo2 = (ORI (LIS 0x3333), 0x3333); 5113 dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC); 5114 dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F); 5115 dag Hi4 = (ORI (LIS 0xF0F0), 0xF0F0); 5116} 5117 5118def Shift1 { 5119 dag Right = (RLWINM $A, 31, 1, 31); 5120 dag Left = (RLWINM $A, 1, 0, 30); 5121} 5122 5123def Swap1 { 5124 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1), 5125 (AND Shift1.Left, MaskValues.Hi1)); 5126} 5127 5128def Shift2 { 5129 dag Right = (RLWINM Swap1.Bit, 30, 2, 31); 5130 dag Left = (RLWINM Swap1.Bit, 2, 0, 29); 5131} 5132 5133def Swap2 { 5134 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2), 5135 (AND Shift2.Left, MaskValues.Hi2)); 5136} 5137 5138def Shift4 { 5139 dag Right = (RLWINM Swap2.Bits, 28, 4, 31); 5140 dag Left = (RLWINM Swap2.Bits, 4, 0, 27); 5141} 5142 5143def Swap4 { 5144 dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4), 5145 (AND Shift4.Left, MaskValues.Hi4)); 5146} 5147 5148def Rotate { 5149 dag Left3Bytes = (RLWINM Swap4.Bits, 24, 0, 31); 5150} 5151 5152def RotateInsertByte3 { 5153 dag Left = (RLWIMI Rotate.Left3Bytes, Swap4.Bits, 8, 8, 15); 5154} 5155 5156def RotateInsertByte1 { 5157 dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31); 5158} 5159 5160// Clear the upper half of the register when in 64-bit mode 5161let Predicates = [In64BitMode] in 5162def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>; 5163let Predicates = [In32BitMode] in 5164def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>; 5165 5166// Fast 64-bit reverse bits algorithm: 5167// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5168// n = ((n >> 1) & 0x5555555555555555) | ((n << 1) & 0xAAAAAAAAAAAAAAAA); 5169// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5170// n = ((n >> 2) & 0x3333333333333333) | ((n << 2) & 0xCCCCCCCCCCCCCCCC); 5171// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5172// n = ((n >> 4) & 0x0F0F0F0F0F0F0F0F) | ((n << 4) & 0xF0F0F0F0F0F0F0F0); 5173// Step 4: byte reverse (Suppose n = [B0,B1,B2,B3,B4,B5,B6,B7]): 5174// Apply the same byte reverse algorithm mentioned above for the fast 32-bit 5175// reverse to both the high 32 bit and low 32 bit of the 64 bit value. And 5176// then OR them together to get the final result. 5177def MaskValues64 { 5178 dag Lo1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo1, sub_32)); 5179 dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32)); 5180 dag Lo2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo2, sub_32)); 5181 dag Hi2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi2, sub_32)); 5182 dag Lo4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo4, sub_32)); 5183 dag Hi4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi4, sub_32)); 5184} 5185 5186def DWMaskValues { 5187 dag Lo1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo1, 32, 31), 0x5555), 0x5555); 5188 dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA); 5189 dag Lo2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo2, 32, 31), 0x3333), 0x3333); 5190 dag Hi2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi2, 32, 31), 0xCCCC), 0xCCCC); 5191 dag Lo4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo4, 32, 31), 0x0F0F), 0x0F0F); 5192 dag Hi4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi4, 32, 31), 0xF0F0), 0xF0F0); 5193} 5194 5195def DWSwapInByte { 5196 dag Swap1 = (OR8 (AND8 (RLDICL $A, 63, 1), DWMaskValues.Lo1), 5197 (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1)); 5198 dag Swap2 = (OR8 (AND8 (RLDICL Swap1, 62, 2), DWMaskValues.Lo2), 5199 (AND8 (RLDICR Swap1, 2, 61), DWMaskValues.Hi2)); 5200 dag Swap4 = (OR8 (AND8 (RLDICL Swap2, 60, 4), DWMaskValues.Lo4), 5201 (AND8 (RLDICR Swap2, 4, 59), DWMaskValues.Hi4)); 5202} 5203 5204// Intra-byte swap is done, now start inter-byte swap. 5205def DWBytes4567 { 5206 dag Word = (i32 (EXTRACT_SUBREG DWSwapInByte.Swap4, sub_32)); 5207} 5208 5209def DWBytes7456 { 5210 dag Word = (RLWINM DWBytes4567.Word, 24, 0, 31); 5211} 5212 5213def DWBytes7656 { 5214 dag Word = (RLWIMI DWBytes7456.Word, DWBytes4567.Word, 8, 8, 15); 5215} 5216 5217// B7 B6 B5 B4 in the right order 5218def DWBytes7654 { 5219 dag Word = (RLWIMI DWBytes7656.Word, DWBytes4567.Word, 8, 24, 31); 5220 dag DWord = 5221 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5222} 5223 5224def DWBytes0123 { 5225 dag Word = (i32 (EXTRACT_SUBREG (RLDICL DWSwapInByte.Swap4, 32, 32), sub_32)); 5226} 5227 5228def DWBytes3012 { 5229 dag Word = (RLWINM DWBytes0123.Word, 24, 0, 31); 5230} 5231 5232def DWBytes3212 { 5233 dag Word = (RLWIMI DWBytes3012.Word, DWBytes0123.Word, 8, 8, 15); 5234} 5235 5236// B3 B2 B1 B0 in the right order 5237def DWBytes3210 { 5238 dag Word = (RLWIMI DWBytes3212.Word, DWBytes0123.Word, 8, 24, 31); 5239 dag DWord = 5240 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5241} 5242 5243// These instructions store a hash computed from the value of the link register 5244// and the value of the stack pointer. 5245let mayStore = 1 in { 5246def HASHST : XForm_XD6_RA5_RB5<31, 722, (outs), 5247 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5248 "hashst $RB, $addr", IIC_IntGeneral, []>; 5249def HASHSTP : XForm_XD6_RA5_RB5<31, 658, (outs), 5250 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5251 "hashstp $RB, $addr", IIC_IntGeneral, []>; 5252} 5253 5254// These instructions check a hash computed from the value of the link register 5255// and the value of the stack pointer. The hasSideEffects flag is needed as the 5256// instruction may TRAP if the hash does not match the hash stored at the 5257// specified address. 5258let mayLoad = 1, hasSideEffects = 1 in { 5259def HASHCHK : XForm_XD6_RA5_RB5<31, 754, (outs), 5260 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5261 "hashchk $RB, $addr", IIC_IntGeneral, []>; 5262def HASHCHKP : XForm_XD6_RA5_RB5<31, 690, (outs), 5263 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5264 "hashchkp $RB, $addr", IIC_IntGeneral, []>; 5265} 5266 5267let Defs = [CR7], Itinerary = IIC_LdStSync in 5268def CFENCE : PPCPostRAExpPseudo<(outs), (ins gprc:$cr), "#CFENCE", []>; 5269 5270// Now both high word and low word are reversed, next 5271// swap the high word and low word. 5272def : Pat<(i64 (bitreverse i64:$A)), 5273 (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>; 5274 5275def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A), 5276 (STWCX gprc:$A, ForceXForm:$dst)>; 5277def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 4), 5278 (STWCX gprc:$A, ForceXForm:$dst)>; 5279def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A), 5280 (STBCX gprc:$A, ForceXForm:$dst)>; 5281def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 1), 5282 (STBCX gprc:$A, ForceXForm:$dst)>; 5283 5284def : Pat<(int_ppc_fcfid f64:$A), 5285 (XSCVSXDDP $A)>; 5286def : Pat<(int_ppc_fcfud f64:$A), 5287 (XSCVUXDDP $A)>; 5288def : Pat<(int_ppc_fctid f64:$A), 5289 (FCTID $A)>; 5290def : Pat<(int_ppc_fctidz f64:$A), 5291 (XSCVDPSXDS $A)>; 5292def : Pat<(int_ppc_fctiw f64:$A), 5293 (FCTIW $A)>; 5294def : Pat<(int_ppc_fctiwz f64:$A), 5295 (XSCVDPSXWS $A)>; 5296def : Pat<(int_ppc_fctudz f64:$A), 5297 (XSCVDPUXDS $A)>; 5298def : Pat<(int_ppc_fctuwz f64:$A), 5299 (XSCVDPUXWS $A)>; 5300 5301def : Pat<(int_ppc_mfmsr), (MFMSR)>; 5302def : Pat<(int_ppc_mftbu), (MFTB 269)>; 5303def : Pat<(i32 (int_ppc_mfspr timm:$SPR)), 5304 (MFSPR $SPR)>; 5305def : Pat<(int_ppc_mtspr timm:$SPR, gprc:$RT), 5306 (MTSPR $SPR, $RT)>; 5307def : Pat<(int_ppc_mtmsr gprc:$RS), 5308 (MTMSR $RS, 0)>; 5309 5310let Predicates = [IsISA2_07] in { 5311 def : Pat<(int_ppc_sthcx ForceXForm:$dst, gprc:$A), 5312 (STHCX gprc:$A, ForceXForm:$dst)>; 5313 def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 2), 5314 (STHCX gprc:$A, ForceXForm:$dst)>; 5315} 5316def : Pat<(int_ppc_dcbtstt ForceXForm:$dst), 5317 (DCBTST 16, ForceXForm:$dst)>; 5318def : Pat<(int_ppc_dcbtt ForceXForm:$dst), 5319 (DCBT 16, ForceXForm:$dst)>; 5320 5321def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT), 5322 (STFIWX f64:$XT, ForceXForm:$dst)>; 5323