10b57cec5SDimitry Andric//===- PPCInstrVSX.td - The PowerPC VSX Extension --*- tablegen -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file describes the VSX extension to the PowerPC instruction set. 100b57cec5SDimitry Andric// 110b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric// *********************************** NOTE *********************************** 140b57cec5SDimitry Andric// ** For POWER8 Little Endian, the VSX swap optimization relies on knowing ** 150b57cec5SDimitry Andric// ** which VMX and VSX instructions are lane-sensitive and which are not. ** 160b57cec5SDimitry Andric// ** A lane-sensitive instruction relies, implicitly or explicitly, on ** 170b57cec5SDimitry Andric// ** whether lanes are numbered from left to right. An instruction like ** 180b57cec5SDimitry Andric// ** VADDFP is not lane-sensitive, because each lane of the result vector ** 190b57cec5SDimitry Andric// ** relies only on the corresponding lane of the source vectors. However, ** 200b57cec5SDimitry Andric// ** an instruction like VMULESB is lane-sensitive, because "even" and ** 210b57cec5SDimitry Andric// ** "odd" lanes are different for big-endian and little-endian numbering. ** 220b57cec5SDimitry Andric// ** ** 230b57cec5SDimitry Andric// ** When adding new VMX and VSX instructions, please consider whether they ** 240b57cec5SDimitry Andric// ** are lane-sensitive. If so, they must be added to a switch statement ** 250b57cec5SDimitry Andric// ** in PPCVSXSwapRemoval::gatherVectorInstructions(). ** 260b57cec5SDimitry Andric// **************************************************************************** 270b57cec5SDimitry Andric 285ffd83dbSDimitry Andric// *********************************** NOTE *********************************** 295ffd83dbSDimitry Andric// ** When adding new anonymous patterns to this file, please add them to ** 305ffd83dbSDimitry Andric// ** the section titled Anonymous Patterns. Chances are that the existing ** 315ffd83dbSDimitry Andric// ** predicate blocks already contain a combination of features that you ** 325ffd83dbSDimitry Andric// ** are after. There is a list of blocks at the top of the section. If ** 335ffd83dbSDimitry Andric// ** you definitely need a new combination of predicates, please add that ** 345ffd83dbSDimitry Andric// ** combination to the list. ** 355ffd83dbSDimitry Andric// ** File Structure: ** 365ffd83dbSDimitry Andric// ** - Custom PPCISD node definitions ** 375ffd83dbSDimitry Andric// ** - Predicate definitions: predicates to specify the subtargets for ** 385ffd83dbSDimitry Andric// ** which an instruction or pattern can be emitted. ** 395ffd83dbSDimitry Andric// ** - Instruction formats: classes instantiated by the instructions. ** 405ffd83dbSDimitry Andric// ** These generally correspond to instruction formats in section 1.6 of ** 415ffd83dbSDimitry Andric// ** the ISA document. ** 425ffd83dbSDimitry Andric// ** - Instruction definitions: the actual definitions of the instructions ** 435ffd83dbSDimitry Andric// ** often including input patterns that they match. ** 445ffd83dbSDimitry Andric// ** - Helper DAG definitions: We define a number of dag objects to use as ** 455ffd83dbSDimitry Andric// ** input or output patterns for consciseness of the code. ** 465ffd83dbSDimitry Andric// ** - Anonymous patterns: input patterns that an instruction matches can ** 475ffd83dbSDimitry Andric// ** often not be specified as part of the instruction definition, so an ** 485ffd83dbSDimitry Andric// ** anonymous pattern must be specified mapping an input pattern to an ** 495ffd83dbSDimitry Andric// ** output pattern. These are generally guarded by subtarget predicates. ** 505ffd83dbSDimitry Andric// ** - Instruction aliases: used to define extended mnemonics for assembly ** 515ffd83dbSDimitry Andric// ** printing (for example: xxswapd for xxpermdi with 0x2 as the imm). ** 525ffd83dbSDimitry Andric// **************************************************************************** 535ffd83dbSDimitry Andric 540b57cec5SDimitry Andricdef SDT_PPCldvsxlh : SDTypeProfile<1, 1, [ 550b57cec5SDimitry Andric SDTCisVT<0, v4f32>, SDTCisPtrTy<1> 560b57cec5SDimitry Andric]>; 570b57cec5SDimitry Andric 588bcb0991SDimitry Andricdef SDT_PPCfpexth : SDTypeProfile<1, 2, [ 598bcb0991SDimitry Andric SDTCisVT<0, v2f64>, SDTCisVT<1, v4f32>, SDTCisPtrTy<2> 608bcb0991SDimitry Andric]>; 618bcb0991SDimitry Andric 628bcb0991SDimitry Andricdef SDT_PPCldsplat : SDTypeProfile<1, 1, [ 638bcb0991SDimitry Andric SDTCisVec<0>, SDTCisPtrTy<1> 640b57cec5SDimitry Andric]>; 650b57cec5SDimitry Andric 660b57cec5SDimitry Andric// Little-endian-specific nodes. 670b57cec5SDimitry Andricdef SDT_PPClxvd2x : SDTypeProfile<1, 1, [ 680b57cec5SDimitry Andric SDTCisVT<0, v2f64>, SDTCisPtrTy<1> 690b57cec5SDimitry Andric]>; 700b57cec5SDimitry Andricdef SDT_PPCstxvd2x : SDTypeProfile<0, 2, [ 710b57cec5SDimitry Andric SDTCisVT<0, v2f64>, SDTCisPtrTy<1> 720b57cec5SDimitry Andric]>; 730b57cec5SDimitry Andricdef SDT_PPCxxswapd : SDTypeProfile<1, 1, [ 740b57cec5SDimitry Andric SDTCisSameAs<0, 1> 750b57cec5SDimitry Andric]>; 760b57cec5SDimitry Andricdef SDTVecConv : SDTypeProfile<1, 2, [ 770b57cec5SDimitry Andric SDTCisVec<0>, SDTCisVec<1>, SDTCisPtrTy<2> 780b57cec5SDimitry Andric]>; 798bcb0991SDimitry Andricdef SDT_PPCld_vec_be : SDTypeProfile<1, 1, [ 808bcb0991SDimitry Andric SDTCisVec<0>, SDTCisPtrTy<1> 818bcb0991SDimitry Andric]>; 828bcb0991SDimitry Andricdef SDT_PPCst_vec_be : SDTypeProfile<0, 2, [ 838bcb0991SDimitry Andric SDTCisVec<0>, SDTCisPtrTy<1> 848bcb0991SDimitry Andric]>; 850b57cec5SDimitry Andric 86bdd1243dSDimitry Andricdef SDT_PPCxxperm : SDTypeProfile<1, 3, [ 87bdd1243dSDimitry Andric SDTCisVT<0, v2f64>, SDTCisVT<1, v2f64>, 88bdd1243dSDimitry Andric SDTCisVT<2, v2f64>, SDTCisVT<3, v4i32>]>; 895ffd83dbSDimitry Andric//--------------------------- Custom PPC nodes -------------------------------// 900b57cec5SDimitry Andricdef PPClxvd2x : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x, 910b57cec5SDimitry Andric [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 920b57cec5SDimitry Andricdef PPCstxvd2x : SDNode<"PPCISD::STXVD2X", SDT_PPCstxvd2x, 930b57cec5SDimitry Andric [SDNPHasChain, SDNPMayStore]>; 948bcb0991SDimitry Andricdef PPCld_vec_be : SDNode<"PPCISD::LOAD_VEC_BE", SDT_PPCld_vec_be, 958bcb0991SDimitry Andric [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 968bcb0991SDimitry Andricdef PPCst_vec_be : SDNode<"PPCISD::STORE_VEC_BE", SDT_PPCst_vec_be, 978bcb0991SDimitry Andric [SDNPHasChain, SDNPMayStore]>; 980b57cec5SDimitry Andricdef PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>; 990b57cec5SDimitry Andricdef PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>; 1000b57cec5SDimitry Andricdef PPCmtvsra : SDNode<"PPCISD::MTVSRA", SDTUnaryOp, []>; 1010b57cec5SDimitry Andricdef PPCmtvsrz : SDNode<"PPCISD::MTVSRZ", SDTUnaryOp, []>; 1020b57cec5SDimitry Andricdef PPCsvec2fp : SDNode<"PPCISD::SINT_VEC_TO_FP", SDTVecConv, []>; 1030b57cec5SDimitry Andricdef PPCuvec2fp: SDNode<"PPCISD::UINT_VEC_TO_FP", SDTVecConv, []>; 1040b57cec5SDimitry Andricdef PPCswapNoChain : SDNode<"PPCISD::SWAP_NO_CHAIN", SDT_PPCxxswapd>; 1050b57cec5SDimitry Andric 1068bcb0991SDimitry Andricdef PPCfpexth : SDNode<"PPCISD::FP_EXTEND_HALF", SDT_PPCfpexth, []>; 1070b57cec5SDimitry Andricdef PPCldvsxlh : SDNode<"PPCISD::LD_VSX_LH", SDT_PPCldvsxlh, 1080b57cec5SDimitry Andric [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 1098bcb0991SDimitry Andricdef PPCldsplat : SDNode<"PPCISD::LD_SPLAT", SDT_PPCldsplat, 1108bcb0991SDimitry Andric [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 111349cc55cSDimitry Andricdef PPCzextldsplat : SDNode<"PPCISD::ZEXT_LD_SPLAT", SDT_PPCldsplat, 112349cc55cSDimitry Andric [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 113349cc55cSDimitry Andricdef PPCsextldsplat : SDNode<"PPCISD::SEXT_LD_SPLAT", SDT_PPCldsplat, 114349cc55cSDimitry Andric [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 1155ffd83dbSDimitry Andricdef PPCSToV : SDNode<"PPCISD::SCALAR_TO_VECTOR_PERMUTED", 1165ffd83dbSDimitry Andric SDTypeProfile<1, 1, []>, []>; 1170b57cec5SDimitry Andric 118bdd1243dSDimitry Andricdef PPCxxperm : SDNode<"PPCISD::XXPERM", SDT_PPCxxperm, []>; 1195ffd83dbSDimitry Andric//-------------------------- Predicate definitions ---------------------------// 1205ffd83dbSDimitry Andricdef HasVSX : Predicate<"Subtarget->hasVSX()">; 1215ffd83dbSDimitry Andricdef IsLittleEndian : Predicate<"Subtarget->isLittleEndian()">; 1225ffd83dbSDimitry Andricdef IsBigEndian : Predicate<"!Subtarget->isLittleEndian()">; 123e8d8bef9SDimitry Andricdef IsPPC64 : Predicate<"Subtarget->isPPC64()">; 1245ffd83dbSDimitry Andricdef HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">; 12506c3fb27SDimitry Andricdef NoP8Vector : Predicate<"!Subtarget->hasP8Vector()">; 1265ffd83dbSDimitry Andricdef HasP8Vector : Predicate<"Subtarget->hasP8Vector()">; 1275ffd83dbSDimitry Andricdef HasDirectMove : Predicate<"Subtarget->hasDirectMove()">; 1285ffd83dbSDimitry Andricdef NoP9Vector : Predicate<"!Subtarget->hasP9Vector()">; 1295ffd83dbSDimitry Andricdef HasP9Vector : Predicate<"Subtarget->hasP9Vector()">; 1305ffd83dbSDimitry Andricdef NoP9Altivec : Predicate<"!Subtarget->hasP9Altivec()">; 131fe6060f1SDimitry Andricdef NoP10Vector: Predicate<"!Subtarget->hasP10Vector()">; 13206c3fb27SDimitry Andricdef HasP10Vector: Predicate<"Subtarget->hasP10Vector()">; 1335ffd83dbSDimitry Andric 1340eae32dcSDimitry Andricdef PPCldsplatAlign16 : PatFrag<(ops node:$ptr), (PPCldsplat node:$ptr), [{ 1350eae32dcSDimitry Andric return cast<MemIntrinsicSDNode>(N)->getAlign() >= Align(16) && 1360eae32dcSDimitry Andric isOffsetMultipleOf(N, 16); 1370eae32dcSDimitry Andric}]>; 1380eae32dcSDimitry Andric 1395ffd83dbSDimitry Andric//--------------------- VSX-specific instruction formats ---------------------// 1405ffd83dbSDimitry Andric// By default, all VSX instructions are to be selected over their Altivec 1415ffd83dbSDimitry Andric// counter parts and they do not have unmodeled sideeffects. 1425ffd83dbSDimitry Andriclet AddedComplexity = 400, hasSideEffects = 0 in { 1430b57cec5SDimitry Andricmulticlass XX3Form_Rcr<bits<6> opcode, bits<7> xo, string asmbase, 1440b57cec5SDimitry Andric string asmstr, InstrItinClass itin, Intrinsic Int, 1450b57cec5SDimitry Andric ValueType OutTy, ValueType InTy> { 1460b57cec5SDimitry Andric let BaseName = asmbase in { 1470b57cec5SDimitry Andric def NAME : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1480b57cec5SDimitry Andric !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1490b57cec5SDimitry Andric [(set OutTy:$XT, (Int InTy:$XA, InTy:$XB))]>; 1500b57cec5SDimitry Andric let Defs = [CR6] in 151480093f4SDimitry Andric def _rec : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1520b57cec5SDimitry Andric !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1530b57cec5SDimitry Andric [(set InTy:$XT, 154e8d8bef9SDimitry Andric (InTy (PPCvcmp_rec InTy:$XA, InTy:$XB, xo)))]>, 155480093f4SDimitry Andric isRecordForm; 1560b57cec5SDimitry Andric } 1570b57cec5SDimitry Andric} 1580b57cec5SDimitry Andric 1590b57cec5SDimitry Andric// Instruction form with a single input register for instructions such as 1600b57cec5SDimitry Andric// XXPERMDI. The reason for defining this is that specifying multiple chained 1610b57cec5SDimitry Andric// operands (such as loads) to an instruction will perform both chained 1620b57cec5SDimitry Andric// operations rather than coalescing them into a single register - even though 1630b57cec5SDimitry Andric// the source memory location is the same. This simply forces the instruction 1640b57cec5SDimitry Andric// to use the same register for both inputs. 1650b57cec5SDimitry Andric// For example, an output DAG such as this: 1660b57cec5SDimitry Andric// (XXPERMDI (LXSIBZX xoaddr:$src), (LXSIBZX xoaddr:$src ), 0)) 1670b57cec5SDimitry Andric// would result in two load instructions emitted and used as separate inputs 1680b57cec5SDimitry Andric// to the XXPERMDI instruction. 1690b57cec5SDimitry Andricclass XX3Form_2s<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1700b57cec5SDimitry Andric InstrItinClass itin, list<dag> pattern> 1710b57cec5SDimitry Andric : XX3Form_2<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1720b57cec5SDimitry Andric let XB = XA; 1730b57cec5SDimitry Andric} 1740b57cec5SDimitry Andric 1755ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasP9Vector] in { 1765ffd83dbSDimitry Andricclass X_VT5_XO5_VB5<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 1775ffd83dbSDimitry Andric list<dag> pattern> 17806c3fb27SDimitry Andric : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$RST), (ins vrrc:$RB), 17906c3fb27SDimitry Andric !strconcat(opc, " $RST, $RB"), IIC_VecFP, pattern>; 1800b57cec5SDimitry Andric 1815ffd83dbSDimitry Andric// [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /] 1825ffd83dbSDimitry Andricclass X_VT5_XO5_VB5_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 1835ffd83dbSDimitry Andric list<dag> pattern> 1845ffd83dbSDimitry Andric : X_VT5_XO5_VB5<opcode, xo2, xo, opc, pattern>, isRecordForm; 1855ffd83dbSDimitry Andric 1865ffd83dbSDimitry Andric// [PO VRT XO VRB XO /], but the VRB is only used the left 64 bits (or less), 1875ffd83dbSDimitry Andric// So we use different operand class for VRB 1885ffd83dbSDimitry Andricclass X_VT5_XO5_VB5_TyVB<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 1895ffd83dbSDimitry Andric RegisterOperand vbtype, list<dag> pattern> 19006c3fb27SDimitry Andric : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$RST), (ins vbtype:$RB), 19106c3fb27SDimitry Andric !strconcat(opc, " $RST, $RB"), IIC_VecFP, pattern>; 1925ffd83dbSDimitry Andric 1935ffd83dbSDimitry Andric// [PO VRT XO VRB XO /] 1945ffd83dbSDimitry Andricclass X_VT5_XO5_VB5_VSFR<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 1955ffd83dbSDimitry Andric list<dag> pattern> 19606c3fb27SDimitry Andric : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vfrc:$RST), (ins vrrc:$RB), 19706c3fb27SDimitry Andric !strconcat(opc, " $RST, $RB"), IIC_VecFP, pattern>; 1985ffd83dbSDimitry Andric 1995ffd83dbSDimitry Andric// [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /] 2005ffd83dbSDimitry Andricclass X_VT5_XO5_VB5_VSFR_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 2015ffd83dbSDimitry Andric list<dag> pattern> 2025ffd83dbSDimitry Andric : X_VT5_XO5_VB5_VSFR<opcode, xo2, xo, opc, pattern>, isRecordForm; 2035ffd83dbSDimitry Andric 2045ffd83dbSDimitry Andric// [PO T XO B XO BX /] 2055ffd83dbSDimitry Andricclass XX2_RT5_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc, 2065ffd83dbSDimitry Andric list<dag> pattern> 20706c3fb27SDimitry Andric : XX2_RD5_XO5_RS6<opcode, xo2, xo, (outs g8rc:$RT), (ins vsfrc:$XB), 20806c3fb27SDimitry Andric !strconcat(opc, " $RT, $XB"), IIC_VecFP, pattern>; 2095ffd83dbSDimitry Andric 2105ffd83dbSDimitry Andric// [PO T XO B XO BX TX] 2115ffd83dbSDimitry Andricclass XX2_XT6_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc, 2125ffd83dbSDimitry Andric RegisterOperand vtype, list<dag> pattern> 2135ffd83dbSDimitry Andric : XX2_RD6_XO5_RS6<opcode, xo2, xo, (outs vtype:$XT), (ins vtype:$XB), 2145ffd83dbSDimitry Andric !strconcat(opc, " $XT, $XB"), IIC_VecFP, pattern>; 2155ffd83dbSDimitry Andric 2165ffd83dbSDimitry Andric// [PO T A B XO AX BX TX], src and dest register use different operand class 2175ffd83dbSDimitry Andricclass XX3_XT5_XA5_XB5<bits<6> opcode, bits<8> xo, string opc, 2185ffd83dbSDimitry Andric RegisterOperand xty, RegisterOperand aty, RegisterOperand bty, 2195ffd83dbSDimitry Andric InstrItinClass itin, list<dag> pattern> 2205ffd83dbSDimitry Andric : XX3Form<opcode, xo, (outs xty:$XT), (ins aty:$XA, bty:$XB), 2215ffd83dbSDimitry Andric !strconcat(opc, " $XT, $XA, $XB"), itin, pattern>; 2225ffd83dbSDimitry Andric 2235ffd83dbSDimitry Andric// [PO VRT VRA VRB XO /] 2245ffd83dbSDimitry Andricclass X_VT5_VA5_VB5<bits<6> opcode, bits<10> xo, string opc, 2255ffd83dbSDimitry Andric list<dag> pattern> 22606c3fb27SDimitry Andric : XForm_1<opcode, xo, (outs vrrc:$RST), (ins vrrc:$RA, vrrc:$RB), 22706c3fb27SDimitry Andric !strconcat(opc, " $RST, $RA, $RB"), IIC_VecFP, pattern>; 2285ffd83dbSDimitry Andric 2295ffd83dbSDimitry Andric// [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /] 2305ffd83dbSDimitry Andricclass X_VT5_VA5_VB5_Ro<bits<6> opcode, bits<10> xo, string opc, 2315ffd83dbSDimitry Andric list<dag> pattern> 2325ffd83dbSDimitry Andric : X_VT5_VA5_VB5<opcode, xo, opc, pattern>, isRecordForm; 2335ffd83dbSDimitry Andric 2345ffd83dbSDimitry Andric// [PO VRT VRA VRB XO /] 2355ffd83dbSDimitry Andricclass X_VT5_VA5_VB5_FMA<bits<6> opcode, bits<10> xo, string opc, 2365ffd83dbSDimitry Andric list<dag> pattern> 23706c3fb27SDimitry Andric : XForm_1<opcode, xo, (outs vrrc:$RST), (ins vrrc:$RSTi, vrrc:$RA, vrrc:$RB), 23806c3fb27SDimitry Andric !strconcat(opc, " $RST, $RA, $RB"), IIC_VecFP, pattern>, 23906c3fb27SDimitry Andric RegConstraint<"$RSTi = $RST">, NoEncode<"$RSTi">; 2405ffd83dbSDimitry Andric 2415ffd83dbSDimitry Andric// [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /] 2425ffd83dbSDimitry Andricclass X_VT5_VA5_VB5_FMA_Ro<bits<6> opcode, bits<10> xo, string opc, 2435ffd83dbSDimitry Andric list<dag> pattern> 2445ffd83dbSDimitry Andric : X_VT5_VA5_VB5_FMA<opcode, xo, opc, pattern>, isRecordForm; 2455ffd83dbSDimitry Andric 2465ffd83dbSDimitry Andricclass Z23_VT5_R1_VB5_RMC2_EX1<bits<6> opcode, bits<8> xo, bit ex, string opc, 2475ffd83dbSDimitry Andric list<dag> pattern> 2485ffd83dbSDimitry Andric : Z23Form_8<opcode, xo, 24906c3fb27SDimitry Andric (outs vrrc:$VRT), (ins u1imm:$R, vrrc:$VRB, u2imm:$idx), 25006c3fb27SDimitry Andric !strconcat(opc, " $R, $VRT, $VRB, $idx"), IIC_VecFP, pattern> { 2515ffd83dbSDimitry Andric let RC = ex; 2525ffd83dbSDimitry Andric} 2535ffd83dbSDimitry Andric 2545ffd83dbSDimitry Andric// [PO BF // VRA VRB XO /] 2555ffd83dbSDimitry Andricclass X_BF3_VA5_VB5<bits<6> opcode, bits<10> xo, string opc, 2565ffd83dbSDimitry Andric list<dag> pattern> 25706c3fb27SDimitry Andric : XForm_17<opcode, xo, (outs crrc:$BF), (ins vrrc:$RA, vrrc:$RB), 25806c3fb27SDimitry Andric !strconcat(opc, " $BF, $RA, $RB"), IIC_FPCompare> { 2595ffd83dbSDimitry Andric let Pattern = pattern; 2605ffd83dbSDimitry Andric} 2615ffd83dbSDimitry Andric 2625ffd83dbSDimitry Andric// [PO T RA RB XO TX] almost equal to [PO S RA RB XO SX], but has different 2635ffd83dbSDimitry Andric// "out" and "in" dag 2645ffd83dbSDimitry Andricclass X_XT6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, 2655ffd83dbSDimitry Andric RegisterOperand vtype, list<dag> pattern> 26606c3fb27SDimitry Andric : XX1Form_memOp<opcode, xo, (outs vtype:$XT), (ins (memrr $RA, $RB):$addr), 26706c3fb27SDimitry Andric !strconcat(opc, " $XT, $addr"), IIC_LdStLFD, pattern>; 2685ffd83dbSDimitry Andric 2695ffd83dbSDimitry Andric// [PO S RA RB XO SX] 2705ffd83dbSDimitry Andricclass X_XS6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, 2715ffd83dbSDimitry Andric RegisterOperand vtype, list<dag> pattern> 27206c3fb27SDimitry Andric : XX1Form_memOp<opcode, xo, (outs), (ins vtype:$XT, (memrr $RA, $RB):$addr), 27306c3fb27SDimitry Andric !strconcat(opc, " $XT, $addr"), IIC_LdStSTFD, pattern>; 2745ffd83dbSDimitry Andric} // Predicates = HasP9Vector 2755ffd83dbSDimitry Andric} // AddedComplexity = 400, hasSideEffects = 0 2765ffd83dbSDimitry Andric 2775ffd83dbSDimitry Andricmulticlass ScalToVecWPermute<ValueType Ty, dag In, dag NonPermOut, dag PermOut> { 2785ffd83dbSDimitry Andric def : Pat<(Ty (scalar_to_vector In)), (Ty NonPermOut)>; 2795ffd83dbSDimitry Andric def : Pat<(Ty (PPCSToV In)), (Ty PermOut)>; 2805ffd83dbSDimitry Andric} 2815ffd83dbSDimitry Andric 2825ffd83dbSDimitry Andric//-------------------------- Instruction definitions -------------------------// 2835ffd83dbSDimitry Andric// VSX instructions require the VSX feature, they are to be selected over 2845ffd83dbSDimitry Andric// equivalent Altivec patterns (as they address a larger register set) and 2855ffd83dbSDimitry Andric// they do not have unmodeled side effects. 2865ffd83dbSDimitry Andriclet Predicates = [HasVSX], AddedComplexity = 400 in { 2875ffd83dbSDimitry Andriclet hasSideEffects = 0 in { 2880b57cec5SDimitry Andric 2890b57cec5SDimitry Andric // Load indexed instructions 2900b57cec5SDimitry Andric let mayLoad = 1, mayStore = 0 in { 2910b57cec5SDimitry Andric let CodeSize = 3 in 2920b57cec5SDimitry Andric def LXSDX : XX1Form_memOp<31, 588, 29306c3fb27SDimitry Andric (outs vsfrc:$XT), (ins (memrr $RA, $RB):$addr), 29406c3fb27SDimitry Andric "lxsdx $XT, $addr", IIC_LdStLFD, 2950b57cec5SDimitry Andric []>; 2960b57cec5SDimitry Andric 2970b57cec5SDimitry Andric // Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later 2980b57cec5SDimitry Andric let CodeSize = 3 in 29906c3fb27SDimitry Andric def XFLOADf64 : PseudoXFormMemOp<(outs vsfrc:$XT), (ins (memrr $RA, $RB):$addr), 3000b57cec5SDimitry Andric "#XFLOADf64", 30106c3fb27SDimitry Andric [(set f64:$XT, (load XForm:$addr))]>; 3020b57cec5SDimitry Andric 3030b57cec5SDimitry Andric let Predicates = [HasVSX, HasOnlySwappingMemOps] in 3040b57cec5SDimitry Andric def LXVD2X : XX1Form_memOp<31, 844, 30506c3fb27SDimitry Andric (outs vsrc:$XT), (ins (memrr $RA, $RB):$addr), 30606c3fb27SDimitry Andric "lxvd2x $XT, $addr", IIC_LdStLFD, 307fe6060f1SDimitry Andric []>; 3080b57cec5SDimitry Andric 3090b57cec5SDimitry Andric def LXVDSX : XX1Form_memOp<31, 332, 31006c3fb27SDimitry Andric (outs vsrc:$XT), (ins (memrr $RA, $RB):$addr), 31106c3fb27SDimitry Andric "lxvdsx $XT, $addr", IIC_LdStLFD, []>; 3120b57cec5SDimitry Andric 3130b57cec5SDimitry Andric let Predicates = [HasVSX, HasOnlySwappingMemOps] in 3140b57cec5SDimitry Andric def LXVW4X : XX1Form_memOp<31, 780, 31506c3fb27SDimitry Andric (outs vsrc:$XT), (ins (memrr $RA, $RB):$addr), 31606c3fb27SDimitry Andric "lxvw4x $XT, $addr", IIC_LdStLFD, 3170b57cec5SDimitry Andric []>; 3180b57cec5SDimitry Andric } // mayLoad 3190b57cec5SDimitry Andric 3200b57cec5SDimitry Andric // Store indexed instructions 3210b57cec5SDimitry Andric let mayStore = 1, mayLoad = 0 in { 3220b57cec5SDimitry Andric let CodeSize = 3 in 3230b57cec5SDimitry Andric def STXSDX : XX1Form_memOp<31, 716, 32406c3fb27SDimitry Andric (outs), (ins vsfrc:$XT, (memrr $RA, $RB):$addr), 32506c3fb27SDimitry Andric "stxsdx $XT, $addr", IIC_LdStSTFD, 3260b57cec5SDimitry Andric []>; 3270b57cec5SDimitry Andric 3280b57cec5SDimitry Andric // Pseudo instruction XFSTOREf64 will be expanded to STXSDX or STFDX later 3290b57cec5SDimitry Andric let CodeSize = 3 in 33006c3fb27SDimitry Andric def XFSTOREf64 : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, (memrr $RA, $RB):$addr), 3310b57cec5SDimitry Andric "#XFSTOREf64", 33206c3fb27SDimitry Andric [(store f64:$XT, XForm:$addr)]>; 3330b57cec5SDimitry Andric 3340b57cec5SDimitry Andric let Predicates = [HasVSX, HasOnlySwappingMemOps] in { 3350b57cec5SDimitry Andric // The behaviour of this instruction is endianness-specific so we provide no 3360b57cec5SDimitry Andric // pattern to match it without considering endianness. 3370b57cec5SDimitry Andric def STXVD2X : XX1Form_memOp<31, 972, 33806c3fb27SDimitry Andric (outs), (ins vsrc:$XT, (memrr $RA, $RB):$addr), 33906c3fb27SDimitry Andric "stxvd2x $XT, $addr", IIC_LdStSTFD, 3400b57cec5SDimitry Andric []>; 3410b57cec5SDimitry Andric 3420b57cec5SDimitry Andric def STXVW4X : XX1Form_memOp<31, 908, 34306c3fb27SDimitry Andric (outs), (ins vsrc:$XT, (memrr $RA, $RB):$addr), 34406c3fb27SDimitry Andric "stxvw4x $XT, $addr", IIC_LdStSTFD, 3450b57cec5SDimitry Andric []>; 3460b57cec5SDimitry Andric } 3470b57cec5SDimitry Andric } // mayStore 3480b57cec5SDimitry Andric 349e8d8bef9SDimitry Andric let mayRaiseFPException = 1 in { 350e8d8bef9SDimitry Andric let Uses = [RM] in { 3510b57cec5SDimitry Andric // Add/Mul Instructions 3520b57cec5SDimitry Andric let isCommutable = 1 in { 3530b57cec5SDimitry Andric def XSADDDP : XX3Form<60, 32, 3540b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 3550b57cec5SDimitry Andric "xsadddp $XT, $XA, $XB", IIC_VecFP, 3565ffd83dbSDimitry Andric [(set f64:$XT, (any_fadd f64:$XA, f64:$XB))]>; 3570b57cec5SDimitry Andric def XSMULDP : XX3Form<60, 48, 3580b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 3590b57cec5SDimitry Andric "xsmuldp $XT, $XA, $XB", IIC_VecFP, 3605ffd83dbSDimitry Andric [(set f64:$XT, (any_fmul f64:$XA, f64:$XB))]>; 3610b57cec5SDimitry Andric 3620b57cec5SDimitry Andric def XVADDDP : XX3Form<60, 96, 3630b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 3640b57cec5SDimitry Andric "xvadddp $XT, $XA, $XB", IIC_VecFP, 3655ffd83dbSDimitry Andric [(set v2f64:$XT, (any_fadd v2f64:$XA, v2f64:$XB))]>; 3660b57cec5SDimitry Andric 3670b57cec5SDimitry Andric def XVADDSP : XX3Form<60, 64, 3680b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 3690b57cec5SDimitry Andric "xvaddsp $XT, $XA, $XB", IIC_VecFP, 3705ffd83dbSDimitry Andric [(set v4f32:$XT, (any_fadd v4f32:$XA, v4f32:$XB))]>; 3710b57cec5SDimitry Andric 3720b57cec5SDimitry Andric def XVMULDP : XX3Form<60, 112, 3730b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 3740b57cec5SDimitry Andric "xvmuldp $XT, $XA, $XB", IIC_VecFP, 3755ffd83dbSDimitry Andric [(set v2f64:$XT, (any_fmul v2f64:$XA, v2f64:$XB))]>; 3760b57cec5SDimitry Andric 3770b57cec5SDimitry Andric def XVMULSP : XX3Form<60, 80, 3780b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 3790b57cec5SDimitry Andric "xvmulsp $XT, $XA, $XB", IIC_VecFP, 3805ffd83dbSDimitry Andric [(set v4f32:$XT, (any_fmul v4f32:$XA, v4f32:$XB))]>; 3810b57cec5SDimitry Andric } 3820b57cec5SDimitry Andric 3830b57cec5SDimitry Andric // Subtract Instructions 3840b57cec5SDimitry Andric def XSSUBDP : XX3Form<60, 40, 3850b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 3860b57cec5SDimitry Andric "xssubdp $XT, $XA, $XB", IIC_VecFP, 3875ffd83dbSDimitry Andric [(set f64:$XT, (any_fsub f64:$XA, f64:$XB))]>; 3880b57cec5SDimitry Andric 3890b57cec5SDimitry Andric def XVSUBDP : XX3Form<60, 104, 3900b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 3910b57cec5SDimitry Andric "xvsubdp $XT, $XA, $XB", IIC_VecFP, 3925ffd83dbSDimitry Andric [(set v2f64:$XT, (any_fsub v2f64:$XA, v2f64:$XB))]>; 3930b57cec5SDimitry Andric def XVSUBSP : XX3Form<60, 72, 3940b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 3950b57cec5SDimitry Andric "xvsubsp $XT, $XA, $XB", IIC_VecFP, 3965ffd83dbSDimitry Andric [(set v4f32:$XT, (any_fsub v4f32:$XA, v4f32:$XB))]>; 3970b57cec5SDimitry Andric 3980b57cec5SDimitry Andric // FMA Instructions 3990b57cec5SDimitry Andric let BaseName = "XSMADDADP" in { 4000b57cec5SDimitry Andric let isCommutable = 1 in 4010b57cec5SDimitry Andric def XSMADDADP : XX3Form<60, 33, 4020b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 4030b57cec5SDimitry Andric "xsmaddadp $XT, $XA, $XB", IIC_VecFP, 4045ffd83dbSDimitry Andric [(set f64:$XT, (any_fma f64:$XA, f64:$XB, f64:$XTi))]>, 4050b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 4060b57cec5SDimitry Andric AltVSXFMARel; 4070b57cec5SDimitry Andric let IsVSXFMAAlt = 1 in 4080b57cec5SDimitry Andric def XSMADDMDP : XX3Form<60, 41, 4090b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 4100b57cec5SDimitry Andric "xsmaddmdp $XT, $XA, $XB", IIC_VecFP, []>, 4110b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 4120b57cec5SDimitry Andric AltVSXFMARel; 4130b57cec5SDimitry Andric } 4140b57cec5SDimitry Andric 4150b57cec5SDimitry Andric let BaseName = "XSMSUBADP" in { 4160b57cec5SDimitry Andric let isCommutable = 1 in 4170b57cec5SDimitry Andric def XSMSUBADP : XX3Form<60, 49, 4180b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 4190b57cec5SDimitry Andric "xsmsubadp $XT, $XA, $XB", IIC_VecFP, 4205ffd83dbSDimitry Andric [(set f64:$XT, (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>, 4210b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 4220b57cec5SDimitry Andric AltVSXFMARel; 4230b57cec5SDimitry Andric let IsVSXFMAAlt = 1 in 4240b57cec5SDimitry Andric def XSMSUBMDP : XX3Form<60, 57, 4250b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 4260b57cec5SDimitry Andric "xsmsubmdp $XT, $XA, $XB", IIC_VecFP, []>, 4270b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 4280b57cec5SDimitry Andric AltVSXFMARel; 4290b57cec5SDimitry Andric } 4300b57cec5SDimitry Andric 4310b57cec5SDimitry Andric let BaseName = "XSNMADDADP" in { 4320b57cec5SDimitry Andric let isCommutable = 1 in 4330b57cec5SDimitry Andric def XSNMADDADP : XX3Form<60, 161, 4340b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 4350b57cec5SDimitry Andric "xsnmaddadp $XT, $XA, $XB", IIC_VecFP, 4365ffd83dbSDimitry Andric [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, f64:$XTi)))]>, 4370b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 4380b57cec5SDimitry Andric AltVSXFMARel; 4390b57cec5SDimitry Andric let IsVSXFMAAlt = 1 in 4400b57cec5SDimitry Andric def XSNMADDMDP : XX3Form<60, 169, 4410b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 4420b57cec5SDimitry Andric "xsnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>, 4430b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 4440b57cec5SDimitry Andric AltVSXFMARel; 4450b57cec5SDimitry Andric } 4460b57cec5SDimitry Andric 4470b57cec5SDimitry Andric let BaseName = "XSNMSUBADP" in { 4480b57cec5SDimitry Andric let isCommutable = 1 in 4490b57cec5SDimitry Andric def XSNMSUBADP : XX3Form<60, 177, 4500b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 4510b57cec5SDimitry Andric "xsnmsubadp $XT, $XA, $XB", IIC_VecFP, 4525ffd83dbSDimitry Andric [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>, 4530b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 4540b57cec5SDimitry Andric AltVSXFMARel; 4550b57cec5SDimitry Andric let IsVSXFMAAlt = 1 in 4560b57cec5SDimitry Andric def XSNMSUBMDP : XX3Form<60, 185, 4570b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 4580b57cec5SDimitry Andric "xsnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>, 4590b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 4600b57cec5SDimitry Andric AltVSXFMARel; 4610b57cec5SDimitry Andric } 4620b57cec5SDimitry Andric 4630b57cec5SDimitry Andric let BaseName = "XVMADDADP" in { 4640b57cec5SDimitry Andric let isCommutable = 1 in 4650b57cec5SDimitry Andric def XVMADDADP : XX3Form<60, 97, 4660b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 4670b57cec5SDimitry Andric "xvmaddadp $XT, $XA, $XB", IIC_VecFP, 4685ffd83dbSDimitry Andric [(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>, 4690b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 4700b57cec5SDimitry Andric AltVSXFMARel; 4710b57cec5SDimitry Andric let IsVSXFMAAlt = 1 in 4720b57cec5SDimitry Andric def XVMADDMDP : XX3Form<60, 105, 4730b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 4740b57cec5SDimitry Andric "xvmaddmdp $XT, $XA, $XB", IIC_VecFP, []>, 4750b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 4760b57cec5SDimitry Andric AltVSXFMARel; 4770b57cec5SDimitry Andric } 4780b57cec5SDimitry Andric 4790b57cec5SDimitry Andric let BaseName = "XVMADDASP" in { 4800b57cec5SDimitry Andric let isCommutable = 1 in 4810b57cec5SDimitry Andric def XVMADDASP : XX3Form<60, 65, 4820b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 4830b57cec5SDimitry Andric "xvmaddasp $XT, $XA, $XB", IIC_VecFP, 4845ffd83dbSDimitry Andric [(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>, 4850b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 4860b57cec5SDimitry Andric AltVSXFMARel; 4870b57cec5SDimitry Andric let IsVSXFMAAlt = 1 in 4880b57cec5SDimitry Andric def XVMADDMSP : XX3Form<60, 73, 4890b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 4900b57cec5SDimitry Andric "xvmaddmsp $XT, $XA, $XB", IIC_VecFP, []>, 4910b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 4920b57cec5SDimitry Andric AltVSXFMARel; 4930b57cec5SDimitry Andric } 4940b57cec5SDimitry Andric 4950b57cec5SDimitry Andric let BaseName = "XVMSUBADP" in { 4960b57cec5SDimitry Andric let isCommutable = 1 in 4970b57cec5SDimitry Andric def XVMSUBADP : XX3Form<60, 113, 4980b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 4990b57cec5SDimitry Andric "xvmsubadp $XT, $XA, $XB", IIC_VecFP, 5005ffd83dbSDimitry Andric [(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>, 5010b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 5020b57cec5SDimitry Andric AltVSXFMARel; 5030b57cec5SDimitry Andric let IsVSXFMAAlt = 1 in 5040b57cec5SDimitry Andric def XVMSUBMDP : XX3Form<60, 121, 5050b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 5060b57cec5SDimitry Andric "xvmsubmdp $XT, $XA, $XB", IIC_VecFP, []>, 5070b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 5080b57cec5SDimitry Andric AltVSXFMARel; 5090b57cec5SDimitry Andric } 5100b57cec5SDimitry Andric 5110b57cec5SDimitry Andric let BaseName = "XVMSUBASP" in { 5120b57cec5SDimitry Andric let isCommutable = 1 in 5130b57cec5SDimitry Andric def XVMSUBASP : XX3Form<60, 81, 5140b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 5150b57cec5SDimitry Andric "xvmsubasp $XT, $XA, $XB", IIC_VecFP, 5165ffd83dbSDimitry Andric [(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>, 5170b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 5180b57cec5SDimitry Andric AltVSXFMARel; 5190b57cec5SDimitry Andric let IsVSXFMAAlt = 1 in 5200b57cec5SDimitry Andric def XVMSUBMSP : XX3Form<60, 89, 5210b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 5220b57cec5SDimitry Andric "xvmsubmsp $XT, $XA, $XB", IIC_VecFP, []>, 5230b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 5240b57cec5SDimitry Andric AltVSXFMARel; 5250b57cec5SDimitry Andric } 5260b57cec5SDimitry Andric 5270b57cec5SDimitry Andric let BaseName = "XVNMADDADP" in { 5280b57cec5SDimitry Andric let isCommutable = 1 in 5290b57cec5SDimitry Andric def XVNMADDADP : XX3Form<60, 225, 5300b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 5310b57cec5SDimitry Andric "xvnmaddadp $XT, $XA, $XB", IIC_VecFP, 5325ffd83dbSDimitry Andric [(set v2f64:$XT, (fneg (any_fma v2f64:$XA, v2f64:$XB, v2f64:$XTi)))]>, 5330b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 5340b57cec5SDimitry Andric AltVSXFMARel; 5350b57cec5SDimitry Andric let IsVSXFMAAlt = 1 in 5360b57cec5SDimitry Andric def XVNMADDMDP : XX3Form<60, 233, 5370b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 5380b57cec5SDimitry Andric "xvnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>, 5390b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 5400b57cec5SDimitry Andric AltVSXFMARel; 5410b57cec5SDimitry Andric } 5420b57cec5SDimitry Andric 5430b57cec5SDimitry Andric let BaseName = "XVNMADDASP" in { 5440b57cec5SDimitry Andric let isCommutable = 1 in 5450b57cec5SDimitry Andric def XVNMADDASP : XX3Form<60, 193, 5460b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 5470b57cec5SDimitry Andric "xvnmaddasp $XT, $XA, $XB", IIC_VecFP, 5480b57cec5SDimitry Andric [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>, 5490b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 5500b57cec5SDimitry Andric AltVSXFMARel; 5510b57cec5SDimitry Andric let IsVSXFMAAlt = 1 in 5520b57cec5SDimitry Andric def XVNMADDMSP : XX3Form<60, 201, 5530b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 5540b57cec5SDimitry Andric "xvnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>, 5550b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 5560b57cec5SDimitry Andric AltVSXFMARel; 5570b57cec5SDimitry Andric } 5580b57cec5SDimitry Andric 5590b57cec5SDimitry Andric let BaseName = "XVNMSUBADP" in { 5600b57cec5SDimitry Andric let isCommutable = 1 in 5610b57cec5SDimitry Andric def XVNMSUBADP : XX3Form<60, 241, 5620b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 5630b57cec5SDimitry Andric "xvnmsubadp $XT, $XA, $XB", IIC_VecFP, 5645ffd83dbSDimitry Andric [(set v2f64:$XT, (fneg (any_fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi))))]>, 5650b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 5660b57cec5SDimitry Andric AltVSXFMARel; 5670b57cec5SDimitry Andric let IsVSXFMAAlt = 1 in 5680b57cec5SDimitry Andric def XVNMSUBMDP : XX3Form<60, 249, 5690b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 5700b57cec5SDimitry Andric "xvnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>, 5710b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 5720b57cec5SDimitry Andric AltVSXFMARel; 5730b57cec5SDimitry Andric } 5740b57cec5SDimitry Andric 5750b57cec5SDimitry Andric let BaseName = "XVNMSUBASP" in { 5760b57cec5SDimitry Andric let isCommutable = 1 in 5770b57cec5SDimitry Andric def XVNMSUBASP : XX3Form<60, 209, 5780b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 5790b57cec5SDimitry Andric "xvnmsubasp $XT, $XA, $XB", IIC_VecFP, 5805ffd83dbSDimitry Andric [(set v4f32:$XT, (fneg (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>, 5810b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 5820b57cec5SDimitry Andric AltVSXFMARel; 5830b57cec5SDimitry Andric let IsVSXFMAAlt = 1 in 5840b57cec5SDimitry Andric def XVNMSUBMSP : XX3Form<60, 217, 5850b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 5860b57cec5SDimitry Andric "xvnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>, 5870b57cec5SDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 5880b57cec5SDimitry Andric AltVSXFMARel; 5890b57cec5SDimitry Andric } 5900b57cec5SDimitry Andric 5910b57cec5SDimitry Andric // Division Instructions 5920b57cec5SDimitry Andric def XSDIVDP : XX3Form<60, 56, 5930b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 5940b57cec5SDimitry Andric "xsdivdp $XT, $XA, $XB", IIC_FPDivD, 5955ffd83dbSDimitry Andric [(set f64:$XT, (any_fdiv f64:$XA, f64:$XB))]>; 5960b57cec5SDimitry Andric def XSSQRTDP : XX2Form<60, 75, 5970b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 5980b57cec5SDimitry Andric "xssqrtdp $XT, $XB", IIC_FPSqrtD, 5995ffd83dbSDimitry Andric [(set f64:$XT, (any_fsqrt f64:$XB))]>; 6000b57cec5SDimitry Andric 6010b57cec5SDimitry Andric def XSREDP : XX2Form<60, 90, 6020b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 6030b57cec5SDimitry Andric "xsredp $XT, $XB", IIC_VecFP, 6040b57cec5SDimitry Andric [(set f64:$XT, (PPCfre f64:$XB))]>; 6050b57cec5SDimitry Andric def XSRSQRTEDP : XX2Form<60, 74, 6060b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 6070b57cec5SDimitry Andric "xsrsqrtedp $XT, $XB", IIC_VecFP, 6080b57cec5SDimitry Andric [(set f64:$XT, (PPCfrsqrte f64:$XB))]>; 6090b57cec5SDimitry Andric 610e8d8bef9SDimitry Andric let mayRaiseFPException = 0 in { 6110b57cec5SDimitry Andric def XSTDIVDP : XX3Form_1<60, 61, 61206c3fb27SDimitry Andric (outs crrc:$CR), (ins vsfrc:$XA, vsfrc:$XB), 61306c3fb27SDimitry Andric "xstdivdp $CR, $XA, $XB", IIC_FPCompare, []>; 6140b57cec5SDimitry Andric def XSTSQRTDP : XX2Form_1<60, 106, 61506c3fb27SDimitry Andric (outs crrc:$CR), (ins vsfrc:$XB), 61606c3fb27SDimitry Andric "xstsqrtdp $CR, $XB", IIC_FPCompare, 61706c3fb27SDimitry Andric [(set i32:$CR, (PPCftsqrt f64:$XB))]>; 618e8d8bef9SDimitry Andric def XVTDIVDP : XX3Form_1<60, 125, 61906c3fb27SDimitry Andric (outs crrc:$CR), (ins vsrc:$XA, vsrc:$XB), 62006c3fb27SDimitry Andric "xvtdivdp $CR, $XA, $XB", IIC_FPCompare, []>; 621e8d8bef9SDimitry Andric def XVTDIVSP : XX3Form_1<60, 93, 62206c3fb27SDimitry Andric (outs crrc:$CR), (ins vsrc:$XA, vsrc:$XB), 62306c3fb27SDimitry Andric "xvtdivsp $CR, $XA, $XB", IIC_FPCompare, []>; 624e8d8bef9SDimitry Andric 625e8d8bef9SDimitry Andric def XVTSQRTDP : XX2Form_1<60, 234, 62606c3fb27SDimitry Andric (outs crrc:$CR), (ins vsrc:$XB), 62706c3fb27SDimitry Andric "xvtsqrtdp $CR, $XB", IIC_FPCompare, 62806c3fb27SDimitry Andric [(set i32:$CR, (PPCftsqrt v2f64:$XB))]>; 629e8d8bef9SDimitry Andric def XVTSQRTSP : XX2Form_1<60, 170, 63006c3fb27SDimitry Andric (outs crrc:$CR), (ins vsrc:$XB), 63106c3fb27SDimitry Andric "xvtsqrtsp $CR, $XB", IIC_FPCompare, 63206c3fb27SDimitry Andric [(set i32:$CR, (PPCftsqrt v4f32:$XB))]>; 633e8d8bef9SDimitry Andric } 6340b57cec5SDimitry Andric 6350b57cec5SDimitry Andric def XVDIVDP : XX3Form<60, 120, 6360b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 6370b57cec5SDimitry Andric "xvdivdp $XT, $XA, $XB", IIC_FPDivD, 6385ffd83dbSDimitry Andric [(set v2f64:$XT, (any_fdiv v2f64:$XA, v2f64:$XB))]>; 6390b57cec5SDimitry Andric def XVDIVSP : XX3Form<60, 88, 6400b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 6410b57cec5SDimitry Andric "xvdivsp $XT, $XA, $XB", IIC_FPDivS, 6425ffd83dbSDimitry Andric [(set v4f32:$XT, (any_fdiv v4f32:$XA, v4f32:$XB))]>; 6430b57cec5SDimitry Andric 6440b57cec5SDimitry Andric def XVSQRTDP : XX2Form<60, 203, 6450b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 6460b57cec5SDimitry Andric "xvsqrtdp $XT, $XB", IIC_FPSqrtD, 6475ffd83dbSDimitry Andric [(set v2f64:$XT, (any_fsqrt v2f64:$XB))]>; 6480b57cec5SDimitry Andric def XVSQRTSP : XX2Form<60, 139, 6490b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 6500b57cec5SDimitry Andric "xvsqrtsp $XT, $XB", IIC_FPSqrtS, 6515ffd83dbSDimitry Andric [(set v4f32:$XT, (any_fsqrt v4f32:$XB))]>; 6520b57cec5SDimitry Andric 6530b57cec5SDimitry Andric def XVREDP : XX2Form<60, 218, 6540b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 6550b57cec5SDimitry Andric "xvredp $XT, $XB", IIC_VecFP, 6560b57cec5SDimitry Andric [(set v2f64:$XT, (PPCfre v2f64:$XB))]>; 6570b57cec5SDimitry Andric def XVRESP : XX2Form<60, 154, 6580b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 6590b57cec5SDimitry Andric "xvresp $XT, $XB", IIC_VecFP, 6600b57cec5SDimitry Andric [(set v4f32:$XT, (PPCfre v4f32:$XB))]>; 6610b57cec5SDimitry Andric 6620b57cec5SDimitry Andric def XVRSQRTEDP : XX2Form<60, 202, 6630b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 6640b57cec5SDimitry Andric "xvrsqrtedp $XT, $XB", IIC_VecFP, 6650b57cec5SDimitry Andric [(set v2f64:$XT, (PPCfrsqrte v2f64:$XB))]>; 6660b57cec5SDimitry Andric def XVRSQRTESP : XX2Form<60, 138, 6670b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 6680b57cec5SDimitry Andric "xvrsqrtesp $XT, $XB", IIC_VecFP, 6690b57cec5SDimitry Andric [(set v4f32:$XT, (PPCfrsqrte v4f32:$XB))]>; 6700b57cec5SDimitry Andric 6710b57cec5SDimitry Andric // Compare Instructions 6720b57cec5SDimitry Andric def XSCMPODP : XX3Form_1<60, 43, 67306c3fb27SDimitry Andric (outs crrc:$CR), (ins vsfrc:$XA, vsfrc:$XB), 67406c3fb27SDimitry Andric "xscmpodp $CR, $XA, $XB", IIC_FPCompare, []>; 6750b57cec5SDimitry Andric def XSCMPUDP : XX3Form_1<60, 35, 67606c3fb27SDimitry Andric (outs crrc:$CR), (ins vsfrc:$XA, vsfrc:$XB), 67706c3fb27SDimitry Andric "xscmpudp $CR, $XA, $XB", IIC_FPCompare, []>; 6780b57cec5SDimitry Andric 6790b57cec5SDimitry Andric defm XVCMPEQDP : XX3Form_Rcr<60, 99, 6800b57cec5SDimitry Andric "xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare, 6810b57cec5SDimitry Andric int_ppc_vsx_xvcmpeqdp, v2i64, v2f64>; 6820b57cec5SDimitry Andric defm XVCMPEQSP : XX3Form_Rcr<60, 67, 6830b57cec5SDimitry Andric "xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare, 6840b57cec5SDimitry Andric int_ppc_vsx_xvcmpeqsp, v4i32, v4f32>; 6850b57cec5SDimitry Andric defm XVCMPGEDP : XX3Form_Rcr<60, 115, 6860b57cec5SDimitry Andric "xvcmpgedp", "$XT, $XA, $XB", IIC_VecFPCompare, 6870b57cec5SDimitry Andric int_ppc_vsx_xvcmpgedp, v2i64, v2f64>; 6880b57cec5SDimitry Andric defm XVCMPGESP : XX3Form_Rcr<60, 83, 6890b57cec5SDimitry Andric "xvcmpgesp", "$XT, $XA, $XB", IIC_VecFPCompare, 6900b57cec5SDimitry Andric int_ppc_vsx_xvcmpgesp, v4i32, v4f32>; 6910b57cec5SDimitry Andric defm XVCMPGTDP : XX3Form_Rcr<60, 107, 6920b57cec5SDimitry Andric "xvcmpgtdp", "$XT, $XA, $XB", IIC_VecFPCompare, 6930b57cec5SDimitry Andric int_ppc_vsx_xvcmpgtdp, v2i64, v2f64>; 6940b57cec5SDimitry Andric defm XVCMPGTSP : XX3Form_Rcr<60, 75, 6950b57cec5SDimitry Andric "xvcmpgtsp", "$XT, $XA, $XB", IIC_VecFPCompare, 6960b57cec5SDimitry Andric int_ppc_vsx_xvcmpgtsp, v4i32, v4f32>; 6970b57cec5SDimitry Andric 6980b57cec5SDimitry Andric // Move Instructions 699e8d8bef9SDimitry Andric let mayRaiseFPException = 0 in { 7000b57cec5SDimitry Andric def XSABSDP : XX2Form<60, 345, 7010b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 7020b57cec5SDimitry Andric "xsabsdp $XT, $XB", IIC_VecFP, 7030b57cec5SDimitry Andric [(set f64:$XT, (fabs f64:$XB))]>; 7040b57cec5SDimitry Andric def XSNABSDP : XX2Form<60, 361, 7050b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 7060b57cec5SDimitry Andric "xsnabsdp $XT, $XB", IIC_VecFP, 7070b57cec5SDimitry Andric [(set f64:$XT, (fneg (fabs f64:$XB)))]>; 70881ad6265SDimitry Andric let isCodeGenOnly = 1 in 70981ad6265SDimitry Andric def XSNABSDPs : XX2Form<60, 361, 71081ad6265SDimitry Andric (outs vssrc:$XT), (ins vssrc:$XB), 71181ad6265SDimitry Andric "xsnabsdp $XT, $XB", IIC_VecFP, 71281ad6265SDimitry Andric [(set f32:$XT, (fneg (fabs f32:$XB)))]>; 7130b57cec5SDimitry Andric def XSNEGDP : XX2Form<60, 377, 7140b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 7150b57cec5SDimitry Andric "xsnegdp $XT, $XB", IIC_VecFP, 7160b57cec5SDimitry Andric [(set f64:$XT, (fneg f64:$XB))]>; 7170b57cec5SDimitry Andric def XSCPSGNDP : XX3Form<60, 176, 7180b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 7190b57cec5SDimitry Andric "xscpsgndp $XT, $XA, $XB", IIC_VecFP, 7200b57cec5SDimitry Andric [(set f64:$XT, (fcopysign f64:$XB, f64:$XA))]>; 7210b57cec5SDimitry Andric 7220b57cec5SDimitry Andric def XVABSDP : XX2Form<60, 473, 7230b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 7240b57cec5SDimitry Andric "xvabsdp $XT, $XB", IIC_VecFP, 7250b57cec5SDimitry Andric [(set v2f64:$XT, (fabs v2f64:$XB))]>; 7260b57cec5SDimitry Andric 7270b57cec5SDimitry Andric def XVABSSP : XX2Form<60, 409, 7280b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 7290b57cec5SDimitry Andric "xvabssp $XT, $XB", IIC_VecFP, 7300b57cec5SDimitry Andric [(set v4f32:$XT, (fabs v4f32:$XB))]>; 7310b57cec5SDimitry Andric 7320b57cec5SDimitry Andric def XVCPSGNDP : XX3Form<60, 240, 7330b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 7340b57cec5SDimitry Andric "xvcpsgndp $XT, $XA, $XB", IIC_VecFP, 7350b57cec5SDimitry Andric [(set v2f64:$XT, (fcopysign v2f64:$XB, v2f64:$XA))]>; 7360b57cec5SDimitry Andric def XVCPSGNSP : XX3Form<60, 208, 7370b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 7380b57cec5SDimitry Andric "xvcpsgnsp $XT, $XA, $XB", IIC_VecFP, 7390b57cec5SDimitry Andric [(set v4f32:$XT, (fcopysign v4f32:$XB, v4f32:$XA))]>; 7400b57cec5SDimitry Andric 7410b57cec5SDimitry Andric def XVNABSDP : XX2Form<60, 489, 7420b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 7430b57cec5SDimitry Andric "xvnabsdp $XT, $XB", IIC_VecFP, 7440b57cec5SDimitry Andric [(set v2f64:$XT, (fneg (fabs v2f64:$XB)))]>; 7450b57cec5SDimitry Andric def XVNABSSP : XX2Form<60, 425, 7460b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 7470b57cec5SDimitry Andric "xvnabssp $XT, $XB", IIC_VecFP, 7480b57cec5SDimitry Andric [(set v4f32:$XT, (fneg (fabs v4f32:$XB)))]>; 7490b57cec5SDimitry Andric 7500b57cec5SDimitry Andric def XVNEGDP : XX2Form<60, 505, 7510b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 7520b57cec5SDimitry Andric "xvnegdp $XT, $XB", IIC_VecFP, 7530b57cec5SDimitry Andric [(set v2f64:$XT, (fneg v2f64:$XB))]>; 7540b57cec5SDimitry Andric def XVNEGSP : XX2Form<60, 441, 7550b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 7560b57cec5SDimitry Andric "xvnegsp $XT, $XB", IIC_VecFP, 7570b57cec5SDimitry Andric [(set v4f32:$XT, (fneg v4f32:$XB))]>; 758e8d8bef9SDimitry Andric } 7590b57cec5SDimitry Andric 7600b57cec5SDimitry Andric // Conversion Instructions 7610b57cec5SDimitry Andric def XSCVDPSP : XX2Form<60, 265, 7620b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 7630b57cec5SDimitry Andric "xscvdpsp $XT, $XB", IIC_VecFP, []>; 7640b57cec5SDimitry Andric def XSCVDPSXDS : XX2Form<60, 344, 7650b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 7660b57cec5SDimitry Andric "xscvdpsxds $XT, $XB", IIC_VecFP, 767e8d8bef9SDimitry Andric [(set f64:$XT, (PPCany_fctidz f64:$XB))]>; 7680b57cec5SDimitry Andric let isCodeGenOnly = 1 in 7690b57cec5SDimitry Andric def XSCVDPSXDSs : XX2Form<60, 344, 7700b57cec5SDimitry Andric (outs vssrc:$XT), (ins vssrc:$XB), 7710b57cec5SDimitry Andric "xscvdpsxds $XT, $XB", IIC_VecFP, 772e8d8bef9SDimitry Andric [(set f32:$XT, (PPCany_fctidz f32:$XB))]>; 7730b57cec5SDimitry Andric def XSCVDPSXWS : XX2Form<60, 88, 7740b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 7750b57cec5SDimitry Andric "xscvdpsxws $XT, $XB", IIC_VecFP, 776e8d8bef9SDimitry Andric [(set f64:$XT, (PPCany_fctiwz f64:$XB))]>; 7770b57cec5SDimitry Andric let isCodeGenOnly = 1 in 7780b57cec5SDimitry Andric def XSCVDPSXWSs : XX2Form<60, 88, 7790b57cec5SDimitry Andric (outs vssrc:$XT), (ins vssrc:$XB), 7800b57cec5SDimitry Andric "xscvdpsxws $XT, $XB", IIC_VecFP, 781e8d8bef9SDimitry Andric [(set f32:$XT, (PPCany_fctiwz f32:$XB))]>; 7820b57cec5SDimitry Andric def XSCVDPUXDS : XX2Form<60, 328, 7830b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 7840b57cec5SDimitry Andric "xscvdpuxds $XT, $XB", IIC_VecFP, 785e8d8bef9SDimitry Andric [(set f64:$XT, (PPCany_fctiduz f64:$XB))]>; 7860b57cec5SDimitry Andric let isCodeGenOnly = 1 in 7870b57cec5SDimitry Andric def XSCVDPUXDSs : XX2Form<60, 328, 7880b57cec5SDimitry Andric (outs vssrc:$XT), (ins vssrc:$XB), 7890b57cec5SDimitry Andric "xscvdpuxds $XT, $XB", IIC_VecFP, 790e8d8bef9SDimitry Andric [(set f32:$XT, (PPCany_fctiduz f32:$XB))]>; 7910b57cec5SDimitry Andric def XSCVDPUXWS : XX2Form<60, 72, 7920b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 7930b57cec5SDimitry Andric "xscvdpuxws $XT, $XB", IIC_VecFP, 794e8d8bef9SDimitry Andric [(set f64:$XT, (PPCany_fctiwuz f64:$XB))]>; 7950b57cec5SDimitry Andric let isCodeGenOnly = 1 in 7960b57cec5SDimitry Andric def XSCVDPUXWSs : XX2Form<60, 72, 7970b57cec5SDimitry Andric (outs vssrc:$XT), (ins vssrc:$XB), 7980b57cec5SDimitry Andric "xscvdpuxws $XT, $XB", IIC_VecFP, 799e8d8bef9SDimitry Andric [(set f32:$XT, (PPCany_fctiwuz f32:$XB))]>; 8000b57cec5SDimitry Andric def XSCVSPDP : XX2Form<60, 329, 8010b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 8020b57cec5SDimitry Andric "xscvspdp $XT, $XB", IIC_VecFP, []>; 8030b57cec5SDimitry Andric def XSCVSXDDP : XX2Form<60, 376, 8040b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 8050b57cec5SDimitry Andric "xscvsxddp $XT, $XB", IIC_VecFP, 806e8d8bef9SDimitry Andric [(set f64:$XT, (PPCany_fcfid f64:$XB))]>; 8070b57cec5SDimitry Andric def XSCVUXDDP : XX2Form<60, 360, 8080b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 8090b57cec5SDimitry Andric "xscvuxddp $XT, $XB", IIC_VecFP, 810e8d8bef9SDimitry Andric [(set f64:$XT, (PPCany_fcfidu f64:$XB))]>; 8110b57cec5SDimitry Andric 8120b57cec5SDimitry Andric def XVCVDPSP : XX2Form<60, 393, 8130b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 8140b57cec5SDimitry Andric "xvcvdpsp $XT, $XB", IIC_VecFP, 8150b57cec5SDimitry Andric [(set v4f32:$XT, (int_ppc_vsx_xvcvdpsp v2f64:$XB))]>; 8160b57cec5SDimitry Andric def XVCVDPSXDS : XX2Form<60, 472, 8170b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 8180b57cec5SDimitry Andric "xvcvdpsxds $XT, $XB", IIC_VecFP, 819e8d8bef9SDimitry Andric [(set v2i64:$XT, (any_fp_to_sint v2f64:$XB))]>; 8200b57cec5SDimitry Andric def XVCVDPSXWS : XX2Form<60, 216, 8210b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 8220b57cec5SDimitry Andric "xvcvdpsxws $XT, $XB", IIC_VecFP, 8230b57cec5SDimitry Andric [(set v4i32:$XT, (int_ppc_vsx_xvcvdpsxws v2f64:$XB))]>; 8240b57cec5SDimitry Andric def XVCVDPUXDS : XX2Form<60, 456, 8250b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 8260b57cec5SDimitry Andric "xvcvdpuxds $XT, $XB", IIC_VecFP, 827e8d8bef9SDimitry Andric [(set v2i64:$XT, (any_fp_to_uint v2f64:$XB))]>; 8280b57cec5SDimitry Andric def XVCVDPUXWS : XX2Form<60, 200, 8290b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 8300b57cec5SDimitry Andric "xvcvdpuxws $XT, $XB", IIC_VecFP, 8310b57cec5SDimitry Andric [(set v4i32:$XT, (int_ppc_vsx_xvcvdpuxws v2f64:$XB))]>; 8320b57cec5SDimitry Andric 8330b57cec5SDimitry Andric def XVCVSPDP : XX2Form<60, 457, 8340b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 8350b57cec5SDimitry Andric "xvcvspdp $XT, $XB", IIC_VecFP, 8360b57cec5SDimitry Andric [(set v2f64:$XT, (int_ppc_vsx_xvcvspdp v4f32:$XB))]>; 8370b57cec5SDimitry Andric def XVCVSPSXDS : XX2Form<60, 408, 8380b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 839fe6060f1SDimitry Andric "xvcvspsxds $XT, $XB", IIC_VecFP, 840fe6060f1SDimitry Andric [(set v2i64:$XT, (int_ppc_vsx_xvcvspsxds v4f32:$XB))]>; 8410b57cec5SDimitry Andric def XVCVSPSXWS : XX2Form<60, 152, 8420b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 8430b57cec5SDimitry Andric "xvcvspsxws $XT, $XB", IIC_VecFP, 844e8d8bef9SDimitry Andric [(set v4i32:$XT, (any_fp_to_sint v4f32:$XB))]>; 8450b57cec5SDimitry Andric def XVCVSPUXDS : XX2Form<60, 392, 8460b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 847fe6060f1SDimitry Andric "xvcvspuxds $XT, $XB", IIC_VecFP, 848fe6060f1SDimitry Andric [(set v2i64:$XT, (int_ppc_vsx_xvcvspuxds v4f32:$XB))]>; 8490b57cec5SDimitry Andric def XVCVSPUXWS : XX2Form<60, 136, 8500b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 8510b57cec5SDimitry Andric "xvcvspuxws $XT, $XB", IIC_VecFP, 852e8d8bef9SDimitry Andric [(set v4i32:$XT, (any_fp_to_uint v4f32:$XB))]>; 8530b57cec5SDimitry Andric def XVCVSXDDP : XX2Form<60, 504, 8540b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 8550b57cec5SDimitry Andric "xvcvsxddp $XT, $XB", IIC_VecFP, 856e8d8bef9SDimitry Andric [(set v2f64:$XT, (any_sint_to_fp v2i64:$XB))]>; 8570b57cec5SDimitry Andric def XVCVSXDSP : XX2Form<60, 440, 8580b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 8590b57cec5SDimitry Andric "xvcvsxdsp $XT, $XB", IIC_VecFP, 8600b57cec5SDimitry Andric [(set v4f32:$XT, (int_ppc_vsx_xvcvsxdsp v2i64:$XB))]>; 8610b57cec5SDimitry Andric def XVCVSXWSP : XX2Form<60, 184, 8620b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 8630b57cec5SDimitry Andric "xvcvsxwsp $XT, $XB", IIC_VecFP, 864e8d8bef9SDimitry Andric [(set v4f32:$XT, (any_sint_to_fp v4i32:$XB))]>; 8650b57cec5SDimitry Andric def XVCVUXDDP : XX2Form<60, 488, 8660b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 8670b57cec5SDimitry Andric "xvcvuxddp $XT, $XB", IIC_VecFP, 868e8d8bef9SDimitry Andric [(set v2f64:$XT, (any_uint_to_fp v2i64:$XB))]>; 8690b57cec5SDimitry Andric def XVCVUXDSP : XX2Form<60, 424, 8700b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 8710b57cec5SDimitry Andric "xvcvuxdsp $XT, $XB", IIC_VecFP, 8720b57cec5SDimitry Andric [(set v4f32:$XT, (int_ppc_vsx_xvcvuxdsp v2i64:$XB))]>; 873e8d8bef9SDimitry Andric def XVCVUXWSP : XX2Form<60, 168, 874e8d8bef9SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 875e8d8bef9SDimitry Andric "xvcvuxwsp $XT, $XB", IIC_VecFP, 876e8d8bef9SDimitry Andric [(set v4f32:$XT, (any_uint_to_fp v4i32:$XB))]>; 877e8d8bef9SDimitry Andric 878e8d8bef9SDimitry Andric let mayRaiseFPException = 0 in { 879e8d8bef9SDimitry Andric def XVCVSXWDP : XX2Form<60, 248, 880e8d8bef9SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 881e8d8bef9SDimitry Andric "xvcvsxwdp $XT, $XB", IIC_VecFP, 882e8d8bef9SDimitry Andric [(set v2f64:$XT, (int_ppc_vsx_xvcvsxwdp v4i32:$XB))]>; 8830b57cec5SDimitry Andric def XVCVUXWDP : XX2Form<60, 232, 8840b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 8850b57cec5SDimitry Andric "xvcvuxwdp $XT, $XB", IIC_VecFP, 8860b57cec5SDimitry Andric [(set v2f64:$XT, (int_ppc_vsx_xvcvuxwdp v4i32:$XB))]>; 887e8d8bef9SDimitry Andric } 8880b57cec5SDimitry Andric 889e8d8bef9SDimitry Andric // Rounding Instructions respecting current rounding mode 8900b57cec5SDimitry Andric def XSRDPIC : XX2Form<60, 107, 8910b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 892349cc55cSDimitry Andric "xsrdpic $XT, $XB", IIC_VecFP, []>; 8930b57cec5SDimitry Andric def XVRDPIC : XX2Form<60, 235, 8940b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 895349cc55cSDimitry Andric "xvrdpic $XT, $XB", IIC_VecFP, []>; 8960b57cec5SDimitry Andric def XVRSPIC : XX2Form<60, 171, 8970b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 898349cc55cSDimitry Andric "xvrspic $XT, $XB", IIC_VecFP, []>; 8990b57cec5SDimitry Andric // Max/Min Instructions 9000b57cec5SDimitry Andric let isCommutable = 1 in { 9010b57cec5SDimitry Andric def XSMAXDP : XX3Form<60, 160, 9020b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 9030b57cec5SDimitry Andric "xsmaxdp $XT, $XA, $XB", IIC_VecFP, 9040b57cec5SDimitry Andric [(set vsfrc:$XT, 9050b57cec5SDimitry Andric (int_ppc_vsx_xsmaxdp vsfrc:$XA, vsfrc:$XB))]>; 9060b57cec5SDimitry Andric def XSMINDP : XX3Form<60, 168, 9070b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 9080b57cec5SDimitry Andric "xsmindp $XT, $XA, $XB", IIC_VecFP, 9090b57cec5SDimitry Andric [(set vsfrc:$XT, 9100b57cec5SDimitry Andric (int_ppc_vsx_xsmindp vsfrc:$XA, vsfrc:$XB))]>; 9110b57cec5SDimitry Andric 9120b57cec5SDimitry Andric def XVMAXDP : XX3Form<60, 224, 9130b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 9140b57cec5SDimitry Andric "xvmaxdp $XT, $XA, $XB", IIC_VecFP, 9150b57cec5SDimitry Andric [(set vsrc:$XT, 9160b57cec5SDimitry Andric (int_ppc_vsx_xvmaxdp vsrc:$XA, vsrc:$XB))]>; 9170b57cec5SDimitry Andric def XVMINDP : XX3Form<60, 232, 9180b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 9190b57cec5SDimitry Andric "xvmindp $XT, $XA, $XB", IIC_VecFP, 9200b57cec5SDimitry Andric [(set vsrc:$XT, 9210b57cec5SDimitry Andric (int_ppc_vsx_xvmindp vsrc:$XA, vsrc:$XB))]>; 9220b57cec5SDimitry Andric 9230b57cec5SDimitry Andric def XVMAXSP : XX3Form<60, 192, 9240b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 9250b57cec5SDimitry Andric "xvmaxsp $XT, $XA, $XB", IIC_VecFP, 9260b57cec5SDimitry Andric [(set vsrc:$XT, 9270b57cec5SDimitry Andric (int_ppc_vsx_xvmaxsp vsrc:$XA, vsrc:$XB))]>; 9280b57cec5SDimitry Andric def XVMINSP : XX3Form<60, 200, 9290b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 9300b57cec5SDimitry Andric "xvminsp $XT, $XA, $XB", IIC_VecFP, 9310b57cec5SDimitry Andric [(set vsrc:$XT, 9320b57cec5SDimitry Andric (int_ppc_vsx_xvminsp vsrc:$XA, vsrc:$XB))]>; 9330b57cec5SDimitry Andric } // isCommutable 934e8d8bef9SDimitry Andric } // Uses = [RM] 935e8d8bef9SDimitry Andric 936e8d8bef9SDimitry Andric // Rounding Instructions with static direction. 937e8d8bef9SDimitry Andric def XSRDPI : XX2Form<60, 73, 938e8d8bef9SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 939e8d8bef9SDimitry Andric "xsrdpi $XT, $XB", IIC_VecFP, 940e8d8bef9SDimitry Andric [(set f64:$XT, (any_fround f64:$XB))]>; 941e8d8bef9SDimitry Andric def XSRDPIM : XX2Form<60, 121, 942e8d8bef9SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 943e8d8bef9SDimitry Andric "xsrdpim $XT, $XB", IIC_VecFP, 944e8d8bef9SDimitry Andric [(set f64:$XT, (any_ffloor f64:$XB))]>; 945e8d8bef9SDimitry Andric def XSRDPIP : XX2Form<60, 105, 946e8d8bef9SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 947e8d8bef9SDimitry Andric "xsrdpip $XT, $XB", IIC_VecFP, 948e8d8bef9SDimitry Andric [(set f64:$XT, (any_fceil f64:$XB))]>; 949e8d8bef9SDimitry Andric def XSRDPIZ : XX2Form<60, 89, 950e8d8bef9SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XB), 951e8d8bef9SDimitry Andric "xsrdpiz $XT, $XB", IIC_VecFP, 952e8d8bef9SDimitry Andric [(set f64:$XT, (any_ftrunc f64:$XB))]>; 953e8d8bef9SDimitry Andric 954e8d8bef9SDimitry Andric def XVRDPI : XX2Form<60, 201, 955e8d8bef9SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 956e8d8bef9SDimitry Andric "xvrdpi $XT, $XB", IIC_VecFP, 957e8d8bef9SDimitry Andric [(set v2f64:$XT, (any_fround v2f64:$XB))]>; 958e8d8bef9SDimitry Andric def XVRDPIM : XX2Form<60, 249, 959e8d8bef9SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 960e8d8bef9SDimitry Andric "xvrdpim $XT, $XB", IIC_VecFP, 961e8d8bef9SDimitry Andric [(set v2f64:$XT, (any_ffloor v2f64:$XB))]>; 962e8d8bef9SDimitry Andric def XVRDPIP : XX2Form<60, 233, 963e8d8bef9SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 964e8d8bef9SDimitry Andric "xvrdpip $XT, $XB", IIC_VecFP, 965e8d8bef9SDimitry Andric [(set v2f64:$XT, (any_fceil v2f64:$XB))]>; 966e8d8bef9SDimitry Andric def XVRDPIZ : XX2Form<60, 217, 967e8d8bef9SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 968e8d8bef9SDimitry Andric "xvrdpiz $XT, $XB", IIC_VecFP, 969e8d8bef9SDimitry Andric [(set v2f64:$XT, (any_ftrunc v2f64:$XB))]>; 970e8d8bef9SDimitry Andric 971e8d8bef9SDimitry Andric def XVRSPI : XX2Form<60, 137, 972e8d8bef9SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 973e8d8bef9SDimitry Andric "xvrspi $XT, $XB", IIC_VecFP, 974e8d8bef9SDimitry Andric [(set v4f32:$XT, (any_fround v4f32:$XB))]>; 975e8d8bef9SDimitry Andric def XVRSPIM : XX2Form<60, 185, 976e8d8bef9SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 977e8d8bef9SDimitry Andric "xvrspim $XT, $XB", IIC_VecFP, 978e8d8bef9SDimitry Andric [(set v4f32:$XT, (any_ffloor v4f32:$XB))]>; 979e8d8bef9SDimitry Andric def XVRSPIP : XX2Form<60, 169, 980e8d8bef9SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 981e8d8bef9SDimitry Andric "xvrspip $XT, $XB", IIC_VecFP, 982e8d8bef9SDimitry Andric [(set v4f32:$XT, (any_fceil v4f32:$XB))]>; 983e8d8bef9SDimitry Andric def XVRSPIZ : XX2Form<60, 153, 984e8d8bef9SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB), 985e8d8bef9SDimitry Andric "xvrspiz $XT, $XB", IIC_VecFP, 986e8d8bef9SDimitry Andric [(set v4f32:$XT, (any_ftrunc v4f32:$XB))]>; 987e8d8bef9SDimitry Andric } // mayRaiseFPException 9880b57cec5SDimitry Andric 9890b57cec5SDimitry Andric // Logical Instructions 9900b57cec5SDimitry Andric let isCommutable = 1 in 9910b57cec5SDimitry Andric def XXLAND : XX3Form<60, 130, 9920b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 9930b57cec5SDimitry Andric "xxland $XT, $XA, $XB", IIC_VecGeneral, 9940b57cec5SDimitry Andric [(set v4i32:$XT, (and v4i32:$XA, v4i32:$XB))]>; 9950b57cec5SDimitry Andric def XXLANDC : XX3Form<60, 138, 9960b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 9970b57cec5SDimitry Andric "xxlandc $XT, $XA, $XB", IIC_VecGeneral, 9980b57cec5SDimitry Andric [(set v4i32:$XT, (and v4i32:$XA, 999fe6060f1SDimitry Andric (vnot v4i32:$XB)))]>; 10000b57cec5SDimitry Andric let isCommutable = 1 in { 10010b57cec5SDimitry Andric def XXLNOR : XX3Form<60, 162, 10020b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 10030b57cec5SDimitry Andric "xxlnor $XT, $XA, $XB", IIC_VecGeneral, 1004fe6060f1SDimitry Andric [(set v4i32:$XT, (vnot (or v4i32:$XA, 10050b57cec5SDimitry Andric v4i32:$XB)))]>; 10060b57cec5SDimitry Andric def XXLOR : XX3Form<60, 146, 10070b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 10080b57cec5SDimitry Andric "xxlor $XT, $XA, $XB", IIC_VecGeneral, 10090b57cec5SDimitry Andric [(set v4i32:$XT, (or v4i32:$XA, v4i32:$XB))]>; 10100b57cec5SDimitry Andric let isCodeGenOnly = 1 in 10110b57cec5SDimitry Andric def XXLORf: XX3Form<60, 146, 10120b57cec5SDimitry Andric (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 10130b57cec5SDimitry Andric "xxlor $XT, $XA, $XB", IIC_VecGeneral, []>; 10140b57cec5SDimitry Andric def XXLXOR : XX3Form<60, 154, 10150b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 10160b57cec5SDimitry Andric "xxlxor $XT, $XA, $XB", IIC_VecGeneral, 10170b57cec5SDimitry Andric [(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>; 10180b57cec5SDimitry Andric } // isCommutable 10190b57cec5SDimitry Andric 10200b57cec5SDimitry Andric let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1, 10210b57cec5SDimitry Andric isReMaterializable = 1 in { 10228bcb0991SDimitry Andric def XXLXORz : XX3Form_SameOp<60, 154, (outs vsrc:$XT), (ins), 10230b57cec5SDimitry Andric "xxlxor $XT, $XT, $XT", IIC_VecGeneral, 10240b57cec5SDimitry Andric [(set v4i32:$XT, (v4i32 immAllZerosV))]>; 10258bcb0991SDimitry Andric def XXLXORdpz : XX3Form_SameOp<60, 154, 10260b57cec5SDimitry Andric (outs vsfrc:$XT), (ins), 10270b57cec5SDimitry Andric "xxlxor $XT, $XT, $XT", IIC_VecGeneral, 10280b57cec5SDimitry Andric [(set f64:$XT, (fpimm0))]>; 10298bcb0991SDimitry Andric def XXLXORspz : XX3Form_SameOp<60, 154, 10300b57cec5SDimitry Andric (outs vssrc:$XT), (ins), 10310b57cec5SDimitry Andric "xxlxor $XT, $XT, $XT", IIC_VecGeneral, 10320b57cec5SDimitry Andric [(set f32:$XT, (fpimm0))]>; 10330b57cec5SDimitry Andric } 10340b57cec5SDimitry Andric 10350b57cec5SDimitry Andric // Permutation Instructions 10360b57cec5SDimitry Andric def XXMRGHW : XX3Form<60, 18, 10370b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 10380b57cec5SDimitry Andric "xxmrghw $XT, $XA, $XB", IIC_VecPerm, []>; 10390b57cec5SDimitry Andric def XXMRGLW : XX3Form<60, 50, 10400b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 10410b57cec5SDimitry Andric "xxmrglw $XT, $XA, $XB", IIC_VecPerm, []>; 10420b57cec5SDimitry Andric 10430b57cec5SDimitry Andric def XXPERMDI : XX3Form_2<60, 10, 104406c3fb27SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$D), 104506c3fb27SDimitry Andric "xxpermdi $XT, $XA, $XB, $D", IIC_VecPerm, 10460b57cec5SDimitry Andric [(set v2i64:$XT, (PPCxxpermdi v2i64:$XA, v2i64:$XB, 104706c3fb27SDimitry Andric imm32SExt16:$D))]>; 10480b57cec5SDimitry Andric let isCodeGenOnly = 1 in 1049349cc55cSDimitry Andric // Note that the input register class for `$XA` of XXPERMDIs is `vsfrc` which 1050349cc55cSDimitry Andric // is not the same with the input register class(`vsrc`) of XXPERMDI instruction. 1051349cc55cSDimitry Andric // We did this on purpose because: 1052349cc55cSDimitry Andric // 1: The input is primarily for loads that load a partial vector(LFIWZX, 1053349cc55cSDimitry Andric // etc.), no need for SUBREG_TO_REG. 1054349cc55cSDimitry Andric // 2: With `vsfrc` register class, in the final assembly, float registers 1055349cc55cSDimitry Andric // like `f0` are used instead of vector scalar register like `vs0`. This 1056349cc55cSDimitry Andric // helps readability. 105706c3fb27SDimitry Andric def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$D), 105806c3fb27SDimitry Andric "xxpermdi $XT, $XA, $XA, $D", IIC_VecPerm, []>; 10590b57cec5SDimitry Andric def XXSEL : XX4Form<60, 3, 10600b57cec5SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC), 10610b57cec5SDimitry Andric "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>; 10620b57cec5SDimitry Andric 10630b57cec5SDimitry Andric def XXSLDWI : XX3Form_2<60, 2, 106406c3fb27SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$D), 106506c3fb27SDimitry Andric "xxsldwi $XT, $XA, $XB, $D", IIC_VecPerm, 10660b57cec5SDimitry Andric [(set v4i32:$XT, (PPCvecshl v4i32:$XA, v4i32:$XB, 106706c3fb27SDimitry Andric imm32SExt16:$D))]>; 10680b57cec5SDimitry Andric 10690b57cec5SDimitry Andric let isCodeGenOnly = 1 in 10700b57cec5SDimitry Andric def XXSLDWIs : XX3Form_2s<60, 2, 107106c3fb27SDimitry Andric (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$D), 107206c3fb27SDimitry Andric "xxsldwi $XT, $XA, $XA, $D", IIC_VecPerm, []>; 10730b57cec5SDimitry Andric 10740b57cec5SDimitry Andric def XXSPLTW : XX2Form_2<60, 164, 107506c3fb27SDimitry Andric (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$D), 107606c3fb27SDimitry Andric "xxspltw $XT, $XB, $D", IIC_VecPerm, 10770b57cec5SDimitry Andric [(set v4i32:$XT, 107806c3fb27SDimitry Andric (PPCxxsplt v4i32:$XB, imm32SExt16:$D))]>; 10790b57cec5SDimitry Andric let isCodeGenOnly = 1 in 10800b57cec5SDimitry Andric def XXSPLTWs : XX2Form_2<60, 164, 108106c3fb27SDimitry Andric (outs vsrc:$XT), (ins vsfrc:$XB, u2imm:$D), 108206c3fb27SDimitry Andric "xxspltw $XT, $XB, $D", IIC_VecPerm, []>; 10830b57cec5SDimitry Andric 10845ffd83dbSDimitry Andric// The following VSX instructions were introduced in Power ISA 2.07 10855ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasP8Vector] in { 10865ffd83dbSDimitry Andric let isCommutable = 1 in { 10875ffd83dbSDimitry Andric def XXLEQV : XX3Form<60, 186, 10885ffd83dbSDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 10895ffd83dbSDimitry Andric "xxleqv $XT, $XA, $XB", IIC_VecGeneral, 1090fe6060f1SDimitry Andric [(set v4i32:$XT, (vnot (xor v4i32:$XA, v4i32:$XB)))]>; 10915ffd83dbSDimitry Andric def XXLNAND : XX3Form<60, 178, 10925ffd83dbSDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 10935ffd83dbSDimitry Andric "xxlnand $XT, $XA, $XB", IIC_VecGeneral, 1094fe6060f1SDimitry Andric [(set v4i32:$XT, (vnot (and v4i32:$XA, v4i32:$XB)))]>; 10955ffd83dbSDimitry Andric } // isCommutable 10960b57cec5SDimitry Andric 10975ffd83dbSDimitry Andric let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1, 10985ffd83dbSDimitry Andric isReMaterializable = 1 in { 10995ffd83dbSDimitry Andric def XXLEQVOnes : XX3Form_SameOp<60, 186, (outs vsrc:$XT), (ins), 11005ffd83dbSDimitry Andric "xxleqv $XT, $XT, $XT", IIC_VecGeneral, 11015ffd83dbSDimitry Andric [(set v4i32:$XT, (bitconvert (v16i8 immAllOnesV)))]>; 11025ffd83dbSDimitry Andric } 11035ffd83dbSDimitry Andric 11045ffd83dbSDimitry Andric def XXLORC : XX3Form<60, 170, 11055ffd83dbSDimitry Andric (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 11065ffd83dbSDimitry Andric "xxlorc $XT, $XA, $XB", IIC_VecGeneral, 1107fe6060f1SDimitry Andric [(set v4i32:$XT, (or v4i32:$XA, (vnot v4i32:$XB)))]>; 11085ffd83dbSDimitry Andric 11095ffd83dbSDimitry Andric // VSX scalar loads introduced in ISA 2.07 11105ffd83dbSDimitry Andric let mayLoad = 1, mayStore = 0 in { 11115ffd83dbSDimitry Andric let CodeSize = 3 in 111206c3fb27SDimitry Andric def LXSSPX : XX1Form_memOp<31, 524, (outs vssrc:$XT), (ins (memrr $RA, $RB):$addr), 111306c3fb27SDimitry Andric "lxsspx $XT, $addr", IIC_LdStLFD, []>; 111406c3fb27SDimitry Andric def LXSIWAX : XX1Form_memOp<31, 76, (outs vsfrc:$XT), (ins (memrr $RA, $RB):$addr), 111506c3fb27SDimitry Andric "lxsiwax $XT, $addr", IIC_LdStLFD, []>; 111606c3fb27SDimitry Andric def LXSIWZX : XX1Form_memOp<31, 12, (outs vsfrc:$XT), (ins (memrr $RA, $RB):$addr), 111706c3fb27SDimitry Andric "lxsiwzx $XT, $addr", IIC_LdStLFD, []>; 11185ffd83dbSDimitry Andric 11195ffd83dbSDimitry Andric // Pseudo instruction XFLOADf32 will be expanded to LXSSPX or LFSX later 11205ffd83dbSDimitry Andric let CodeSize = 3 in 11215ffd83dbSDimitry Andric def XFLOADf32 : PseudoXFormMemOp<(outs vssrc:$XT), (ins memrr:$src), 11225ffd83dbSDimitry Andric "#XFLOADf32", 1123fe6060f1SDimitry Andric [(set f32:$XT, (load XForm:$src))]>; 11245ffd83dbSDimitry Andric // Pseudo instruction LIWAX will be expanded to LXSIWAX or LFIWAX later 11255ffd83dbSDimitry Andric def LIWAX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), 11265ffd83dbSDimitry Andric "#LIWAX", 1127fe6060f1SDimitry Andric [(set f64:$XT, (PPClfiwax ForceXForm:$src))]>; 11285ffd83dbSDimitry Andric // Pseudo instruction LIWZX will be expanded to LXSIWZX or LFIWZX later 11295ffd83dbSDimitry Andric def LIWZX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), 11305ffd83dbSDimitry Andric "#LIWZX", 1131fe6060f1SDimitry Andric [(set f64:$XT, (PPClfiwzx ForceXForm:$src))]>; 11325ffd83dbSDimitry Andric } // mayLoad 11335ffd83dbSDimitry Andric 11345ffd83dbSDimitry Andric // VSX scalar stores introduced in ISA 2.07 11355ffd83dbSDimitry Andric let mayStore = 1, mayLoad = 0 in { 11365ffd83dbSDimitry Andric let CodeSize = 3 in 113706c3fb27SDimitry Andric def STXSSPX : XX1Form_memOp<31, 652, (outs), (ins vssrc:$XT, (memrr $RA, $RB):$addr), 113806c3fb27SDimitry Andric "stxsspx $XT, $addr", IIC_LdStSTFD, []>; 113906c3fb27SDimitry Andric def STXSIWX : XX1Form_memOp<31, 140, (outs), (ins vsfrc:$XT, (memrr $RA, $RB):$addr), 114006c3fb27SDimitry Andric "stxsiwx $XT, $addr", IIC_LdStSTFD, []>; 11415ffd83dbSDimitry Andric 11425ffd83dbSDimitry Andric // Pseudo instruction XFSTOREf32 will be expanded to STXSSPX or STFSX later 11435ffd83dbSDimitry Andric let CodeSize = 3 in 11445ffd83dbSDimitry Andric def XFSTOREf32 : PseudoXFormMemOp<(outs), (ins vssrc:$XT, memrr:$dst), 11455ffd83dbSDimitry Andric "#XFSTOREf32", 1146fe6060f1SDimitry Andric [(store f32:$XT, XForm:$dst)]>; 11475ffd83dbSDimitry Andric // Pseudo instruction STIWX will be expanded to STXSIWX or STFIWX later 11485ffd83dbSDimitry Andric def STIWX : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst), 11495ffd83dbSDimitry Andric "#STIWX", 1150fe6060f1SDimitry Andric [(PPCstfiwx f64:$XT, ForceXForm:$dst)]>; 11515ffd83dbSDimitry Andric } // mayStore 11525ffd83dbSDimitry Andric 11535ffd83dbSDimitry Andric // VSX Elementary Scalar FP arithmetic (SP) 11545ffd83dbSDimitry Andric let mayRaiseFPException = 1 in { 11555ffd83dbSDimitry Andric let isCommutable = 1 in { 11565ffd83dbSDimitry Andric def XSADDSP : XX3Form<60, 0, 11575ffd83dbSDimitry Andric (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB), 11585ffd83dbSDimitry Andric "xsaddsp $XT, $XA, $XB", IIC_VecFP, 11595ffd83dbSDimitry Andric [(set f32:$XT, (any_fadd f32:$XA, f32:$XB))]>; 11605ffd83dbSDimitry Andric def XSMULSP : XX3Form<60, 16, 11615ffd83dbSDimitry Andric (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB), 11625ffd83dbSDimitry Andric "xsmulsp $XT, $XA, $XB", IIC_VecFP, 11635ffd83dbSDimitry Andric [(set f32:$XT, (any_fmul f32:$XA, f32:$XB))]>; 11645ffd83dbSDimitry Andric } // isCommutable 11655ffd83dbSDimitry Andric 11665ffd83dbSDimitry Andric def XSSUBSP : XX3Form<60, 8, 11675ffd83dbSDimitry Andric (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB), 11685ffd83dbSDimitry Andric "xssubsp $XT, $XA, $XB", IIC_VecFP, 11695ffd83dbSDimitry Andric [(set f32:$XT, (any_fsub f32:$XA, f32:$XB))]>; 11705ffd83dbSDimitry Andric def XSDIVSP : XX3Form<60, 24, 11715ffd83dbSDimitry Andric (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB), 11725ffd83dbSDimitry Andric "xsdivsp $XT, $XA, $XB", IIC_FPDivS, 11735ffd83dbSDimitry Andric [(set f32:$XT, (any_fdiv f32:$XA, f32:$XB))]>; 11745ffd83dbSDimitry Andric 11755ffd83dbSDimitry Andric def XSRESP : XX2Form<60, 26, 11765ffd83dbSDimitry Andric (outs vssrc:$XT), (ins vssrc:$XB), 11775ffd83dbSDimitry Andric "xsresp $XT, $XB", IIC_VecFP, 11785ffd83dbSDimitry Andric [(set f32:$XT, (PPCfre f32:$XB))]>; 11795ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1180e8d8bef9SDimitry Andric let hasSideEffects = 1 in 11815ffd83dbSDimitry Andric def XSRSP : XX2Form<60, 281, 11825ffd83dbSDimitry Andric (outs vssrc:$XT), (ins vsfrc:$XB), 11835ffd83dbSDimitry Andric "xsrsp $XT, $XB", IIC_VecFP, 11845ffd83dbSDimitry Andric [(set f32:$XT, (any_fpround f64:$XB))]>; 11855ffd83dbSDimitry Andric def XSSQRTSP : XX2Form<60, 11, 11865ffd83dbSDimitry Andric (outs vssrc:$XT), (ins vssrc:$XB), 11875ffd83dbSDimitry Andric "xssqrtsp $XT, $XB", IIC_FPSqrtS, 11885ffd83dbSDimitry Andric [(set f32:$XT, (any_fsqrt f32:$XB))]>; 11895ffd83dbSDimitry Andric def XSRSQRTESP : XX2Form<60, 10, 11905ffd83dbSDimitry Andric (outs vssrc:$XT), (ins vssrc:$XB), 11915ffd83dbSDimitry Andric "xsrsqrtesp $XT, $XB", IIC_VecFP, 11925ffd83dbSDimitry Andric [(set f32:$XT, (PPCfrsqrte f32:$XB))]>; 11935ffd83dbSDimitry Andric 11945ffd83dbSDimitry Andric // FMA Instructions 11955ffd83dbSDimitry Andric let BaseName = "XSMADDASP" in { 11965ffd83dbSDimitry Andric let isCommutable = 1 in 11975ffd83dbSDimitry Andric def XSMADDASP : XX3Form<60, 1, 11985ffd83dbSDimitry Andric (outs vssrc:$XT), 11995ffd83dbSDimitry Andric (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 12005ffd83dbSDimitry Andric "xsmaddasp $XT, $XA, $XB", IIC_VecFP, 12015ffd83dbSDimitry Andric [(set f32:$XT, (any_fma f32:$XA, f32:$XB, f32:$XTi))]>, 12025ffd83dbSDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 12035ffd83dbSDimitry Andric AltVSXFMARel; 12045ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 12055ffd83dbSDimitry Andric let IsVSXFMAAlt = 1, hasSideEffects = 1 in 12065ffd83dbSDimitry Andric def XSMADDMSP : XX3Form<60, 9, 12075ffd83dbSDimitry Andric (outs vssrc:$XT), 12085ffd83dbSDimitry Andric (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 12095ffd83dbSDimitry Andric "xsmaddmsp $XT, $XA, $XB", IIC_VecFP, []>, 12105ffd83dbSDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 12115ffd83dbSDimitry Andric AltVSXFMARel; 12125ffd83dbSDimitry Andric } 12135ffd83dbSDimitry Andric 12145ffd83dbSDimitry Andric let BaseName = "XSMSUBASP" in { 12155ffd83dbSDimitry Andric let isCommutable = 1 in 12165ffd83dbSDimitry Andric def XSMSUBASP : XX3Form<60, 17, 12175ffd83dbSDimitry Andric (outs vssrc:$XT), 12185ffd83dbSDimitry Andric (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 12195ffd83dbSDimitry Andric "xsmsubasp $XT, $XA, $XB", IIC_VecFP, 12205ffd83dbSDimitry Andric [(set f32:$XT, (any_fma f32:$XA, f32:$XB, 12215ffd83dbSDimitry Andric (fneg f32:$XTi)))]>, 12225ffd83dbSDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 12235ffd83dbSDimitry Andric AltVSXFMARel; 12245ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 12255ffd83dbSDimitry Andric let IsVSXFMAAlt = 1, hasSideEffects = 1 in 12265ffd83dbSDimitry Andric def XSMSUBMSP : XX3Form<60, 25, 12275ffd83dbSDimitry Andric (outs vssrc:$XT), 12285ffd83dbSDimitry Andric (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 12295ffd83dbSDimitry Andric "xsmsubmsp $XT, $XA, $XB", IIC_VecFP, []>, 12305ffd83dbSDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 12315ffd83dbSDimitry Andric AltVSXFMARel; 12325ffd83dbSDimitry Andric } 12335ffd83dbSDimitry Andric 12345ffd83dbSDimitry Andric let BaseName = "XSNMADDASP" in { 12355ffd83dbSDimitry Andric let isCommutable = 1 in 12365ffd83dbSDimitry Andric def XSNMADDASP : XX3Form<60, 129, 12375ffd83dbSDimitry Andric (outs vssrc:$XT), 12385ffd83dbSDimitry Andric (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 12395ffd83dbSDimitry Andric "xsnmaddasp $XT, $XA, $XB", IIC_VecFP, 12405ffd83dbSDimitry Andric [(set f32:$XT, (fneg (any_fma f32:$XA, f32:$XB, 12415ffd83dbSDimitry Andric f32:$XTi)))]>, 12425ffd83dbSDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 12435ffd83dbSDimitry Andric AltVSXFMARel; 12445ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 12455ffd83dbSDimitry Andric let IsVSXFMAAlt = 1, hasSideEffects = 1 in 12465ffd83dbSDimitry Andric def XSNMADDMSP : XX3Form<60, 137, 12475ffd83dbSDimitry Andric (outs vssrc:$XT), 12485ffd83dbSDimitry Andric (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 12495ffd83dbSDimitry Andric "xsnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>, 12505ffd83dbSDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 12515ffd83dbSDimitry Andric AltVSXFMARel; 12525ffd83dbSDimitry Andric } 12535ffd83dbSDimitry Andric 12545ffd83dbSDimitry Andric let BaseName = "XSNMSUBASP" in { 12555ffd83dbSDimitry Andric let isCommutable = 1 in 12565ffd83dbSDimitry Andric def XSNMSUBASP : XX3Form<60, 145, 12575ffd83dbSDimitry Andric (outs vssrc:$XT), 12585ffd83dbSDimitry Andric (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 12595ffd83dbSDimitry Andric "xsnmsubasp $XT, $XA, $XB", IIC_VecFP, 12605ffd83dbSDimitry Andric [(set f32:$XT, (fneg (any_fma f32:$XA, f32:$XB, 12615ffd83dbSDimitry Andric (fneg f32:$XTi))))]>, 12625ffd83dbSDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 12635ffd83dbSDimitry Andric AltVSXFMARel; 12645ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 12655ffd83dbSDimitry Andric let IsVSXFMAAlt = 1, hasSideEffects = 1 in 12665ffd83dbSDimitry Andric def XSNMSUBMSP : XX3Form<60, 153, 12675ffd83dbSDimitry Andric (outs vssrc:$XT), 12685ffd83dbSDimitry Andric (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 12695ffd83dbSDimitry Andric "xsnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>, 12705ffd83dbSDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 12715ffd83dbSDimitry Andric AltVSXFMARel; 12725ffd83dbSDimitry Andric } 12735ffd83dbSDimitry Andric 12745ffd83dbSDimitry Andric // Single Precision Conversions (FP <-> INT) 12755ffd83dbSDimitry Andric def XSCVSXDSP : XX2Form<60, 312, 12765ffd83dbSDimitry Andric (outs vssrc:$XT), (ins vsfrc:$XB), 12775ffd83dbSDimitry Andric "xscvsxdsp $XT, $XB", IIC_VecFP, 1278e8d8bef9SDimitry Andric [(set f32:$XT, (PPCany_fcfids f64:$XB))]>; 12795ffd83dbSDimitry Andric def XSCVUXDSP : XX2Form<60, 296, 12805ffd83dbSDimitry Andric (outs vssrc:$XT), (ins vsfrc:$XB), 12815ffd83dbSDimitry Andric "xscvuxdsp $XT, $XB", IIC_VecFP, 1282e8d8bef9SDimitry Andric [(set f32:$XT, (PPCany_fcfidus f64:$XB))]>; 1283e8d8bef9SDimitry Andric } // mayRaiseFPException 12845ffd83dbSDimitry Andric 12855ffd83dbSDimitry Andric // Conversions between vector and scalar single precision 12865ffd83dbSDimitry Andric def XSCVDPSPN : XX2Form<60, 267, (outs vsrc:$XT), (ins vssrc:$XB), 12875ffd83dbSDimitry Andric "xscvdpspn $XT, $XB", IIC_VecFP, []>; 12885ffd83dbSDimitry Andric def XSCVSPDPN : XX2Form<60, 331, (outs vssrc:$XT), (ins vsrc:$XB), 12895ffd83dbSDimitry Andric "xscvspdpn $XT, $XB", IIC_VecFP, []>; 12905ffd83dbSDimitry Andric 12915ffd83dbSDimitry Andric let Predicates = [HasVSX, HasDirectMove] in { 12925ffd83dbSDimitry Andric // VSX direct move instructions 129306c3fb27SDimitry Andric def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$RA), (ins vsfrc:$XT), 129406c3fb27SDimitry Andric "mfvsrd $RA, $XT", IIC_VecGeneral, 129506c3fb27SDimitry Andric [(set i64:$RA, (PPCmfvsr f64:$XT))]>, 12965ffd83dbSDimitry Andric Requires<[In64BitMode]>; 12975ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 12985ffd83dbSDimitry Andric let isCodeGenOnly = 1, hasSideEffects = 1 in 129906c3fb27SDimitry Andric def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$RA), (ins vsrc:$XT), 130006c3fb27SDimitry Andric "mfvsrd $RA, $XT", IIC_VecGeneral, 13015ffd83dbSDimitry Andric []>, 13025ffd83dbSDimitry Andric Requires<[In64BitMode]>; 130306c3fb27SDimitry Andric def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$RA), (ins vsfrc:$XT), 130406c3fb27SDimitry Andric "mfvsrwz $RA, $XT", IIC_VecGeneral, 130506c3fb27SDimitry Andric [(set i32:$RA, (PPCmfvsr f64:$XT))]>, ZExt32To64; 13065ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 13075ffd83dbSDimitry Andric let isCodeGenOnly = 1, hasSideEffects = 1 in 130806c3fb27SDimitry Andric def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$RA), (ins vsrc:$XT), 130906c3fb27SDimitry Andric "mfvsrwz $RA, $XT", IIC_VecGeneral, 13105ffd83dbSDimitry Andric []>; 131106c3fb27SDimitry Andric def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$RA), 131206c3fb27SDimitry Andric "mtvsrd $XT, $RA", IIC_VecGeneral, 131306c3fb27SDimitry Andric [(set f64:$XT, (PPCmtvsra i64:$RA))]>, 13145ffd83dbSDimitry Andric Requires<[In64BitMode]>; 13155ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 13165ffd83dbSDimitry Andric let isCodeGenOnly = 1, hasSideEffects = 1 in 131706c3fb27SDimitry Andric def MTVRD : XX1_RS6_RD5_XO<31, 179, (outs vsrc:$XT), (ins g8rc:$RA), 131806c3fb27SDimitry Andric "mtvsrd $XT, $RA", IIC_VecGeneral, 13195ffd83dbSDimitry Andric []>, 13205ffd83dbSDimitry Andric Requires<[In64BitMode]>; 132106c3fb27SDimitry Andric def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$RA), 132206c3fb27SDimitry Andric "mtvsrwa $XT, $RA", IIC_VecGeneral, 132306c3fb27SDimitry Andric [(set f64:$XT, (PPCmtvsra i32:$RA))]>; 13245ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 13255ffd83dbSDimitry Andric let isCodeGenOnly = 1, hasSideEffects = 1 in 132606c3fb27SDimitry Andric def MTVRWA : XX1_RS6_RD5_XO<31, 211, (outs vsrc:$XT), (ins gprc:$RA), 132706c3fb27SDimitry Andric "mtvsrwa $XT, $RA", IIC_VecGeneral, 13285ffd83dbSDimitry Andric []>; 132906c3fb27SDimitry Andric def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$RA), 133006c3fb27SDimitry Andric "mtvsrwz $XT, $RA", IIC_VecGeneral, 133106c3fb27SDimitry Andric [(set f64:$XT, (PPCmtvsrz i32:$RA))]>; 13325ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 13335ffd83dbSDimitry Andric let isCodeGenOnly = 1, hasSideEffects = 1 in 133406c3fb27SDimitry Andric def MTVRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsrc:$XT), (ins gprc:$RA), 133506c3fb27SDimitry Andric "mtvsrwz $XT, $RA", IIC_VecGeneral, 13365ffd83dbSDimitry Andric []>; 13375ffd83dbSDimitry Andric } // HasDirectMove 13385ffd83dbSDimitry Andric 13395ffd83dbSDimitry Andric} // HasVSX, HasP8Vector 13405ffd83dbSDimitry Andric 13415ffd83dbSDimitry Andriclet Predicates = [HasVSX, IsISA3_0, HasDirectMove] in { 134206c3fb27SDimitry Andricdef MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$RA), 134306c3fb27SDimitry Andric "mtvsrws $XT, $RA", IIC_VecGeneral, []>; 13445ffd83dbSDimitry Andric 134506c3fb27SDimitry Andricdef MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc_nox0:$RA, g8rc:$RB), 134606c3fb27SDimitry Andric "mtvsrdd $XT, $RA, $RB", IIC_VecGeneral, 13475ffd83dbSDimitry Andric []>, Requires<[In64BitMode]>; 13485ffd83dbSDimitry Andric 134906c3fb27SDimitry Andricdef MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$RA), (ins vsrc:$XT), 135006c3fb27SDimitry Andric "mfvsrld $RA, $XT", IIC_VecGeneral, 13515ffd83dbSDimitry Andric []>, Requires<[In64BitMode]>; 13525ffd83dbSDimitry Andric 13535ffd83dbSDimitry Andric} // HasVSX, IsISA3_0, HasDirectMove 13545ffd83dbSDimitry Andric 13555ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasP9Vector] in { 13565ffd83dbSDimitry Andric // Quad-Precision Scalar Move Instructions: 13575ffd83dbSDimitry Andric // Copy Sign 13585ffd83dbSDimitry Andric def XSCPSGNQP : X_VT5_VA5_VB5<63, 100, "xscpsgnqp", 135906c3fb27SDimitry Andric [(set f128:$RST, 136006c3fb27SDimitry Andric (fcopysign f128:$RB, f128:$RA))]>; 13615ffd83dbSDimitry Andric 13625ffd83dbSDimitry Andric // Absolute/Negative-Absolute/Negate 13635ffd83dbSDimitry Andric def XSABSQP : X_VT5_XO5_VB5<63, 0, 804, "xsabsqp", 136406c3fb27SDimitry Andric [(set f128:$RST, (fabs f128:$RB))]>; 13655ffd83dbSDimitry Andric def XSNABSQP : X_VT5_XO5_VB5<63, 8, 804, "xsnabsqp", 136606c3fb27SDimitry Andric [(set f128:$RST, (fneg (fabs f128:$RB)))]>; 13675ffd83dbSDimitry Andric def XSNEGQP : X_VT5_XO5_VB5<63, 16, 804, "xsnegqp", 136806c3fb27SDimitry Andric [(set f128:$RST, (fneg f128:$RB))]>; 13695ffd83dbSDimitry Andric 13705ffd83dbSDimitry Andric //===--------------------------------------------------------------------===// 13715ffd83dbSDimitry Andric // Quad-Precision Scalar Floating-Point Arithmetic Instructions: 13725ffd83dbSDimitry Andric 13735ffd83dbSDimitry Andric // Add/Divide/Multiply/Subtract 13745ffd83dbSDimitry Andric let mayRaiseFPException = 1 in { 13755ffd83dbSDimitry Andric let isCommutable = 1 in { 13765ffd83dbSDimitry Andric def XSADDQP : X_VT5_VA5_VB5 <63, 4, "xsaddqp", 137706c3fb27SDimitry Andric [(set f128:$RST, (any_fadd f128:$RA, f128:$RB))]>; 13785ffd83dbSDimitry Andric def XSMULQP : X_VT5_VA5_VB5 <63, 36, "xsmulqp", 137906c3fb27SDimitry Andric [(set f128:$RST, (any_fmul f128:$RA, f128:$RB))]>; 13805ffd83dbSDimitry Andric } 13815ffd83dbSDimitry Andric def XSSUBQP : X_VT5_VA5_VB5 <63, 516, "xssubqp" , 138206c3fb27SDimitry Andric [(set f128:$RST, (any_fsub f128:$RA, f128:$RB))]>; 13835ffd83dbSDimitry Andric def XSDIVQP : X_VT5_VA5_VB5 <63, 548, "xsdivqp", 138406c3fb27SDimitry Andric [(set f128:$RST, (any_fdiv f128:$RA, f128:$RB))]>; 13855ffd83dbSDimitry Andric // Square-Root 13865ffd83dbSDimitry Andric def XSSQRTQP : X_VT5_XO5_VB5 <63, 27, 804, "xssqrtqp", 138706c3fb27SDimitry Andric [(set f128:$RST, (any_fsqrt f128:$RB))]>; 13885ffd83dbSDimitry Andric // (Negative) Multiply-{Add/Subtract} 13895ffd83dbSDimitry Andric def XSMADDQP : X_VT5_VA5_VB5_FMA <63, 388, "xsmaddqp", 139006c3fb27SDimitry Andric [(set f128:$RST, 139106c3fb27SDimitry Andric (any_fma f128:$RA, f128:$RB, f128:$RSTi))]>; 13925ffd83dbSDimitry Andric def XSMSUBQP : X_VT5_VA5_VB5_FMA <63, 420, "xsmsubqp" , 139306c3fb27SDimitry Andric [(set f128:$RST, 139406c3fb27SDimitry Andric (any_fma f128:$RA, f128:$RB, 139506c3fb27SDimitry Andric (fneg f128:$RSTi)))]>; 13965ffd83dbSDimitry Andric def XSNMADDQP : X_VT5_VA5_VB5_FMA <63, 452, "xsnmaddqp", 139706c3fb27SDimitry Andric [(set f128:$RST, 139806c3fb27SDimitry Andric (fneg (any_fma f128:$RA, f128:$RB, 139906c3fb27SDimitry Andric f128:$RSTi)))]>; 14005ffd83dbSDimitry Andric def XSNMSUBQP : X_VT5_VA5_VB5_FMA <63, 484, "xsnmsubqp", 140106c3fb27SDimitry Andric [(set f128:$RST, 140206c3fb27SDimitry Andric (fneg (any_fma f128:$RA, f128:$RB, 140306c3fb27SDimitry Andric (fneg f128:$RSTi))))]>; 14045ffd83dbSDimitry Andric 14055ffd83dbSDimitry Andric let isCommutable = 1 in { 14065ffd83dbSDimitry Andric def XSADDQPO : X_VT5_VA5_VB5_Ro<63, 4, "xsaddqpo", 140706c3fb27SDimitry Andric [(set f128:$RST, 14085ffd83dbSDimitry Andric (int_ppc_addf128_round_to_odd 140906c3fb27SDimitry Andric f128:$RA, f128:$RB))]>; 14105ffd83dbSDimitry Andric def XSMULQPO : X_VT5_VA5_VB5_Ro<63, 36, "xsmulqpo", 141106c3fb27SDimitry Andric [(set f128:$RST, 14125ffd83dbSDimitry Andric (int_ppc_mulf128_round_to_odd 141306c3fb27SDimitry Andric f128:$RA, f128:$RB))]>; 14145ffd83dbSDimitry Andric } 14155ffd83dbSDimitry Andric def XSSUBQPO : X_VT5_VA5_VB5_Ro<63, 516, "xssubqpo", 141606c3fb27SDimitry Andric [(set f128:$RST, 14175ffd83dbSDimitry Andric (int_ppc_subf128_round_to_odd 141806c3fb27SDimitry Andric f128:$RA, f128:$RB))]>; 14195ffd83dbSDimitry Andric def XSDIVQPO : X_VT5_VA5_VB5_Ro<63, 548, "xsdivqpo", 142006c3fb27SDimitry Andric [(set f128:$RST, 14215ffd83dbSDimitry Andric (int_ppc_divf128_round_to_odd 142206c3fb27SDimitry Andric f128:$RA, f128:$RB))]>; 14235ffd83dbSDimitry Andric def XSSQRTQPO : X_VT5_XO5_VB5_Ro<63, 27, 804, "xssqrtqpo", 142406c3fb27SDimitry Andric [(set f128:$RST, 142506c3fb27SDimitry Andric (int_ppc_sqrtf128_round_to_odd f128:$RB))]>; 14265ffd83dbSDimitry Andric 14275ffd83dbSDimitry Andric 14285ffd83dbSDimitry Andric def XSMADDQPO : X_VT5_VA5_VB5_FMA_Ro<63, 388, "xsmaddqpo", 142906c3fb27SDimitry Andric [(set f128:$RST, 14305ffd83dbSDimitry Andric (int_ppc_fmaf128_round_to_odd 143106c3fb27SDimitry Andric f128:$RA,f128:$RB,f128:$RSTi))]>; 14325ffd83dbSDimitry Andric 14335ffd83dbSDimitry Andric def XSMSUBQPO : X_VT5_VA5_VB5_FMA_Ro<63, 420, "xsmsubqpo" , 143406c3fb27SDimitry Andric [(set f128:$RST, 14355ffd83dbSDimitry Andric (int_ppc_fmaf128_round_to_odd 143606c3fb27SDimitry Andric f128:$RA, f128:$RB, (fneg f128:$RSTi)))]>; 14375ffd83dbSDimitry Andric def XSNMADDQPO: X_VT5_VA5_VB5_FMA_Ro<63, 452, "xsnmaddqpo", 143806c3fb27SDimitry Andric [(set f128:$RST, 14395ffd83dbSDimitry Andric (fneg (int_ppc_fmaf128_round_to_odd 144006c3fb27SDimitry Andric f128:$RA, f128:$RB, f128:$RSTi)))]>; 14415ffd83dbSDimitry Andric def XSNMSUBQPO: X_VT5_VA5_VB5_FMA_Ro<63, 484, "xsnmsubqpo", 144206c3fb27SDimitry Andric [(set f128:$RST, 14435ffd83dbSDimitry Andric (fneg (int_ppc_fmaf128_round_to_odd 144406c3fb27SDimitry Andric f128:$RA, f128:$RB, (fneg f128:$RSTi))))]>; 14455ffd83dbSDimitry Andric } // mayRaiseFPException 14465ffd83dbSDimitry Andric 14475ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 14485ffd83dbSDimitry Andric // QP Compare Ordered/Unordered 14495ffd83dbSDimitry Andric let hasSideEffects = 1 in { 14505ffd83dbSDimitry Andric // DP/QP Compare Exponents 14515ffd83dbSDimitry Andric def XSCMPEXPDP : XX3Form_1<60, 59, 145206c3fb27SDimitry Andric (outs crrc:$CR), (ins vsfrc:$XA, vsfrc:$XB), 145306c3fb27SDimitry Andric "xscmpexpdp $CR, $XA, $XB", IIC_FPCompare, []>; 14545ffd83dbSDimitry Andric def XSCMPEXPQP : X_BF3_VA5_VB5<63, 164, "xscmpexpqp", []>; 14555ffd83dbSDimitry Andric 1456e8d8bef9SDimitry Andric let mayRaiseFPException = 1 in { 1457e8d8bef9SDimitry Andric def XSCMPOQP : X_BF3_VA5_VB5<63, 132, "xscmpoqp", []>; 1458e8d8bef9SDimitry Andric def XSCMPUQP : X_BF3_VA5_VB5<63, 644, "xscmpuqp", []>; 1459e8d8bef9SDimitry Andric 14605ffd83dbSDimitry Andric // DP Compare ==, >=, >, != 14615ffd83dbSDimitry Andric // Use vsrc for XT, because the entire register of XT is set. 14625ffd83dbSDimitry Andric // XT.dword[1] = 0x0000_0000_0000_0000 14635ffd83dbSDimitry Andric def XSCMPEQDP : XX3_XT5_XA5_XB5<60, 3, "xscmpeqdp", vsrc, vsfrc, vsfrc, 14645ffd83dbSDimitry Andric IIC_FPCompare, []>; 14655ffd83dbSDimitry Andric def XSCMPGEDP : XX3_XT5_XA5_XB5<60, 19, "xscmpgedp", vsrc, vsfrc, vsfrc, 14665ffd83dbSDimitry Andric IIC_FPCompare, []>; 14675ffd83dbSDimitry Andric def XSCMPGTDP : XX3_XT5_XA5_XB5<60, 11, "xscmpgtdp", vsrc, vsfrc, vsfrc, 14685ffd83dbSDimitry Andric IIC_FPCompare, []>; 14695ffd83dbSDimitry Andric } 1470e8d8bef9SDimitry Andric } 14715ffd83dbSDimitry Andric 14725ffd83dbSDimitry Andric //===--------------------------------------------------------------------===// 14735ffd83dbSDimitry Andric // Quad-Precision Floating-Point Conversion Instructions: 14745ffd83dbSDimitry Andric 14755ffd83dbSDimitry Andric let mayRaiseFPException = 1 in { 14765ffd83dbSDimitry Andric // Convert DP -> QP 14775ffd83dbSDimitry Andric def XSCVDPQP : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc, 147806c3fb27SDimitry Andric [(set f128:$RST, (any_fpextend f64:$RB))]>; 14795ffd83dbSDimitry Andric 14805ffd83dbSDimitry Andric // Round & Convert QP -> DP (dword[1] is set to zero) 14815ffd83dbSDimitry Andric def XSCVQPDP : X_VT5_XO5_VB5_VSFR<63, 20, 836, "xscvqpdp" , []>; 14825ffd83dbSDimitry Andric def XSCVQPDPO : X_VT5_XO5_VB5_VSFR_Ro<63, 20, 836, "xscvqpdpo", 148306c3fb27SDimitry Andric [(set f64:$RST, 14845ffd83dbSDimitry Andric (int_ppc_truncf128_round_to_odd 148506c3fb27SDimitry Andric f128:$RB))]>; 14865ffd83dbSDimitry Andric } 14875ffd83dbSDimitry Andric 14885ffd83dbSDimitry Andric // Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero) 1489e8d8bef9SDimitry Andric let mayRaiseFPException = 1 in { 149006c3fb27SDimitry Andric def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", 149106c3fb27SDimitry Andric [(set f128:$RST, (PPCany_fctidz f128:$RB))]>; 149206c3fb27SDimitry Andric def XSCVQPSWZ : X_VT5_XO5_VB5<63, 9, 836, "xscvqpswz", 149306c3fb27SDimitry Andric [(set f128:$RST, (PPCany_fctiwz f128:$RB))]>; 149406c3fb27SDimitry Andric def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", 149506c3fb27SDimitry Andric [(set f128:$RST, (PPCany_fctiduz f128:$RB))]>; 149606c3fb27SDimitry Andric def XSCVQPUWZ : X_VT5_XO5_VB5<63, 1, 836, "xscvqpuwz", 149706c3fb27SDimitry Andric [(set f128:$RST, (PPCany_fctiwuz f128:$RB))]>; 14985ffd83dbSDimitry Andric } 14995ffd83dbSDimitry Andric 15005ffd83dbSDimitry Andric // Convert (Un)Signed DWord -> QP. 15015ffd83dbSDimitry Andric def XSCVSDQP : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>; 15025ffd83dbSDimitry Andric def XSCVUDQP : X_VT5_XO5_VB5_TyVB<63, 2, 836, "xscvudqp", vfrc, []>; 15035ffd83dbSDimitry Andric 15045ffd83dbSDimitry Andric // (Round &) Convert DP <-> HP 15055ffd83dbSDimitry Andric // Note! xscvdphp's src and dest register both use the left 64 bits, so we use 15065ffd83dbSDimitry Andric // vsfrc for src and dest register. xscvhpdp's src only use the left 16 bits, 15075ffd83dbSDimitry Andric // but we still use vsfrc for it. 15085ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1509e8d8bef9SDimitry Andric let hasSideEffects = 1, mayRaiseFPException = 1 in { 15105ffd83dbSDimitry Andric def XSCVDPHP : XX2_XT6_XO5_XB6<60, 17, 347, "xscvdphp", vsfrc, []>; 15115ffd83dbSDimitry Andric def XSCVHPDP : XX2_XT6_XO5_XB6<60, 16, 347, "xscvhpdp", vsfrc, []>; 15125ffd83dbSDimitry Andric } 15135ffd83dbSDimitry Andric 1514e8d8bef9SDimitry Andric let mayRaiseFPException = 1 in { 15155ffd83dbSDimitry Andric // Vector HP -> SP 15165ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 15175ffd83dbSDimitry Andric let hasSideEffects = 1 in 15185ffd83dbSDimitry Andric def XVCVHPSP : XX2_XT6_XO5_XB6<60, 24, 475, "xvcvhpsp", vsrc, []>; 15195ffd83dbSDimitry Andric def XVCVSPHP : XX2_XT6_XO5_XB6<60, 25, 475, "xvcvsphp", vsrc, 15205ffd83dbSDimitry Andric [(set v4f32:$XT, 15215ffd83dbSDimitry Andric (int_ppc_vsx_xvcvsphp v4f32:$XB))]>; 15225ffd83dbSDimitry Andric 15235ffd83dbSDimitry Andric // Round to Quad-Precision Integer [with Inexact] 15245ffd83dbSDimitry Andric def XSRQPI : Z23_VT5_R1_VB5_RMC2_EX1<63, 5, 0, "xsrqpi" , []>; 15255ffd83dbSDimitry Andric def XSRQPIX : Z23_VT5_R1_VB5_RMC2_EX1<63, 5, 1, "xsrqpix", []>; 15265ffd83dbSDimitry Andric 15275ffd83dbSDimitry Andric // Round Quad-Precision to Double-Extended Precision (fp80) 15285ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 15295ffd83dbSDimitry Andric let hasSideEffects = 1 in 15305ffd83dbSDimitry Andric def XSRQPXP : Z23_VT5_R1_VB5_RMC2_EX1<63, 37, 0, "xsrqpxp", []>; 1531e8d8bef9SDimitry Andric } 15325ffd83dbSDimitry Andric 15335ffd83dbSDimitry Andric //===--------------------------------------------------------------------===// 15345ffd83dbSDimitry Andric // Insert/Extract Instructions 15355ffd83dbSDimitry Andric 15365ffd83dbSDimitry Andric // Insert Exponent DP/QP 15375ffd83dbSDimitry Andric // XT NOTE: XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU 153806c3fb27SDimitry Andric def XSIEXPDP : XX1Form <60, 918, (outs vsrc:$XT), (ins g8rc:$RA, g8rc:$RB), 153906c3fb27SDimitry Andric "xsiexpdp $XT, $RA, $RB", IIC_VecFP, []>; 1540fe6060f1SDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1541fe6060f1SDimitry Andric let hasSideEffects = 1 in { 15425ffd83dbSDimitry Andric // vB NOTE: only vB.dword[0] is used, that's why we don't use 15435ffd83dbSDimitry Andric // X_VT5_VA5_VB5 form 154406c3fb27SDimitry Andric def XSIEXPQP : XForm_18<63, 868, (outs vrrc:$FRT), (ins vrrc:$FRA, vsfrc:$FRB), 154506c3fb27SDimitry Andric "xsiexpqp $FRT, $FRA, $FRB", IIC_VecFP, []>; 15465ffd83dbSDimitry Andric } 15475ffd83dbSDimitry Andric 15485ffd83dbSDimitry Andric // Extract Exponent/Significand DP/QP 15495ffd83dbSDimitry Andric def XSXEXPDP : XX2_RT5_XO5_XB6<60, 0, 347, "xsxexpdp", []>; 15505ffd83dbSDimitry Andric def XSXSIGDP : XX2_RT5_XO5_XB6<60, 1, 347, "xsxsigdp", []>; 15515ffd83dbSDimitry Andric 1552fe6060f1SDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1553fe6060f1SDimitry Andric let hasSideEffects = 1 in { 15545ffd83dbSDimitry Andric def XSXEXPQP : X_VT5_XO5_VB5 <63, 2, 804, "xsxexpqp", []>; 15555ffd83dbSDimitry Andric def XSXSIGQP : X_VT5_XO5_VB5 <63, 18, 804, "xsxsigqp", []>; 15565ffd83dbSDimitry Andric } 15575ffd83dbSDimitry Andric 15585ffd83dbSDimitry Andric // Vector Insert Word 15595ffd83dbSDimitry Andric // XB NOTE: Only XB.dword[1] is used, but we use vsrc on XB. 15605ffd83dbSDimitry Andric def XXINSERTW : 15615ffd83dbSDimitry Andric XX2_RD6_UIM5_RS6<60, 181, (outs vsrc:$XT), 156206c3fb27SDimitry Andric (ins vsrc:$XTi, vsrc:$XB, u4imm:$UIM5), 156306c3fb27SDimitry Andric "xxinsertw $XT, $XB, $UIM5", IIC_VecFP, 15645ffd83dbSDimitry Andric [(set v4i32:$XT, (PPCvecinsert v4i32:$XTi, v4i32:$XB, 156506c3fb27SDimitry Andric imm32SExt16:$UIM5))]>, 15665ffd83dbSDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; 15675ffd83dbSDimitry Andric 15685ffd83dbSDimitry Andric // Vector Extract Unsigned Word 15695ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 15705ffd83dbSDimitry Andric let hasSideEffects = 1 in 15715ffd83dbSDimitry Andric def XXEXTRACTUW : XX2_RD6_UIM5_RS6<60, 165, 157206c3fb27SDimitry Andric (outs vsfrc:$XT), (ins vsrc:$XB, u4imm:$UIM5), 157306c3fb27SDimitry Andric "xxextractuw $XT, $XB, $UIM5", IIC_VecFP, []>; 15745ffd83dbSDimitry Andric 15755ffd83dbSDimitry Andric // Vector Insert Exponent DP/SP 15765ffd83dbSDimitry Andric def XVIEXPDP : XX3_XT5_XA5_XB5<60, 248, "xviexpdp", vsrc, vsrc, vsrc, 15775ffd83dbSDimitry Andric IIC_VecFP, [(set v2f64: $XT,(int_ppc_vsx_xviexpdp v2i64:$XA, v2i64:$XB))]>; 15785ffd83dbSDimitry Andric def XVIEXPSP : XX3_XT5_XA5_XB5<60, 216, "xviexpsp", vsrc, vsrc, vsrc, 15795ffd83dbSDimitry Andric IIC_VecFP, [(set v4f32: $XT,(int_ppc_vsx_xviexpsp v4i32:$XA, v4i32:$XB))]>; 15805ffd83dbSDimitry Andric 15815ffd83dbSDimitry Andric // Vector Extract Exponent/Significand DP/SP 15825ffd83dbSDimitry Andric def XVXEXPDP : XX2_XT6_XO5_XB6<60, 0, 475, "xvxexpdp", vsrc, 15835ffd83dbSDimitry Andric [(set v2i64: $XT, 15845ffd83dbSDimitry Andric (int_ppc_vsx_xvxexpdp v2f64:$XB))]>; 15855ffd83dbSDimitry Andric def XVXEXPSP : XX2_XT6_XO5_XB6<60, 8, 475, "xvxexpsp", vsrc, 15865ffd83dbSDimitry Andric [(set v4i32: $XT, 15875ffd83dbSDimitry Andric (int_ppc_vsx_xvxexpsp v4f32:$XB))]>; 15885ffd83dbSDimitry Andric def XVXSIGDP : XX2_XT6_XO5_XB6<60, 1, 475, "xvxsigdp", vsrc, 15895ffd83dbSDimitry Andric [(set v2i64: $XT, 15905ffd83dbSDimitry Andric (int_ppc_vsx_xvxsigdp v2f64:$XB))]>; 15915ffd83dbSDimitry Andric def XVXSIGSP : XX2_XT6_XO5_XB6<60, 9, 475, "xvxsigsp", vsrc, 15925ffd83dbSDimitry Andric [(set v4i32: $XT, 15935ffd83dbSDimitry Andric (int_ppc_vsx_xvxsigsp v4f32:$XB))]>; 15945ffd83dbSDimitry Andric 15955ffd83dbSDimitry Andric // Test Data Class SP/DP/QP 15965ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 15975ffd83dbSDimitry Andric let hasSideEffects = 1 in { 15985ffd83dbSDimitry Andric def XSTSTDCSP : XX2_BF3_DCMX7_RS6<60, 298, 15995ffd83dbSDimitry Andric (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB), 16005ffd83dbSDimitry Andric "xststdcsp $BF, $XB, $DCMX", IIC_VecFP, []>; 16015ffd83dbSDimitry Andric def XSTSTDCDP : XX2_BF3_DCMX7_RS6<60, 362, 16025ffd83dbSDimitry Andric (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB), 16035ffd83dbSDimitry Andric "xststdcdp $BF, $XB, $DCMX", IIC_VecFP, []>; 16045ffd83dbSDimitry Andric def XSTSTDCQP : X_BF3_DCMX7_RS5 <63, 708, 160506c3fb27SDimitry Andric (outs crrc:$BF), (ins u7imm:$DCMX, vrrc:$VB), 160606c3fb27SDimitry Andric "xststdcqp $BF, $VB, $DCMX", IIC_VecFP, []>; 16075ffd83dbSDimitry Andric } 16085ffd83dbSDimitry Andric 16095ffd83dbSDimitry Andric // Vector Test Data Class SP/DP 16105ffd83dbSDimitry Andric def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5, 16115ffd83dbSDimitry Andric (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB), 16125ffd83dbSDimitry Andric "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP, 16135ffd83dbSDimitry Andric [(set v4i32: $XT, 16145ffd83dbSDimitry Andric (int_ppc_vsx_xvtstdcsp v4f32:$XB, timm:$DCMX))]>; 16155ffd83dbSDimitry Andric def XVTSTDCDP : XX2_RD6_DCMX7_RS6<60, 15, 5, 16165ffd83dbSDimitry Andric (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB), 16175ffd83dbSDimitry Andric "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP, 16185ffd83dbSDimitry Andric [(set v2i64: $XT, 16195ffd83dbSDimitry Andric (int_ppc_vsx_xvtstdcdp v2f64:$XB, timm:$DCMX))]>; 16205ffd83dbSDimitry Andric 16215ffd83dbSDimitry Andric // Maximum/Minimum Type-C/Type-J DP 1622e8d8bef9SDimitry Andric let mayRaiseFPException = 1 in { 16235ffd83dbSDimitry Andric def XSMAXCDP : XX3_XT5_XA5_XB5<60, 128, "xsmaxcdp", vsfrc, vsfrc, vsfrc, 16245ffd83dbSDimitry Andric IIC_VecFP, 16255ffd83dbSDimitry Andric [(set f64:$XT, (PPCxsmaxc f64:$XA, f64:$XB))]>; 16265ffd83dbSDimitry Andric def XSMINCDP : XX3_XT5_XA5_XB5<60, 136, "xsmincdp", vsfrc, vsfrc, vsfrc, 16275ffd83dbSDimitry Andric IIC_VecFP, 16285ffd83dbSDimitry Andric [(set f64:$XT, (PPCxsminc f64:$XA, f64:$XB))]>; 16295ffd83dbSDimitry Andric 16305ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 16315ffd83dbSDimitry Andric let hasSideEffects = 1 in { 16325ffd83dbSDimitry Andric def XSMAXJDP : XX3_XT5_XA5_XB5<60, 144, "xsmaxjdp", vsrc, vsfrc, vsfrc, 16335ffd83dbSDimitry Andric IIC_VecFP, []>; 16345ffd83dbSDimitry Andric def XSMINJDP : XX3_XT5_XA5_XB5<60, 152, "xsminjdp", vsrc, vsfrc, vsfrc, 16355ffd83dbSDimitry Andric IIC_VecFP, []>; 16365ffd83dbSDimitry Andric } 1637e8d8bef9SDimitry Andric } 16385ffd83dbSDimitry Andric 16395ffd83dbSDimitry Andric // Vector Byte-Reverse H/W/D/Q Word 16405ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 16415ffd83dbSDimitry Andric let hasSideEffects = 1 in 16425ffd83dbSDimitry Andric def XXBRH : XX2_XT6_XO5_XB6<60, 7, 475, "xxbrh", vsrc, []>; 16435ffd83dbSDimitry Andric def XXBRW : XX2_XT6_XO5_XB6<60, 15, 475, "xxbrw", vsrc, 16445ffd83dbSDimitry Andric [(set v4i32:$XT, (bswap v4i32:$XB))]>; 16455ffd83dbSDimitry Andric def XXBRD : XX2_XT6_XO5_XB6<60, 23, 475, "xxbrd", vsrc, 16465ffd83dbSDimitry Andric [(set v2i64:$XT, (bswap v2i64:$XB))]>; 16475ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 16485ffd83dbSDimitry Andric let hasSideEffects = 1 in 16495ffd83dbSDimitry Andric def XXBRQ : XX2_XT6_XO5_XB6<60, 31, 475, "xxbrq", vsrc, []>; 16505ffd83dbSDimitry Andric 16515ffd83dbSDimitry Andric // Vector Permute 1652bdd1243dSDimitry Andric def XXPERM : XX3Form<60, 26, (outs vsrc:$XT), 1653bdd1243dSDimitry Andric (ins vsrc:$XA, vsrc:$XTi, vsrc:$XB), 1654bdd1243dSDimitry Andric "xxperm $XT, $XA, $XB", IIC_VecPerm, []>, 1655bdd1243dSDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; 1656bdd1243dSDimitry Andric def XXPERMR : XX3Form<60, 58, (outs vsrc:$XT), 1657bdd1243dSDimitry Andric (ins vsrc:$XA, vsrc:$XTi, vsrc:$XB), 1658bdd1243dSDimitry Andric "xxpermr $XT, $XA, $XB", IIC_VecPerm, []>, 1659bdd1243dSDimitry Andric RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; 16605ffd83dbSDimitry Andric 16615ffd83dbSDimitry Andric // Vector Splat Immediate Byte 16625ffd83dbSDimitry Andric // FIXME: Setting the hasSideEffects flag here to match current behaviour. 16635ffd83dbSDimitry Andric let hasSideEffects = 1 in 16645ffd83dbSDimitry Andric def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8), 16655ffd83dbSDimitry Andric "xxspltib $XT, $IMM8", IIC_VecPerm, []>; 16665ffd83dbSDimitry Andric 16675ffd83dbSDimitry Andric // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in 16685ffd83dbSDimitry Andric // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging. 16695ffd83dbSDimitry Andric let mayLoad = 1, mayStore = 0 in { 16705ffd83dbSDimitry Andric // Load Vector 167106c3fb27SDimitry Andric def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins (memrix16 $DQ, $RA):$addr), 167206c3fb27SDimitry Andric "lxv $XT, $addr", IIC_LdStLFD, []>; 16735ffd83dbSDimitry Andric // Load DWord 167406c3fb27SDimitry Andric def LXSD : DSForm_1<57, 2, (outs vfrc:$RST), (ins (memrix $D, $RA):$addr), 167506c3fb27SDimitry Andric "lxsd $RST, $addr", IIC_LdStLFD, []>; 16765ffd83dbSDimitry Andric // Load SP from src, convert it to DP, and place in dword[0] 167706c3fb27SDimitry Andric def LXSSP : DSForm_1<57, 3, (outs vfrc:$RST), (ins (memrix $D, $RA):$addr), 167806c3fb27SDimitry Andric "lxssp $RST, $addr", IIC_LdStLFD, []>; 16795ffd83dbSDimitry Andric 16805ffd83dbSDimitry Andric // Load as Integer Byte/Halfword & Zero Indexed 16815ffd83dbSDimitry Andric def LXSIBZX : X_XT6_RA5_RB5<31, 781, "lxsibzx", vsfrc, 168206c3fb27SDimitry Andric [(set f64:$XT, (PPClxsizx ForceXForm:$addr, 1))]>; 16835ffd83dbSDimitry Andric def LXSIHZX : X_XT6_RA5_RB5<31, 813, "lxsihzx", vsfrc, 168406c3fb27SDimitry Andric [(set f64:$XT, (PPClxsizx ForceXForm:$addr, 2))]>; 16855ffd83dbSDimitry Andric 16865ffd83dbSDimitry Andric // Load Vector Halfword*8/Byte*16 Indexed 16875ffd83dbSDimitry Andric def LXVH8X : X_XT6_RA5_RB5<31, 812, "lxvh8x" , vsrc, []>; 16885ffd83dbSDimitry Andric def LXVB16X : X_XT6_RA5_RB5<31, 876, "lxvb16x", vsrc, []>; 16895ffd83dbSDimitry Andric 16905ffd83dbSDimitry Andric // Load Vector Indexed 16915ffd83dbSDimitry Andric def LXVX : X_XT6_RA5_RB5<31, 268, "lxvx" , vsrc, 169206c3fb27SDimitry Andric [(set v2f64:$XT, (load XForm:$addr))]>; 16935ffd83dbSDimitry Andric // Load Vector (Left-justified) with Length 169406c3fb27SDimitry Andric def LXVL : XX1Form_memOp<31, 269, (outs vsrc:$XT), (ins (memr $RA):$addr, g8rc:$RB), 169506c3fb27SDimitry Andric "lxvl $XT, $addr, $RB", IIC_LdStLoad, 169606c3fb27SDimitry Andric [(set v4i32:$XT, (int_ppc_vsx_lxvl addr:$addr, i64:$RB))]>; 169706c3fb27SDimitry Andric def LXVLL : XX1Form_memOp<31,301, (outs vsrc:$XT), (ins (memr $RA):$addr, g8rc:$RB), 169806c3fb27SDimitry Andric "lxvll $XT, $addr, $RB", IIC_LdStLoad, 169906c3fb27SDimitry Andric [(set v4i32:$XT, (int_ppc_vsx_lxvll addr:$addr, i64:$RB))]>; 17005ffd83dbSDimitry Andric 17015ffd83dbSDimitry Andric // Load Vector Word & Splat Indexed 17025ffd83dbSDimitry Andric def LXVWSX : X_XT6_RA5_RB5<31, 364, "lxvwsx" , vsrc, []>; 17035ffd83dbSDimitry Andric } // mayLoad 17045ffd83dbSDimitry Andric 17055ffd83dbSDimitry Andric // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in 17065ffd83dbSDimitry Andric // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging. 17075ffd83dbSDimitry Andric let mayStore = 1, mayLoad = 0 in { 17085ffd83dbSDimitry Andric // Store Vector 170906c3fb27SDimitry Andric def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, (memrix16 $DQ, $RA):$addr), 171006c3fb27SDimitry Andric "stxv $XT, $addr", IIC_LdStSTFD, []>; 17115ffd83dbSDimitry Andric // Store DWord 171206c3fb27SDimitry Andric def STXSD : DSForm_1<61, 2, (outs), (ins vfrc:$RST, (memrix $D, $RA):$addr), 171306c3fb27SDimitry Andric "stxsd $RST, $addr", IIC_LdStSTFD, []>; 17145ffd83dbSDimitry Andric // Convert DP of dword[0] to SP, and Store to dst 171506c3fb27SDimitry Andric def STXSSP : DSForm_1<61, 3, (outs), (ins vfrc:$RST, (memrix $D, $RA):$addr), 171606c3fb27SDimitry Andric "stxssp $RST, $addr", IIC_LdStSTFD, []>; 17175ffd83dbSDimitry Andric 17185ffd83dbSDimitry Andric // Store as Integer Byte/Halfword Indexed 17195ffd83dbSDimitry Andric def STXSIBX : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsfrc, 172006c3fb27SDimitry Andric [(PPCstxsix f64:$XT, ForceXForm:$addr, 1)]>; 17215ffd83dbSDimitry Andric def STXSIHX : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsfrc, 172206c3fb27SDimitry Andric [(PPCstxsix f64:$XT, ForceXForm:$addr, 2)]>; 17235ffd83dbSDimitry Andric let isCodeGenOnly = 1 in { 17245ffd83dbSDimitry Andric def STXSIBXv : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsrc, []>; 17255ffd83dbSDimitry Andric def STXSIHXv : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsrc, []>; 17265ffd83dbSDimitry Andric } 17275ffd83dbSDimitry Andric 17285ffd83dbSDimitry Andric // Store Vector Halfword*8/Byte*16 Indexed 17295ffd83dbSDimitry Andric def STXVH8X : X_XS6_RA5_RB5<31, 940, "stxvh8x" , vsrc, []>; 17305ffd83dbSDimitry Andric def STXVB16X : X_XS6_RA5_RB5<31, 1004, "stxvb16x", vsrc, []>; 17315ffd83dbSDimitry Andric 17325ffd83dbSDimitry Andric // Store Vector Indexed 17335ffd83dbSDimitry Andric def STXVX : X_XS6_RA5_RB5<31, 396, "stxvx" , vsrc, 173406c3fb27SDimitry Andric [(store v2f64:$XT, XForm:$addr)]>; 17355ffd83dbSDimitry Andric 17365ffd83dbSDimitry Andric // Store Vector (Left-justified) with Length 17375ffd83dbSDimitry Andric def STXVL : XX1Form_memOp<31, 397, (outs), 173806c3fb27SDimitry Andric (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB), 173906c3fb27SDimitry Andric "stxvl $XT, $addr, $RB", IIC_LdStLoad, 174006c3fb27SDimitry Andric [(int_ppc_vsx_stxvl v4i32:$XT, addr:$addr, 174106c3fb27SDimitry Andric i64:$RB)]>; 17425ffd83dbSDimitry Andric def STXVLL : XX1Form_memOp<31, 429, (outs), 174306c3fb27SDimitry Andric (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB), 174406c3fb27SDimitry Andric "stxvll $XT, $addr, $RB", IIC_LdStLoad, 174506c3fb27SDimitry Andric [(int_ppc_vsx_stxvll v4i32:$XT, addr:$addr, 174606c3fb27SDimitry Andric i64:$RB)]>; 17475ffd83dbSDimitry Andric } // mayStore 17485ffd83dbSDimitry Andric 17495ffd83dbSDimitry Andric def DFLOADf32 : PPCPostRAExpPseudo<(outs vssrc:$XT), (ins memrix:$src), 17505ffd83dbSDimitry Andric "#DFLOADf32", 1751fe6060f1SDimitry Andric [(set f32:$XT, (load DSForm:$src))]>; 17525ffd83dbSDimitry Andric def DFLOADf64 : PPCPostRAExpPseudo<(outs vsfrc:$XT), (ins memrix:$src), 17535ffd83dbSDimitry Andric "#DFLOADf64", 1754fe6060f1SDimitry Andric [(set f64:$XT, (load DSForm:$src))]>; 17555ffd83dbSDimitry Andric def DFSTOREf32 : PPCPostRAExpPseudo<(outs), (ins vssrc:$XT, memrix:$dst), 17565ffd83dbSDimitry Andric "#DFSTOREf32", 1757fe6060f1SDimitry Andric [(store f32:$XT, DSForm:$dst)]>; 17585ffd83dbSDimitry Andric def DFSTOREf64 : PPCPostRAExpPseudo<(outs), (ins vsfrc:$XT, memrix:$dst), 17595ffd83dbSDimitry Andric "#DFSTOREf64", 1760fe6060f1SDimitry Andric [(store f64:$XT, DSForm:$dst)]>; 17615ffd83dbSDimitry Andric 17625ffd83dbSDimitry Andric let mayStore = 1 in { 17635ffd83dbSDimitry Andric def SPILLTOVSR_STX : PseudoXFormMemOp<(outs), 17645ffd83dbSDimitry Andric (ins spilltovsrrc:$XT, memrr:$dst), 17655ffd83dbSDimitry Andric "#SPILLTOVSR_STX", []>; 17665ffd83dbSDimitry Andric def SPILLTOVSR_ST : PPCPostRAExpPseudo<(outs), (ins spilltovsrrc:$XT, memrix:$dst), 17675ffd83dbSDimitry Andric "#SPILLTOVSR_ST", []>; 17685ffd83dbSDimitry Andric } 17695ffd83dbSDimitry Andric let mayLoad = 1 in { 17705ffd83dbSDimitry Andric def SPILLTOVSR_LDX : PseudoXFormMemOp<(outs spilltovsrrc:$XT), 17715ffd83dbSDimitry Andric (ins memrr:$src), 17725ffd83dbSDimitry Andric "#SPILLTOVSR_LDX", []>; 17735ffd83dbSDimitry Andric def SPILLTOVSR_LD : PPCPostRAExpPseudo<(outs spilltovsrrc:$XT), (ins memrix:$src), 17745ffd83dbSDimitry Andric "#SPILLTOVSR_LD", []>; 17755ffd83dbSDimitry Andric 17765ffd83dbSDimitry Andric } 17775ffd83dbSDimitry Andric } // HasP9Vector 17785ffd83dbSDimitry Andric} // hasSideEffects = 0 17795ffd83dbSDimitry Andric 17805ffd83dbSDimitry Andriclet PPC970_Single = 1, AddedComplexity = 400 in { 17810b57cec5SDimitry Andric 17820b57cec5SDimitry Andric def SELECT_CC_VSRC: PPCCustomInserterPseudo<(outs vsrc:$dst), 17830b57cec5SDimitry Andric (ins crrc:$cond, vsrc:$T, vsrc:$F, i32imm:$BROPC), 17840b57cec5SDimitry Andric "#SELECT_CC_VSRC", 17850b57cec5SDimitry Andric []>; 17860b57cec5SDimitry Andric def SELECT_VSRC: PPCCustomInserterPseudo<(outs vsrc:$dst), 17870b57cec5SDimitry Andric (ins crbitrc:$cond, vsrc:$T, vsrc:$F), 17880b57cec5SDimitry Andric "#SELECT_VSRC", 17890b57cec5SDimitry Andric [(set v2f64:$dst, 17900b57cec5SDimitry Andric (select i1:$cond, v2f64:$T, v2f64:$F))]>; 17910b57cec5SDimitry Andric def SELECT_CC_VSFRC: PPCCustomInserterPseudo<(outs f8rc:$dst), 17920b57cec5SDimitry Andric (ins crrc:$cond, f8rc:$T, f8rc:$F, 17930b57cec5SDimitry Andric i32imm:$BROPC), "#SELECT_CC_VSFRC", 17940b57cec5SDimitry Andric []>; 17950b57cec5SDimitry Andric def SELECT_VSFRC: PPCCustomInserterPseudo<(outs f8rc:$dst), 17960b57cec5SDimitry Andric (ins crbitrc:$cond, f8rc:$T, f8rc:$F), 17970b57cec5SDimitry Andric "#SELECT_VSFRC", 17980b57cec5SDimitry Andric [(set f64:$dst, 17990b57cec5SDimitry Andric (select i1:$cond, f64:$T, f64:$F))]>; 18000b57cec5SDimitry Andric def SELECT_CC_VSSRC: PPCCustomInserterPseudo<(outs f4rc:$dst), 18010b57cec5SDimitry Andric (ins crrc:$cond, f4rc:$T, f4rc:$F, 18020b57cec5SDimitry Andric i32imm:$BROPC), "#SELECT_CC_VSSRC", 18030b57cec5SDimitry Andric []>; 18040b57cec5SDimitry Andric def SELECT_VSSRC: PPCCustomInserterPseudo<(outs f4rc:$dst), 18050b57cec5SDimitry Andric (ins crbitrc:$cond, f4rc:$T, f4rc:$F), 18060b57cec5SDimitry Andric "#SELECT_VSSRC", 18070b57cec5SDimitry Andric [(set f32:$dst, 18080b57cec5SDimitry Andric (select i1:$cond, f32:$T, f32:$F))]>; 18090b57cec5SDimitry Andric} 18100b57cec5SDimitry Andric} 18110b57cec5SDimitry Andric 18125ffd83dbSDimitry Andric//----------------------------- DAG Definitions ------------------------------// 1813fe6060f1SDimitry Andric 1814fe6060f1SDimitry Andric// Output dag used to bitcast f32 to i32 and f64 to i64 1815fe6060f1SDimitry Andricdef Bitcast { 1816fe6060f1SDimitry Andric dag FltToInt = (i32 (MFVSRWZ (EXTRACT_SUBREG (XSCVDPSPN $A), sub_64))); 1817fe6060f1SDimitry Andric dag DblToLong = (i64 (MFVSRD $A)); 1818fe6060f1SDimitry Andric} 1819fe6060f1SDimitry Andric 1820480093f4SDimitry Andricdef FpMinMax { 1821480093f4SDimitry Andric dag F32Min = (COPY_TO_REGCLASS (XSMINDP (COPY_TO_REGCLASS $A, VSFRC), 1822480093f4SDimitry Andric (COPY_TO_REGCLASS $B, VSFRC)), 1823480093f4SDimitry Andric VSSRC); 1824480093f4SDimitry Andric dag F32Max = (COPY_TO_REGCLASS (XSMAXDP (COPY_TO_REGCLASS $A, VSFRC), 1825480093f4SDimitry Andric (COPY_TO_REGCLASS $B, VSFRC)), 1826480093f4SDimitry Andric VSSRC); 1827480093f4SDimitry Andric} 1828480093f4SDimitry Andric 18290b57cec5SDimitry Andricdef ScalarLoads { 1830fe6060f1SDimitry Andric dag Li8 = (i32 (extloadi8 ForceXForm:$src)); 1831fe6060f1SDimitry Andric dag ZELi8 = (i32 (zextloadi8 ForceXForm:$src)); 1832fe6060f1SDimitry Andric dag ZELi8i64 = (i64 (zextloadi8 ForceXForm:$src)); 1833fe6060f1SDimitry Andric dag SELi8 = (i32 (sext_inreg (extloadi8 ForceXForm:$src), i8)); 1834fe6060f1SDimitry Andric dag SELi8i64 = (i64 (sext_inreg (extloadi8 ForceXForm:$src), i8)); 18350b57cec5SDimitry Andric 1836fe6060f1SDimitry Andric dag Li16 = (i32 (extloadi16 ForceXForm:$src)); 1837fe6060f1SDimitry Andric dag ZELi16 = (i32 (zextloadi16 ForceXForm:$src)); 1838fe6060f1SDimitry Andric dag ZELi16i64 = (i64 (zextloadi16 ForceXForm:$src)); 1839fe6060f1SDimitry Andric dag SELi16 = (i32 (sextloadi16 ForceXForm:$src)); 1840fe6060f1SDimitry Andric dag SELi16i64 = (i64 (sextloadi16 ForceXForm:$src)); 18410b57cec5SDimitry Andric 1842fe6060f1SDimitry Andric dag Li32 = (i32 (load ForceXForm:$src)); 18430b57cec5SDimitry Andric} 18440b57cec5SDimitry Andric 18450b57cec5SDimitry Andricdef DWToSPExtractConv { 18460b57cec5SDimitry Andric dag El0US1 = (f32 (PPCfcfidus 18470b57cec5SDimitry Andric (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 0)))))); 18480b57cec5SDimitry Andric dag El1US1 = (f32 (PPCfcfidus 18490b57cec5SDimitry Andric (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 1)))))); 18500b57cec5SDimitry Andric dag El0US2 = (f32 (PPCfcfidus 18510b57cec5SDimitry Andric (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 0)))))); 18520b57cec5SDimitry Andric dag El1US2 = (f32 (PPCfcfidus 18530b57cec5SDimitry Andric (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 1)))))); 18540b57cec5SDimitry Andric dag El0SS1 = (f32 (PPCfcfids 18550b57cec5SDimitry Andric (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 0)))))); 18560b57cec5SDimitry Andric dag El1SS1 = (f32 (PPCfcfids 18570b57cec5SDimitry Andric (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 1)))))); 18580b57cec5SDimitry Andric dag El0SS2 = (f32 (PPCfcfids 18590b57cec5SDimitry Andric (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 0)))))); 18600b57cec5SDimitry Andric dag El1SS2 = (f32 (PPCfcfids 18610b57cec5SDimitry Andric (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 1)))))); 18620b57cec5SDimitry Andric dag BVU = (v4f32 (build_vector El0US1, El1US1, El0US2, El1US2)); 18630b57cec5SDimitry Andric dag BVS = (v4f32 (build_vector El0SS1, El1SS1, El0SS2, El1SS2)); 18640b57cec5SDimitry Andric} 18650b57cec5SDimitry Andric 18665ffd83dbSDimitry Andricdef WToDPExtractConv { 18675ffd83dbSDimitry Andric dag El0S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 0)))); 18685ffd83dbSDimitry Andric dag El1S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 1)))); 18695ffd83dbSDimitry Andric dag El2S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 2)))); 18705ffd83dbSDimitry Andric dag El3S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 3)))); 18715ffd83dbSDimitry Andric dag El0U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 0)))); 18725ffd83dbSDimitry Andric dag El1U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 1)))); 18735ffd83dbSDimitry Andric dag El2U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 2)))); 18745ffd83dbSDimitry Andric dag El3U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 3)))); 18755ffd83dbSDimitry Andric dag BV02S = (v2f64 (build_vector El0S, El2S)); 18765ffd83dbSDimitry Andric dag BV13S = (v2f64 (build_vector El1S, El3S)); 18775ffd83dbSDimitry Andric dag BV02U = (v2f64 (build_vector El0U, El2U)); 18785ffd83dbSDimitry Andric dag BV13U = (v2f64 (build_vector El1U, El3U)); 18798bcb0991SDimitry Andric} 18808bcb0991SDimitry Andric 18810b57cec5SDimitry Andric/* Direct moves of various widths from GPR's into VSR's. Each move lines 18820b57cec5SDimitry Andric the value up into element 0 (both BE and LE). Namely, entities smaller than 18830b57cec5SDimitry Andric a doubleword are shifted left and moved for BE. For LE, they're moved, then 18840b57cec5SDimitry Andric swapped to go into the least significant element of the VSR. 18850b57cec5SDimitry Andric*/ 18860b57cec5SDimitry Andricdef MovesToVSR { 18870b57cec5SDimitry Andric dag BE_BYTE_0 = 18880b57cec5SDimitry Andric (MTVSRD 18890b57cec5SDimitry Andric (RLDICR 18900b57cec5SDimitry Andric (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 56, 7)); 18910b57cec5SDimitry Andric dag BE_HALF_0 = 18920b57cec5SDimitry Andric (MTVSRD 18930b57cec5SDimitry Andric (RLDICR 18940b57cec5SDimitry Andric (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 48, 15)); 18950b57cec5SDimitry Andric dag BE_WORD_0 = 18960b57cec5SDimitry Andric (MTVSRD 18970b57cec5SDimitry Andric (RLDICR 18980b57cec5SDimitry Andric (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 32, 31)); 18990b57cec5SDimitry Andric dag BE_DWORD_0 = (MTVSRD $A); 19000b57cec5SDimitry Andric 19010b57cec5SDimitry Andric dag LE_MTVSRW = (MTVSRD (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32)); 19020b57cec5SDimitry Andric dag LE_WORD_1 = (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), 19030b57cec5SDimitry Andric LE_MTVSRW, sub_64)); 19040b57cec5SDimitry Andric dag LE_WORD_0 = (XXPERMDI LE_WORD_1, LE_WORD_1, 2); 19050b57cec5SDimitry Andric dag LE_DWORD_1 = (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), 19060b57cec5SDimitry Andric BE_DWORD_0, sub_64)); 19070b57cec5SDimitry Andric dag LE_DWORD_0 = (XXPERMDI LE_DWORD_1, LE_DWORD_1, 2); 19080b57cec5SDimitry Andric} 19090b57cec5SDimitry Andric 19100b57cec5SDimitry Andric/* Patterns for extracting elements out of vectors. Integer elements are 19110b57cec5SDimitry Andric extracted using direct move operations. Patterns for extracting elements 19120b57cec5SDimitry Andric whose indices are not available at compile time are also provided with 19130b57cec5SDimitry Andric various _VARIABLE_ patterns. 19140b57cec5SDimitry Andric The numbering for the DAG's is for LE, but when used on BE, the correct 19150b57cec5SDimitry Andric LE element can just be used (i.e. LE_BYTE_2 == BE_BYTE_13). 19160b57cec5SDimitry Andric*/ 19170b57cec5SDimitry Andricdef VectorExtractions { 19180b57cec5SDimitry Andric // Doubleword extraction 19190b57cec5SDimitry Andric dag LE_DWORD_0 = 19200b57cec5SDimitry Andric (MFVSRD 19210b57cec5SDimitry Andric (EXTRACT_SUBREG 19220b57cec5SDimitry Andric (XXPERMDI (COPY_TO_REGCLASS $S, VSRC), 19230b57cec5SDimitry Andric (COPY_TO_REGCLASS $S, VSRC), 2), sub_64)); 19240b57cec5SDimitry Andric dag LE_DWORD_1 = (MFVSRD 19250b57cec5SDimitry Andric (EXTRACT_SUBREG 19260b57cec5SDimitry Andric (v2i64 (COPY_TO_REGCLASS $S, VSRC)), sub_64)); 19270b57cec5SDimitry Andric 19280b57cec5SDimitry Andric // Word extraction 19290b57cec5SDimitry Andric dag LE_WORD_0 = (MFVSRWZ (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64)); 19300b57cec5SDimitry Andric dag LE_WORD_1 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 1), sub_64)); 19310b57cec5SDimitry Andric dag LE_WORD_2 = (MFVSRWZ (EXTRACT_SUBREG 19320b57cec5SDimitry Andric (v2i64 (COPY_TO_REGCLASS $S, VSRC)), sub_64)); 19330b57cec5SDimitry Andric dag LE_WORD_3 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 3), sub_64)); 19340b57cec5SDimitry Andric 19350b57cec5SDimitry Andric // Halfword extraction 19360b57cec5SDimitry Andric dag LE_HALF_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 48), sub_32)); 19370b57cec5SDimitry Andric dag LE_HALF_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 48, 48), sub_32)); 19380b57cec5SDimitry Andric dag LE_HALF_2 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 32, 48), sub_32)); 19390b57cec5SDimitry Andric dag LE_HALF_3 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 16, 48), sub_32)); 19400b57cec5SDimitry Andric dag LE_HALF_4 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 0, 48), sub_32)); 19410b57cec5SDimitry Andric dag LE_HALF_5 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 48, 48), sub_32)); 19420b57cec5SDimitry Andric dag LE_HALF_6 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 32, 48), sub_32)); 19430b57cec5SDimitry Andric dag LE_HALF_7 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 16, 48), sub_32)); 19440b57cec5SDimitry Andric 19450b57cec5SDimitry Andric // Byte extraction 19460b57cec5SDimitry Andric dag LE_BYTE_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 56), sub_32)); 19470b57cec5SDimitry Andric dag LE_BYTE_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 56, 56), sub_32)); 19480b57cec5SDimitry Andric dag LE_BYTE_2 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 48, 56), sub_32)); 19490b57cec5SDimitry Andric dag LE_BYTE_3 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 40, 56), sub_32)); 19500b57cec5SDimitry Andric dag LE_BYTE_4 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 32, 56), sub_32)); 19510b57cec5SDimitry Andric dag LE_BYTE_5 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 24, 56), sub_32)); 19520b57cec5SDimitry Andric dag LE_BYTE_6 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 16, 56), sub_32)); 19530b57cec5SDimitry Andric dag LE_BYTE_7 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 8, 56), sub_32)); 19540b57cec5SDimitry Andric dag LE_BYTE_8 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 0, 56), sub_32)); 19550b57cec5SDimitry Andric dag LE_BYTE_9 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 56, 56), sub_32)); 19560b57cec5SDimitry Andric dag LE_BYTE_10 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 48, 56), sub_32)); 19570b57cec5SDimitry Andric dag LE_BYTE_11 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 40, 56), sub_32)); 19580b57cec5SDimitry Andric dag LE_BYTE_12 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 32, 56), sub_32)); 19590b57cec5SDimitry Andric dag LE_BYTE_13 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 24, 56), sub_32)); 19600b57cec5SDimitry Andric dag LE_BYTE_14 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 16, 56), sub_32)); 19610b57cec5SDimitry Andric dag LE_BYTE_15 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 8, 56), sub_32)); 19620b57cec5SDimitry Andric 19630b57cec5SDimitry Andric /* Variable element number (BE and LE patterns must be specified separately) 19640b57cec5SDimitry Andric This is a rather involved process. 19650b57cec5SDimitry Andric 19660b57cec5SDimitry Andric Conceptually, this is how the move is accomplished: 19670b57cec5SDimitry Andric 1. Identify which doubleword contains the element 19680b57cec5SDimitry Andric 2. Shift in the VMX register so that the correct doubleword is correctly 19690b57cec5SDimitry Andric lined up for the MFVSRD 19700b57cec5SDimitry Andric 3. Perform the move so that the element (along with some extra stuff) 19710b57cec5SDimitry Andric is in the GPR 19720b57cec5SDimitry Andric 4. Right shift within the GPR so that the element is right-justified 19730b57cec5SDimitry Andric 19740b57cec5SDimitry Andric Of course, the index is an element number which has a different meaning 19750b57cec5SDimitry Andric on LE/BE so the patterns have to be specified separately. 19760b57cec5SDimitry Andric 19770b57cec5SDimitry Andric Note: The final result will be the element right-justified with high 19780b57cec5SDimitry Andric order bits being arbitrarily defined (namely, whatever was in the 19790b57cec5SDimitry Andric vector register to the left of the value originally). 19800b57cec5SDimitry Andric */ 19810b57cec5SDimitry Andric 19820b57cec5SDimitry Andric /* LE variable byte 19830b57cec5SDimitry Andric Number 1. above: 19840b57cec5SDimitry Andric - For elements 0-7, we shift left by 8 bytes since they're on the right 19850b57cec5SDimitry Andric - For elements 8-15, we need not shift (shift left by zero bytes) 19860b57cec5SDimitry Andric This is accomplished by inverting the bits of the index and AND-ing 19870b57cec5SDimitry Andric with 0x8 (i.e. clearing all bits of the index and inverting bit 60). 19880b57cec5SDimitry Andric */ 19890b57cec5SDimitry Andric dag LE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDC8 (LI8 8), $Idx))); 19900b57cec5SDimitry Andric 19910b57cec5SDimitry Andric // Number 2. above: 19920b57cec5SDimitry Andric // - Now that we set up the shift amount, we shift in the VMX register 19930b57cec5SDimitry Andric dag LE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, LE_VBYTE_PERM_VEC)); 19940b57cec5SDimitry Andric 19950b57cec5SDimitry Andric // Number 3. above: 19960b57cec5SDimitry Andric // - The doubleword containing our element is moved to a GPR 19970b57cec5SDimitry Andric dag LE_MV_VBYTE = (MFVSRD 19980b57cec5SDimitry Andric (EXTRACT_SUBREG 19990b57cec5SDimitry Andric (v2i64 (COPY_TO_REGCLASS LE_VBYTE_PERMUTE, VSRC)), 20000b57cec5SDimitry Andric sub_64)); 20010b57cec5SDimitry Andric 20020b57cec5SDimitry Andric /* Number 4. above: 20030b57cec5SDimitry Andric - Truncate the element number to the range 0-7 (8-15 are symmetrical 20040b57cec5SDimitry Andric and out of range values are truncated accordingly) 20050b57cec5SDimitry Andric - Multiply by 8 as we need to shift right by the number of bits, not bytes 20060b57cec5SDimitry Andric - Shift right in the GPR by the calculated value 20070b57cec5SDimitry Andric */ 20080b57cec5SDimitry Andric dag LE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 7), $Idx), 3, 60), 20090b57cec5SDimitry Andric sub_32); 20100b57cec5SDimitry Andric dag LE_VARIABLE_BYTE = (EXTRACT_SUBREG (SRD LE_MV_VBYTE, LE_VBYTE_SHIFT), 20110b57cec5SDimitry Andric sub_32); 20120b57cec5SDimitry Andric 20130b57cec5SDimitry Andric /* LE variable halfword 20140b57cec5SDimitry Andric Number 1. above: 20150b57cec5SDimitry Andric - For elements 0-3, we shift left by 8 since they're on the right 20160b57cec5SDimitry Andric - For elements 4-7, we need not shift (shift left by zero bytes) 20170b57cec5SDimitry Andric Similarly to the byte pattern, we invert the bits of the index, but we 20180b57cec5SDimitry Andric AND with 0x4 (i.e. clear all bits of the index and invert bit 61). 20190b57cec5SDimitry Andric Of course, the shift is still by 8 bytes, so we must multiply by 2. 20200b57cec5SDimitry Andric */ 20210b57cec5SDimitry Andric dag LE_VHALF_PERM_VEC = 20220b57cec5SDimitry Andric (v16i8 (LVSL ZERO8, (RLDICR (ANDC8 (LI8 4), $Idx), 1, 62))); 20230b57cec5SDimitry Andric 20240b57cec5SDimitry Andric // Number 2. above: 20250b57cec5SDimitry Andric // - Now that we set up the shift amount, we shift in the VMX register 20260b57cec5SDimitry Andric dag LE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, LE_VHALF_PERM_VEC)); 20270b57cec5SDimitry Andric 20280b57cec5SDimitry Andric // Number 3. above: 20290b57cec5SDimitry Andric // - The doubleword containing our element is moved to a GPR 20300b57cec5SDimitry Andric dag LE_MV_VHALF = (MFVSRD 20310b57cec5SDimitry Andric (EXTRACT_SUBREG 20320b57cec5SDimitry Andric (v2i64 (COPY_TO_REGCLASS LE_VHALF_PERMUTE, VSRC)), 20330b57cec5SDimitry Andric sub_64)); 20340b57cec5SDimitry Andric 20350b57cec5SDimitry Andric /* Number 4. above: 20360b57cec5SDimitry Andric - Truncate the element number to the range 0-3 (4-7 are symmetrical 20370b57cec5SDimitry Andric and out of range values are truncated accordingly) 20380b57cec5SDimitry Andric - Multiply by 16 as we need to shift right by the number of bits 20390b57cec5SDimitry Andric - Shift right in the GPR by the calculated value 20400b57cec5SDimitry Andric */ 20410b57cec5SDimitry Andric dag LE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 3), $Idx), 4, 59), 20420b57cec5SDimitry Andric sub_32); 20430b57cec5SDimitry Andric dag LE_VARIABLE_HALF = (EXTRACT_SUBREG (SRD LE_MV_VHALF, LE_VHALF_SHIFT), 20440b57cec5SDimitry Andric sub_32); 20450b57cec5SDimitry Andric 20460b57cec5SDimitry Andric /* LE variable word 20470b57cec5SDimitry Andric Number 1. above: 20480b57cec5SDimitry Andric - For elements 0-1, we shift left by 8 since they're on the right 20490b57cec5SDimitry Andric - For elements 2-3, we need not shift 20500b57cec5SDimitry Andric */ 20510b57cec5SDimitry Andric dag LE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8, 20520b57cec5SDimitry Andric (RLDICR (ANDC8 (LI8 2), $Idx), 2, 61))); 20530b57cec5SDimitry Andric 20540b57cec5SDimitry Andric // Number 2. above: 20550b57cec5SDimitry Andric // - Now that we set up the shift amount, we shift in the VMX register 20560b57cec5SDimitry Andric dag LE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, LE_VWORD_PERM_VEC)); 20570b57cec5SDimitry Andric 20580b57cec5SDimitry Andric // Number 3. above: 20590b57cec5SDimitry Andric // - The doubleword containing our element is moved to a GPR 20600b57cec5SDimitry Andric dag LE_MV_VWORD = (MFVSRD 20610b57cec5SDimitry Andric (EXTRACT_SUBREG 20620b57cec5SDimitry Andric (v2i64 (COPY_TO_REGCLASS LE_VWORD_PERMUTE, VSRC)), 20630b57cec5SDimitry Andric sub_64)); 20640b57cec5SDimitry Andric 20650b57cec5SDimitry Andric /* Number 4. above: 20660b57cec5SDimitry Andric - Truncate the element number to the range 0-1 (2-3 are symmetrical 20670b57cec5SDimitry Andric and out of range values are truncated accordingly) 20680b57cec5SDimitry Andric - Multiply by 32 as we need to shift right by the number of bits 20690b57cec5SDimitry Andric - Shift right in the GPR by the calculated value 20700b57cec5SDimitry Andric */ 20710b57cec5SDimitry Andric dag LE_VWORD_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 1), $Idx), 5, 58), 20720b57cec5SDimitry Andric sub_32); 20730b57cec5SDimitry Andric dag LE_VARIABLE_WORD = (EXTRACT_SUBREG (SRD LE_MV_VWORD, LE_VWORD_SHIFT), 20740b57cec5SDimitry Andric sub_32); 20750b57cec5SDimitry Andric 20760b57cec5SDimitry Andric /* LE variable doubleword 20770b57cec5SDimitry Andric Number 1. above: 20780b57cec5SDimitry Andric - For element 0, we shift left by 8 since it's on the right 20790b57cec5SDimitry Andric - For element 1, we need not shift 20800b57cec5SDimitry Andric */ 20810b57cec5SDimitry Andric dag LE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8, 20820b57cec5SDimitry Andric (RLDICR (ANDC8 (LI8 1), $Idx), 3, 60))); 20830b57cec5SDimitry Andric 20840b57cec5SDimitry Andric // Number 2. above: 20850b57cec5SDimitry Andric // - Now that we set up the shift amount, we shift in the VMX register 20860b57cec5SDimitry Andric dag LE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, LE_VDWORD_PERM_VEC)); 20870b57cec5SDimitry Andric 20880b57cec5SDimitry Andric // Number 3. above: 20890b57cec5SDimitry Andric // - The doubleword containing our element is moved to a GPR 20900b57cec5SDimitry Andric // - Number 4. is not needed for the doubleword as the value is 64-bits 20910b57cec5SDimitry Andric dag LE_VARIABLE_DWORD = 20920b57cec5SDimitry Andric (MFVSRD (EXTRACT_SUBREG 20930b57cec5SDimitry Andric (v2i64 (COPY_TO_REGCLASS LE_VDWORD_PERMUTE, VSRC)), 20940b57cec5SDimitry Andric sub_64)); 20950b57cec5SDimitry Andric 20960b57cec5SDimitry Andric /* LE variable float 20970b57cec5SDimitry Andric - Shift the vector to line up the desired element to BE Word 0 20980b57cec5SDimitry Andric - Convert 32-bit float to a 64-bit single precision float 20990b57cec5SDimitry Andric */ 21000b57cec5SDimitry Andric dag LE_VFLOAT_PERM_VEC = (v16i8 (LVSL ZERO8, 21010b57cec5SDimitry Andric (RLDICR (XOR8 (LI8 3), $Idx), 2, 61))); 21020b57cec5SDimitry Andric dag LE_VFLOAT_PERMUTE = (VPERM $S, $S, LE_VFLOAT_PERM_VEC); 21030b57cec5SDimitry Andric dag LE_VARIABLE_FLOAT = (XSCVSPDPN LE_VFLOAT_PERMUTE); 21040b57cec5SDimitry Andric 21050b57cec5SDimitry Andric /* LE variable double 21060b57cec5SDimitry Andric Same as the LE doubleword except there is no move. 21070b57cec5SDimitry Andric */ 21080b57cec5SDimitry Andric dag LE_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)), 21090b57cec5SDimitry Andric (v16i8 (COPY_TO_REGCLASS $S, VRRC)), 21100b57cec5SDimitry Andric LE_VDWORD_PERM_VEC)); 21110b57cec5SDimitry Andric dag LE_VARIABLE_DOUBLE = (COPY_TO_REGCLASS LE_VDOUBLE_PERMUTE, VSRC); 21120b57cec5SDimitry Andric 21130b57cec5SDimitry Andric /* BE variable byte 21140b57cec5SDimitry Andric The algorithm here is the same as the LE variable byte except: 21150b57cec5SDimitry Andric - The shift in the VMX register is by 0/8 for opposite element numbers so 21160b57cec5SDimitry Andric we simply AND the element number with 0x8 21170b57cec5SDimitry Andric - The order of elements after the move to GPR is reversed, so we invert 21180b57cec5SDimitry Andric the bits of the index prior to truncating to the range 0-7 21190b57cec5SDimitry Andric */ 2120480093f4SDimitry Andric dag BE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDI8_rec $Idx, 8))); 21210b57cec5SDimitry Andric dag BE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, BE_VBYTE_PERM_VEC)); 21220b57cec5SDimitry Andric dag BE_MV_VBYTE = (MFVSRD 21230b57cec5SDimitry Andric (EXTRACT_SUBREG 21240b57cec5SDimitry Andric (v2i64 (COPY_TO_REGCLASS BE_VBYTE_PERMUTE, VSRC)), 21250b57cec5SDimitry Andric sub_64)); 21260b57cec5SDimitry Andric dag BE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 7), $Idx), 3, 60), 21270b57cec5SDimitry Andric sub_32); 21280b57cec5SDimitry Andric dag BE_VARIABLE_BYTE = (EXTRACT_SUBREG (SRD BE_MV_VBYTE, BE_VBYTE_SHIFT), 21290b57cec5SDimitry Andric sub_32); 21300b57cec5SDimitry Andric 21310b57cec5SDimitry Andric /* BE variable halfword 21320b57cec5SDimitry Andric The algorithm here is the same as the LE variable halfword except: 21330b57cec5SDimitry Andric - The shift in the VMX register is by 0/8 for opposite element numbers so 21340b57cec5SDimitry Andric we simply AND the element number with 0x4 and multiply by 2 21350b57cec5SDimitry Andric - The order of elements after the move to GPR is reversed, so we invert 21360b57cec5SDimitry Andric the bits of the index prior to truncating to the range 0-3 21370b57cec5SDimitry Andric */ 21380b57cec5SDimitry Andric dag BE_VHALF_PERM_VEC = (v16i8 (LVSL ZERO8, 2139480093f4SDimitry Andric (RLDICR (ANDI8_rec $Idx, 4), 1, 62))); 21400b57cec5SDimitry Andric dag BE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, BE_VHALF_PERM_VEC)); 21410b57cec5SDimitry Andric dag BE_MV_VHALF = (MFVSRD 21420b57cec5SDimitry Andric (EXTRACT_SUBREG 21430b57cec5SDimitry Andric (v2i64 (COPY_TO_REGCLASS BE_VHALF_PERMUTE, VSRC)), 21440b57cec5SDimitry Andric sub_64)); 21450b57cec5SDimitry Andric dag BE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 3), $Idx), 4, 59), 21460b57cec5SDimitry Andric sub_32); 21470b57cec5SDimitry Andric dag BE_VARIABLE_HALF = (EXTRACT_SUBREG (SRD BE_MV_VHALF, BE_VHALF_SHIFT), 21480b57cec5SDimitry Andric sub_32); 21490b57cec5SDimitry Andric 21500b57cec5SDimitry Andric /* BE variable word 21510b57cec5SDimitry Andric The algorithm is the same as the LE variable word except: 21520b57cec5SDimitry Andric - The shift in the VMX register happens for opposite element numbers 21530b57cec5SDimitry Andric - The order of elements after the move to GPR is reversed, so we invert 21540b57cec5SDimitry Andric the bits of the index prior to truncating to the range 0-1 21550b57cec5SDimitry Andric */ 21560b57cec5SDimitry Andric dag BE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8, 2157480093f4SDimitry Andric (RLDICR (ANDI8_rec $Idx, 2), 2, 61))); 21580b57cec5SDimitry Andric dag BE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VWORD_PERM_VEC)); 21590b57cec5SDimitry Andric dag BE_MV_VWORD = (MFVSRD 21600b57cec5SDimitry Andric (EXTRACT_SUBREG 21610b57cec5SDimitry Andric (v2i64 (COPY_TO_REGCLASS BE_VWORD_PERMUTE, VSRC)), 21620b57cec5SDimitry Andric sub_64)); 21630b57cec5SDimitry Andric dag BE_VWORD_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 1), $Idx), 5, 58), 21640b57cec5SDimitry Andric sub_32); 21650b57cec5SDimitry Andric dag BE_VARIABLE_WORD = (EXTRACT_SUBREG (SRD BE_MV_VWORD, BE_VWORD_SHIFT), 21660b57cec5SDimitry Andric sub_32); 21670b57cec5SDimitry Andric 21680b57cec5SDimitry Andric /* BE variable doubleword 21690b57cec5SDimitry Andric Same as the LE doubleword except we shift in the VMX register for opposite 21700b57cec5SDimitry Andric element indices. 21710b57cec5SDimitry Andric */ 21720b57cec5SDimitry Andric dag BE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8, 2173480093f4SDimitry Andric (RLDICR (ANDI8_rec $Idx, 1), 3, 60))); 21740b57cec5SDimitry Andric dag BE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VDWORD_PERM_VEC)); 21750b57cec5SDimitry Andric dag BE_VARIABLE_DWORD = 21760b57cec5SDimitry Andric (MFVSRD (EXTRACT_SUBREG 21770b57cec5SDimitry Andric (v2i64 (COPY_TO_REGCLASS BE_VDWORD_PERMUTE, VSRC)), 21780b57cec5SDimitry Andric sub_64)); 21790b57cec5SDimitry Andric 21800b57cec5SDimitry Andric /* BE variable float 21810b57cec5SDimitry Andric - Shift the vector to line up the desired element to BE Word 0 21820b57cec5SDimitry Andric - Convert 32-bit float to a 64-bit single precision float 21830b57cec5SDimitry Andric */ 21840b57cec5SDimitry Andric dag BE_VFLOAT_PERM_VEC = (v16i8 (LVSL ZERO8, (RLDICR $Idx, 2, 61))); 21850b57cec5SDimitry Andric dag BE_VFLOAT_PERMUTE = (VPERM $S, $S, BE_VFLOAT_PERM_VEC); 21860b57cec5SDimitry Andric dag BE_VARIABLE_FLOAT = (XSCVSPDPN BE_VFLOAT_PERMUTE); 21870b57cec5SDimitry Andric 2188fe6060f1SDimitry Andric // BE variable float 32-bit version 2189fe6060f1SDimitry Andric dag BE_32B_VFLOAT_PERM_VEC = (v16i8 (LVSL (i32 ZERO), (RLWINM $Idx, 2, 0, 29))); 2190fe6060f1SDimitry Andric dag BE_32B_VFLOAT_PERMUTE = (VPERM $S, $S, BE_32B_VFLOAT_PERM_VEC); 2191fe6060f1SDimitry Andric dag BE_32B_VARIABLE_FLOAT = (XSCVSPDPN BE_32B_VFLOAT_PERMUTE); 2192fe6060f1SDimitry Andric 21930b57cec5SDimitry Andric /* BE variable double 21940b57cec5SDimitry Andric Same as the BE doubleword except there is no move. 21950b57cec5SDimitry Andric */ 21960b57cec5SDimitry Andric dag BE_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)), 21970b57cec5SDimitry Andric (v16i8 (COPY_TO_REGCLASS $S, VRRC)), 21980b57cec5SDimitry Andric BE_VDWORD_PERM_VEC)); 21990b57cec5SDimitry Andric dag BE_VARIABLE_DOUBLE = (COPY_TO_REGCLASS BE_VDOUBLE_PERMUTE, VSRC); 2200fe6060f1SDimitry Andric 2201fe6060f1SDimitry Andric // BE variable double 32-bit version 2202fe6060f1SDimitry Andric dag BE_32B_VDWORD_PERM_VEC = (v16i8 (LVSL (i32 ZERO), 2203fe6060f1SDimitry Andric (RLWINM (ANDI_rec $Idx, 1), 3, 0, 28))); 2204fe6060f1SDimitry Andric dag BE_32B_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)), 2205fe6060f1SDimitry Andric (v16i8 (COPY_TO_REGCLASS $S, VRRC)), 2206fe6060f1SDimitry Andric BE_32B_VDWORD_PERM_VEC)); 2207fe6060f1SDimitry Andric dag BE_32B_VARIABLE_DOUBLE = (COPY_TO_REGCLASS BE_32B_VDOUBLE_PERMUTE, VSRC); 22080b57cec5SDimitry Andric} 22090b57cec5SDimitry Andric 22100b57cec5SDimitry Andricdef AlignValues { 2211fe6060f1SDimitry Andric dag F32_TO_BE_WORD1 = (v4f32 (XSCVDPSPN $B)); 2212fe6060f1SDimitry Andric dag I32_TO_BE_WORD1 = (SUBREG_TO_REG (i64 1), (MTVSRWZ $B), sub_64); 22130b57cec5SDimitry Andric} 22140b57cec5SDimitry Andric 22150b57cec5SDimitry Andric// Integer extend helper dags 32 -> 64 22160b57cec5SDimitry Andricdef AnyExts { 22170b57cec5SDimitry Andric dag A = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32); 22180b57cec5SDimitry Andric dag B = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $B, sub_32); 22190b57cec5SDimitry Andric dag C = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $C, sub_32); 22200b57cec5SDimitry Andric dag D = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $D, sub_32); 22210b57cec5SDimitry Andric} 22220b57cec5SDimitry Andric 22230b57cec5SDimitry Andricdef DblToFlt { 22245ffd83dbSDimitry Andric dag A0 = (f32 (any_fpround (f64 (extractelt v2f64:$A, 0)))); 22255ffd83dbSDimitry Andric dag A1 = (f32 (any_fpround (f64 (extractelt v2f64:$A, 1)))); 22265ffd83dbSDimitry Andric dag B0 = (f32 (any_fpround (f64 (extractelt v2f64:$B, 0)))); 22275ffd83dbSDimitry Andric dag B1 = (f32 (any_fpround (f64 (extractelt v2f64:$B, 1)))); 22280b57cec5SDimitry Andric} 22290b57cec5SDimitry Andric 22300b57cec5SDimitry Andricdef ExtDbl { 22310b57cec5SDimitry Andric dag A0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 0)))))); 22320b57cec5SDimitry Andric dag A1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 1)))))); 22330b57cec5SDimitry Andric dag B0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 0)))))); 22340b57cec5SDimitry Andric dag B1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 1)))))); 22350b57cec5SDimitry Andric dag A0U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$A, 0)))))); 22360b57cec5SDimitry Andric dag A1U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$A, 1)))))); 22370b57cec5SDimitry Andric dag B0U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$B, 0)))))); 22380b57cec5SDimitry Andric dag B1U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$B, 1)))))); 22390b57cec5SDimitry Andric} 22400b57cec5SDimitry Andric 22410b57cec5SDimitry Andricdef ByteToWord { 22420b57cec5SDimitry Andric dag LE_A0 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 0)), i8)); 22430b57cec5SDimitry Andric dag LE_A1 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 4)), i8)); 22440b57cec5SDimitry Andric dag LE_A2 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 8)), i8)); 22450b57cec5SDimitry Andric dag LE_A3 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 12)), i8)); 22460b57cec5SDimitry Andric dag BE_A0 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 3)), i8)); 22470b57cec5SDimitry Andric dag BE_A1 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 7)), i8)); 22480b57cec5SDimitry Andric dag BE_A2 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 11)), i8)); 22490b57cec5SDimitry Andric dag BE_A3 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 15)), i8)); 22500b57cec5SDimitry Andric} 22510b57cec5SDimitry Andric 22520b57cec5SDimitry Andricdef ByteToDWord { 22530b57cec5SDimitry Andric dag LE_A0 = (i64 (sext_inreg 22540b57cec5SDimitry Andric (i64 (anyext (i32 (vector_extract v16i8:$A, 0)))), i8)); 22550b57cec5SDimitry Andric dag LE_A1 = (i64 (sext_inreg 22560b57cec5SDimitry Andric (i64 (anyext (i32 (vector_extract v16i8:$A, 8)))), i8)); 22570b57cec5SDimitry Andric dag BE_A0 = (i64 (sext_inreg 22580b57cec5SDimitry Andric (i64 (anyext (i32 (vector_extract v16i8:$A, 7)))), i8)); 22590b57cec5SDimitry Andric dag BE_A1 = (i64 (sext_inreg 22600b57cec5SDimitry Andric (i64 (anyext (i32 (vector_extract v16i8:$A, 15)))), i8)); 22610b57cec5SDimitry Andric} 22620b57cec5SDimitry Andric 22630b57cec5SDimitry Andricdef HWordToWord { 22640b57cec5SDimitry Andric dag LE_A0 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 0)), i16)); 22650b57cec5SDimitry Andric dag LE_A1 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 2)), i16)); 22660b57cec5SDimitry Andric dag LE_A2 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 4)), i16)); 22670b57cec5SDimitry Andric dag LE_A3 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 6)), i16)); 22680b57cec5SDimitry Andric dag BE_A0 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 1)), i16)); 22690b57cec5SDimitry Andric dag BE_A1 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 3)), i16)); 22700b57cec5SDimitry Andric dag BE_A2 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 5)), i16)); 22710b57cec5SDimitry Andric dag BE_A3 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 7)), i16)); 22720b57cec5SDimitry Andric} 22730b57cec5SDimitry Andric 22740b57cec5SDimitry Andricdef HWordToDWord { 22750b57cec5SDimitry Andric dag LE_A0 = (i64 (sext_inreg 22760b57cec5SDimitry Andric (i64 (anyext (i32 (vector_extract v8i16:$A, 0)))), i16)); 22770b57cec5SDimitry Andric dag LE_A1 = (i64 (sext_inreg 22780b57cec5SDimitry Andric (i64 (anyext (i32 (vector_extract v8i16:$A, 4)))), i16)); 22790b57cec5SDimitry Andric dag BE_A0 = (i64 (sext_inreg 22800b57cec5SDimitry Andric (i64 (anyext (i32 (vector_extract v8i16:$A, 3)))), i16)); 22810b57cec5SDimitry Andric dag BE_A1 = (i64 (sext_inreg 22820b57cec5SDimitry Andric (i64 (anyext (i32 (vector_extract v8i16:$A, 7)))), i16)); 22830b57cec5SDimitry Andric} 22840b57cec5SDimitry Andric 22850b57cec5SDimitry Andricdef WordToDWord { 22860b57cec5SDimitry Andric dag LE_A0 = (i64 (sext (i32 (vector_extract v4i32:$A, 0)))); 22870b57cec5SDimitry Andric dag LE_A1 = (i64 (sext (i32 (vector_extract v4i32:$A, 2)))); 22880b57cec5SDimitry Andric dag BE_A0 = (i64 (sext (i32 (vector_extract v4i32:$A, 1)))); 22890b57cec5SDimitry Andric dag BE_A1 = (i64 (sext (i32 (vector_extract v4i32:$A, 3)))); 22900b57cec5SDimitry Andric} 22910b57cec5SDimitry Andric 22920b57cec5SDimitry Andricdef FltToIntLoad { 2293fe6060f1SDimitry Andric dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (extloadf32 ForceXForm:$A))))); 22940b57cec5SDimitry Andric} 22950b57cec5SDimitry Andricdef FltToUIntLoad { 2296fe6060f1SDimitry Andric dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (extloadf32 ForceXForm:$A))))); 22970b57cec5SDimitry Andric} 22980b57cec5SDimitry Andricdef FltToLongLoad { 2299fe6060f1SDimitry Andric dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 ForceXForm:$A))))); 23000b57cec5SDimitry Andric} 23010b57cec5SDimitry Andricdef FltToLongLoadP9 { 2302fe6060f1SDimitry Andric dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 DSForm:$A))))); 23030b57cec5SDimitry Andric} 23040b57cec5SDimitry Andricdef FltToULongLoad { 2305fe6060f1SDimitry Andric dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 ForceXForm:$A))))); 23060b57cec5SDimitry Andric} 23070b57cec5SDimitry Andricdef FltToULongLoadP9 { 2308fe6060f1SDimitry Andric dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 DSForm:$A))))); 23090b57cec5SDimitry Andric} 23100b57cec5SDimitry Andricdef FltToLong { 23110b57cec5SDimitry Andric dag A = (i64 (PPCmfvsr (f64 (PPCfctidz (fpextend f32:$A))))); 23120b57cec5SDimitry Andric} 23130b57cec5SDimitry Andricdef FltToULong { 23140b57cec5SDimitry Andric dag A = (i64 (PPCmfvsr (f64 (PPCfctiduz (fpextend f32:$A))))); 23150b57cec5SDimitry Andric} 23160b57cec5SDimitry Andricdef DblToInt { 23170b57cec5SDimitry Andric dag A = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$A)))); 23180b57cec5SDimitry Andric dag B = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$B)))); 23190b57cec5SDimitry Andric dag C = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$C)))); 23200b57cec5SDimitry Andric dag D = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$D)))); 23210b57cec5SDimitry Andric} 23220b57cec5SDimitry Andricdef DblToUInt { 23230b57cec5SDimitry Andric dag A = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$A)))); 23240b57cec5SDimitry Andric dag B = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$B)))); 23250b57cec5SDimitry Andric dag C = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$C)))); 23260b57cec5SDimitry Andric dag D = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$D)))); 23270b57cec5SDimitry Andric} 23280b57cec5SDimitry Andricdef DblToLong { 23290b57cec5SDimitry Andric dag A = (i64 (PPCmfvsr (f64 (PPCfctidz f64:$A)))); 23300b57cec5SDimitry Andric} 23310b57cec5SDimitry Andricdef DblToULong { 23320b57cec5SDimitry Andric dag A = (i64 (PPCmfvsr (f64 (PPCfctiduz f64:$A)))); 23330b57cec5SDimitry Andric} 23340b57cec5SDimitry Andricdef DblToIntLoad { 2335fe6060f1SDimitry Andric dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load ForceXForm:$A))))); 23360b57cec5SDimitry Andric} 23370b57cec5SDimitry Andricdef DblToIntLoadP9 { 2338fe6060f1SDimitry Andric dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load DSForm:$A))))); 23390b57cec5SDimitry Andric} 23400b57cec5SDimitry Andricdef DblToUIntLoad { 2341fe6060f1SDimitry Andric dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load ForceXForm:$A))))); 23420b57cec5SDimitry Andric} 23430b57cec5SDimitry Andricdef DblToUIntLoadP9 { 2344fe6060f1SDimitry Andric dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load DSForm:$A))))); 23450b57cec5SDimitry Andric} 23460b57cec5SDimitry Andricdef DblToLongLoad { 2347fe6060f1SDimitry Andric dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (load ForceXForm:$A))))); 23480b57cec5SDimitry Andric} 23490b57cec5SDimitry Andricdef DblToULongLoad { 2350fe6060f1SDimitry Andric dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (load ForceXForm:$A))))); 23510b57cec5SDimitry Andric} 23520b57cec5SDimitry Andric 2353480093f4SDimitry Andric// FP load dags (for f32 -> v4f32) 2354480093f4SDimitry Andricdef LoadFP { 2355fe6060f1SDimitry Andric dag A = (f32 (load ForceXForm:$A)); 2356fe6060f1SDimitry Andric dag B = (f32 (load ForceXForm:$B)); 2357fe6060f1SDimitry Andric dag C = (f32 (load ForceXForm:$C)); 2358fe6060f1SDimitry Andric dag D = (f32 (load ForceXForm:$D)); 2359480093f4SDimitry Andric} 2360480093f4SDimitry Andric 23610b57cec5SDimitry Andric// FP merge dags (for f32 -> v4f32) 23620b57cec5SDimitry Andricdef MrgFP { 2363fe6060f1SDimitry Andric dag LD32A = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64); 2364fe6060f1SDimitry Andric dag LD32B = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$B), sub_64); 2365fe6060f1SDimitry Andric dag LD32C = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$C), sub_64); 2366fe6060f1SDimitry Andric dag LD32D = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$D), sub_64); 2367fe6060f1SDimitry Andric dag AC = (XVCVDPSP (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64), 2368fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), $C, sub_64), 0)); 2369fe6060f1SDimitry Andric dag BD = (XVCVDPSP (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), 2370fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), $D, sub_64), 0)); 23710b57cec5SDimitry Andric dag ABhToFlt = (XVCVDPSP (XXPERMDI $A, $B, 0)); 23720b57cec5SDimitry Andric dag ABlToFlt = (XVCVDPSP (XXPERMDI $A, $B, 3)); 23730b57cec5SDimitry Andric dag BAhToFlt = (XVCVDPSP (XXPERMDI $B, $A, 0)); 23740b57cec5SDimitry Andric dag BAlToFlt = (XVCVDPSP (XXPERMDI $B, $A, 3)); 23750b57cec5SDimitry Andric} 23760b57cec5SDimitry Andric 23770b57cec5SDimitry Andric// Word-element merge dags - conversions from f64 to i32 merged into vectors. 23780b57cec5SDimitry Andricdef MrgWords { 23790b57cec5SDimitry Andric // For big endian, we merge low and hi doublewords (A, B). 23800b57cec5SDimitry Andric dag A0B0 = (v2f64 (XXPERMDI v2f64:$A, v2f64:$B, 0)); 23810b57cec5SDimitry Andric dag A1B1 = (v2f64 (XXPERMDI v2f64:$A, v2f64:$B, 3)); 23820b57cec5SDimitry Andric dag CVA1B1S = (v4i32 (XVCVDPSXWS A1B1)); 23830b57cec5SDimitry Andric dag CVA0B0S = (v4i32 (XVCVDPSXWS A0B0)); 23840b57cec5SDimitry Andric dag CVA1B1U = (v4i32 (XVCVDPUXWS A1B1)); 23850b57cec5SDimitry Andric dag CVA0B0U = (v4i32 (XVCVDPUXWS A0B0)); 23860b57cec5SDimitry Andric 23870b57cec5SDimitry Andric // For little endian, we merge low and hi doublewords (B, A). 23880b57cec5SDimitry Andric dag B1A1 = (v2f64 (XXPERMDI v2f64:$B, v2f64:$A, 0)); 23890b57cec5SDimitry Andric dag B0A0 = (v2f64 (XXPERMDI v2f64:$B, v2f64:$A, 3)); 23900b57cec5SDimitry Andric dag CVB1A1S = (v4i32 (XVCVDPSXWS B1A1)); 23910b57cec5SDimitry Andric dag CVB0A0S = (v4i32 (XVCVDPSXWS B0A0)); 23920b57cec5SDimitry Andric dag CVB1A1U = (v4i32 (XVCVDPUXWS B1A1)); 23930b57cec5SDimitry Andric dag CVB0A0U = (v4i32 (XVCVDPUXWS B0A0)); 23940b57cec5SDimitry Andric 23950b57cec5SDimitry Andric // For big endian, we merge hi doublewords of (A, C) and (B, D), convert 23960b57cec5SDimitry Andric // then merge. 2397fe6060f1SDimitry Andric dag AC = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$A, sub_64), 2398fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), f64:$C, sub_64), 0)); 2399fe6060f1SDimitry Andric dag BD = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$B, sub_64), 2400fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), f64:$D, sub_64), 0)); 24010b57cec5SDimitry Andric dag CVACS = (v4i32 (XVCVDPSXWS AC)); 24020b57cec5SDimitry Andric dag CVBDS = (v4i32 (XVCVDPSXWS BD)); 24030b57cec5SDimitry Andric dag CVACU = (v4i32 (XVCVDPUXWS AC)); 24040b57cec5SDimitry Andric dag CVBDU = (v4i32 (XVCVDPUXWS BD)); 24050b57cec5SDimitry Andric 24060b57cec5SDimitry Andric // For little endian, we merge hi doublewords of (D, B) and (C, A), convert 24070b57cec5SDimitry Andric // then merge. 2408fe6060f1SDimitry Andric dag DB = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$D, sub_64), 2409fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), f64:$B, sub_64), 0)); 2410fe6060f1SDimitry Andric dag CA = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$C, sub_64), 2411fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), f64:$A, sub_64), 0)); 24120b57cec5SDimitry Andric dag CVDBS = (v4i32 (XVCVDPSXWS DB)); 24130b57cec5SDimitry Andric dag CVCAS = (v4i32 (XVCVDPSXWS CA)); 24140b57cec5SDimitry Andric dag CVDBU = (v4i32 (XVCVDPUXWS DB)); 24150b57cec5SDimitry Andric dag CVCAU = (v4i32 (XVCVDPUXWS CA)); 24160b57cec5SDimitry Andric} 24170b57cec5SDimitry Andric 2418fe6060f1SDimitry Andricdef DblwdCmp { 2419fe6060f1SDimitry Andric dag SGTW = (v2i64 (v2i64 (VCMPGTSW v2i64:$vA, v2i64:$vB))); 2420fe6060f1SDimitry Andric dag UGTW = (v2i64 (v2i64 (VCMPGTUW v2i64:$vA, v2i64:$vB))); 2421fe6060f1SDimitry Andric dag EQW = (v2i64 (v2i64 (VCMPEQUW v2i64:$vA, v2i64:$vB))); 2422fe6060f1SDimitry Andric dag UGTWSHAND = (v2i64 (XXLAND (v2i64 (XXSLDWI UGTW, UGTW, 1)), EQW)); 2423fe6060f1SDimitry Andric dag EQWSHAND = (v2i64 (XXLAND (v2i64 (XXSLDWI EQW, EQW, 1)), EQW)); 2424fe6060f1SDimitry Andric dag SGTWOR = (v2i64 (XXLOR SGTW, UGTWSHAND)); 2425fe6060f1SDimitry Andric dag UGTWOR = (v2i64 (XXLOR UGTW, UGTWSHAND)); 2426fe6060f1SDimitry Andric dag MRGSGT = (v2i64 (XXPERMDI (v2i64 (XXSPLTW SGTWOR, 0)), 2427fe6060f1SDimitry Andric (v2i64 (XXSPLTW SGTWOR, 2)), 0)); 2428fe6060f1SDimitry Andric dag MRGUGT = (v2i64 (XXPERMDI (v2i64 (XXSPLTW UGTWOR, 0)), 2429fe6060f1SDimitry Andric (v2i64 (XXSPLTW UGTWOR, 2)), 0)); 2430fe6060f1SDimitry Andric dag MRGEQ = (v2i64 (XXPERMDI (v2i64 (XXSPLTW EQWSHAND, 0)), 2431fe6060f1SDimitry Andric (v2i64 (XXSPLTW EQWSHAND, 2)), 0)); 2432fe6060f1SDimitry Andric} 2433fe6060f1SDimitry Andric 24345ffd83dbSDimitry Andric//---------------------------- Anonymous Patterns ----------------------------// 24355ffd83dbSDimitry Andric// Predicate combinations are kept in roughly chronological order in terms of 24365ffd83dbSDimitry Andric// instruction availability in the architecture. For example, VSX came in with 24375ffd83dbSDimitry Andric// ISA 2.06 (Power7). There have since been additions in ISA 2.07 (Power8) and 24385ffd83dbSDimitry Andric// ISA 3.0 (Power9). However, the granularity of features on later subtargets 24395ffd83dbSDimitry Andric// is finer for various reasons. For example, we have Power8Vector, 24405ffd83dbSDimitry Andric// Power8Altivec, DirectMove that all came in with ISA 2.07. The situation is 24415ffd83dbSDimitry Andric// similar with ISA 3.0 with Power9Vector, Power9Altivec, IsISA3_0. Then there 24425ffd83dbSDimitry Andric// are orthogonal predicates such as endianness for which the order was 24435ffd83dbSDimitry Andric// arbitrarily chosen to be Big, Little. 24445ffd83dbSDimitry Andric// 24455ffd83dbSDimitry Andric// Predicate combinations available: 2446e8d8bef9SDimitry Andric// [HasVSX, IsLittleEndian, HasP8Altivec] Altivec patterns using VSX instr. 2447e8d8bef9SDimitry Andric// [HasVSX, IsBigEndian, HasP8Altivec] Altivec patterns using VSX instr. 24485ffd83dbSDimitry Andric// [HasVSX] 24495ffd83dbSDimitry Andric// [HasVSX, IsBigEndian] 24505ffd83dbSDimitry Andric// [HasVSX, IsLittleEndian] 24515ffd83dbSDimitry Andric// [HasVSX, NoP9Vector] 2452e8d8bef9SDimitry Andric// [HasVSX, NoP9Vector, IsLittleEndian] 2453fe6060f1SDimitry Andric// [HasVSX, NoP9Vector, IsBigEndian] 24545ffd83dbSDimitry Andric// [HasVSX, HasOnlySwappingMemOps] 24555ffd83dbSDimitry Andric// [HasVSX, HasOnlySwappingMemOps, IsBigEndian] 245606c3fb27SDimitry Andric// [HasVSX, NoP8Vector] 24575ffd83dbSDimitry Andric// [HasVSX, HasP8Vector] 2458fe6060f1SDimitry Andric// [HasVSX, HasP8Vector, IsBigEndian] 2459e8d8bef9SDimitry Andric// [HasVSX, HasP8Vector, IsBigEndian, IsPPC64] 24605ffd83dbSDimitry Andric// [HasVSX, HasP8Vector, IsLittleEndian] 2461e8d8bef9SDimitry Andric// [HasVSX, HasP8Vector, NoP9Vector, IsBigEndian, IsPPC64] 24625ffd83dbSDimitry Andric// [HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian] 24634824e7fdSDimitry Andric// [HasVSX, HasP8Altivec] 24645ffd83dbSDimitry Andric// [HasVSX, HasDirectMove] 24655ffd83dbSDimitry Andric// [HasVSX, HasDirectMove, IsBigEndian] 24665ffd83dbSDimitry Andric// [HasVSX, HasDirectMove, IsLittleEndian] 2467e8d8bef9SDimitry Andric// [HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian, IsPPC64] 2468e8d8bef9SDimitry Andric// [HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64] 24695ffd83dbSDimitry Andric// [HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian] 24705ffd83dbSDimitry Andric// [HasVSX, HasDirectMove, NoP9Vector, IsLittleEndian] 24715ffd83dbSDimitry Andric// [HasVSX, HasP9Vector] 2472fe6060f1SDimitry Andric// [HasVSX, HasP9Vector, NoP10Vector] 2473fe6060f1SDimitry Andric// [HasVSX, HasP9Vector, IsBigEndian] 2474e8d8bef9SDimitry Andric// [HasVSX, HasP9Vector, IsBigEndian, IsPPC64] 24755ffd83dbSDimitry Andric// [HasVSX, HasP9Vector, IsLittleEndian] 24765ffd83dbSDimitry Andric// [HasVSX, HasP9Altivec] 2477e8d8bef9SDimitry Andric// [HasVSX, HasP9Altivec, IsBigEndian, IsPPC64] 24785ffd83dbSDimitry Andric// [HasVSX, HasP9Altivec, IsLittleEndian] 2479e8d8bef9SDimitry Andric// [HasVSX, IsISA3_0, HasDirectMove, IsBigEndian, IsPPC64] 24805ffd83dbSDimitry Andric// [HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian] 24810b57cec5SDimitry Andric 2482e8d8bef9SDimitry Andric// These Altivec patterns are here because we need a VSX instruction to match 2483e8d8bef9SDimitry Andric// the intrinsic (but only for little endian system). 2484e8d8bef9SDimitry Andriclet Predicates = [HasVSX, IsLittleEndian, HasP8Altivec] in 2485e8d8bef9SDimitry Andric def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor v16i8:$a, 2486e8d8bef9SDimitry Andric v16i8:$b, v16i8:$c)), 2487e8d8bef9SDimitry Andric (v16i8 (VPERMXOR $a, $b, (XXLNOR (COPY_TO_REGCLASS $c, VSRC), 2488e8d8bef9SDimitry Andric (COPY_TO_REGCLASS $c, VSRC))))>; 2489e8d8bef9SDimitry Andriclet Predicates = [HasVSX, IsBigEndian, HasP8Altivec] in 2490e8d8bef9SDimitry Andric def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor v16i8:$a, 2491e8d8bef9SDimitry Andric v16i8:$b, v16i8:$c)), 2492e8d8bef9SDimitry Andric (v16i8 (VPERMXOR $a, $b, $c))>; 24934824e7fdSDimitry Andriclet Predicates = [HasVSX, HasP8Altivec] in 24944824e7fdSDimitry Andric def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor_be v16i8:$a, 24954824e7fdSDimitry Andric v16i8:$b, v16i8:$c)), 24964824e7fdSDimitry Andric (v16i8 (VPERMXOR $a, $b, $c))>; 2497e8d8bef9SDimitry Andric 24985ffd83dbSDimitry Andriclet AddedComplexity = 400 in { 24995ffd83dbSDimitry Andric// Valid for any VSX subtarget, regardless of endianness. 25000b57cec5SDimitry Andriclet Predicates = [HasVSX] in { 2501fe6060f1SDimitry Andricdef : Pat<(v4i32 (vnot v4i32:$A)), 25025ffd83dbSDimitry Andric (v4i32 (XXLNOR $A, $A))>; 2503fe6060f1SDimitry Andricdef : Pat<(v4i32 (or (and (vnot v4i32:$C), v4i32:$A), 25045ffd83dbSDimitry Andric (and v4i32:$B, v4i32:$C))), 25055ffd83dbSDimitry Andric (v4i32 (XXSEL $A, $B, $C))>; 25065ffd83dbSDimitry Andric 2507bdd1243dSDimitry Andricdef : Pat<(f64 (fpimm0neg)), 2508bdd1243dSDimitry Andric (f64 (XSNEGDP (XXLXORdpz)))>; 2509bdd1243dSDimitry Andric 2510bdd1243dSDimitry Andricdef : Pat<(f64 (nzFPImmExactInti5:$A)), 2511bdd1243dSDimitry Andric (COPY_TO_REGCLASS (XVCVSXWDP (COPY_TO_REGCLASS 2512bdd1243dSDimitry Andric (VSPLTISW (getFPAs5BitExactInt fpimm:$A)), VSRC)), VSFRC)>; 2513bdd1243dSDimitry Andric 25145ffd83dbSDimitry Andric// Additional fnmsub pattern for PPC specific ISD opcode 25155ffd83dbSDimitry Andricdef : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C), 25165ffd83dbSDimitry Andric (XSNMSUBADP $C, $A, $B)>; 25175ffd83dbSDimitry Andricdef : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)), 25185ffd83dbSDimitry Andric (XSMSUBADP $C, $A, $B)>; 25195ffd83dbSDimitry Andricdef : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)), 25205ffd83dbSDimitry Andric (XSNMADDADP $C, $A, $B)>; 25215ffd83dbSDimitry Andric 25225ffd83dbSDimitry Andricdef : Pat<(PPCfnmsub v2f64:$A, v2f64:$B, v2f64:$C), 25235ffd83dbSDimitry Andric (XVNMSUBADP $C, $A, $B)>; 25245ffd83dbSDimitry Andricdef : Pat<(fneg (PPCfnmsub v2f64:$A, v2f64:$B, v2f64:$C)), 25255ffd83dbSDimitry Andric (XVMSUBADP $C, $A, $B)>; 25265ffd83dbSDimitry Andricdef : Pat<(PPCfnmsub v2f64:$A, v2f64:$B, (fneg v2f64:$C)), 25275ffd83dbSDimitry Andric (XVNMADDADP $C, $A, $B)>; 25285ffd83dbSDimitry Andric 25295ffd83dbSDimitry Andricdef : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C), 25305ffd83dbSDimitry Andric (XVNMSUBASP $C, $A, $B)>; 25315ffd83dbSDimitry Andricdef : Pat<(fneg (PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C)), 25325ffd83dbSDimitry Andric (XVMSUBASP $C, $A, $B)>; 25335ffd83dbSDimitry Andricdef : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, (fneg v4f32:$C)), 25345ffd83dbSDimitry Andric (XVNMADDASP $C, $A, $B)>; 25355ffd83dbSDimitry Andric 2536e8d8bef9SDimitry Andricdef : Pat<(PPCfsqrt f64:$frA), (XSSQRTDP $frA)>; 2537e8d8bef9SDimitry Andricdef : Pat<(PPCfsqrt v2f64:$frA), (XVSQRTDP $frA)>; 2538e8d8bef9SDimitry Andricdef : Pat<(PPCfsqrt v4f32:$frA), (XVSQRTSP $frA)>; 2539e8d8bef9SDimitry Andric 25405ffd83dbSDimitry Andricdef : Pat<(v2f64 (bitconvert v4f32:$A)), 25415ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VSRC)>; 25425ffd83dbSDimitry Andricdef : Pat<(v2f64 (bitconvert v4i32:$A)), 25435ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VSRC)>; 25445ffd83dbSDimitry Andricdef : Pat<(v2f64 (bitconvert v8i16:$A)), 25455ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VSRC)>; 25465ffd83dbSDimitry Andricdef : Pat<(v2f64 (bitconvert v16i8:$A)), 25475ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VSRC)>; 25485ffd83dbSDimitry Andric 25495ffd83dbSDimitry Andricdef : Pat<(v4f32 (bitconvert v2f64:$A)), 25505ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VRRC)>; 25515ffd83dbSDimitry Andricdef : Pat<(v4i32 (bitconvert v2f64:$A)), 25525ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VRRC)>; 25535ffd83dbSDimitry Andricdef : Pat<(v8i16 (bitconvert v2f64:$A)), 25545ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VRRC)>; 25555ffd83dbSDimitry Andricdef : Pat<(v16i8 (bitconvert v2f64:$A)), 25565ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VRRC)>; 25575ffd83dbSDimitry Andric 25585ffd83dbSDimitry Andricdef : Pat<(v2i64 (bitconvert v4f32:$A)), 25595ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VSRC)>; 25605ffd83dbSDimitry Andricdef : Pat<(v2i64 (bitconvert v4i32:$A)), 25615ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VSRC)>; 25625ffd83dbSDimitry Andricdef : Pat<(v2i64 (bitconvert v8i16:$A)), 25635ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VSRC)>; 25645ffd83dbSDimitry Andricdef : Pat<(v2i64 (bitconvert v16i8:$A)), 25655ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VSRC)>; 25665ffd83dbSDimitry Andric 25675ffd83dbSDimitry Andricdef : Pat<(v4f32 (bitconvert v2i64:$A)), 25685ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VRRC)>; 25695ffd83dbSDimitry Andricdef : Pat<(v4i32 (bitconvert v2i64:$A)), 25705ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VRRC)>; 25715ffd83dbSDimitry Andricdef : Pat<(v8i16 (bitconvert v2i64:$A)), 25725ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VRRC)>; 25735ffd83dbSDimitry Andricdef : Pat<(v16i8 (bitconvert v2i64:$A)), 25745ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VRRC)>; 25755ffd83dbSDimitry Andric 25765ffd83dbSDimitry Andricdef : Pat<(v2f64 (bitconvert v2i64:$A)), 25775ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VRRC)>; 25785ffd83dbSDimitry Andricdef : Pat<(v2i64 (bitconvert v2f64:$A)), 25795ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VRRC)>; 25805ffd83dbSDimitry Andric 25815ffd83dbSDimitry Andricdef : Pat<(v2f64 (bitconvert v1i128:$A)), 25825ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VRRC)>; 25835ffd83dbSDimitry Andricdef : Pat<(v1i128 (bitconvert v2f64:$A)), 25845ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VRRC)>; 25855ffd83dbSDimitry Andric 25865ffd83dbSDimitry Andricdef : Pat<(v2i64 (bitconvert f128:$A)), 25875ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VRRC)>; 25885ffd83dbSDimitry Andricdef : Pat<(v4i32 (bitconvert f128:$A)), 25895ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VRRC)>; 25905ffd83dbSDimitry Andricdef : Pat<(v8i16 (bitconvert f128:$A)), 25915ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VRRC)>; 25925ffd83dbSDimitry Andricdef : Pat<(v16i8 (bitconvert f128:$A)), 25935ffd83dbSDimitry Andric (COPY_TO_REGCLASS $A, VRRC)>; 25945ffd83dbSDimitry Andric 25955ffd83dbSDimitry Andricdef : Pat<(v2f64 (PPCsvec2fp v4i32:$C, 0)), 25965ffd83dbSDimitry Andric (v2f64 (XVCVSXWDP (v2i64 (XXMRGHW $C, $C))))>; 25975ffd83dbSDimitry Andricdef : Pat<(v2f64 (PPCsvec2fp v4i32:$C, 1)), 25985ffd83dbSDimitry Andric (v2f64 (XVCVSXWDP (v2i64 (XXMRGLW $C, $C))))>; 25995ffd83dbSDimitry Andric 26005ffd83dbSDimitry Andricdef : Pat<(v2f64 (PPCuvec2fp v4i32:$C, 0)), 26015ffd83dbSDimitry Andric (v2f64 (XVCVUXWDP (v2i64 (XXMRGHW $C, $C))))>; 26025ffd83dbSDimitry Andricdef : Pat<(v2f64 (PPCuvec2fp v4i32:$C, 1)), 26035ffd83dbSDimitry Andric (v2f64 (XVCVUXWDP (v2i64 (XXMRGLW $C, $C))))>; 26045ffd83dbSDimitry Andric 26055ffd83dbSDimitry Andricdef : Pat<(v2f64 (PPCfpexth v4f32:$C, 0)), (XVCVSPDP (XXMRGHW $C, $C))>; 26065ffd83dbSDimitry Andricdef : Pat<(v2f64 (PPCfpexth v4f32:$C, 1)), (XVCVSPDP (XXMRGLW $C, $C))>; 26075ffd83dbSDimitry Andric 26085ffd83dbSDimitry Andric// Permutes. 26095ffd83dbSDimitry Andricdef : Pat<(v2f64 (PPCxxswapd v2f64:$src)), (XXPERMDI $src, $src, 2)>; 26105ffd83dbSDimitry Andricdef : Pat<(v2i64 (PPCxxswapd v2i64:$src)), (XXPERMDI $src, $src, 2)>; 26115ffd83dbSDimitry Andricdef : Pat<(v4f32 (PPCxxswapd v4f32:$src)), (XXPERMDI $src, $src, 2)>; 26125ffd83dbSDimitry Andricdef : Pat<(v4i32 (PPCxxswapd v4i32:$src)), (XXPERMDI $src, $src, 2)>; 26135ffd83dbSDimitry Andricdef : Pat<(v2f64 (PPCswapNoChain v2f64:$src)), (XXPERMDI $src, $src, 2)>; 26145ffd83dbSDimitry Andric 26155ffd83dbSDimitry Andric// PPCvecshl XT, XA, XA, 2 can be selected to both XXSLDWI XT,XA,XA,2 and 26165ffd83dbSDimitry Andric// XXSWAPD XT,XA (i.e. XXPERMDI XT,XA,XA,2), the later one is more profitable. 26175ffd83dbSDimitry Andricdef : Pat<(v4i32 (PPCvecshl v4i32:$src, v4i32:$src, 2)), 26185ffd83dbSDimitry Andric (XXPERMDI $src, $src, 2)>; 26195ffd83dbSDimitry Andric 26205ffd83dbSDimitry Andric// Selects. 26215ffd83dbSDimitry Andricdef : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLT)), 26225ffd83dbSDimitry Andric (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>; 26235ffd83dbSDimitry Andricdef : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULT)), 26245ffd83dbSDimitry Andric (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>; 26255ffd83dbSDimitry Andricdef : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLE)), 26265ffd83dbSDimitry Andric (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>; 26275ffd83dbSDimitry Andricdef : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULE)), 26285ffd83dbSDimitry Andric (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>; 26295ffd83dbSDimitry Andricdef : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETEQ)), 26305ffd83dbSDimitry Andric (SELECT_VSRC (CREQV $lhs, $rhs), $tval, $fval)>; 26315ffd83dbSDimitry Andricdef : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGE)), 26325ffd83dbSDimitry Andric (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>; 26335ffd83dbSDimitry Andricdef : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGE)), 26345ffd83dbSDimitry Andric (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>; 26355ffd83dbSDimitry Andricdef : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGT)), 26365ffd83dbSDimitry Andric (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>; 26375ffd83dbSDimitry Andricdef : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGT)), 26385ffd83dbSDimitry Andric (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>; 26395ffd83dbSDimitry Andricdef : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETNE)), 26405ffd83dbSDimitry Andric (SELECT_VSRC (CRXOR $lhs, $rhs), $tval, $fval)>; 26415ffd83dbSDimitry Andric 26425ffd83dbSDimitry Andricdef : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 26435ffd83dbSDimitry Andric (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>; 26445ffd83dbSDimitry Andricdef : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 26455ffd83dbSDimitry Andric (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>; 26465ffd83dbSDimitry Andricdef : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 26475ffd83dbSDimitry Andric (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>; 26485ffd83dbSDimitry Andricdef : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 26495ffd83dbSDimitry Andric (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>; 26505ffd83dbSDimitry Andricdef : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 26515ffd83dbSDimitry Andric (SELECT_VSFRC (CREQV $lhs, $rhs), $tval, $fval)>; 26525ffd83dbSDimitry Andricdef : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 26535ffd83dbSDimitry Andric (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>; 26545ffd83dbSDimitry Andricdef : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 26555ffd83dbSDimitry Andric (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>; 26565ffd83dbSDimitry Andricdef : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 26575ffd83dbSDimitry Andric (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>; 26585ffd83dbSDimitry Andricdef : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 26595ffd83dbSDimitry Andric (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>; 26605ffd83dbSDimitry Andricdef : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 26615ffd83dbSDimitry Andric (SELECT_VSFRC (CRXOR $lhs, $rhs), $tval, $fval)>; 26625ffd83dbSDimitry Andric 26635ffd83dbSDimitry Andric// Divides. 26645ffd83dbSDimitry Andricdef : Pat<(int_ppc_vsx_xvdivsp v4f32:$A, v4f32:$B), 26655ffd83dbSDimitry Andric (XVDIVSP $A, $B)>; 26665ffd83dbSDimitry Andricdef : Pat<(int_ppc_vsx_xvdivdp v2f64:$A, v2f64:$B), 26675ffd83dbSDimitry Andric (XVDIVDP $A, $B)>; 26685ffd83dbSDimitry Andric 2669e8d8bef9SDimitry Andric// Vector test for software divide and sqrt. 2670e8d8bef9SDimitry Andricdef : Pat<(i32 (int_ppc_vsx_xvtdivdp v2f64:$A, v2f64:$B)), 2671e8d8bef9SDimitry Andric (COPY_TO_REGCLASS (XVTDIVDP $A, $B), GPRC)>; 2672e8d8bef9SDimitry Andricdef : Pat<(i32 (int_ppc_vsx_xvtdivsp v4f32:$A, v4f32:$B)), 2673e8d8bef9SDimitry Andric (COPY_TO_REGCLASS (XVTDIVSP $A, $B), GPRC)>; 2674e8d8bef9SDimitry Andricdef : Pat<(i32 (int_ppc_vsx_xvtsqrtdp v2f64:$A)), 2675e8d8bef9SDimitry Andric (COPY_TO_REGCLASS (XVTSQRTDP $A), GPRC)>; 2676e8d8bef9SDimitry Andricdef : Pat<(i32 (int_ppc_vsx_xvtsqrtsp v4f32:$A)), 2677e8d8bef9SDimitry Andric (COPY_TO_REGCLASS (XVTSQRTSP $A), GPRC)>; 2678e8d8bef9SDimitry Andric 26795ffd83dbSDimitry Andric// Reciprocal estimate 26805ffd83dbSDimitry Andricdef : Pat<(int_ppc_vsx_xvresp v4f32:$A), 26815ffd83dbSDimitry Andric (XVRESP $A)>; 26825ffd83dbSDimitry Andricdef : Pat<(int_ppc_vsx_xvredp v2f64:$A), 26835ffd83dbSDimitry Andric (XVREDP $A)>; 26845ffd83dbSDimitry Andric 26855ffd83dbSDimitry Andric// Recip. square root estimate 26865ffd83dbSDimitry Andricdef : Pat<(int_ppc_vsx_xvrsqrtesp v4f32:$A), 26875ffd83dbSDimitry Andric (XVRSQRTESP $A)>; 26885ffd83dbSDimitry Andricdef : Pat<(int_ppc_vsx_xvrsqrtedp v2f64:$A), 26895ffd83dbSDimitry Andric (XVRSQRTEDP $A)>; 26905ffd83dbSDimitry Andric 26915ffd83dbSDimitry Andric// Vector selection 26925ffd83dbSDimitry Andricdef : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)), 26935ffd83dbSDimitry Andric (COPY_TO_REGCLASS 26945ffd83dbSDimitry Andric (XXSEL (COPY_TO_REGCLASS $vC, VSRC), 26955ffd83dbSDimitry Andric (COPY_TO_REGCLASS $vB, VSRC), 26965ffd83dbSDimitry Andric (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>; 26975ffd83dbSDimitry Andricdef : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)), 26985ffd83dbSDimitry Andric (COPY_TO_REGCLASS 26995ffd83dbSDimitry Andric (XXSEL (COPY_TO_REGCLASS $vC, VSRC), 27005ffd83dbSDimitry Andric (COPY_TO_REGCLASS $vB, VSRC), 27015ffd83dbSDimitry Andric (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>; 27025ffd83dbSDimitry Andricdef : Pat<(vselect v4i32:$vA, v4i32:$vB, v4i32:$vC), 27035ffd83dbSDimitry Andric (XXSEL $vC, $vB, $vA)>; 27045ffd83dbSDimitry Andricdef : Pat<(vselect v2i64:$vA, v2i64:$vB, v2i64:$vC), 27055ffd83dbSDimitry Andric (XXSEL $vC, $vB, $vA)>; 27065ffd83dbSDimitry Andricdef : Pat<(vselect v4i32:$vA, v4f32:$vB, v4f32:$vC), 27075ffd83dbSDimitry Andric (XXSEL $vC, $vB, $vA)>; 27085ffd83dbSDimitry Andricdef : Pat<(vselect v2i64:$vA, v2f64:$vB, v2f64:$vC), 27095ffd83dbSDimitry Andric (XXSEL $vC, $vB, $vA)>; 2710fe6060f1SDimitry Andricdef : Pat<(v1i128 (vselect v1i128:$vA, v1i128:$vB, v1i128:$vC)), 2711fe6060f1SDimitry Andric (COPY_TO_REGCLASS 2712fe6060f1SDimitry Andric (XXSEL (COPY_TO_REGCLASS $vC, VSRC), 2713fe6060f1SDimitry Andric (COPY_TO_REGCLASS $vB, VSRC), 2714fe6060f1SDimitry Andric (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>; 27155ffd83dbSDimitry Andric 27165ffd83dbSDimitry Andricdef : Pat<(v4f32 (any_fmaxnum v4f32:$src1, v4f32:$src2)), 27175ffd83dbSDimitry Andric (v4f32 (XVMAXSP $src1, $src2))>; 27185ffd83dbSDimitry Andricdef : Pat<(v4f32 (any_fminnum v4f32:$src1, v4f32:$src2)), 27195ffd83dbSDimitry Andric (v4f32 (XVMINSP $src1, $src2))>; 27205ffd83dbSDimitry Andricdef : Pat<(v2f64 (any_fmaxnum v2f64:$src1, v2f64:$src2)), 27215ffd83dbSDimitry Andric (v2f64 (XVMAXDP $src1, $src2))>; 27225ffd83dbSDimitry Andricdef : Pat<(v2f64 (any_fminnum v2f64:$src1, v2f64:$src2)), 27235ffd83dbSDimitry Andric (v2f64 (XVMINDP $src1, $src2))>; 27245ffd83dbSDimitry Andric 27255ffd83dbSDimitry Andric// f32 abs 27265ffd83dbSDimitry Andricdef : Pat<(f32 (fabs f32:$S)), 27275ffd83dbSDimitry Andric (f32 (COPY_TO_REGCLASS (XSABSDP 27285ffd83dbSDimitry Andric (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 27295ffd83dbSDimitry Andric 27305ffd83dbSDimitry Andric// f32 nabs 27315ffd83dbSDimitry Andricdef : Pat<(f32 (fneg (fabs f32:$S))), 27325ffd83dbSDimitry Andric (f32 (COPY_TO_REGCLASS (XSNABSDP 27335ffd83dbSDimitry Andric (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 27345ffd83dbSDimitry Andric 27355ffd83dbSDimitry Andric// f32 Min. 27365ffd83dbSDimitry Andricdef : Pat<(f32 (fminnum_ieee f32:$A, f32:$B)), 27375ffd83dbSDimitry Andric (f32 FpMinMax.F32Min)>; 27385ffd83dbSDimitry Andricdef : Pat<(f32 (fminnum_ieee (fcanonicalize f32:$A), f32:$B)), 27395ffd83dbSDimitry Andric (f32 FpMinMax.F32Min)>; 27405ffd83dbSDimitry Andricdef : Pat<(f32 (fminnum_ieee f32:$A, (fcanonicalize f32:$B))), 27415ffd83dbSDimitry Andric (f32 FpMinMax.F32Min)>; 27425ffd83dbSDimitry Andricdef : Pat<(f32 (fminnum_ieee (fcanonicalize f32:$A), (fcanonicalize f32:$B))), 27435ffd83dbSDimitry Andric (f32 FpMinMax.F32Min)>; 27445ffd83dbSDimitry Andric// F32 Max. 27455ffd83dbSDimitry Andricdef : Pat<(f32 (fmaxnum_ieee f32:$A, f32:$B)), 27465ffd83dbSDimitry Andric (f32 FpMinMax.F32Max)>; 27475ffd83dbSDimitry Andricdef : Pat<(f32 (fmaxnum_ieee (fcanonicalize f32:$A), f32:$B)), 27485ffd83dbSDimitry Andric (f32 FpMinMax.F32Max)>; 27495ffd83dbSDimitry Andricdef : Pat<(f32 (fmaxnum_ieee f32:$A, (fcanonicalize f32:$B))), 27505ffd83dbSDimitry Andric (f32 FpMinMax.F32Max)>; 27515ffd83dbSDimitry Andricdef : Pat<(f32 (fmaxnum_ieee (fcanonicalize f32:$A), (fcanonicalize f32:$B))), 27525ffd83dbSDimitry Andric (f32 FpMinMax.F32Max)>; 27535ffd83dbSDimitry Andric 27545ffd83dbSDimitry Andric// f64 Min. 27555ffd83dbSDimitry Andricdef : Pat<(f64 (fminnum_ieee f64:$A, f64:$B)), 27565ffd83dbSDimitry Andric (f64 (XSMINDP $A, $B))>; 27575ffd83dbSDimitry Andricdef : Pat<(f64 (fminnum_ieee (fcanonicalize f64:$A), f64:$B)), 27585ffd83dbSDimitry Andric (f64 (XSMINDP $A, $B))>; 27595ffd83dbSDimitry Andricdef : Pat<(f64 (fminnum_ieee f64:$A, (fcanonicalize f64:$B))), 27605ffd83dbSDimitry Andric (f64 (XSMINDP $A, $B))>; 27615ffd83dbSDimitry Andricdef : Pat<(f64 (fminnum_ieee (fcanonicalize f64:$A), (fcanonicalize f64:$B))), 27625ffd83dbSDimitry Andric (f64 (XSMINDP $A, $B))>; 27635ffd83dbSDimitry Andric// f64 Max. 27645ffd83dbSDimitry Andricdef : Pat<(f64 (fmaxnum_ieee f64:$A, f64:$B)), 27655ffd83dbSDimitry Andric (f64 (XSMAXDP $A, $B))>; 27665ffd83dbSDimitry Andricdef : Pat<(f64 (fmaxnum_ieee (fcanonicalize f64:$A), f64:$B)), 27675ffd83dbSDimitry Andric (f64 (XSMAXDP $A, $B))>; 27685ffd83dbSDimitry Andricdef : Pat<(f64 (fmaxnum_ieee f64:$A, (fcanonicalize f64:$B))), 27695ffd83dbSDimitry Andric (f64 (XSMAXDP $A, $B))>; 27705ffd83dbSDimitry Andricdef : Pat<(f64 (fmaxnum_ieee (fcanonicalize f64:$A), (fcanonicalize f64:$B))), 27715ffd83dbSDimitry Andric (f64 (XSMAXDP $A, $B))>; 27725ffd83dbSDimitry Andric 2773fe6060f1SDimitry Andricdef : Pat<(int_ppc_vsx_stxvd2x_be v2f64:$rS, ForceXForm:$dst), 2774fe6060f1SDimitry Andric (STXVD2X $rS, ForceXForm:$dst)>; 2775fe6060f1SDimitry Andricdef : Pat<(int_ppc_vsx_stxvw4x_be v4i32:$rS, ForceXForm:$dst), 2776fe6060f1SDimitry Andric (STXVW4X $rS, ForceXForm:$dst)>; 2777fe6060f1SDimitry Andricdef : Pat<(v4i32 (int_ppc_vsx_lxvw4x_be ForceXForm:$src)), (LXVW4X ForceXForm:$src)>; 2778fe6060f1SDimitry Andricdef : Pat<(v2f64 (int_ppc_vsx_lxvd2x_be ForceXForm:$src)), (LXVD2X ForceXForm:$src)>; 27795ffd83dbSDimitry Andric 27805ffd83dbSDimitry Andric// Rounding for single precision. 27815ffd83dbSDimitry Andricdef : Pat<(f32 (any_fround f32:$S)), 27825ffd83dbSDimitry Andric (f32 (COPY_TO_REGCLASS (XSRDPI 27835ffd83dbSDimitry Andric (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 27845ffd83dbSDimitry Andricdef : Pat<(f32 (any_ffloor f32:$S)), 27855ffd83dbSDimitry Andric (f32 (COPY_TO_REGCLASS (XSRDPIM 27865ffd83dbSDimitry Andric (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 27875ffd83dbSDimitry Andricdef : Pat<(f32 (any_fceil f32:$S)), 27885ffd83dbSDimitry Andric (f32 (COPY_TO_REGCLASS (XSRDPIP 27895ffd83dbSDimitry Andric (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 27905ffd83dbSDimitry Andricdef : Pat<(f32 (any_ftrunc f32:$S)), 27915ffd83dbSDimitry Andric (f32 (COPY_TO_REGCLASS (XSRDPIZ 27925ffd83dbSDimitry Andric (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 27935ffd83dbSDimitry Andricdef : Pat<(f32 (any_frint f32:$S)), 27945ffd83dbSDimitry Andric (f32 (COPY_TO_REGCLASS (XSRDPIC 27955ffd83dbSDimitry Andric (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2796e8d8bef9SDimitry Andricdef : Pat<(v4f32 (any_frint v4f32:$S)), (v4f32 (XVRSPIC $S))>; 27975ffd83dbSDimitry Andric 27985ffd83dbSDimitry Andric// Rounding for double precision. 2799e8d8bef9SDimitry Andricdef : Pat<(f64 (any_frint f64:$S)), (f64 (XSRDPIC $S))>; 2800e8d8bef9SDimitry Andricdef : Pat<(v2f64 (any_frint v2f64:$S)), (v2f64 (XVRDPIC $S))>; 28015ffd83dbSDimitry Andric 2802349cc55cSDimitry Andric// Rounding without exceptions (nearbyint). Due to strange tblgen behaviour, 2803349cc55cSDimitry Andric// these need to be defined after the any_frint versions so ISEL will correctly 2804349cc55cSDimitry Andric// add the chain to the strict versions. 2805349cc55cSDimitry Andricdef : Pat<(f32 (fnearbyint f32:$S)), 2806349cc55cSDimitry Andric (f32 (COPY_TO_REGCLASS (XSRDPIC 2807349cc55cSDimitry Andric (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2808349cc55cSDimitry Andricdef : Pat<(f64 (fnearbyint f64:$S)), 2809349cc55cSDimitry Andric (f64 (XSRDPIC $S))>; 2810349cc55cSDimitry Andricdef : Pat<(v2f64 (fnearbyint v2f64:$S)), 2811349cc55cSDimitry Andric (v2f64 (XVRDPIC $S))>; 2812349cc55cSDimitry Andricdef : Pat<(v4f32 (fnearbyint v4f32:$S)), 2813349cc55cSDimitry Andric (v4f32 (XVRSPIC $S))>; 2814349cc55cSDimitry Andric 28155ffd83dbSDimitry Andric// Materialize a zero-vector of long long 28165ffd83dbSDimitry Andricdef : Pat<(v2i64 immAllZerosV), 28175ffd83dbSDimitry Andric (v2i64 (XXLXORz))>; 28185ffd83dbSDimitry Andric 28190b57cec5SDimitry Andric// Build vectors of floating point converted to i32. 28200b57cec5SDimitry Andricdef : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.A, 28210b57cec5SDimitry Andric DblToInt.A, DblToInt.A)), 2822fe6060f1SDimitry Andric (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS $A), sub_64), 1))>; 28230b57cec5SDimitry Andricdef : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.A, 28240b57cec5SDimitry Andric DblToUInt.A, DblToUInt.A)), 2825fe6060f1SDimitry Andric (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS $A), sub_64), 1))>; 28260b57cec5SDimitry Andricdef : Pat<(v2i64 (build_vector DblToLong.A, DblToLong.A)), 2827fe6060f1SDimitry Andric (v2i64 (XXPERMDI (SUBREG_TO_REG (i64 1), (XSCVDPSXDS $A), sub_64), 2828fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPSXDS $A), sub_64), 0))>; 28290b57cec5SDimitry Andricdef : Pat<(v2i64 (build_vector DblToULong.A, DblToULong.A)), 2830fe6060f1SDimitry Andric (v2i64 (XXPERMDI (SUBREG_TO_REG (i64 1), (XSCVDPUXDS $A), sub_64), 2831fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPUXDS $A), sub_64), 0))>; 2832349cc55cSDimitry Andricdef : Pat<(v4i32 (PPCSToV DblToInt.A)), 2833349cc55cSDimitry Andric (v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS f64:$A), sub_64))>; 2834349cc55cSDimitry Andricdef : Pat<(v4i32 (PPCSToV DblToUInt.A)), 2835349cc55cSDimitry Andric (v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPUXWS f64:$A), sub_64))>; 28365ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 28375ffd83dbSDimitry Andric v4i32, FltToIntLoad.A, 2838fe6060f1SDimitry Andric (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1), 2839fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>; 28405ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 28415ffd83dbSDimitry Andric v4i32, FltToUIntLoad.A, 2842fe6060f1SDimitry Andric (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1), 2843fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>; 2844fe6060f1SDimitry Andricdef : Pat<(v4f32 (build_vector (f32 (fpround f64:$A)), (f32 (fpround f64:$A)), 2845fe6060f1SDimitry Andric (f32 (fpround f64:$A)), (f32 (fpround f64:$A)))), 2846fe6060f1SDimitry Andric (v4f32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$A), sub_64), 0))>; 2847fe6060f1SDimitry Andric 28480b57cec5SDimitry Andricdef : Pat<(v4f32 (build_vector f32:$A, f32:$A, f32:$A, f32:$A)), 28490b57cec5SDimitry Andric (v4f32 (XXSPLTW (v4f32 (XSCVDPSPN $A)), 0))>; 2850349cc55cSDimitry Andric 2851349cc55cSDimitry Andric// Splat loads. 2852fe6060f1SDimitry Andricdef : Pat<(v2f64 (PPCldsplat ForceXForm:$A)), 2853fe6060f1SDimitry Andric (v2f64 (LXVDSX ForceXForm:$A))>; 2854349cc55cSDimitry Andricdef : Pat<(v4f32 (PPCldsplat ForceXForm:$A)), 2855349cc55cSDimitry Andric (v4f32 (XXSPLTW (SUBREG_TO_REG (i64 1), (LFIWZX ForceXForm:$A), sub_64), 1))>; 2856fe6060f1SDimitry Andricdef : Pat<(v2i64 (PPCldsplat ForceXForm:$A)), 2857fe6060f1SDimitry Andric (v2i64 (LXVDSX ForceXForm:$A))>; 2858349cc55cSDimitry Andricdef : Pat<(v4i32 (PPCldsplat ForceXForm:$A)), 2859349cc55cSDimitry Andric (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (LFIWZX ForceXForm:$A), sub_64), 1))>; 2860349cc55cSDimitry Andricdef : Pat<(v2i64 (PPCzextldsplat ForceXForm:$A)), 2861349cc55cSDimitry Andric (v2i64 (XXPERMDIs (LFIWZX ForceXForm:$A), 0))>; 2862349cc55cSDimitry Andricdef : Pat<(v2i64 (PPCsextldsplat ForceXForm:$A)), 2863349cc55cSDimitry Andric (v2i64 (XXPERMDIs (LFIWAX ForceXForm:$A), 0))>; 28640b57cec5SDimitry Andric 28650b57cec5SDimitry Andric// Build vectors of floating point converted to i64. 28660b57cec5SDimitry Andricdef : Pat<(v2i64 (build_vector FltToLong.A, FltToLong.A)), 28670b57cec5SDimitry Andric (v2i64 (XXPERMDIs 28680b57cec5SDimitry Andric (COPY_TO_REGCLASS (XSCVDPSXDSs $A), VSFRC), 0))>; 28690b57cec5SDimitry Andricdef : Pat<(v2i64 (build_vector FltToULong.A, FltToULong.A)), 28700b57cec5SDimitry Andric (v2i64 (XXPERMDIs 28710b57cec5SDimitry Andric (COPY_TO_REGCLASS (XSCVDPUXDSs $A), VSFRC), 0))>; 28725ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 28735ffd83dbSDimitry Andric v2i64, DblToLongLoad.A, 2874fe6060f1SDimitry Andric (XVCVDPSXDS (LXVDSX ForceXForm:$A)), (XVCVDPSXDS (LXVDSX ForceXForm:$A))>; 28755ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 28765ffd83dbSDimitry Andric v2i64, DblToULongLoad.A, 2877fe6060f1SDimitry Andric (XVCVDPUXDS (LXVDSX ForceXForm:$A)), (XVCVDPUXDS (LXVDSX ForceXForm:$A))>; 2878fe6060f1SDimitry Andric 2879fe6060f1SDimitry Andric// Doubleword vector predicate comparisons without Power8. 2880fe6060f1SDimitry Andriclet AddedComplexity = 0 in { 2881fe6060f1SDimitry Andricdef : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 967)), 2882fe6060f1SDimitry Andric (VCMPGTUB_rec DblwdCmp.MRGSGT, (v2i64 (XXLXORz)))>; 2883fe6060f1SDimitry Andricdef : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 711)), 2884fe6060f1SDimitry Andric (VCMPGTUB_rec DblwdCmp.MRGUGT, (v2i64 (XXLXORz)))>; 2885fe6060f1SDimitry Andricdef : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 199)), 2886fe6060f1SDimitry Andric (VCMPGTUB_rec DblwdCmp.MRGEQ, (v2i64 (XXLXORz)))>; 2887fe6060f1SDimitry Andric} // AddedComplexity = 0 2888fe6060f1SDimitry Andric 2889fe6060f1SDimitry Andric// XL Compat builtins. 2890fe6060f1SDimitry Andricdef : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (XSMSUBMDP $A, $B, $C)>; 2891fe6060f1SDimitry Andricdef : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (XSNMADDMDP $A, $B, $C)>; 2892fe6060f1SDimitry Andricdef : Pat<(int_ppc_fre f64:$A), (XSREDP $A)>; 2893fe6060f1SDimitry Andricdef : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>; 289481ad6265SDimitry Andricdef : Pat<(int_ppc_fnabs f64:$A), (XSNABSDP $A)>; 289581ad6265SDimitry Andricdef : Pat<(int_ppc_fnabss f32:$A), (XSNABSDPs $A)>; 289681ad6265SDimitry Andric 289781ad6265SDimitry Andric// XXMRG[LH]W is a direct replacement for VMRG[LH]W respectively. 289881ad6265SDimitry Andric// Prefer the VSX form for greater register range. 289981ad6265SDimitry Andricdef:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef), 290081ad6265SDimitry Andric (COPY_TO_REGCLASS (XXMRGLW (COPY_TO_REGCLASS $vA, VSRC), 290181ad6265SDimitry Andric (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>; 290281ad6265SDimitry Andricdef:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef), 290381ad6265SDimitry Andric (COPY_TO_REGCLASS (XXMRGHW (COPY_TO_REGCLASS $vA, VSRC), 290481ad6265SDimitry Andric (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>; 290581ad6265SDimitry Andricdef:Pat<(vmrglw_shuffle v16i8:$vA, v16i8:$vB), 290681ad6265SDimitry Andric (COPY_TO_REGCLASS (XXMRGLW (COPY_TO_REGCLASS $vA, VSRC), 290781ad6265SDimitry Andric (COPY_TO_REGCLASS $vB, VSRC)), VRRC)>; 290881ad6265SDimitry Andricdef:Pat<(vmrghw_shuffle v16i8:$vA, v16i8:$vB), 290981ad6265SDimitry Andric (COPY_TO_REGCLASS (XXMRGHW (COPY_TO_REGCLASS $vA, VSRC), 291081ad6265SDimitry Andric (COPY_TO_REGCLASS $vB, VSRC)), VRRC)>; 291181ad6265SDimitry Andricdef:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB), 291281ad6265SDimitry Andric (COPY_TO_REGCLASS (XXMRGLW (COPY_TO_REGCLASS $vB, VSRC), 291381ad6265SDimitry Andric (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>; 291481ad6265SDimitry Andricdef:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB), 291581ad6265SDimitry Andric (COPY_TO_REGCLASS (XXMRGHW (COPY_TO_REGCLASS $vB, VSRC), 291681ad6265SDimitry Andric (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>; 291706c3fb27SDimitry Andricdef : Pat<(PPCstore_scal_int_from_vsr f64:$src, XForm:$dst, 8), 291806c3fb27SDimitry Andric (STXSDX $src, XForm:$dst)>; 291906c3fb27SDimitry Andricdef : Pat<(PPCstore_scal_int_from_vsr f128:$src, XForm:$dst, 8), 292006c3fb27SDimitry Andric (STXSDX (COPY_TO_REGCLASS $src, VSFRC), XForm:$dst)>; 29215ffd83dbSDimitry Andric} // HasVSX 29220b57cec5SDimitry Andric 29235ffd83dbSDimitry Andric// Any big endian VSX subtarget. 29245ffd83dbSDimitry Andriclet Predicates = [HasVSX, IsBigEndian] in { 29255ffd83dbSDimitry Andricdef : Pat<(v2f64 (scalar_to_vector f64:$A)), 29265ffd83dbSDimitry Andric (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>; 29270b57cec5SDimitry Andric 29285ffd83dbSDimitry Andricdef : Pat<(f64 (extractelt v2f64:$S, 0)), 29295ffd83dbSDimitry Andric (f64 (EXTRACT_SUBREG $S, sub_64))>; 29305ffd83dbSDimitry Andricdef : Pat<(f64 (extractelt v2f64:$S, 1)), 29315ffd83dbSDimitry Andric (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>; 29325ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))), 29335ffd83dbSDimitry Andric (f64 (XSCVSXDDP (COPY_TO_REGCLASS $S, VSFRC)))>; 29345ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))), 29355ffd83dbSDimitry Andric (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; 29365ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))), 29375ffd83dbSDimitry Andric (f64 (XSCVUXDDP (COPY_TO_REGCLASS $S, VSFRC)))>; 29385ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))), 29395ffd83dbSDimitry Andric (f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; 29400b57cec5SDimitry Andric 29415ffd83dbSDimitry Andricdef : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)), 29425ffd83dbSDimitry Andric (f64 VectorExtractions.BE_VARIABLE_DOUBLE)>; 29430b57cec5SDimitry Andric 29440b57cec5SDimitry Andricdef : Pat<(v2f64 (build_vector f64:$A, f64:$B)), 29450b57cec5SDimitry Andric (v2f64 (XXPERMDI 2946fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), $A, sub_64), 2947fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>; 2948480093f4SDimitry Andric// Using VMRGEW to assemble the final vector would be a lower latency 2949480093f4SDimitry Andric// solution. However, we choose to go with the slightly higher latency 2950480093f4SDimitry Andric// XXPERMDI for 2 reasons: 2951480093f4SDimitry Andric// 1. This is likely to occur in unrolled loops where regpressure is high, 2952480093f4SDimitry Andric// so we want to use the latter as it has access to all 64 VSX registers. 2953480093f4SDimitry Andric// 2. Using Altivec instructions in this sequence would likely cause the 2954480093f4SDimitry Andric// allocation of Altivec registers even for the loads which in turn would 2955480093f4SDimitry Andric// force the use of LXSIWZX for the loads, adding a cycle of latency to 2956480093f4SDimitry Andric// each of the loads which would otherwise be able to use LFIWZX. 2957480093f4SDimitry Andricdef : Pat<(v4f32 (build_vector LoadFP.A, LoadFP.B, LoadFP.C, LoadFP.D)), 2958480093f4SDimitry Andric (v4f32 (XXPERMDI (XXMRGHW MrgFP.LD32A, MrgFP.LD32B), 2959480093f4SDimitry Andric (XXMRGHW MrgFP.LD32C, MrgFP.LD32D), 3))>; 29600b57cec5SDimitry Andricdef : Pat<(v4f32 (build_vector f32:$A, f32:$B, f32:$C, f32:$D)), 29610b57cec5SDimitry Andric (VMRGEW MrgFP.AC, MrgFP.BD)>; 29620b57cec5SDimitry Andricdef : Pat<(v4f32 (build_vector DblToFlt.A0, DblToFlt.A1, 29630b57cec5SDimitry Andric DblToFlt.B0, DblToFlt.B1)), 29640b57cec5SDimitry Andric (v4f32 (VMRGEW MrgFP.ABhToFlt, MrgFP.ABlToFlt))>; 29650b57cec5SDimitry Andric 29660b57cec5SDimitry Andric// Convert 4 doubles to a vector of ints. 29670b57cec5SDimitry Andricdef : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.B, 29680b57cec5SDimitry Andric DblToInt.C, DblToInt.D)), 29690b57cec5SDimitry Andric (v4i32 (VMRGEW MrgWords.CVACS, MrgWords.CVBDS))>; 29700b57cec5SDimitry Andricdef : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.B, 29710b57cec5SDimitry Andric DblToUInt.C, DblToUInt.D)), 29720b57cec5SDimitry Andric (v4i32 (VMRGEW MrgWords.CVACU, MrgWords.CVBDU))>; 29730b57cec5SDimitry Andricdef : Pat<(v4i32 (build_vector ExtDbl.A0S, ExtDbl.A1S, 29740b57cec5SDimitry Andric ExtDbl.B0S, ExtDbl.B1S)), 29750b57cec5SDimitry Andric (v4i32 (VMRGEW MrgWords.CVA0B0S, MrgWords.CVA1B1S))>; 29760b57cec5SDimitry Andricdef : Pat<(v4i32 (build_vector ExtDbl.A0U, ExtDbl.A1U, 29770b57cec5SDimitry Andric ExtDbl.B0U, ExtDbl.B1U)), 29780b57cec5SDimitry Andric (v4i32 (VMRGEW MrgWords.CVA0B0U, MrgWords.CVA1B1U))>; 29795ffd83dbSDimitry Andricdef : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 29805ffd83dbSDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 1))))), 29815ffd83dbSDimitry Andric (v2f64 (XVCVSPDP (XXMRGHW $A, $A)))>; 29825ffd83dbSDimitry Andricdef : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 29835ffd83dbSDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 0))))), 29845ffd83dbSDimitry Andric (v2f64 (XXPERMDI (XVCVSPDP (XXMRGHW $A, $A)), 29855ffd83dbSDimitry Andric (XVCVSPDP (XXMRGHW $A, $A)), 2))>; 29865ffd83dbSDimitry Andricdef : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 29875ffd83dbSDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 2))))), 29885ffd83dbSDimitry Andric (v2f64 (XVCVSPDP $A))>; 29895ffd83dbSDimitry Andricdef : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 29905ffd83dbSDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 3))))), 299106c3fb27SDimitry Andric (v2f64 (XVCVSPDP (XXSLDWI $A, $A, 1)))>; 29925ffd83dbSDimitry Andricdef : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 2))), 29935ffd83dbSDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 3))))), 29945ffd83dbSDimitry Andric (v2f64 (XVCVSPDP (XXMRGLW $A, $A)))>; 29955ffd83dbSDimitry Andricdef : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))), 29965ffd83dbSDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 2))))), 29975ffd83dbSDimitry Andric (v2f64 (XXPERMDI (XVCVSPDP (XXMRGLW $A, $A)), 29985ffd83dbSDimitry Andric (XVCVSPDP (XXMRGLW $A, $A)), 2))>; 29995ffd83dbSDimitry Andricdef : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 30005ffd83dbSDimitry Andric (f64 (fpextend (extractelt v4f32:$B, 0))))), 30015ffd83dbSDimitry Andric (v2f64 (XVCVSPDP (XXPERMDI $A, $B, 0)))>; 30025ffd83dbSDimitry Andricdef : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))), 30035ffd83dbSDimitry Andric (f64 (fpextend (extractelt v4f32:$B, 3))))), 30045ffd83dbSDimitry Andric (v2f64 (XVCVSPDP (XXSLDWI (XXPERMDI $A, $B, 3), 30055ffd83dbSDimitry Andric (XXPERMDI $A, $B, 3), 1)))>; 3006fe6060f1SDimitry Andricdef : Pat<(v2i64 (fp_to_sint 3007fe6060f1SDimitry Andric (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 3008fe6060f1SDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 2)))))), 3009fe6060f1SDimitry Andric (v2i64 (XVCVSPSXDS $A))>; 3010fe6060f1SDimitry Andricdef : Pat<(v2i64 (fp_to_uint 3011fe6060f1SDimitry Andric (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 3012fe6060f1SDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 2)))))), 3013fe6060f1SDimitry Andric (v2i64 (XVCVSPUXDS $A))>; 3014fe6060f1SDimitry Andricdef : Pat<(v2i64 (fp_to_sint 3015fe6060f1SDimitry Andric (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 3016fe6060f1SDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 3)))))), 3017fe6060f1SDimitry Andric (v2i64 (XVCVSPSXDS (XXSLDWI $A, $A, 1)))>; 3018fe6060f1SDimitry Andricdef : Pat<(v2i64 (fp_to_uint 3019fe6060f1SDimitry Andric (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 3020fe6060f1SDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 3)))))), 3021fe6060f1SDimitry Andric (v2i64 (XVCVSPUXDS (XXSLDWI $A, $A, 1)))>; 30225ffd83dbSDimitry Andricdef : Pat<WToDPExtractConv.BV02S, 30235ffd83dbSDimitry Andric (v2f64 (XVCVSXWDP $A))>; 30245ffd83dbSDimitry Andricdef : Pat<WToDPExtractConv.BV13S, 3025349cc55cSDimitry Andric (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 1)))>; 30265ffd83dbSDimitry Andricdef : Pat<WToDPExtractConv.BV02U, 30275ffd83dbSDimitry Andric (v2f64 (XVCVUXWDP $A))>; 30285ffd83dbSDimitry Andricdef : Pat<WToDPExtractConv.BV13U, 3029349cc55cSDimitry Andric (v2f64 (XVCVUXWDP (XXSLDWI $A, $A, 1)))>; 3030fe6060f1SDimitry Andricdef : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 0)), 3031fe6060f1SDimitry Andric (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), $A, 1))>; 3032fe6060f1SDimitry Andricdef : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 1)), 3033fe6060f1SDimitry Andric (v2f64 (XXPERMDI $A, (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>; 30345ffd83dbSDimitry Andric} // HasVSX, IsBigEndian 30350b57cec5SDimitry Andric 30365ffd83dbSDimitry Andric// Any little endian VSX subtarget. 30375ffd83dbSDimitry Andriclet Predicates = [HasVSX, IsLittleEndian] in { 30385ffd83dbSDimitry Andricdefm : ScalToVecWPermute<v2f64, (f64 f64:$A), 30395ffd83dbSDimitry Andric (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64), 30405ffd83dbSDimitry Andric (SUBREG_TO_REG (i64 1), $A, sub_64), 0), 30415ffd83dbSDimitry Andric (SUBREG_TO_REG (i64 1), $A, sub_64)>; 30420b57cec5SDimitry Andric 30435ffd83dbSDimitry Andricdef : Pat<(f64 (extractelt v2f64:$S, 0)), 30445ffd83dbSDimitry Andric (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>; 30455ffd83dbSDimitry Andricdef : Pat<(f64 (extractelt v2f64:$S, 1)), 30465ffd83dbSDimitry Andric (f64 (EXTRACT_SUBREG $S, sub_64))>; 30470b57cec5SDimitry Andric 3048fe6060f1SDimitry Andricdef : Pat<(v2f64 (PPCld_vec_be ForceXForm:$src)), (LXVD2X ForceXForm:$src)>; 3049fe6060f1SDimitry Andricdef : Pat<(PPCst_vec_be v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>; 3050fe6060f1SDimitry Andricdef : Pat<(v4f32 (PPCld_vec_be ForceXForm:$src)), (LXVW4X ForceXForm:$src)>; 3051fe6060f1SDimitry Andricdef : Pat<(PPCst_vec_be v4f32:$rS, ForceXForm:$dst), (STXVW4X $rS, ForceXForm:$dst)>; 3052fe6060f1SDimitry Andricdef : Pat<(v2i64 (PPCld_vec_be ForceXForm:$src)), (LXVD2X ForceXForm:$src)>; 3053fe6060f1SDimitry Andricdef : Pat<(PPCst_vec_be v2i64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>; 3054fe6060f1SDimitry Andricdef : Pat<(v4i32 (PPCld_vec_be ForceXForm:$src)), (LXVW4X ForceXForm:$src)>; 3055fe6060f1SDimitry Andricdef : Pat<(PPCst_vec_be v4i32:$rS, ForceXForm:$dst), (STXVW4X $rS, ForceXForm:$dst)>; 30565ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))), 30575ffd83dbSDimitry Andric (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; 30585ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))), 30595ffd83dbSDimitry Andric (f64 (XSCVSXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>; 30605ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))), 30615ffd83dbSDimitry Andric (f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; 30625ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))), 30635ffd83dbSDimitry Andric (f64 (XSCVUXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>; 30640b57cec5SDimitry Andric 30655ffd83dbSDimitry Andricdef : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)), 30665ffd83dbSDimitry Andric (f64 VectorExtractions.LE_VARIABLE_DOUBLE)>; 30675ffd83dbSDimitry Andric 30680b57cec5SDimitry Andric// Little endian, available on all targets with VSX 30690b57cec5SDimitry Andricdef : Pat<(v2f64 (build_vector f64:$A, f64:$B)), 30700b57cec5SDimitry Andric (v2f64 (XXPERMDI 3071fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), $B, sub_64), 3072fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), $A, sub_64), 0))>; 3073480093f4SDimitry Andric// Using VMRGEW to assemble the final vector would be a lower latency 3074480093f4SDimitry Andric// solution. However, we choose to go with the slightly higher latency 3075480093f4SDimitry Andric// XXPERMDI for 2 reasons: 3076480093f4SDimitry Andric// 1. This is likely to occur in unrolled loops where regpressure is high, 3077480093f4SDimitry Andric// so we want to use the latter as it has access to all 64 VSX registers. 3078480093f4SDimitry Andric// 2. Using Altivec instructions in this sequence would likely cause the 3079480093f4SDimitry Andric// allocation of Altivec registers even for the loads which in turn would 3080480093f4SDimitry Andric// force the use of LXSIWZX for the loads, adding a cycle of latency to 3081480093f4SDimitry Andric// each of the loads which would otherwise be able to use LFIWZX. 3082480093f4SDimitry Andricdef : Pat<(v4f32 (build_vector LoadFP.A, LoadFP.B, LoadFP.C, LoadFP.D)), 3083480093f4SDimitry Andric (v4f32 (XXPERMDI (XXMRGHW MrgFP.LD32D, MrgFP.LD32C), 3084480093f4SDimitry Andric (XXMRGHW MrgFP.LD32B, MrgFP.LD32A), 3))>; 30850b57cec5SDimitry Andricdef : Pat<(v4f32 (build_vector f32:$D, f32:$C, f32:$B, f32:$A)), 30860b57cec5SDimitry Andric (VMRGEW MrgFP.AC, MrgFP.BD)>; 30870b57cec5SDimitry Andricdef : Pat<(v4f32 (build_vector DblToFlt.A0, DblToFlt.A1, 30880b57cec5SDimitry Andric DblToFlt.B0, DblToFlt.B1)), 30890b57cec5SDimitry Andric (v4f32 (VMRGEW MrgFP.BAhToFlt, MrgFP.BAlToFlt))>; 30900b57cec5SDimitry Andric 30910b57cec5SDimitry Andric// Convert 4 doubles to a vector of ints. 30920b57cec5SDimitry Andricdef : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.B, 30930b57cec5SDimitry Andric DblToInt.C, DblToInt.D)), 30940b57cec5SDimitry Andric (v4i32 (VMRGEW MrgWords.CVDBS, MrgWords.CVCAS))>; 30950b57cec5SDimitry Andricdef : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.B, 30960b57cec5SDimitry Andric DblToUInt.C, DblToUInt.D)), 30970b57cec5SDimitry Andric (v4i32 (VMRGEW MrgWords.CVDBU, MrgWords.CVCAU))>; 30980b57cec5SDimitry Andricdef : Pat<(v4i32 (build_vector ExtDbl.A0S, ExtDbl.A1S, 30990b57cec5SDimitry Andric ExtDbl.B0S, ExtDbl.B1S)), 31000b57cec5SDimitry Andric (v4i32 (VMRGEW MrgWords.CVB1A1S, MrgWords.CVB0A0S))>; 31010b57cec5SDimitry Andricdef : Pat<(v4i32 (build_vector ExtDbl.A0U, ExtDbl.A1U, 31020b57cec5SDimitry Andric ExtDbl.B0U, ExtDbl.B1U)), 31030b57cec5SDimitry Andric (v4i32 (VMRGEW MrgWords.CVB1A1U, MrgWords.CVB0A0U))>; 31045ffd83dbSDimitry Andricdef : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 31055ffd83dbSDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 1))))), 31065ffd83dbSDimitry Andric (v2f64 (XVCVSPDP (XXMRGLW $A, $A)))>; 31075ffd83dbSDimitry Andricdef : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 31085ffd83dbSDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 0))))), 31095ffd83dbSDimitry Andric (v2f64 (XXPERMDI (XVCVSPDP (XXMRGLW $A, $A)), 31105ffd83dbSDimitry Andric (XVCVSPDP (XXMRGLW $A, $A)), 2))>; 31115ffd83dbSDimitry Andricdef : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 31125ffd83dbSDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 2))))), 31135ffd83dbSDimitry Andric (v2f64 (XVCVSPDP (XXSLDWI $A, $A, 1)))>; 31145ffd83dbSDimitry Andricdef : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 31155ffd83dbSDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 3))))), 31165ffd83dbSDimitry Andric (v2f64 (XVCVSPDP $A))>; 31175ffd83dbSDimitry Andricdef : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 2))), 31185ffd83dbSDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 3))))), 31195ffd83dbSDimitry Andric (v2f64 (XVCVSPDP (XXMRGHW $A, $A)))>; 31205ffd83dbSDimitry Andricdef : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))), 31215ffd83dbSDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 2))))), 31225ffd83dbSDimitry Andric (v2f64 (XXPERMDI (XVCVSPDP (XXMRGHW $A, $A)), 31235ffd83dbSDimitry Andric (XVCVSPDP (XXMRGHW $A, $A)), 2))>; 31245ffd83dbSDimitry Andricdef : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 31255ffd83dbSDimitry Andric (f64 (fpextend (extractelt v4f32:$B, 0))))), 31265ffd83dbSDimitry Andric (v2f64 (XVCVSPDP (XXSLDWI (XXPERMDI $B, $A, 3), 31275ffd83dbSDimitry Andric (XXPERMDI $B, $A, 3), 1)))>; 31285ffd83dbSDimitry Andricdef : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))), 31295ffd83dbSDimitry Andric (f64 (fpextend (extractelt v4f32:$B, 3))))), 31305ffd83dbSDimitry Andric (v2f64 (XVCVSPDP (XXPERMDI $B, $A, 0)))>; 3131fe6060f1SDimitry Andricdef : Pat<(v2i64 (fp_to_sint 3132fe6060f1SDimitry Andric (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 3133fe6060f1SDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 3)))))), 3134fe6060f1SDimitry Andric (v2i64 (XVCVSPSXDS $A))>; 3135fe6060f1SDimitry Andricdef : Pat<(v2i64 (fp_to_uint 3136fe6060f1SDimitry Andric (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 3137fe6060f1SDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 3)))))), 3138fe6060f1SDimitry Andric (v2i64 (XVCVSPUXDS $A))>; 3139fe6060f1SDimitry Andricdef : Pat<(v2i64 (fp_to_sint 3140fe6060f1SDimitry Andric (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 3141fe6060f1SDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 2)))))), 3142fe6060f1SDimitry Andric (v2i64 (XVCVSPSXDS (XXSLDWI $A, $A, 1)))>; 3143fe6060f1SDimitry Andricdef : Pat<(v2i64 (fp_to_uint 3144fe6060f1SDimitry Andric (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 3145fe6060f1SDimitry Andric (f64 (fpextend (extractelt v4f32:$A, 2)))))), 3146fe6060f1SDimitry Andric (v2i64 (XVCVSPUXDS (XXSLDWI $A, $A, 1)))>; 31475ffd83dbSDimitry Andricdef : Pat<WToDPExtractConv.BV02S, 31485ffd83dbSDimitry Andric (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 1)))>; 31495ffd83dbSDimitry Andricdef : Pat<WToDPExtractConv.BV13S, 31505ffd83dbSDimitry Andric (v2f64 (XVCVSXWDP $A))>; 31515ffd83dbSDimitry Andricdef : Pat<WToDPExtractConv.BV02U, 31525ffd83dbSDimitry Andric (v2f64 (XVCVUXWDP (XXSLDWI $A, $A, 1)))>; 31535ffd83dbSDimitry Andricdef : Pat<WToDPExtractConv.BV13U, 31545ffd83dbSDimitry Andric (v2f64 (XVCVUXWDP $A))>; 3155fe6060f1SDimitry Andricdef : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 0)), 3156fe6060f1SDimitry Andric (v2f64 (XXPERMDI $A, (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>; 3157fe6060f1SDimitry Andricdef : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 1)), 3158fe6060f1SDimitry Andric (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), $A, 1))>; 31595ffd83dbSDimitry Andric} // HasVSX, IsLittleEndian 31600b57cec5SDimitry Andric 31615ffd83dbSDimitry Andric// Any pre-Power9 VSX subtarget. 31625ffd83dbSDimitry Andriclet Predicates = [HasVSX, NoP9Vector] in { 316306c3fb27SDimitry Andricdef : Pat<(PPCstore_scal_int_from_vsr f64:$src, ForceXForm:$dst, 8), 316406c3fb27SDimitry Andric (STXSDX $src, ForceXForm:$dst)>; 316506c3fb27SDimitry Andricdef : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 8), 316606c3fb27SDimitry Andric (STXSDX (COPY_TO_REGCLASS $src, VSFRC), ForceXForm:$dst)>; 31675ffd83dbSDimitry Andric 31685ffd83dbSDimitry Andric// Load-and-splat with fp-to-int conversion (using X-Form VSX/FP loads). 31695ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 31705ffd83dbSDimitry Andric v4i32, DblToIntLoad.A, 3171fe6060f1SDimitry Andric (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1), 3172fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64)>; 31735ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 31745ffd83dbSDimitry Andric v4i32, DblToUIntLoad.A, 3175fe6060f1SDimitry Andric (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1), 3176fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64)>; 31775ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 31785ffd83dbSDimitry Andric v2i64, FltToLongLoad.A, 3179fe6060f1SDimitry Andric (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), 0), 3180fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), 31815ffd83dbSDimitry Andric VSFRC)), sub_64)>; 31825ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 31835ffd83dbSDimitry Andric v2i64, FltToULongLoad.A, 3184fe6060f1SDimitry Andric (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), 0), 3185fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), 31865ffd83dbSDimitry Andric VSFRC)), sub_64)>; 31875ffd83dbSDimitry Andric} // HasVSX, NoP9Vector 31885ffd83dbSDimitry Andric 3189e8d8bef9SDimitry Andric// Any little endian pre-Power9 VSX subtarget. 3190e8d8bef9SDimitry Andriclet Predicates = [HasVSX, NoP9Vector, IsLittleEndian] in { 3191e8d8bef9SDimitry Andric// Load-and-splat using only X-Form VSX loads. 3192e8d8bef9SDimitry Andricdefm : ScalToVecWPermute< 3193fe6060f1SDimitry Andric v2i64, (i64 (load ForceXForm:$src)), 3194fe6060f1SDimitry Andric (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2), 3195fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>; 3196e8d8bef9SDimitry Andricdefm : ScalToVecWPermute< 3197fe6060f1SDimitry Andric v2f64, (f64 (load ForceXForm:$src)), 3198fe6060f1SDimitry Andric (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2), 3199fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>; 32000eae32dcSDimitry Andric 32010eae32dcSDimitry Andric// Splat loads. 32020eae32dcSDimitry Andricdef : Pat<(v8i16 (PPCldsplatAlign16 ForceXForm:$A)), 32030eae32dcSDimitry Andric (v8i16 (VSPLTH 7, (LVX ForceXForm:$A)))>; 32040eae32dcSDimitry Andricdef : Pat<(v16i8 (PPCldsplatAlign16 ForceXForm:$A)), 32050eae32dcSDimitry Andric (v16i8 (VSPLTB 15, (LVX ForceXForm:$A)))>; 3206e8d8bef9SDimitry Andric} // HasVSX, NoP9Vector, IsLittleEndian 3207e8d8bef9SDimitry Andric 3208fe6060f1SDimitry Andriclet Predicates = [HasVSX, NoP9Vector, IsBigEndian] in { 3209fe6060f1SDimitry Andric def : Pat<(v2f64 (int_ppc_vsx_lxvd2x ForceXForm:$src)), 3210fe6060f1SDimitry Andric (LXVD2X ForceXForm:$src)>; 3211fe6060f1SDimitry Andric def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, ForceXForm:$dst), 3212fe6060f1SDimitry Andric (STXVD2X $rS, ForceXForm:$dst)>; 32130eae32dcSDimitry Andric 32140eae32dcSDimitry Andric // Splat loads. 32150eae32dcSDimitry Andric def : Pat<(v8i16 (PPCldsplatAlign16 ForceXForm:$A)), 32160eae32dcSDimitry Andric (v8i16 (VSPLTH 0, (LVX ForceXForm:$A)))>; 32170eae32dcSDimitry Andric def : Pat<(v16i8 (PPCldsplatAlign16 ForceXForm:$A)), 32180eae32dcSDimitry Andric (v16i8 (VSPLTB 0, (LVX ForceXForm:$A)))>; 3219fe6060f1SDimitry Andric} // HasVSX, NoP9Vector, IsBigEndian 3220fe6060f1SDimitry Andric 32215ffd83dbSDimitry Andric// Any VSX subtarget that only has loads and stores that load in big endian 32225ffd83dbSDimitry Andric// order regardless of endianness. This is really pre-Power9 subtargets. 32235ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasOnlySwappingMemOps] in { 3224fe6060f1SDimitry Andric def : Pat<(v2f64 (PPClxvd2x ForceXForm:$src)), (LXVD2X ForceXForm:$src)>; 32255ffd83dbSDimitry Andric 32265ffd83dbSDimitry Andric // Stores. 3227fe6060f1SDimitry Andric def : Pat<(PPCstxvd2x v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>; 32285ffd83dbSDimitry Andric} // HasVSX, HasOnlySwappingMemOps 32295ffd83dbSDimitry Andric 3230e8d8bef9SDimitry Andric// Big endian VSX subtarget that only has loads and stores that always 3231e8d8bef9SDimitry Andric// load in big endian order. Really big endian pre-Power9 subtargets. 32325ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasOnlySwappingMemOps, IsBigEndian] in { 3233fe6060f1SDimitry Andric def : Pat<(v2f64 (load ForceXForm:$src)), (LXVD2X ForceXForm:$src)>; 3234fe6060f1SDimitry Andric def : Pat<(v2i64 (load ForceXForm:$src)), (LXVD2X ForceXForm:$src)>; 3235fe6060f1SDimitry Andric def : Pat<(v4i32 (load ForceXForm:$src)), (LXVW4X ForceXForm:$src)>; 3236fe6060f1SDimitry Andric def : Pat<(v4i32 (int_ppc_vsx_lxvw4x ForceXForm:$src)), (LXVW4X ForceXForm:$src)>; 3237fe6060f1SDimitry Andric def : Pat<(store v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>; 3238fe6060f1SDimitry Andric def : Pat<(store v2i64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>; 3239fe6060f1SDimitry Andric def : Pat<(store v4i32:$XT, ForceXForm:$dst), (STXVW4X $XT, ForceXForm:$dst)>; 3240fe6060f1SDimitry Andric def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, ForceXForm:$dst), 3241fe6060f1SDimitry Andric (STXVW4X $rS, ForceXForm:$dst)>; 3242fe6060f1SDimitry Andric def : Pat<(v2i64 (scalar_to_vector (i64 (load ForceXForm:$src)))), 3243fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>; 32445ffd83dbSDimitry Andric} // HasVSX, HasOnlySwappingMemOps, IsBigEndian 32455ffd83dbSDimitry Andric 324606c3fb27SDimitry Andric// Target before Power8 with VSX. 324706c3fb27SDimitry Andriclet Predicates = [HasVSX, NoP8Vector] in { 324806c3fb27SDimitry Andricdef : Pat<(f32 (fpimm0neg)), 324906c3fb27SDimitry Andric (f32 (COPY_TO_REGCLASS (XSNEGDP (XXLXORdpz)), F4RC))>; 325006c3fb27SDimitry Andric 325106c3fb27SDimitry Andricdef : Pat<(f32 (nzFPImmExactInti5:$A)), 325206c3fb27SDimitry Andric (COPY_TO_REGCLASS (XVCVSXWDP (COPY_TO_REGCLASS 325306c3fb27SDimitry Andric (VSPLTISW (getFPAs5BitExactInt fpimm:$A)), VSRC)), F4RC)>; 325406c3fb27SDimitry Andric 325506c3fb27SDimitry Andric} // HasVSX, NoP8Vector 325606c3fb27SDimitry Andric 32575ffd83dbSDimitry Andric// Any Power8 VSX subtarget. 32585ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasP8Vector] in { 32595ffd83dbSDimitry Andricdef : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B), 32605ffd83dbSDimitry Andric (XXLEQV $A, $B)>; 3261fe6060f1SDimitry Andricdef : Pat<(f64 (extloadf32 XForm:$src)), 3262fe6060f1SDimitry Andric (COPY_TO_REGCLASS (XFLOADf32 XForm:$src), VSFRC)>; 3263fe6060f1SDimitry Andricdef : Pat<(f32 (fpround (f64 (extloadf32 ForceXForm:$src)))), 3264fe6060f1SDimitry Andric (f32 (XFLOADf32 ForceXForm:$src))>; 32655ffd83dbSDimitry Andricdef : Pat<(f64 (any_fpextend f32:$src)), 32665ffd83dbSDimitry Andric (COPY_TO_REGCLASS $src, VSFRC)>; 32675ffd83dbSDimitry Andric 326806c3fb27SDimitry Andricdef : Pat<(f32 (fpimm0neg)), 326906c3fb27SDimitry Andric (f32 (COPY_TO_REGCLASS (XSNEGDP (XXLXORdpz)), VSSRC))>; 327006c3fb27SDimitry Andric 327106c3fb27SDimitry Andricdef : Pat<(f32 (nzFPImmExactInti5:$A)), 327206c3fb27SDimitry Andric (COPY_TO_REGCLASS (XVCVSXWDP (COPY_TO_REGCLASS 327306c3fb27SDimitry Andric (VSPLTISW (getFPAs5BitExactInt fpimm:$A)), VSRC)), VSSRC)>; 327406c3fb27SDimitry Andric 32755ffd83dbSDimitry Andricdef : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 32765ffd83dbSDimitry Andric (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>; 32775ffd83dbSDimitry Andricdef : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 32785ffd83dbSDimitry Andric (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>; 32795ffd83dbSDimitry Andricdef : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 32805ffd83dbSDimitry Andric (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>; 32815ffd83dbSDimitry Andricdef : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 32825ffd83dbSDimitry Andric (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>; 32835ffd83dbSDimitry Andricdef : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 32845ffd83dbSDimitry Andric (SELECT_VSSRC (CREQV $lhs, $rhs), $tval, $fval)>; 32855ffd83dbSDimitry Andricdef : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 32865ffd83dbSDimitry Andric (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>; 32875ffd83dbSDimitry Andricdef : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 32885ffd83dbSDimitry Andric (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>; 32895ffd83dbSDimitry Andricdef : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 32905ffd83dbSDimitry Andric (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>; 32915ffd83dbSDimitry Andricdef : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 32925ffd83dbSDimitry Andric (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>; 32935ffd83dbSDimitry Andricdef : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 32945ffd83dbSDimitry Andric (SELECT_VSSRC (CRXOR $lhs, $rhs), $tval, $fval)>; 32955ffd83dbSDimitry Andric 32965ffd83dbSDimitry Andric// Additional fnmsub pattern for PPC specific ISD opcode 32975ffd83dbSDimitry Andricdef : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C), 32985ffd83dbSDimitry Andric (XSNMSUBASP $C, $A, $B)>; 32995ffd83dbSDimitry Andricdef : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)), 33005ffd83dbSDimitry Andric (XSMSUBASP $C, $A, $B)>; 33015ffd83dbSDimitry Andricdef : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)), 33025ffd83dbSDimitry Andric (XSNMADDASP $C, $A, $B)>; 33035ffd83dbSDimitry Andric 33045ffd83dbSDimitry Andric// f32 neg 33055ffd83dbSDimitry Andric// Although XSNEGDP is available in P7, we want to select it starting from P8, 33065ffd83dbSDimitry Andric// so that FNMSUBS can be selected for fneg-fmsub pattern on P7. (VSX version, 33075ffd83dbSDimitry Andric// XSNMSUBASP, is available since P8) 33085ffd83dbSDimitry Andricdef : Pat<(f32 (fneg f32:$S)), 33095ffd83dbSDimitry Andric (f32 (COPY_TO_REGCLASS (XSNEGDP 33105ffd83dbSDimitry Andric (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 33115ffd83dbSDimitry Andric 33125ffd83dbSDimitry Andric// Instructions for converting float to i32 feeding a store. 331306c3fb27SDimitry Andricdef : Pat<(PPCstore_scal_int_from_vsr f64:$src, ForceXForm:$dst, 4), 331406c3fb27SDimitry Andric (STIWX $src, ForceXForm:$dst)>; 331506c3fb27SDimitry Andricdef : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 4), 331606c3fb27SDimitry Andric (STIWX (COPY_TO_REGCLASS $src, VSFRC), ForceXForm:$dst)>; 331706c3fb27SDimitry Andric 331806c3fb27SDimitry Andricdef : Pat<(PPCstore_scal_int_from_vsr f64:$src, ForceXForm:$dst, 4), 331906c3fb27SDimitry Andric (STXSIWX $src, ForceXForm:$dst)>; 332006c3fb27SDimitry Andricdef : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 4), 332106c3fb27SDimitry Andric (STXSIWX (COPY_TO_REGCLASS $src, VSFRC), ForceXForm:$dst)>; 33225ffd83dbSDimitry Andric 33235ffd83dbSDimitry Andricdef : Pat<(v2i64 (smax v2i64:$src1, v2i64:$src2)), 33245ffd83dbSDimitry Andric (v2i64 (VMAXSD (COPY_TO_REGCLASS $src1, VRRC), 33255ffd83dbSDimitry Andric (COPY_TO_REGCLASS $src2, VRRC)))>; 33265ffd83dbSDimitry Andricdef : Pat<(v2i64 (umax v2i64:$src1, v2i64:$src2)), 33275ffd83dbSDimitry Andric (v2i64 (VMAXUD (COPY_TO_REGCLASS $src1, VRRC), 33285ffd83dbSDimitry Andric (COPY_TO_REGCLASS $src2, VRRC)))>; 33295ffd83dbSDimitry Andricdef : Pat<(v2i64 (smin v2i64:$src1, v2i64:$src2)), 33305ffd83dbSDimitry Andric (v2i64 (VMINSD (COPY_TO_REGCLASS $src1, VRRC), 33315ffd83dbSDimitry Andric (COPY_TO_REGCLASS $src2, VRRC)))>; 33325ffd83dbSDimitry Andricdef : Pat<(v2i64 (umin v2i64:$src1, v2i64:$src2)), 33335ffd83dbSDimitry Andric (v2i64 (VMINUD (COPY_TO_REGCLASS $src1, VRRC), 33345ffd83dbSDimitry Andric (COPY_TO_REGCLASS $src2, VRRC)))>; 33355ffd83dbSDimitry Andric 33365ffd83dbSDimitry Andricdef : Pat<(v1i128 (bitconvert (v16i8 immAllOnesV))), 33375ffd83dbSDimitry Andric (v1i128 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>; 33385ffd83dbSDimitry Andricdef : Pat<(v2i64 (bitconvert (v16i8 immAllOnesV))), 33395ffd83dbSDimitry Andric (v2i64 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>; 33405ffd83dbSDimitry Andricdef : Pat<(v8i16 (bitconvert (v16i8 immAllOnesV))), 33415ffd83dbSDimitry Andric (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>; 33425ffd83dbSDimitry Andricdef : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))), 33435ffd83dbSDimitry Andric (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>; 3344fe6060f1SDimitry Andric 3345fe6060f1SDimitry Andric// XL Compat builtins. 3346fe6060f1SDimitry Andricdef : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (XSMSUBMSP $A, $B, $C)>; 3347fe6060f1SDimitry Andricdef : Pat<(int_ppc_fnmadds f32:$A, f32:$B, f32:$C), (XSNMADDMSP $A, $B, $C)>; 3348fe6060f1SDimitry Andricdef : Pat<(int_ppc_fres f32:$A), (XSRESP $A)>; 3349fe6060f1SDimitry Andricdef : Pat<(i32 (int_ppc_extract_exp f64:$A)), 3350fe6060f1SDimitry Andric (EXTRACT_SUBREG (XSXEXPDP (COPY_TO_REGCLASS $A, VSFRC)), sub_32)>; 3351fe6060f1SDimitry Andricdef : Pat<(int_ppc_extract_sig f64:$A), 3352fe6060f1SDimitry Andric (XSXSIGDP (COPY_TO_REGCLASS $A, VSFRC))>; 3353fe6060f1SDimitry Andricdef : Pat<(f64 (int_ppc_insert_exp f64:$A, i64:$B)), 3354fe6060f1SDimitry Andric (COPY_TO_REGCLASS (XSIEXPDP (COPY_TO_REGCLASS $A, G8RC), $B), F8RC)>; 3355fe6060f1SDimitry Andric 3356fe6060f1SDimitry Andricdef : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT), 3357fe6060f1SDimitry Andric (STXSIWX f64:$XT, ForceXForm:$dst)>; 3358fe6060f1SDimitry Andricdef : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>; 33595ffd83dbSDimitry Andric} // HasVSX, HasP8Vector 33605ffd83dbSDimitry Andric 3361fe6060f1SDimitry Andric// Any big endian Power8 VSX subtarget. 3362fe6060f1SDimitry Andriclet Predicates = [HasVSX, HasP8Vector, IsBigEndian] in { 33635ffd83dbSDimitry Andricdef : Pat<DWToSPExtractConv.El0SS1, 33645ffd83dbSDimitry Andric (f32 (XSCVSXDSP (COPY_TO_REGCLASS $S1, VSFRC)))>; 33655ffd83dbSDimitry Andricdef : Pat<DWToSPExtractConv.El1SS1, 33665ffd83dbSDimitry Andric (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>; 33675ffd83dbSDimitry Andricdef : Pat<DWToSPExtractConv.El0US1, 33685ffd83dbSDimitry Andric (f32 (XSCVUXDSP (COPY_TO_REGCLASS $S1, VSFRC)))>; 33695ffd83dbSDimitry Andricdef : Pat<DWToSPExtractConv.El1US1, 33705ffd83dbSDimitry Andric (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>; 33715ffd83dbSDimitry Andric 33725ffd83dbSDimitry Andric// v4f32 scalar <-> vector conversions (BE) 3373fe6060f1SDimitry Andricdefm : ScalToVecWPermute<v4f32, (f32 f32:$A), (XSCVDPSPN $A), (XSCVDPSPN $A)>; 33745ffd83dbSDimitry Andricdef : Pat<(f32 (vector_extract v4f32:$S, 0)), 33755ffd83dbSDimitry Andric (f32 (XSCVSPDPN $S))>; 33765ffd83dbSDimitry Andricdef : Pat<(f32 (vector_extract v4f32:$S, 1)), 33775ffd83dbSDimitry Andric (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>; 33785ffd83dbSDimitry Andricdef : Pat<(f32 (vector_extract v4f32:$S, 2)), 33795ffd83dbSDimitry Andric (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>; 33805ffd83dbSDimitry Andricdef : Pat<(f32 (vector_extract v4f32:$S, 3)), 33815ffd83dbSDimitry Andric (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>; 33825ffd83dbSDimitry Andric 33835ffd83dbSDimitry Andricdef : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))), 33845ffd83dbSDimitry Andric (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 0))))>; 33855ffd83dbSDimitry Andricdef : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))), 33865ffd83dbSDimitry Andric (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 1))))>; 33875ffd83dbSDimitry Andricdef : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))), 33885ffd83dbSDimitry Andric (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 2))))>; 33895ffd83dbSDimitry Andricdef : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))), 33905ffd83dbSDimitry Andric (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 3))))>; 33915ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))), 33925ffd83dbSDimitry Andric (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 0)), VSFRC))>; 33935ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))), 33945ffd83dbSDimitry Andric (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 1)), VSFRC))>; 33955ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))), 33965ffd83dbSDimitry Andric (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 2)), VSFRC))>; 33975ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))), 33985ffd83dbSDimitry Andric (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 3)), VSFRC))>; 33995ffd83dbSDimitry Andric 3400fe6060f1SDimitry Andricdef : Pat<(f32 (vector_extract v4f32:$S, i32:$Idx)), 3401fe6060f1SDimitry Andric (f32 VectorExtractions.BE_32B_VARIABLE_FLOAT)>; 3402fe6060f1SDimitry Andric 3403fe6060f1SDimitry Andricdef : Pat<(f64 (vector_extract v2f64:$S, i32:$Idx)), 3404fe6060f1SDimitry Andric (f64 VectorExtractions.BE_32B_VARIABLE_DOUBLE)>; 340581ad6265SDimitry Andric 340681ad6265SDimitry Andricdefm : ScalToVecWPermute< 340781ad6265SDimitry Andric v4i32, (i32 (load ForceXForm:$src)), 340881ad6265SDimitry Andric (XXSLDWIs (LIWZX ForceXForm:$src), 1), 340981ad6265SDimitry Andric (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; 341081ad6265SDimitry Andricdefm : ScalToVecWPermute< 341181ad6265SDimitry Andric v4f32, (f32 (load ForceXForm:$src)), 341281ad6265SDimitry Andric (XXSLDWIs (LIWZX ForceXForm:$src), 1), 341381ad6265SDimitry Andric (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; 3414fe6060f1SDimitry Andric} // HasVSX, HasP8Vector, IsBigEndian 3415fe6060f1SDimitry Andric 3416fe6060f1SDimitry Andric// Big endian Power8 64Bit VSX subtarget. 3417fe6060f1SDimitry Andriclet Predicates = [HasVSX, HasP8Vector, IsBigEndian, IsPPC64] in { 3418fe6060f1SDimitry Andricdef : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)), 3419fe6060f1SDimitry Andric (f32 VectorExtractions.BE_VARIABLE_FLOAT)>; 3420fe6060f1SDimitry Andric 34215ffd83dbSDimitry Andric// LIWAX - This instruction is used for sign extending i32 -> i64. 34225ffd83dbSDimitry Andric// LIWZX - This instruction will be emitted for i32, f32, and when 34235ffd83dbSDimitry Andric// zero-extending i32 to i64 (zext i32 -> i64). 3424fe6060f1SDimitry Andricdef : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 ForceXForm:$src)))), 3425fe6060f1SDimitry Andric (v2i64 (SUBREG_TO_REG (i64 1), (LIWAX ForceXForm:$src), sub_64))>; 3426fe6060f1SDimitry Andricdef : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 ForceXForm:$src)))), 3427fe6060f1SDimitry Andric (v2i64 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64))>; 34285ffd83dbSDimitry Andric 34295ffd83dbSDimitry Andricdef : Pat<DWToSPExtractConv.BVU, 34305ffd83dbSDimitry Andric (v4f32 (VPKUDUM (XXSLDWI (XVCVUXDSP $S1), (XVCVUXDSP $S1), 3), 34315ffd83dbSDimitry Andric (XXSLDWI (XVCVUXDSP $S2), (XVCVUXDSP $S2), 3)))>; 34325ffd83dbSDimitry Andricdef : Pat<DWToSPExtractConv.BVS, 34335ffd83dbSDimitry Andric (v4f32 (VPKUDUM (XXSLDWI (XVCVSXDSP $S1), (XVCVSXDSP $S1), 3), 34345ffd83dbSDimitry Andric (XXSLDWI (XVCVSXDSP $S2), (XVCVSXDSP $S2), 3)))>; 3435fe6060f1SDimitry Andricdef : Pat<(store (i32 (extractelt v4i32:$A, 1)), ForceXForm:$src), 3436fe6060f1SDimitry Andric (STIWX (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 3437fe6060f1SDimitry Andricdef : Pat<(store (f32 (extractelt v4f32:$A, 1)), ForceXForm:$src), 3438fe6060f1SDimitry Andric (STIWX (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 34395ffd83dbSDimitry Andric 34405ffd83dbSDimitry Andric// Elements in a register on a BE system are in order <0, 1, 2, 3>. 34415ffd83dbSDimitry Andric// The store instructions store the second word from the left. 34425ffd83dbSDimitry Andric// So to align element zero, we need to modulo-left-shift by 3 words. 34435ffd83dbSDimitry Andric// Similar logic applies for elements 2 and 3. 34445ffd83dbSDimitry Andricforeach Idx = [ [0,3], [2,1], [3,2] ] in { 3445fe6060f1SDimitry Andric def : Pat<(store (i32 (extractelt v4i32:$A, !head(Idx))), ForceXForm:$src), 34465ffd83dbSDimitry Andric (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))), 3447fe6060f1SDimitry Andric sub_64), ForceXForm:$src)>; 3448fe6060f1SDimitry Andric def : Pat<(store (f32 (extractelt v4f32:$A, !head(Idx))), ForceXForm:$src), 34495ffd83dbSDimitry Andric (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))), 3450fe6060f1SDimitry Andric sub_64), ForceXForm:$src)>; 34515ffd83dbSDimitry Andric} 3452e8d8bef9SDimitry Andric} // HasVSX, HasP8Vector, IsBigEndian, IsPPC64 34535ffd83dbSDimitry Andric 34545ffd83dbSDimitry Andric// Little endian Power8 VSX subtarget. 34555ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasP8Vector, IsLittleEndian] in { 34565ffd83dbSDimitry Andricdef : Pat<DWToSPExtractConv.El0SS1, 34575ffd83dbSDimitry Andric (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>; 34585ffd83dbSDimitry Andricdef : Pat<DWToSPExtractConv.El1SS1, 34595ffd83dbSDimitry Andric (f32 (XSCVSXDSP (COPY_TO_REGCLASS 34605ffd83dbSDimitry Andric (f64 (COPY_TO_REGCLASS $S1, VSRC)), VSFRC)))>; 34615ffd83dbSDimitry Andricdef : Pat<DWToSPExtractConv.El0US1, 34625ffd83dbSDimitry Andric (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>; 34635ffd83dbSDimitry Andricdef : Pat<DWToSPExtractConv.El1US1, 34645ffd83dbSDimitry Andric (f32 (XSCVUXDSP (COPY_TO_REGCLASS 34655ffd83dbSDimitry Andric (f64 (COPY_TO_REGCLASS $S1, VSRC)), VSFRC)))>; 34665ffd83dbSDimitry Andric 34675ffd83dbSDimitry Andric// v4f32 scalar <-> vector conversions (LE) 34685ffd83dbSDimitry Andric defm : ScalToVecWPermute<v4f32, (f32 f32:$A), 34695ffd83dbSDimitry Andric (XXSLDWI (XSCVDPSPN $A), (XSCVDPSPN $A), 1), 3470fe6060f1SDimitry Andric (XSCVDPSPN $A)>; 34715ffd83dbSDimitry Andricdef : Pat<(f32 (vector_extract v4f32:$S, 0)), 34725ffd83dbSDimitry Andric (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>; 34735ffd83dbSDimitry Andricdef : Pat<(f32 (vector_extract v4f32:$S, 1)), 34745ffd83dbSDimitry Andric (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>; 34755ffd83dbSDimitry Andricdef : Pat<(f32 (vector_extract v4f32:$S, 2)), 34765ffd83dbSDimitry Andric (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>; 34775ffd83dbSDimitry Andricdef : Pat<(f32 (vector_extract v4f32:$S, 3)), 34785ffd83dbSDimitry Andric (f32 (XSCVSPDPN $S))>; 34795ffd83dbSDimitry Andricdef : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)), 34805ffd83dbSDimitry Andric (f32 VectorExtractions.LE_VARIABLE_FLOAT)>; 34815ffd83dbSDimitry Andric 34825ffd83dbSDimitry Andricdef : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))), 34835ffd83dbSDimitry Andric (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 3))))>; 34845ffd83dbSDimitry Andricdef : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))), 34855ffd83dbSDimitry Andric (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 2))))>; 34865ffd83dbSDimitry Andricdef : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))), 34875ffd83dbSDimitry Andric (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 1))))>; 34885ffd83dbSDimitry Andricdef : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))), 34895ffd83dbSDimitry Andric (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 0))))>; 34905ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))), 34915ffd83dbSDimitry Andric (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 3)), VSFRC))>; 34925ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))), 34935ffd83dbSDimitry Andric (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 2)), VSFRC))>; 34945ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))), 34955ffd83dbSDimitry Andric (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 1)), VSFRC))>; 34965ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))), 34975ffd83dbSDimitry Andric (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 0)), VSFRC))>; 34985ffd83dbSDimitry Andric 34995ffd83dbSDimitry Andric// LIWAX - This instruction is used for sign extending i32 -> i64. 35005ffd83dbSDimitry Andric// LIWZX - This instruction will be emitted for i32, f32, and when 35015ffd83dbSDimitry Andric// zero-extending i32 to i64 (zext i32 -> i64). 35025ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 3503fe6060f1SDimitry Andric v2i64, (i64 (sextloadi32 ForceXForm:$src)), 3504fe6060f1SDimitry Andric (XXPERMDIs (LIWAX ForceXForm:$src), 2), 3505fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (LIWAX ForceXForm:$src), sub_64)>; 35065ffd83dbSDimitry Andric 35075ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 3508fe6060f1SDimitry Andric v2i64, (i64 (zextloadi32 ForceXForm:$src)), 3509fe6060f1SDimitry Andric (XXPERMDIs (LIWZX ForceXForm:$src), 2), 3510fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; 35115ffd83dbSDimitry Andric 35125ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 3513fe6060f1SDimitry Andric v4i32, (i32 (load ForceXForm:$src)), 3514fe6060f1SDimitry Andric (XXPERMDIs (LIWZX ForceXForm:$src), 2), 3515fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; 35165ffd83dbSDimitry Andric 35175ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 3518fe6060f1SDimitry Andric v4f32, (f32 (load ForceXForm:$src)), 3519fe6060f1SDimitry Andric (XXPERMDIs (LIWZX ForceXForm:$src), 2), 3520fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; 35215ffd83dbSDimitry Andric 35225ffd83dbSDimitry Andricdef : Pat<DWToSPExtractConv.BVU, 35235ffd83dbSDimitry Andric (v4f32 (VPKUDUM (XXSLDWI (XVCVUXDSP $S2), (XVCVUXDSP $S2), 3), 35245ffd83dbSDimitry Andric (XXSLDWI (XVCVUXDSP $S1), (XVCVUXDSP $S1), 3)))>; 35255ffd83dbSDimitry Andricdef : Pat<DWToSPExtractConv.BVS, 35265ffd83dbSDimitry Andric (v4f32 (VPKUDUM (XXSLDWI (XVCVSXDSP $S2), (XVCVSXDSP $S2), 3), 35275ffd83dbSDimitry Andric (XXSLDWI (XVCVSXDSP $S1), (XVCVSXDSP $S1), 3)))>; 3528fe6060f1SDimitry Andricdef : Pat<(store (i32 (extractelt v4i32:$A, 2)), ForceXForm:$src), 3529fe6060f1SDimitry Andric (STIWX (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 3530fe6060f1SDimitry Andricdef : Pat<(store (f32 (extractelt v4f32:$A, 2)), ForceXForm:$src), 3531fe6060f1SDimitry Andric (STIWX (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 35325ffd83dbSDimitry Andric 35335ffd83dbSDimitry Andric// Elements in a register on a LE system are in order <3, 2, 1, 0>. 35345ffd83dbSDimitry Andric// The store instructions store the second word from the left. 35355ffd83dbSDimitry Andric// So to align element 3, we need to modulo-left-shift by 3 words. 35365ffd83dbSDimitry Andric// Similar logic applies for elements 0 and 1. 35375ffd83dbSDimitry Andricforeach Idx = [ [0,2], [1,1], [3,3] ] in { 3538fe6060f1SDimitry Andric def : Pat<(store (i32 (extractelt v4i32:$A, !head(Idx))), ForceXForm:$src), 35395ffd83dbSDimitry Andric (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))), 3540fe6060f1SDimitry Andric sub_64), ForceXForm:$src)>; 3541fe6060f1SDimitry Andric def : Pat<(store (f32 (extractelt v4f32:$A, !head(Idx))), ForceXForm:$src), 35425ffd83dbSDimitry Andric (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))), 3543fe6060f1SDimitry Andric sub_64), ForceXForm:$src)>; 35445ffd83dbSDimitry Andric} 35455ffd83dbSDimitry Andric} // HasVSX, HasP8Vector, IsLittleEndian 35465ffd83dbSDimitry Andric 35475ffd83dbSDimitry Andric// Big endian pre-Power9 VSX subtarget. 3548e8d8bef9SDimitry Andriclet Predicates = [HasVSX, HasP8Vector, NoP9Vector, IsBigEndian, IsPPC64] in { 3549fe6060f1SDimitry Andricdef : Pat<(store (i64 (extractelt v2i64:$A, 0)), ForceXForm:$src), 3550fe6060f1SDimitry Andric (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 3551fe6060f1SDimitry Andricdef : Pat<(store (f64 (extractelt v2f64:$A, 0)), ForceXForm:$src), 3552fe6060f1SDimitry Andric (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 3553fe6060f1SDimitry Andricdef : Pat<(store (i64 (extractelt v2i64:$A, 1)), ForceXForm:$src), 35545ffd83dbSDimitry Andric (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), 3555fe6060f1SDimitry Andric ForceXForm:$src)>; 3556fe6060f1SDimitry Andricdef : Pat<(store (f64 (extractelt v2f64:$A, 1)), ForceXForm:$src), 35575ffd83dbSDimitry Andric (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), 3558fe6060f1SDimitry Andric ForceXForm:$src)>; 3559e8d8bef9SDimitry Andric} // HasVSX, HasP8Vector, NoP9Vector, IsBigEndian, IsPPC64 35605ffd83dbSDimitry Andric 35615ffd83dbSDimitry Andric// Little endian pre-Power9 VSX subtarget. 35625ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian] in { 3563fe6060f1SDimitry Andricdef : Pat<(store (i64 (extractelt v2i64:$A, 0)), ForceXForm:$src), 35645ffd83dbSDimitry Andric (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), 3565fe6060f1SDimitry Andric ForceXForm:$src)>; 3566fe6060f1SDimitry Andricdef : Pat<(store (f64 (extractelt v2f64:$A, 0)), ForceXForm:$src), 35675ffd83dbSDimitry Andric (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), 3568fe6060f1SDimitry Andric ForceXForm:$src)>; 3569fe6060f1SDimitry Andricdef : Pat<(store (i64 (extractelt v2i64:$A, 1)), ForceXForm:$src), 3570fe6060f1SDimitry Andric (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 3571fe6060f1SDimitry Andricdef : Pat<(store (f64 (extractelt v2f64:$A, 1)), ForceXForm:$src), 3572fe6060f1SDimitry Andric (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 35735ffd83dbSDimitry Andric} // HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian 35745ffd83dbSDimitry Andric 35755ffd83dbSDimitry Andric// Any VSX target with direct moves. 35765ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasDirectMove] in { 35775ffd83dbSDimitry Andric// bitconvert f32 -> i32 35785ffd83dbSDimitry Andric// (convert to 32-bit fp single, shift right 1 word, move to GPR) 3579fe6060f1SDimitry Andricdef : Pat<(i32 (bitconvert f32:$A)), Bitcast.FltToInt>; 3580fe6060f1SDimitry Andric 35815ffd83dbSDimitry Andric// bitconvert i32 -> f32 35825ffd83dbSDimitry Andric// (move to FPR, shift left 1 word, convert to 64-bit fp single) 35835ffd83dbSDimitry Andricdef : Pat<(f32 (bitconvert i32:$A)), 35845ffd83dbSDimitry Andric (f32 (XSCVSPDPN 35855ffd83dbSDimitry Andric (XXSLDWI MovesToVSR.LE_WORD_1, MovesToVSR.LE_WORD_1, 1)))>; 35865ffd83dbSDimitry Andric 35875ffd83dbSDimitry Andric// bitconvert f64 -> i64 35885ffd83dbSDimitry Andric// (move to GPR, nothing else needed) 3589fe6060f1SDimitry Andricdef : Pat<(i64 (bitconvert f64:$A)), Bitcast.DblToLong>; 35905ffd83dbSDimitry Andric 35915ffd83dbSDimitry Andric// bitconvert i64 -> f64 35925ffd83dbSDimitry Andric// (move to FPR, nothing else needed) 35935ffd83dbSDimitry Andricdef : Pat<(f64 (bitconvert i64:$S)), 35945ffd83dbSDimitry Andric (f64 (MTVSRD $S))>; 35955ffd83dbSDimitry Andric 35965ffd83dbSDimitry Andric// Rounding to integer. 35975ffd83dbSDimitry Andricdef : Pat<(i64 (lrint f64:$S)), 35985ffd83dbSDimitry Andric (i64 (MFVSRD (FCTID $S)))>; 35995ffd83dbSDimitry Andricdef : Pat<(i64 (lrint f32:$S)), 36005ffd83dbSDimitry Andric (i64 (MFVSRD (FCTID (COPY_TO_REGCLASS $S, F8RC))))>; 36015ffd83dbSDimitry Andricdef : Pat<(i64 (llrint f64:$S)), 36025ffd83dbSDimitry Andric (i64 (MFVSRD (FCTID $S)))>; 36035ffd83dbSDimitry Andricdef : Pat<(i64 (llrint f32:$S)), 36045ffd83dbSDimitry Andric (i64 (MFVSRD (FCTID (COPY_TO_REGCLASS $S, F8RC))))>; 36055ffd83dbSDimitry Andricdef : Pat<(i64 (lround f64:$S)), 36065ffd83dbSDimitry Andric (i64 (MFVSRD (FCTID (XSRDPI $S))))>; 36075ffd83dbSDimitry Andricdef : Pat<(i64 (lround f32:$S)), 36085ffd83dbSDimitry Andric (i64 (MFVSRD (FCTID (XSRDPI (COPY_TO_REGCLASS $S, VSFRC)))))>; 36095ffd83dbSDimitry Andricdef : Pat<(i64 (llround f64:$S)), 36105ffd83dbSDimitry Andric (i64 (MFVSRD (FCTID (XSRDPI $S))))>; 36115ffd83dbSDimitry Andricdef : Pat<(i64 (llround f32:$S)), 36125ffd83dbSDimitry Andric (i64 (MFVSRD (FCTID (XSRDPI (COPY_TO_REGCLASS $S, VSFRC)))))>; 36135ffd83dbSDimitry Andric 36145ffd83dbSDimitry Andric// Alternate patterns for PPCmtvsrz where the output is v8i16 or v16i8 instead 36155ffd83dbSDimitry Andric// of f64 36165ffd83dbSDimitry Andricdef : Pat<(v8i16 (PPCmtvsrz i32:$A)), 36175ffd83dbSDimitry Andric (v8i16 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64))>; 36185ffd83dbSDimitry Andricdef : Pat<(v16i8 (PPCmtvsrz i32:$A)), 36195ffd83dbSDimitry Andric (v16i8 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64))>; 36205ffd83dbSDimitry Andric 36210b57cec5SDimitry Andric// Endianness-neutral constant splat on P8 and newer targets. The reason 36220b57cec5SDimitry Andric// for this pattern is that on targets with direct moves, we don't expand 36230b57cec5SDimitry Andric// BUILD_VECTOR nodes for v4i32. 36240b57cec5SDimitry Andricdef : Pat<(v4i32 (build_vector immSExt5NonZero:$A, immSExt5NonZero:$A, 36250b57cec5SDimitry Andric immSExt5NonZero:$A, immSExt5NonZero:$A)), 36260b57cec5SDimitry Andric (v4i32 (VSPLTISW imm:$A))>; 3627349cc55cSDimitry Andric 3628349cc55cSDimitry Andric// Splat loads. 3629349cc55cSDimitry Andricdef : Pat<(v8i16 (PPCldsplat ForceXForm:$A)), 3630349cc55cSDimitry Andric (v8i16 (VSPLTHs 3, (MTVSRWZ (LHZX ForceXForm:$A))))>; 3631349cc55cSDimitry Andricdef : Pat<(v16i8 (PPCldsplat ForceXForm:$A)), 3632349cc55cSDimitry Andric (v16i8 (VSPLTBs 7, (MTVSRWZ (LBZX ForceXForm:$A))))>; 36335ffd83dbSDimitry Andric} // HasVSX, HasDirectMove 36340b57cec5SDimitry Andric 36355ffd83dbSDimitry Andric// Big endian VSX subtarget with direct moves. 36365ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasDirectMove, IsBigEndian] in { 36375ffd83dbSDimitry Andric// v16i8 scalar <-> vector conversions (BE) 3638fe6060f1SDimitry Andricdefm : ScalToVecWPermute< 3639fe6060f1SDimitry Andric v16i8, (i32 i32:$A), 3640fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), MovesToVSR.BE_BYTE_0, sub_64), 3641fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; 3642fe6060f1SDimitry Andricdefm : ScalToVecWPermute< 3643fe6060f1SDimitry Andric v8i16, (i32 i32:$A), 3644349cc55cSDimitry Andric (SUBREG_TO_REG (i64 1), MovesToVSR.BE_HALF_0, sub_64), 3645fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; 3646fe6060f1SDimitry Andricdefm : ScalToVecWPermute< 3647fe6060f1SDimitry Andric v4i32, (i32 i32:$A), 3648fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), MovesToVSR.BE_WORD_0, sub_64), 3649fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; 36505ffd83dbSDimitry Andricdef : Pat<(v2i64 (scalar_to_vector i64:$A)), 36515ffd83dbSDimitry Andric (v2i64 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_DWORD_0, sub_64))>; 36525ffd83dbSDimitry Andric 36535ffd83dbSDimitry Andric// v2i64 scalar <-> vector conversions (BE) 36545ffd83dbSDimitry Andricdef : Pat<(i64 (vector_extract v2i64:$S, 0)), 36555ffd83dbSDimitry Andric (i64 VectorExtractions.LE_DWORD_1)>; 36565ffd83dbSDimitry Andricdef : Pat<(i64 (vector_extract v2i64:$S, 1)), 36575ffd83dbSDimitry Andric (i64 VectorExtractions.LE_DWORD_0)>; 36585ffd83dbSDimitry Andricdef : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)), 36595ffd83dbSDimitry Andric (i64 VectorExtractions.BE_VARIABLE_DWORD)>; 36605ffd83dbSDimitry Andric} // HasVSX, HasDirectMove, IsBigEndian 36615ffd83dbSDimitry Andric 36625ffd83dbSDimitry Andric// Little endian VSX subtarget with direct moves. 36635ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasDirectMove, IsLittleEndian] in { 36645ffd83dbSDimitry Andric // v16i8 scalar <-> vector conversions (LE) 36655ffd83dbSDimitry Andric defm : ScalToVecWPermute<v16i8, (i32 i32:$A), 36665ffd83dbSDimitry Andric (COPY_TO_REGCLASS MovesToVSR.LE_WORD_0, VSRC), 36675ffd83dbSDimitry Andric (COPY_TO_REGCLASS MovesToVSR.LE_WORD_1, VSRC)>; 36685ffd83dbSDimitry Andric defm : ScalToVecWPermute<v8i16, (i32 i32:$A), 36695ffd83dbSDimitry Andric (COPY_TO_REGCLASS MovesToVSR.LE_WORD_0, VSRC), 36705ffd83dbSDimitry Andric (COPY_TO_REGCLASS MovesToVSR.LE_WORD_1, VSRC)>; 36715ffd83dbSDimitry Andric defm : ScalToVecWPermute<v4i32, (i32 i32:$A), MovesToVSR.LE_WORD_0, 36725ffd83dbSDimitry Andric (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; 36735ffd83dbSDimitry Andric defm : ScalToVecWPermute<v2i64, (i64 i64:$A), MovesToVSR.LE_DWORD_0, 36745ffd83dbSDimitry Andric MovesToVSR.LE_DWORD_1>; 36755ffd83dbSDimitry Andric 36765ffd83dbSDimitry Andric // v2i64 scalar <-> vector conversions (LE) 36775ffd83dbSDimitry Andric def : Pat<(i64 (vector_extract v2i64:$S, 0)), 36785ffd83dbSDimitry Andric (i64 VectorExtractions.LE_DWORD_0)>; 36795ffd83dbSDimitry Andric def : Pat<(i64 (vector_extract v2i64:$S, 1)), 36805ffd83dbSDimitry Andric (i64 VectorExtractions.LE_DWORD_1)>; 36815ffd83dbSDimitry Andric def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)), 36825ffd83dbSDimitry Andric (i64 VectorExtractions.LE_VARIABLE_DWORD)>; 36835ffd83dbSDimitry Andric} // HasVSX, HasDirectMove, IsLittleEndian 36845ffd83dbSDimitry Andric 36855ffd83dbSDimitry Andric// Big endian pre-P9 VSX subtarget with direct moves. 36865ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian] in { 36875ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 0)), 36885ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_15)>; 36895ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 1)), 36905ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_14)>; 36915ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 2)), 36925ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_13)>; 36935ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 3)), 36945ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_12)>; 36955ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 4)), 36965ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_11)>; 36975ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 5)), 36985ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_10)>; 36995ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 6)), 37005ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_9)>; 37015ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 7)), 37025ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_8)>; 37035ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 8)), 37045ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_7)>; 37055ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 9)), 37065ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_6)>; 37075ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 10)), 37085ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_5)>; 37095ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 11)), 37105ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_4)>; 37115ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 12)), 37125ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_3)>; 37135ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 13)), 37145ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_2)>; 37155ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 14)), 37165ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_1)>; 37175ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 15)), 37185ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_0)>; 37195ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)), 37205ffd83dbSDimitry Andric (i32 VectorExtractions.BE_VARIABLE_BYTE)>; 37215ffd83dbSDimitry Andric 37225ffd83dbSDimitry Andric// v8i16 scalar <-> vector conversions (BE) 37235ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 0)), 37245ffd83dbSDimitry Andric (i32 VectorExtractions.LE_HALF_7)>; 37255ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 1)), 37265ffd83dbSDimitry Andric (i32 VectorExtractions.LE_HALF_6)>; 37275ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 2)), 37285ffd83dbSDimitry Andric (i32 VectorExtractions.LE_HALF_5)>; 37295ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 3)), 37305ffd83dbSDimitry Andric (i32 VectorExtractions.LE_HALF_4)>; 37315ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 4)), 37325ffd83dbSDimitry Andric (i32 VectorExtractions.LE_HALF_3)>; 37335ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 5)), 37345ffd83dbSDimitry Andric (i32 VectorExtractions.LE_HALF_2)>; 37355ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 6)), 37365ffd83dbSDimitry Andric (i32 VectorExtractions.LE_HALF_1)>; 37375ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 7)), 37385ffd83dbSDimitry Andric (i32 VectorExtractions.LE_HALF_0)>; 37395ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)), 37405ffd83dbSDimitry Andric (i32 VectorExtractions.BE_VARIABLE_HALF)>; 37415ffd83dbSDimitry Andric 37425ffd83dbSDimitry Andric// v4i32 scalar <-> vector conversions (BE) 37435ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, 0)), 37445ffd83dbSDimitry Andric (i32 VectorExtractions.LE_WORD_3)>; 37455ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, 1)), 37465ffd83dbSDimitry Andric (i32 VectorExtractions.LE_WORD_2)>; 37475ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, 2)), 37485ffd83dbSDimitry Andric (i32 VectorExtractions.LE_WORD_1)>; 37495ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, 3)), 37505ffd83dbSDimitry Andric (i32 VectorExtractions.LE_WORD_0)>; 37515ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)), 37525ffd83dbSDimitry Andric (i32 VectorExtractions.BE_VARIABLE_WORD)>; 37535ffd83dbSDimitry Andric} // HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian 37545ffd83dbSDimitry Andric 37555ffd83dbSDimitry Andric// Little endian pre-P9 VSX subtarget with direct moves. 37565ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian] in { 37575ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 0)), 37585ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_0)>; 37595ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 1)), 37605ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_1)>; 37615ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 2)), 37625ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_2)>; 37635ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 3)), 37645ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_3)>; 37655ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 4)), 37665ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_4)>; 37675ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 5)), 37685ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_5)>; 37695ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 6)), 37705ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_6)>; 37715ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 7)), 37725ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_7)>; 37735ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 8)), 37745ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_8)>; 37755ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 9)), 37765ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_9)>; 37775ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 10)), 37785ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_10)>; 37795ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 11)), 37805ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_11)>; 37815ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 12)), 37825ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_12)>; 37835ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 13)), 37845ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_13)>; 37855ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 14)), 37865ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_14)>; 37875ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 15)), 37885ffd83dbSDimitry Andric (i32 VectorExtractions.LE_BYTE_15)>; 37895ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)), 37905ffd83dbSDimitry Andric (i32 VectorExtractions.LE_VARIABLE_BYTE)>; 37915ffd83dbSDimitry Andric 37925ffd83dbSDimitry Andric// v8i16 scalar <-> vector conversions (LE) 37935ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 0)), 37945ffd83dbSDimitry Andric (i32 VectorExtractions.LE_HALF_0)>; 37955ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 1)), 37965ffd83dbSDimitry Andric (i32 VectorExtractions.LE_HALF_1)>; 37975ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 2)), 37985ffd83dbSDimitry Andric (i32 VectorExtractions.LE_HALF_2)>; 37995ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 3)), 38005ffd83dbSDimitry Andric (i32 VectorExtractions.LE_HALF_3)>; 38015ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 4)), 38025ffd83dbSDimitry Andric (i32 VectorExtractions.LE_HALF_4)>; 38035ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 5)), 38045ffd83dbSDimitry Andric (i32 VectorExtractions.LE_HALF_5)>; 38055ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 6)), 38065ffd83dbSDimitry Andric (i32 VectorExtractions.LE_HALF_6)>; 38075ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 7)), 38085ffd83dbSDimitry Andric (i32 VectorExtractions.LE_HALF_7)>; 38095ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)), 38105ffd83dbSDimitry Andric (i32 VectorExtractions.LE_VARIABLE_HALF)>; 38115ffd83dbSDimitry Andric 38125ffd83dbSDimitry Andric// v4i32 scalar <-> vector conversions (LE) 38135ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, 0)), 38145ffd83dbSDimitry Andric (i32 VectorExtractions.LE_WORD_0)>; 38155ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, 1)), 38165ffd83dbSDimitry Andric (i32 VectorExtractions.LE_WORD_1)>; 38175ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, 2)), 38185ffd83dbSDimitry Andric (i32 VectorExtractions.LE_WORD_2)>; 38195ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, 3)), 38205ffd83dbSDimitry Andric (i32 VectorExtractions.LE_WORD_3)>; 38215ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)), 38225ffd83dbSDimitry Andric (i32 VectorExtractions.LE_VARIABLE_WORD)>; 38235ffd83dbSDimitry Andric} // HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian 38245ffd83dbSDimitry Andric 3825e8d8bef9SDimitry Andric// Big endian pre-Power9 64Bit VSX subtarget that has direct moves. 3826e8d8bef9SDimitry Andriclet Predicates = [HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64] in { 38270b57cec5SDimitry Andric// Big endian integer vectors using direct moves. 38280b57cec5SDimitry Andricdef : Pat<(v2i64 (build_vector i64:$A, i64:$B)), 38290b57cec5SDimitry Andric (v2i64 (XXPERMDI 3830fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (MTVSRD $A), sub_64), 3831fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (MTVSRD $B), sub_64), 0))>; 38320b57cec5SDimitry Andricdef : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)), 38330b57cec5SDimitry Andric (XXPERMDI 3834fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), 3835fe6060f1SDimitry Andric (MTVSRD (RLDIMI AnyExts.B, AnyExts.A, 32, 0)), sub_64), 3836fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), 3837fe6060f1SDimitry Andric (MTVSRD (RLDIMI AnyExts.D, AnyExts.C, 32, 0)), sub_64), 0)>; 38380b57cec5SDimitry Andricdef : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)), 3839fe6060f1SDimitry Andric (XXSPLTW (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64), 1)>; 3840e8d8bef9SDimitry Andric} // HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64 38410b57cec5SDimitry Andric 38425ffd83dbSDimitry Andric// Little endian pre-Power9 VSX subtarget that has direct moves. 38435ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasDirectMove, NoP9Vector, IsLittleEndian] in { 38440b57cec5SDimitry Andric// Little endian integer vectors using direct moves. 38450b57cec5SDimitry Andricdef : Pat<(v2i64 (build_vector i64:$A, i64:$B)), 38460b57cec5SDimitry Andric (v2i64 (XXPERMDI 3847fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (MTVSRD $B), sub_64), 3848fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (MTVSRD $A), sub_64), 0))>; 38490b57cec5SDimitry Andricdef : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)), 38500b57cec5SDimitry Andric (XXPERMDI 3851fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), 3852fe6060f1SDimitry Andric (MTVSRD (RLDIMI AnyExts.C, AnyExts.D, 32, 0)), sub_64), 3853fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), 3854fe6060f1SDimitry Andric (MTVSRD (RLDIMI AnyExts.A, AnyExts.B, 32, 0)), sub_64), 0)>; 38550b57cec5SDimitry Andricdef : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)), 3856fe6060f1SDimitry Andric (XXSPLTW (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64), 1)>; 38570b57cec5SDimitry Andric} 38580b57cec5SDimitry Andric 38595ffd83dbSDimitry Andric// Any Power9 VSX subtarget. 38605ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasP9Vector] in { 38615ffd83dbSDimitry Andric// Additional fnmsub pattern for PPC specific ISD opcode 38625ffd83dbSDimitry Andricdef : Pat<(PPCfnmsub f128:$A, f128:$B, f128:$C), 38635ffd83dbSDimitry Andric (XSNMSUBQP $C, $A, $B)>; 38645ffd83dbSDimitry Andricdef : Pat<(fneg (PPCfnmsub f128:$A, f128:$B, f128:$C)), 38655ffd83dbSDimitry Andric (XSMSUBQP $C, $A, $B)>; 38665ffd83dbSDimitry Andricdef : Pat<(PPCfnmsub f128:$A, f128:$B, (fneg f128:$C)), 38675ffd83dbSDimitry Andric (XSNMADDQP $C, $A, $B)>; 38688bcb0991SDimitry Andric 3869e8d8bef9SDimitry Andricdef : Pat<(f128 (any_sint_to_fp i64:$src)), 38705ffd83dbSDimitry Andric (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>; 3871e8d8bef9SDimitry Andricdef : Pat<(f128 (any_sint_to_fp (i64 (PPCmfvsr f64:$src)))), 38725ffd83dbSDimitry Andric (f128 (XSCVSDQP $src))>; 3873e8d8bef9SDimitry Andricdef : Pat<(f128 (any_sint_to_fp (i32 (PPCmfvsr f64:$src)))), 38745ffd83dbSDimitry Andric (f128 (XSCVSDQP (VEXTSW2Ds $src)))>; 3875e8d8bef9SDimitry Andricdef : Pat<(f128 (any_uint_to_fp i64:$src)), 38765ffd83dbSDimitry Andric (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>; 3877e8d8bef9SDimitry Andricdef : Pat<(f128 (any_uint_to_fp (i64 (PPCmfvsr f64:$src)))), 38785ffd83dbSDimitry Andric (f128 (XSCVUDQP $src))>; 38795ffd83dbSDimitry Andric 38805ffd83dbSDimitry Andric// Convert (Un)Signed Word -> QP. 3881e8d8bef9SDimitry Andricdef : Pat<(f128 (any_sint_to_fp i32:$src)), 38825ffd83dbSDimitry Andric (f128 (XSCVSDQP (MTVSRWA $src)))>; 3883fe6060f1SDimitry Andricdef : Pat<(f128 (any_sint_to_fp (i32 (load ForceXForm:$src)))), 3884fe6060f1SDimitry Andric (f128 (XSCVSDQP (LIWAX ForceXForm:$src)))>; 3885e8d8bef9SDimitry Andricdef : Pat<(f128 (any_uint_to_fp i32:$src)), 38865ffd83dbSDimitry Andric (f128 (XSCVUDQP (MTVSRWZ $src)))>; 3887fe6060f1SDimitry Andricdef : Pat<(f128 (any_uint_to_fp (i32 (load ForceXForm:$src)))), 3888fe6060f1SDimitry Andric (f128 (XSCVUDQP (LIWZX ForceXForm:$src)))>; 38895ffd83dbSDimitry Andric 38905ffd83dbSDimitry Andric// Pattern for matching Vector HP -> Vector SP intrinsic. Defined as a 38915ffd83dbSDimitry Andric// separate pattern so that it can convert the input register class from 38925ffd83dbSDimitry Andric// VRRC(v8i16) to VSRC. 38935ffd83dbSDimitry Andricdef : Pat<(v4f32 (int_ppc_vsx_xvcvhpsp v8i16:$A)), 38945ffd83dbSDimitry Andric (v4f32 (XVCVHPSP (COPY_TO_REGCLASS $A, VSRC)))>; 38955ffd83dbSDimitry Andric 38965ffd83dbSDimitry Andric// Use current rounding mode 38975ffd83dbSDimitry Andricdef : Pat<(f128 (any_fnearbyint f128:$vB)), (f128 (XSRQPI 0, $vB, 3))>; 38985ffd83dbSDimitry Andric// Round to nearest, ties away from zero 38995ffd83dbSDimitry Andricdef : Pat<(f128 (any_fround f128:$vB)), (f128 (XSRQPI 0, $vB, 0))>; 39005ffd83dbSDimitry Andric// Round towards Zero 39015ffd83dbSDimitry Andricdef : Pat<(f128 (any_ftrunc f128:$vB)), (f128 (XSRQPI 1, $vB, 1))>; 39025ffd83dbSDimitry Andric// Round towards +Inf 39035ffd83dbSDimitry Andricdef : Pat<(f128 (any_fceil f128:$vB)), (f128 (XSRQPI 1, $vB, 2))>; 39045ffd83dbSDimitry Andric// Round towards -Inf 39055ffd83dbSDimitry Andricdef : Pat<(f128 (any_ffloor f128:$vB)), (f128 (XSRQPI 1, $vB, 3))>; 39065ffd83dbSDimitry Andric// Use current rounding mode, [with Inexact] 39075ffd83dbSDimitry Andricdef : Pat<(f128 (any_frint f128:$vB)), (f128 (XSRQPIX 0, $vB, 3))>; 39085ffd83dbSDimitry Andric 39095ffd83dbSDimitry Andricdef : Pat<(f128 (int_ppc_scalar_insert_exp_qp f128:$vA, i64:$vB)), 39105ffd83dbSDimitry Andric (f128 (XSIEXPQP $vA, (MTVSRD $vB)))>; 39115ffd83dbSDimitry Andric 39125ffd83dbSDimitry Andricdef : Pat<(i64 (int_ppc_scalar_extract_expq f128:$vA)), 39135ffd83dbSDimitry Andric (i64 (MFVSRD (EXTRACT_SUBREG 39145ffd83dbSDimitry Andric (v2i64 (XSXEXPQP $vA)), sub_64)))>; 39155ffd83dbSDimitry Andric 39165ffd83dbSDimitry Andric// Extra patterns expanding to vector Extract Word/Insert Word 39175ffd83dbSDimitry Andricdef : Pat<(v4i32 (int_ppc_vsx_xxinsertw v4i32:$A, v2i64:$B, imm:$IMM)), 39185ffd83dbSDimitry Andric (v4i32 (XXINSERTW $A, $B, imm:$IMM))>; 39195ffd83dbSDimitry Andricdef : Pat<(v2i64 (int_ppc_vsx_xxextractuw v2i64:$A, imm:$IMM)), 39205ffd83dbSDimitry Andric (v2i64 (COPY_TO_REGCLASS (XXEXTRACTUW $A, imm:$IMM), VSRC))>; 39215ffd83dbSDimitry Andric 39225ffd83dbSDimitry Andric// Vector Reverse 39235ffd83dbSDimitry Andricdef : Pat<(v8i16 (bswap v8i16 :$A)), 39245ffd83dbSDimitry Andric (v8i16 (COPY_TO_REGCLASS (XXBRH (COPY_TO_REGCLASS $A, VSRC)), VRRC))>; 39255ffd83dbSDimitry Andricdef : Pat<(v1i128 (bswap v1i128 :$A)), 39265ffd83dbSDimitry Andric (v1i128 (COPY_TO_REGCLASS (XXBRQ (COPY_TO_REGCLASS $A, VSRC)), VRRC))>; 39275ffd83dbSDimitry Andric 39285ffd83dbSDimitry Andric// D-Form Load/Store 3929fe6060f1SDimitry Andricforeach Ty = [v4i32, v4f32, v2i64, v2f64] in { 3930fe6060f1SDimitry Andric def : Pat<(Ty (load DQForm:$src)), (LXV memrix16:$src)>; 3931fe6060f1SDimitry Andric def : Pat<(Ty (load XForm:$src)), (LXVX XForm:$src)>; 3932fe6060f1SDimitry Andric def : Pat<(store Ty:$rS, DQForm:$dst), (STXV $rS, memrix16:$dst)>; 3933fe6060f1SDimitry Andric def : Pat<(store Ty:$rS, XForm:$dst), (STXVX $rS, XForm:$dst)>; 3934fe6060f1SDimitry Andric} 3935fe6060f1SDimitry Andric 3936fe6060f1SDimitry Andricdef : Pat<(f128 (load DQForm:$src)), 39375ffd83dbSDimitry Andric (COPY_TO_REGCLASS (LXV memrix16:$src), VRRC)>; 3938fe6060f1SDimitry Andricdef : Pat<(f128 (load XForm:$src)), 3939fe6060f1SDimitry Andric (COPY_TO_REGCLASS (LXVX XForm:$src), VRRC)>; 3940fe6060f1SDimitry Andricdef : Pat<(v4i32 (int_ppc_vsx_lxvw4x DQForm:$src)), (LXV memrix16:$src)>; 3941fe6060f1SDimitry Andricdef : Pat<(v2f64 (int_ppc_vsx_lxvd2x DQForm:$src)), (LXV memrix16:$src)>; 3942fe6060f1SDimitry Andricdef : Pat<(v4i32 (int_ppc_vsx_lxvw4x XForm:$src)), (LXVX XForm:$src)>; 3943fe6060f1SDimitry Andricdef : Pat<(v2f64 (int_ppc_vsx_lxvd2x XForm:$src)), (LXVX XForm:$src)>; 39445ffd83dbSDimitry Andric 3945fe6060f1SDimitry Andricdef : Pat<(store f128:$rS, DQForm:$dst), 39465ffd83dbSDimitry Andric (STXV (COPY_TO_REGCLASS $rS, VSRC), memrix16:$dst)>; 3947fe6060f1SDimitry Andricdef : Pat<(store f128:$rS, XForm:$dst), 3948fe6060f1SDimitry Andric (STXVX (COPY_TO_REGCLASS $rS, VSRC), XForm:$dst)>; 3949fe6060f1SDimitry Andricdef : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, DQForm:$dst), 39505ffd83dbSDimitry Andric (STXV $rS, memrix16:$dst)>; 3951fe6060f1SDimitry Andricdef : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, DQForm:$dst), 39525ffd83dbSDimitry Andric (STXV $rS, memrix16:$dst)>; 3953fe6060f1SDimitry Andricdef : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, XForm:$dst), 3954fe6060f1SDimitry Andric (STXVX $rS, XForm:$dst)>; 3955fe6060f1SDimitry Andricdef : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, XForm:$dst), 3956fe6060f1SDimitry Andric (STXVX $rS, XForm:$dst)>; 39575ffd83dbSDimitry Andric 39585ffd83dbSDimitry Andric// Build vectors from i8 loads 39595ffd83dbSDimitry Andricdefm : ScalToVecWPermute<v8i16, ScalarLoads.ZELi8, 3960fe6060f1SDimitry Andric (VSPLTHs 3, (LXSIBZX ForceXForm:$src)), 3961fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>; 39625ffd83dbSDimitry Andricdefm : ScalToVecWPermute<v4i32, ScalarLoads.ZELi8, 3963fe6060f1SDimitry Andric (XXSPLTWs (LXSIBZX ForceXForm:$src), 1), 3964fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>; 39655ffd83dbSDimitry Andricdefm : ScalToVecWPermute<v2i64, ScalarLoads.ZELi8i64, 3966fe6060f1SDimitry Andric (XXPERMDIs (LXSIBZX ForceXForm:$src), 0), 3967fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>; 3968fe6060f1SDimitry Andricdefm : ScalToVecWPermute< 3969fe6060f1SDimitry Andric v4i32, ScalarLoads.SELi8, 3970fe6060f1SDimitry Andric (XXSPLTWs (VEXTSB2Ws (LXSIBZX ForceXForm:$src)), 1), 3971fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (VEXTSB2Ws (LXSIBZX ForceXForm:$src)), sub_64)>; 3972fe6060f1SDimitry Andricdefm : ScalToVecWPermute< 3973fe6060f1SDimitry Andric v2i64, ScalarLoads.SELi8i64, 3974fe6060f1SDimitry Andric (XXPERMDIs (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), 0), 3975fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), sub_64)>; 39765ffd83dbSDimitry Andric 39775ffd83dbSDimitry Andric// Build vectors from i16 loads 3978fe6060f1SDimitry Andricdefm : ScalToVecWPermute< 3979fe6060f1SDimitry Andric v4i32, ScalarLoads.ZELi16, 3980fe6060f1SDimitry Andric (XXSPLTWs (LXSIHZX ForceXForm:$src), 1), 3981fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>; 3982fe6060f1SDimitry Andricdefm : ScalToVecWPermute< 3983fe6060f1SDimitry Andric v2i64, ScalarLoads.ZELi16i64, 3984fe6060f1SDimitry Andric (XXPERMDIs (LXSIHZX ForceXForm:$src), 0), 3985fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>; 3986fe6060f1SDimitry Andricdefm : ScalToVecWPermute< 3987fe6060f1SDimitry Andric v4i32, ScalarLoads.SELi16, 3988fe6060f1SDimitry Andric (XXSPLTWs (VEXTSH2Ws (LXSIHZX ForceXForm:$src)), 1), 3989fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (VEXTSH2Ws (LXSIHZX ForceXForm:$src)), sub_64)>; 3990fe6060f1SDimitry Andricdefm : ScalToVecWPermute< 3991fe6060f1SDimitry Andric v2i64, ScalarLoads.SELi16i64, 3992fe6060f1SDimitry Andric (XXPERMDIs (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), 0), 3993fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64)>; 39945ffd83dbSDimitry Andric 39955ffd83dbSDimitry Andric// Load/convert and convert/store patterns for f16. 3996fe6060f1SDimitry Andricdef : Pat<(f64 (extloadf16 ForceXForm:$src)), 3997fe6060f1SDimitry Andric (f64 (XSCVHPDP (LXSIHZX ForceXForm:$src)))>; 3998fe6060f1SDimitry Andricdef : Pat<(truncstoref16 f64:$src, ForceXForm:$dst), 3999fe6060f1SDimitry Andric (STXSIHX (XSCVDPHP $src), ForceXForm:$dst)>; 4000fe6060f1SDimitry Andricdef : Pat<(f32 (extloadf16 ForceXForm:$src)), 4001fe6060f1SDimitry Andric (f32 (COPY_TO_REGCLASS (XSCVHPDP (LXSIHZX ForceXForm:$src)), VSSRC))>; 4002fe6060f1SDimitry Andricdef : Pat<(truncstoref16 f32:$src, ForceXForm:$dst), 4003fe6060f1SDimitry Andric (STXSIHX (XSCVDPHP (COPY_TO_REGCLASS $src, VSFRC)), ForceXForm:$dst)>; 40045ffd83dbSDimitry Andricdef : Pat<(f64 (f16_to_fp i32:$A)), 40055ffd83dbSDimitry Andric (f64 (XSCVHPDP (MTVSRWZ $A)))>; 40065ffd83dbSDimitry Andricdef : Pat<(f32 (f16_to_fp i32:$A)), 40075ffd83dbSDimitry Andric (f32 (COPY_TO_REGCLASS (XSCVHPDP (MTVSRWZ $A)), VSSRC))>; 40085ffd83dbSDimitry Andricdef : Pat<(i32 (fp_to_f16 f32:$A)), 40095ffd83dbSDimitry Andric (i32 (MFVSRWZ (XSCVDPHP (COPY_TO_REGCLASS $A, VSFRC))))>; 40105ffd83dbSDimitry Andricdef : Pat<(i32 (fp_to_f16 f64:$A)), (i32 (MFVSRWZ (XSCVDPHP $A)))>; 40115ffd83dbSDimitry Andric 40125ffd83dbSDimitry Andric// Vector sign extensions 40135ffd83dbSDimitry Andricdef : Pat<(f64 (PPCVexts f64:$A, 1)), 40145ffd83dbSDimitry Andric (f64 (COPY_TO_REGCLASS (VEXTSB2Ds $A), VSFRC))>; 40155ffd83dbSDimitry Andricdef : Pat<(f64 (PPCVexts f64:$A, 2)), 40165ffd83dbSDimitry Andric (f64 (COPY_TO_REGCLASS (VEXTSH2Ds $A), VSFRC))>; 40175ffd83dbSDimitry Andric 4018fe6060f1SDimitry Andricdef : Pat<(f64 (extloadf32 DSForm:$src)), 4019fe6060f1SDimitry Andric (COPY_TO_REGCLASS (DFLOADf32 DSForm:$src), VSFRC)>; 4020fe6060f1SDimitry Andricdef : Pat<(f32 (fpround (f64 (extloadf32 DSForm:$src)))), 4021fe6060f1SDimitry Andric (f32 (DFLOADf32 DSForm:$src))>; 40225ffd83dbSDimitry Andric 4023fe6060f1SDimitry Andricdef : Pat<(v4f32 (PPCldvsxlh XForm:$src)), 4024fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>; 4025fe6060f1SDimitry Andricdef : Pat<(v4f32 (PPCldvsxlh DSForm:$src)), 4026fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>; 40275ffd83dbSDimitry Andric 40285ffd83dbSDimitry Andric// Convert (Un)Signed DWord in memory -> QP 4029fe6060f1SDimitry Andricdef : Pat<(f128 (sint_to_fp (i64 (load XForm:$src)))), 4030fe6060f1SDimitry Andric (f128 (XSCVSDQP (LXSDX XForm:$src)))>; 4031fe6060f1SDimitry Andricdef : Pat<(f128 (sint_to_fp (i64 (load DSForm:$src)))), 4032fe6060f1SDimitry Andric (f128 (XSCVSDQP (LXSD DSForm:$src)))>; 4033fe6060f1SDimitry Andricdef : Pat<(f128 (uint_to_fp (i64 (load XForm:$src)))), 4034fe6060f1SDimitry Andric (f128 (XSCVUDQP (LXSDX XForm:$src)))>; 4035fe6060f1SDimitry Andricdef : Pat<(f128 (uint_to_fp (i64 (load DSForm:$src)))), 4036fe6060f1SDimitry Andric (f128 (XSCVUDQP (LXSD DSForm:$src)))>; 40375ffd83dbSDimitry Andric 40385ffd83dbSDimitry Andric// Convert Unsigned HWord in memory -> QP 40395ffd83dbSDimitry Andricdef : Pat<(f128 (uint_to_fp ScalarLoads.ZELi16)), 4040fe6060f1SDimitry Andric (f128 (XSCVUDQP (LXSIHZX XForm:$src)))>; 40415ffd83dbSDimitry Andric 40425ffd83dbSDimitry Andric// Convert Unsigned Byte in memory -> QP 40435ffd83dbSDimitry Andricdef : Pat<(f128 (uint_to_fp ScalarLoads.ZELi8)), 4044fe6060f1SDimitry Andric (f128 (XSCVUDQP (LXSIBZX ForceXForm:$src)))>; 40455ffd83dbSDimitry Andric 40465ffd83dbSDimitry Andric// Truncate & Convert QP -> (Un)Signed (D)Word. 4047e8d8bef9SDimitry Andricdef : Pat<(i64 (any_fp_to_sint f128:$src)), (i64 (MFVRD (XSCVQPSDZ $src)))>; 4048e8d8bef9SDimitry Andricdef : Pat<(i64 (any_fp_to_uint f128:$src)), (i64 (MFVRD (XSCVQPUDZ $src)))>; 4049e8d8bef9SDimitry Andricdef : Pat<(i32 (any_fp_to_sint f128:$src)), 40505ffd83dbSDimitry Andric (i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC)))>; 4051e8d8bef9SDimitry Andricdef : Pat<(i32 (any_fp_to_uint f128:$src)), 40525ffd83dbSDimitry Andric (i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC)))>; 40535ffd83dbSDimitry Andric 40545ffd83dbSDimitry Andric// Instructions for store(fptosi). 405506c3fb27SDimitry Andricdef : Pat<(PPCstore_scal_int_from_vsr f64:$src, DSForm:$dst, 8), 405606c3fb27SDimitry Andric (STXSD $src, DSForm:$dst)>; 405706c3fb27SDimitry Andricdef : Pat<(PPCstore_scal_int_from_vsr f64:$src, ForceXForm:$dst, 2), 405806c3fb27SDimitry Andric (STXSIHX $src, ForceXForm:$dst)>; 405906c3fb27SDimitry Andricdef : Pat<(PPCstore_scal_int_from_vsr f64:$src, ForceXForm:$dst, 1), 406006c3fb27SDimitry Andric (STXSIBX $src, ForceXForm:$dst)>; 40615ffd83dbSDimitry Andric 406206c3fb27SDimitry Andricdef : Pat<(PPCstore_scal_int_from_vsr f128:$src, DSForm:$dst, 8), 406306c3fb27SDimitry Andric (STXSD (COPY_TO_REGCLASS $src, VFRC), DSForm:$dst)>; 406406c3fb27SDimitry Andricdef : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 2), 406506c3fb27SDimitry Andric (STXSIHX (COPY_TO_REGCLASS $src, VSFRC), ForceXForm:$dst)>; 406606c3fb27SDimitry Andricdef : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 1), 406706c3fb27SDimitry Andric (STXSIBX (COPY_TO_REGCLASS $src, VSFRC), ForceXForm:$dst)>; 40685ffd83dbSDimitry Andric 40695ffd83dbSDimitry Andric// Round & Convert QP -> DP/SP 40705ffd83dbSDimitry Andricdef : Pat<(f64 (any_fpround f128:$src)), (f64 (XSCVQPDP $src))>; 40715ffd83dbSDimitry Andricdef : Pat<(f32 (any_fpround f128:$src)), (f32 (XSRSP (XSCVQPDPO $src)))>; 40725ffd83dbSDimitry Andric 40735ffd83dbSDimitry Andric// Convert SP -> QP 40745ffd83dbSDimitry Andricdef : Pat<(f128 (any_fpextend f32:$src)), 40755ffd83dbSDimitry Andric (f128 (XSCVDPQP (COPY_TO_REGCLASS $src, VFRC)))>; 40765ffd83dbSDimitry Andric 40775ffd83dbSDimitry Andricdef : Pat<(f32 (PPCxsmaxc f32:$XA, f32:$XB)), 40785ffd83dbSDimitry Andric (f32 (COPY_TO_REGCLASS (XSMAXCDP (COPY_TO_REGCLASS $XA, VSSRC), 40795ffd83dbSDimitry Andric (COPY_TO_REGCLASS $XB, VSSRC)), 40805ffd83dbSDimitry Andric VSSRC))>; 40815ffd83dbSDimitry Andricdef : Pat<(f32 (PPCxsminc f32:$XA, f32:$XB)), 40825ffd83dbSDimitry Andric (f32 (COPY_TO_REGCLASS (XSMINCDP (COPY_TO_REGCLASS $XA, VSSRC), 40835ffd83dbSDimitry Andric (COPY_TO_REGCLASS $XB, VSSRC)), 40845ffd83dbSDimitry Andric VSSRC))>; 40855ffd83dbSDimitry Andric 40860b57cec5SDimitry Andric// Endianness-neutral patterns for const splats with ISA 3.0 instructions. 4087fe6060f1SDimitry Andricdefm : ScalToVecWPermute<v4i32, (i32 i32:$A), (MTVSRWS $A), 4088fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; 40890b57cec5SDimitry Andricdef : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)), 40900b57cec5SDimitry Andric (v4i32 (MTVSRWS $A))>; 40918bcb0991SDimitry Andricdef : Pat<(v16i8 (build_vector immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 40928bcb0991SDimitry Andric immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 40938bcb0991SDimitry Andric immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 40948bcb0991SDimitry Andric immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 40958bcb0991SDimitry Andric immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 40968bcb0991SDimitry Andric immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 40978bcb0991SDimitry Andric immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 40988bcb0991SDimitry Andric immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A)), 40990b57cec5SDimitry Andric (v16i8 (COPY_TO_REGCLASS (XXSPLTIB imm:$A), VSRC))>; 4100fe6060f1SDimitry Andricdefm : ScalToVecWPermute< 4101fe6060f1SDimitry Andric v4i32, FltToIntLoad.A, 4102fe6060f1SDimitry Andric (XVCVSPSXWS (LXVWSX ForceXForm:$A)), 4103fe6060f1SDimitry Andric (XVCVSPSXWS (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64))>; 4104fe6060f1SDimitry Andricdefm : ScalToVecWPermute< 4105fe6060f1SDimitry Andric v4i32, FltToUIntLoad.A, 4106fe6060f1SDimitry Andric (XVCVSPUXWS (LXVWSX ForceXForm:$A)), 4107fe6060f1SDimitry Andric (XVCVSPUXWS (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64))>; 41085ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 41095ffd83dbSDimitry Andric v4i32, DblToIntLoadP9.A, 4110fe6060f1SDimitry Andric (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64), 1), 4111fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64)>; 41125ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 41135ffd83dbSDimitry Andric v4i32, DblToUIntLoadP9.A, 4114fe6060f1SDimitry Andric (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64), 1), 4115fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64)>; 41165ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 41175ffd83dbSDimitry Andric v2i64, FltToLongLoadP9.A, 4118fe6060f1SDimitry Andric (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), 0), 41195ffd83dbSDimitry Andric (SUBREG_TO_REG 41205ffd83dbSDimitry Andric (i64 1), 4121fe6060f1SDimitry Andric (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64)>; 41225ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 41235ffd83dbSDimitry Andric v2i64, FltToULongLoadP9.A, 4124fe6060f1SDimitry Andric (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), 0), 41255ffd83dbSDimitry Andric (SUBREG_TO_REG 41265ffd83dbSDimitry Andric (i64 1), 4127fe6060f1SDimitry Andric (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64)>; 4128fe6060f1SDimitry Andricdef : Pat<(v4f32 (PPCldsplat ForceXForm:$A)), 4129fe6060f1SDimitry Andric (v4f32 (LXVWSX ForceXForm:$A))>; 4130fe6060f1SDimitry Andricdef : Pat<(v4i32 (PPCldsplat ForceXForm:$A)), 4131fe6060f1SDimitry Andric (v4i32 (LXVWSX ForceXForm:$A))>; 4132349cc55cSDimitry Andricdef : Pat<(v8i16 (PPCldsplat ForceXForm:$A)), 4133349cc55cSDimitry Andric (v8i16 (VSPLTHs 3, (LXSIHZX ForceXForm:$A)))>; 4134349cc55cSDimitry Andricdef : Pat<(v16i8 (PPCldsplat ForceXForm:$A)), 4135349cc55cSDimitry Andric (v16i8 (VSPLTBs 7, (LXSIBZX ForceXForm:$A)))>; 4136bdd1243dSDimitry Andricdef : Pat<(v2f64 (PPCxxperm v2f64:$XT, v2f64:$XB, v4i32:$C)), 4137bdd1243dSDimitry Andric (XXPERM v2f64:$XT, v2f64:$XB, v4i32:$C)>; 41385ffd83dbSDimitry Andric} // HasVSX, HasP9Vector 41395ffd83dbSDimitry Andric 4140fe6060f1SDimitry Andric// Any Power9 VSX subtarget with equivalent length but better Power10 VSX 4141fe6060f1SDimitry Andric// patterns. 4142fe6060f1SDimitry Andric// Two identical blocks are required due to the slightly different predicates: 4143fe6060f1SDimitry Andric// One without P10 instructions, the other is BigEndian only with P10 instructions. 4144fe6060f1SDimitry Andriclet Predicates = [HasVSX, HasP9Vector, NoP10Vector] in { 4145fe6060f1SDimitry Andric// Little endian Power10 subtargets produce a shorter pattern but require a 4146fe6060f1SDimitry Andric// COPY_TO_REGCLASS. The COPY_TO_REGCLASS makes it appear to need two instructions 4147fe6060f1SDimitry Andric// to perform the operation, when only one instruction is produced in practice. 4148fe6060f1SDimitry Andric// The NoP10Vector predicate excludes these patterns from Power10 VSX subtargets. 4149fe6060f1SDimitry Andricdefm : ScalToVecWPermute< 4150fe6060f1SDimitry Andric v16i8, ScalarLoads.Li8, 4151fe6060f1SDimitry Andric (VSPLTBs 7, (LXSIBZX ForceXForm:$src)), 4152fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>; 4153fe6060f1SDimitry Andric// Build vectors from i16 loads 4154fe6060f1SDimitry Andricdefm : ScalToVecWPermute< 4155fe6060f1SDimitry Andric v8i16, ScalarLoads.Li16, 4156fe6060f1SDimitry Andric (VSPLTHs 3, (LXSIHZX ForceXForm:$src)), 4157fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>; 4158fe6060f1SDimitry Andric} // HasVSX, HasP9Vector, NoP10Vector 4159fe6060f1SDimitry Andric 4160fe6060f1SDimitry Andric// Any big endian Power9 VSX subtarget 4161fe6060f1SDimitry Andriclet Predicates = [HasVSX, HasP9Vector, IsBigEndian] in { 4162fe6060f1SDimitry Andric// Power10 VSX subtargets produce a shorter pattern for little endian targets 4163fe6060f1SDimitry Andric// but this is still the best pattern for Power9 and Power10 VSX big endian 4164fe6060f1SDimitry Andric// Build vectors from i8 loads 4165fe6060f1SDimitry Andricdefm : ScalToVecWPermute< 4166fe6060f1SDimitry Andric v16i8, ScalarLoads.Li8, 4167fe6060f1SDimitry Andric (VSPLTBs 7, (LXSIBZX ForceXForm:$src)), 4168fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>; 4169fe6060f1SDimitry Andric// Build vectors from i16 loads 4170fe6060f1SDimitry Andricdefm : ScalToVecWPermute< 4171fe6060f1SDimitry Andric v8i16, ScalarLoads.Li16, 4172fe6060f1SDimitry Andric (VSPLTHs 3, (LXSIHZX ForceXForm:$src)), 4173fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>; 4174fe6060f1SDimitry Andric 41755ffd83dbSDimitry Andricdef : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))), 41765ffd83dbSDimitry Andric (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>; 41775ffd83dbSDimitry Andricdef : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))), 41785ffd83dbSDimitry Andric (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>; 41795ffd83dbSDimitry Andricdef : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))), 41805ffd83dbSDimitry Andric (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>; 41815ffd83dbSDimitry Andricdef : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))), 41825ffd83dbSDimitry Andric (f32 (XSCVUXDSP (XXEXTRACTUW $A, 12)))>; 41835ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))), 41845ffd83dbSDimitry Andric (f64 (XSCVUXDDP (XXEXTRACTUW $A, 0)))>; 41855ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))), 41865ffd83dbSDimitry Andric (f64 (XSCVUXDDP (XXEXTRACTUW $A, 4)))>; 41875ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))), 41885ffd83dbSDimitry Andric (f64 (XSCVUXDDP (XXEXTRACTUW $A, 8)))>; 41895ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))), 41905ffd83dbSDimitry Andric (f64 (XSCVUXDDP (XXEXTRACTUW $A, 12)))>; 41915ffd83dbSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)), 41925ffd83dbSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>; 4193349cc55cSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 0)), 4194349cc55cSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, 4195349cc55cSDimitry Andric (SUBREG_TO_REG (i64 1), 4196349cc55cSDimitry Andric (XSCVDPSXWS f64:$B), sub_64), 4197349cc55cSDimitry Andric 0))>; 4198349cc55cSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 0)), 4199349cc55cSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, 4200349cc55cSDimitry Andric (SUBREG_TO_REG (i64 1), 4201349cc55cSDimitry Andric (XSCVDPUXWS f64:$B), sub_64), 4202349cc55cSDimitry Andric 0))>; 42035ffd83dbSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)), 42045ffd83dbSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>; 4205349cc55cSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 1)), 4206349cc55cSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, 4207349cc55cSDimitry Andric (SUBREG_TO_REG (i64 1), 4208349cc55cSDimitry Andric (XSCVDPSXWS f64:$B), sub_64), 4209349cc55cSDimitry Andric 4))>; 4210349cc55cSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 1)), 4211349cc55cSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, 4212349cc55cSDimitry Andric (SUBREG_TO_REG (i64 1), 4213349cc55cSDimitry Andric (XSCVDPUXWS f64:$B), sub_64), 4214349cc55cSDimitry Andric 4))>; 42155ffd83dbSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)), 42165ffd83dbSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>; 4217349cc55cSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 2)), 4218349cc55cSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, 4219349cc55cSDimitry Andric (SUBREG_TO_REG (i64 1), 4220349cc55cSDimitry Andric (XSCVDPSXWS f64:$B), sub_64), 4221349cc55cSDimitry Andric 8))>; 4222349cc55cSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 2)), 4223349cc55cSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, 4224349cc55cSDimitry Andric (SUBREG_TO_REG (i64 1), 4225349cc55cSDimitry Andric (XSCVDPUXWS f64:$B), sub_64), 4226349cc55cSDimitry Andric 8))>; 42275ffd83dbSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)), 42285ffd83dbSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>; 4229349cc55cSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 3)), 4230349cc55cSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, 4231349cc55cSDimitry Andric (SUBREG_TO_REG (i64 1), 4232349cc55cSDimitry Andric (XSCVDPSXWS f64:$B), sub_64), 4233349cc55cSDimitry Andric 12))>; 4234349cc55cSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 3)), 4235349cc55cSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, 4236349cc55cSDimitry Andric (SUBREG_TO_REG (i64 1), 4237349cc55cSDimitry Andric (XSCVDPUXWS f64:$B), sub_64), 4238349cc55cSDimitry Andric 12))>; 42395ffd83dbSDimitry Andricdef : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)), 42405ffd83dbSDimitry Andric (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>; 42415ffd83dbSDimitry Andricdef : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)), 42425ffd83dbSDimitry Andric (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>; 42435ffd83dbSDimitry Andricdef : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)), 42445ffd83dbSDimitry Andric (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>; 42455ffd83dbSDimitry Andricdef : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)), 42465ffd83dbSDimitry Andric (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>; 42475ffd83dbSDimitry Andric 4248fe6060f1SDimitry Andricdef : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 0)), 4249fe6060f1SDimitry Andric (v4f32 (XXINSERTW v4f32:$A, 4250fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 0))>; 4251fe6060f1SDimitry Andricdef : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 1)), 4252fe6060f1SDimitry Andric (v4f32 (XXINSERTW v4f32:$A, 4253fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 4))>; 4254fe6060f1SDimitry Andricdef : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 2)), 4255fe6060f1SDimitry Andric (v4f32 (XXINSERTW v4f32:$A, 4256fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 8))>; 4257fe6060f1SDimitry Andricdef : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 3)), 4258fe6060f1SDimitry Andric (v4f32 (XXINSERTW v4f32:$A, 4259fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 12))>; 4260fe6060f1SDimitry Andric 42615ffd83dbSDimitry Andric// Scalar stores of i8 4262fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 0)), ForceXForm:$dst), 4263fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 9)), VSRC), ForceXForm:$dst)>; 4264fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 1)), ForceXForm:$dst), 4265fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>; 4266fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 2)), ForceXForm:$dst), 4267fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 11)), VSRC), ForceXForm:$dst)>; 4268fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 3)), ForceXForm:$dst), 4269fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), ForceXForm:$dst)>; 4270fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 4)), ForceXForm:$dst), 4271fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 13)), VSRC), ForceXForm:$dst)>; 4272fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 5)), ForceXForm:$dst), 4273fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), ForceXForm:$dst)>; 4274fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 6)), ForceXForm:$dst), 4275fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 15)), VSRC), ForceXForm:$dst)>; 4276fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 7)), ForceXForm:$dst), 4277fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS $S, VSRC), ForceXForm:$dst)>; 4278fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 8)), ForceXForm:$dst), 4279fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 1)), VSRC), ForceXForm:$dst)>; 4280fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 9)), ForceXForm:$dst), 4281fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), ForceXForm:$dst)>; 4282fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 10)), ForceXForm:$dst), 4283fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 3)), VSRC), ForceXForm:$dst)>; 4284fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 11)), ForceXForm:$dst), 4285fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), ForceXForm:$dst)>; 4286fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 12)), ForceXForm:$dst), 4287fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 5)), VSRC), ForceXForm:$dst)>; 4288fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 13)), ForceXForm:$dst), 4289fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), ForceXForm:$dst)>; 4290fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 14)), ForceXForm:$dst), 4291fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 7)), VSRC), ForceXForm:$dst)>; 4292fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 15)), ForceXForm:$dst), 4293fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), ForceXForm:$dst)>; 42945ffd83dbSDimitry Andric 42955ffd83dbSDimitry Andric// Scalar stores of i16 4296fe6060f1SDimitry Andricdef : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 0)), ForceXForm:$dst), 4297fe6060f1SDimitry Andric (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>; 4298fe6060f1SDimitry Andricdef : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 1)), ForceXForm:$dst), 4299fe6060f1SDimitry Andric (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), ForceXForm:$dst)>; 4300fe6060f1SDimitry Andricdef : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 2)), ForceXForm:$dst), 4301fe6060f1SDimitry Andric (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), ForceXForm:$dst)>; 4302fe6060f1SDimitry Andricdef : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 3)), ForceXForm:$dst), 4303fe6060f1SDimitry Andric (STXSIHXv (COPY_TO_REGCLASS $S, VSRC), ForceXForm:$dst)>; 4304fe6060f1SDimitry Andricdef : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 4)), ForceXForm:$dst), 4305fe6060f1SDimitry Andric (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), ForceXForm:$dst)>; 4306fe6060f1SDimitry Andricdef : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 5)), ForceXForm:$dst), 4307fe6060f1SDimitry Andric (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), ForceXForm:$dst)>; 4308fe6060f1SDimitry Andricdef : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 6)), ForceXForm:$dst), 4309fe6060f1SDimitry Andric (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), ForceXForm:$dst)>; 4310fe6060f1SDimitry Andricdef : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), ForceXForm:$dst), 4311fe6060f1SDimitry Andric (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), ForceXForm:$dst)>; 4312fe6060f1SDimitry Andric} // HasVSX, HasP9Vector, IsBigEndian 43135ffd83dbSDimitry Andric 4314fe6060f1SDimitry Andric// Big endian 64Bit Power9 subtarget. 4315fe6060f1SDimitry Andriclet Predicates = [HasVSX, HasP9Vector, IsBigEndian, IsPPC64] in { 4316fe6060f1SDimitry Andricdef : Pat<(v2i64 (scalar_to_vector (i64 (load DSForm:$src)))), 4317fe6060f1SDimitry Andric (v2i64 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64))>; 4318fe6060f1SDimitry Andricdef : Pat<(v2i64 (scalar_to_vector (i64 (load XForm:$src)))), 4319fe6060f1SDimitry Andric (v2i64 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64))>; 43205ffd83dbSDimitry Andric 4321fe6060f1SDimitry Andricdef : Pat<(v2f64 (scalar_to_vector (f64 (load DSForm:$src)))), 4322fe6060f1SDimitry Andric (v2f64 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64))>; 4323fe6060f1SDimitry Andricdef : Pat<(v2f64 (scalar_to_vector (f64 (load XForm:$src)))), 4324fe6060f1SDimitry Andric (v2f64 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64))>; 4325fe6060f1SDimitry Andricdef : Pat<(store (i64 (extractelt v2i64:$A, 1)), XForm:$src), 43265ffd83dbSDimitry Andric (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4327fe6060f1SDimitry Andric sub_64), XForm:$src)>; 4328fe6060f1SDimitry Andricdef : Pat<(store (f64 (extractelt v2f64:$A, 1)), XForm:$src), 43295ffd83dbSDimitry Andric (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4330fe6060f1SDimitry Andric sub_64), XForm:$src)>; 4331fe6060f1SDimitry Andricdef : Pat<(store (i64 (extractelt v2i64:$A, 0)), XForm:$src), 4332fe6060f1SDimitry Andric (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), XForm:$src)>; 4333fe6060f1SDimitry Andricdef : Pat<(store (f64 (extractelt v2f64:$A, 0)), XForm:$src), 4334fe6060f1SDimitry Andric (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), XForm:$src)>; 4335fe6060f1SDimitry Andricdef : Pat<(store (i64 (extractelt v2i64:$A, 1)), DSForm:$src), 43365ffd83dbSDimitry Andric (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4337fe6060f1SDimitry Andric sub_64), DSForm:$src)>; 4338fe6060f1SDimitry Andricdef : Pat<(store (f64 (extractelt v2f64:$A, 1)), DSForm:$src), 43395ffd83dbSDimitry Andric (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4340fe6060f1SDimitry Andric sub_64), DSForm:$src)>; 4341fe6060f1SDimitry Andricdef : Pat<(store (i64 (extractelt v2i64:$A, 0)), DSForm:$src), 4342fe6060f1SDimitry Andric (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), DSForm:$src)>; 4343fe6060f1SDimitry Andricdef : Pat<(store (f64 (extractelt v2f64:$A, 0)), DSForm:$src), 4344fe6060f1SDimitry Andric (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), DSForm:$src)>; 43455ffd83dbSDimitry Andric 43465ffd83dbSDimitry Andric// (Un)Signed DWord vector extract -> QP 43475ffd83dbSDimitry Andricdef : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))), 43485ffd83dbSDimitry Andric (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>; 43495ffd83dbSDimitry Andricdef : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))), 43505ffd83dbSDimitry Andric (f128 (XSCVSDQP 43515ffd83dbSDimitry Andric (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>; 43525ffd83dbSDimitry Andricdef : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))), 43535ffd83dbSDimitry Andric (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>; 43545ffd83dbSDimitry Andricdef : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))), 43555ffd83dbSDimitry Andric (f128 (XSCVUDQP 43565ffd83dbSDimitry Andric (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>; 43575ffd83dbSDimitry Andric 43585ffd83dbSDimitry Andric// (Un)Signed Word vector extract -> QP 43595ffd83dbSDimitry Andricdef : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 1)))), 43605ffd83dbSDimitry Andric (f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>; 43615ffd83dbSDimitry Andricforeach Idx = [0,2,3] in { 43625ffd83dbSDimitry Andric def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, Idx)))), 43635ffd83dbSDimitry Andric (f128 (XSCVSDQP (EXTRACT_SUBREG 43645ffd83dbSDimitry Andric (VEXTSW2D (VSPLTW Idx, $src)), sub_64)))>; 43655ffd83dbSDimitry Andric} 43665ffd83dbSDimitry Andricforeach Idx = 0-3 in { 43675ffd83dbSDimitry Andric def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, Idx)))), 43685ffd83dbSDimitry Andric (f128 (XSCVUDQP (XXEXTRACTUW $src, !shl(Idx, 2))))>; 43690b57cec5SDimitry Andric} 43700b57cec5SDimitry Andric 4371fe6060f1SDimitry Andric// (Un)Signed HWord vector extract -> QP/DP/SP 43725ffd83dbSDimitry Andricforeach Idx = 0-7 in { 43735ffd83dbSDimitry Andric def : Pat<(f128 (sint_to_fp 43745ffd83dbSDimitry Andric (i32 (sext_inreg 43755ffd83dbSDimitry Andric (vector_extract v8i16:$src, Idx), i16)))), 43765ffd83dbSDimitry Andric (f128 (XSCVSDQP (EXTRACT_SUBREG 43775ffd83dbSDimitry Andric (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)), 43785ffd83dbSDimitry Andric sub_64)))>; 43795ffd83dbSDimitry Andric // The SDAG adds the `and` since an `i16` is being extracted as an `i32`. 43805ffd83dbSDimitry Andric def : Pat<(f128 (uint_to_fp 43815ffd83dbSDimitry Andric (and (i32 (vector_extract v8i16:$src, Idx)), 65535))), 43825ffd83dbSDimitry Andric (f128 (XSCVUDQP (EXTRACT_SUBREG 43835ffd83dbSDimitry Andric (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>; 4384fe6060f1SDimitry Andric def : Pat<(f32 (PPCfcfidus 4385fe6060f1SDimitry Andric (f64 (PPCmtvsrz (and (i32 (vector_extract v8i16:$src, Idx)), 4386fe6060f1SDimitry Andric 65535))))), 4387fe6060f1SDimitry Andric (f32 (XSCVUXDSP (EXTRACT_SUBREG 4388fe6060f1SDimitry Andric (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>; 4389fe6060f1SDimitry Andric def : Pat<(f32 (PPCfcfids 4390fe6060f1SDimitry Andric (f64 (PPCmtvsra 4391fe6060f1SDimitry Andric (i32 (sext_inreg (vector_extract v8i16:$src, Idx), 4392fe6060f1SDimitry Andric i16)))))), 4393fe6060f1SDimitry Andric (f32 (XSCVSXDSP (EXTRACT_SUBREG 4394fe6060f1SDimitry Andric (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)), 4395fe6060f1SDimitry Andric sub_64)))>; 4396fe6060f1SDimitry Andric def : Pat<(f64 (PPCfcfidu 4397fe6060f1SDimitry Andric (f64 (PPCmtvsrz 4398fe6060f1SDimitry Andric (and (i32 (vector_extract v8i16:$src, Idx)), 4399fe6060f1SDimitry Andric 65535))))), 4400fe6060f1SDimitry Andric (f64 (XSCVUXDDP (EXTRACT_SUBREG 4401fe6060f1SDimitry Andric (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>; 4402fe6060f1SDimitry Andric def : Pat<(f64 (PPCfcfid 4403fe6060f1SDimitry Andric (f64 (PPCmtvsra 4404fe6060f1SDimitry Andric (i32 (sext_inreg (vector_extract v8i16:$src, Idx), 4405fe6060f1SDimitry Andric i16)))))), 4406fe6060f1SDimitry Andric (f64 (XSCVSXDDP (EXTRACT_SUBREG 4407fe6060f1SDimitry Andric (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)), 4408fe6060f1SDimitry Andric sub_64)))>; 44090b57cec5SDimitry Andric} 44100b57cec5SDimitry Andric 44115ffd83dbSDimitry Andric// (Un)Signed Byte vector extract -> QP 44125ffd83dbSDimitry Andricforeach Idx = 0-15 in { 44135ffd83dbSDimitry Andric def : Pat<(f128 (sint_to_fp 44145ffd83dbSDimitry Andric (i32 (sext_inreg (vector_extract v16i8:$src, Idx), 44155ffd83dbSDimitry Andric i8)))), 44165ffd83dbSDimitry Andric (f128 (XSCVSDQP (EXTRACT_SUBREG 44175ffd83dbSDimitry Andric (VEXTSB2D (VEXTRACTUB Idx, $src)), sub_64)))>; 44185ffd83dbSDimitry Andric def : Pat<(f128 (uint_to_fp 44195ffd83dbSDimitry Andric (and (i32 (vector_extract v16i8:$src, Idx)), 255))), 44205ffd83dbSDimitry Andric (f128 (XSCVUDQP 44215ffd83dbSDimitry Andric (EXTRACT_SUBREG (VEXTRACTUB Idx, $src), sub_64)))>; 4422fe6060f1SDimitry Andric 4423fe6060f1SDimitry Andric def : Pat<(f32 (PPCfcfidus 4424fe6060f1SDimitry Andric (f64 (PPCmtvsrz 4425fe6060f1SDimitry Andric (and (i32 (vector_extract v16i8:$src, Idx)), 4426fe6060f1SDimitry Andric 255))))), 4427fe6060f1SDimitry Andric (f32 (XSCVUXDSP (EXTRACT_SUBREG 4428fe6060f1SDimitry Andric (VEXTRACTUB !add(Idx, Idx), $src), sub_64)))>; 4429fe6060f1SDimitry Andric def : Pat<(f32 (PPCfcfids 4430fe6060f1SDimitry Andric (f64 (PPCmtvsra 4431fe6060f1SDimitry Andric (i32 (sext_inreg (vector_extract v16i8:$src, Idx), 4432fe6060f1SDimitry Andric i8)))))), 4433fe6060f1SDimitry Andric (f32 (XSCVSXDSP (EXTRACT_SUBREG 4434fe6060f1SDimitry Andric (VEXTSH2D (VEXTRACTUB !add(Idx, Idx), $src)), 4435fe6060f1SDimitry Andric sub_64)))>; 4436fe6060f1SDimitry Andric def : Pat<(f64 (PPCfcfidu 4437fe6060f1SDimitry Andric (f64 (PPCmtvsrz 4438fe6060f1SDimitry Andric (and (i32 (vector_extract v16i8:$src, Idx)), 4439fe6060f1SDimitry Andric 255))))), 4440fe6060f1SDimitry Andric (f64 (XSCVUXDDP (EXTRACT_SUBREG 4441fe6060f1SDimitry Andric (VEXTRACTUB !add(Idx, Idx), $src), sub_64)))>; 4442fe6060f1SDimitry Andric def : Pat<(f64 (PPCfcfid 4443fe6060f1SDimitry Andric (f64 (PPCmtvsra 4444fe6060f1SDimitry Andric (i32 (sext_inreg (vector_extract v16i8:$src, Idx), 4445fe6060f1SDimitry Andric i8)))))), 4446fe6060f1SDimitry Andric (f64 (XSCVSXDDP (EXTRACT_SUBREG 4447fe6060f1SDimitry Andric (VEXTSH2D (VEXTRACTUB !add(Idx, Idx), $src)), 4448fe6060f1SDimitry Andric sub_64)))>; 44490b57cec5SDimitry Andric} 44500b57cec5SDimitry Andric 44515ffd83dbSDimitry Andric// Unsiged int in vsx register -> QP 44525ffd83dbSDimitry Andricdef : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))), 44535ffd83dbSDimitry Andric (f128 (XSCVUDQP 44545ffd83dbSDimitry Andric (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 4)))>; 4455e8d8bef9SDimitry Andric} // HasVSX, HasP9Vector, IsBigEndian, IsPPC64 44565ffd83dbSDimitry Andric 44575ffd83dbSDimitry Andric// Little endian Power9 subtarget. 44585ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasP9Vector, IsLittleEndian] in { 44595ffd83dbSDimitry Andricdef : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))), 44605ffd83dbSDimitry Andric (f32 (XSCVUXDSP (XXEXTRACTUW $A, 12)))>; 44615ffd83dbSDimitry Andricdef : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))), 44625ffd83dbSDimitry Andric (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>; 44635ffd83dbSDimitry Andricdef : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))), 44645ffd83dbSDimitry Andric (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>; 44655ffd83dbSDimitry Andricdef : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))), 44665ffd83dbSDimitry Andric (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>; 44675ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))), 44685ffd83dbSDimitry Andric (f64 (XSCVUXDDP (XXEXTRACTUW $A, 12)))>; 44695ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))), 44705ffd83dbSDimitry Andric (f64 (XSCVUXDDP (XXEXTRACTUW $A, 8)))>; 44715ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))), 44725ffd83dbSDimitry Andric (f64 (XSCVUXDDP (XXEXTRACTUW $A, 4)))>; 44735ffd83dbSDimitry Andricdef : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))), 44745ffd83dbSDimitry Andric (f64 (XSCVUXDDP (XXEXTRACTUW $A, 0)))>; 44755ffd83dbSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)), 44765ffd83dbSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>; 4477349cc55cSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 0)), 4478349cc55cSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, 4479349cc55cSDimitry Andric (SUBREG_TO_REG (i64 1), 4480349cc55cSDimitry Andric (XSCVDPSXWS f64:$B), sub_64), 4481349cc55cSDimitry Andric 12))>; 4482349cc55cSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 0)), 4483349cc55cSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, 4484349cc55cSDimitry Andric (SUBREG_TO_REG (i64 1), 4485349cc55cSDimitry Andric (XSCVDPUXWS f64:$B), sub_64), 4486349cc55cSDimitry Andric 12))>; 44875ffd83dbSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)), 44885ffd83dbSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>; 4489349cc55cSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 1)), 4490349cc55cSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, 4491349cc55cSDimitry Andric (SUBREG_TO_REG (i64 1), 4492349cc55cSDimitry Andric (XSCVDPSXWS f64:$B), sub_64), 4493349cc55cSDimitry Andric 8))>; 4494349cc55cSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 1)), 4495349cc55cSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, 4496349cc55cSDimitry Andric (SUBREG_TO_REG (i64 1), 4497349cc55cSDimitry Andric (XSCVDPUXWS f64:$B), sub_64), 4498349cc55cSDimitry Andric 8))>; 44995ffd83dbSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)), 45005ffd83dbSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>; 4501349cc55cSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 2)), 4502349cc55cSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, 4503349cc55cSDimitry Andric (SUBREG_TO_REG (i64 1), 4504349cc55cSDimitry Andric (XSCVDPSXWS f64:$B), sub_64), 4505349cc55cSDimitry Andric 4))>; 4506349cc55cSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 2)), 4507349cc55cSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, 4508349cc55cSDimitry Andric (SUBREG_TO_REG (i64 1), 4509349cc55cSDimitry Andric (XSCVDPUXWS f64:$B), sub_64), 4510349cc55cSDimitry Andric 4))>; 45115ffd83dbSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)), 45125ffd83dbSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>; 4513349cc55cSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 3)), 4514349cc55cSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, 4515349cc55cSDimitry Andric (SUBREG_TO_REG (i64 1), 4516349cc55cSDimitry Andric (XSCVDPSXWS f64:$B), sub_64), 4517349cc55cSDimitry Andric 0))>; 4518349cc55cSDimitry Andricdef : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 3)), 4519349cc55cSDimitry Andric (v4i32 (XXINSERTW v4i32:$A, 4520349cc55cSDimitry Andric (SUBREG_TO_REG (i64 1), 4521349cc55cSDimitry Andric (XSCVDPUXWS f64:$B), sub_64), 4522349cc55cSDimitry Andric 0))>; 45235ffd83dbSDimitry Andricdef : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)), 45245ffd83dbSDimitry Andric (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>; 45255ffd83dbSDimitry Andricdef : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)), 45265ffd83dbSDimitry Andric (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>; 45275ffd83dbSDimitry Andricdef : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)), 45285ffd83dbSDimitry Andric (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>; 45295ffd83dbSDimitry Andricdef : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)), 45305ffd83dbSDimitry Andric (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>; 45315ffd83dbSDimitry Andric 4532fe6060f1SDimitry Andricdef : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 0)), 4533fe6060f1SDimitry Andric (v4f32 (XXINSERTW v4f32:$A, 4534fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 12))>; 4535fe6060f1SDimitry Andricdef : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 1)), 4536fe6060f1SDimitry Andric (v4f32 (XXINSERTW v4f32:$A, 4537fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 8))>; 4538fe6060f1SDimitry Andricdef : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 2)), 4539fe6060f1SDimitry Andric (v4f32 (XXINSERTW v4f32:$A, 4540fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 4))>; 4541fe6060f1SDimitry Andricdef : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 3)), 4542fe6060f1SDimitry Andric (v4f32 (XXINSERTW v4f32:$A, 4543fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 0))>; 45445ffd83dbSDimitry Andric 4545fe6060f1SDimitry Andricdef : Pat<(v8i16 (PPCld_vec_be ForceXForm:$src)), 4546fe6060f1SDimitry Andric (COPY_TO_REGCLASS (LXVH8X ForceXForm:$src), VRRC)>; 4547fe6060f1SDimitry Andricdef : Pat<(PPCst_vec_be v8i16:$rS, ForceXForm:$dst), 4548fe6060f1SDimitry Andric (STXVH8X (COPY_TO_REGCLASS $rS, VSRC), ForceXForm:$dst)>; 4549fe6060f1SDimitry Andric 4550fe6060f1SDimitry Andricdef : Pat<(v16i8 (PPCld_vec_be ForceXForm:$src)), 4551fe6060f1SDimitry Andric (COPY_TO_REGCLASS (LXVB16X ForceXForm:$src), VRRC)>; 4552fe6060f1SDimitry Andricdef : Pat<(PPCst_vec_be v16i8:$rS, ForceXForm:$dst), 4553fe6060f1SDimitry Andric (STXVB16X (COPY_TO_REGCLASS $rS, VSRC), ForceXForm:$dst)>; 45545ffd83dbSDimitry Andric 45555ffd83dbSDimitry Andric// Scalar stores of i8 4556fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 0)), ForceXForm:$dst), 4557fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), ForceXForm:$dst)>; 4558fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 1)), ForceXForm:$dst), 4559fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 7)), VSRC), ForceXForm:$dst)>; 4560fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 2)), ForceXForm:$dst), 4561fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), ForceXForm:$dst)>; 4562fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 3)), ForceXForm:$dst), 4563fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 5)), VSRC), ForceXForm:$dst)>; 4564fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 4)), ForceXForm:$dst), 4565fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), ForceXForm:$dst)>; 4566fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 5)), ForceXForm:$dst), 4567fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 3)), VSRC), ForceXForm:$dst)>; 4568fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 6)), ForceXForm:$dst), 4569fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), ForceXForm:$dst)>; 4570fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 7)), ForceXForm:$dst), 4571fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 1)), VSRC), ForceXForm:$dst)>; 4572fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 8)), ForceXForm:$dst), 4573fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS $S, VSRC), ForceXForm:$dst)>; 4574fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 9)), ForceXForm:$dst), 4575fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 15)), VSRC), ForceXForm:$dst)>; 4576fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 10)), ForceXForm:$dst), 4577fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), ForceXForm:$dst)>; 4578fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 11)), ForceXForm:$dst), 4579fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 13)), VSRC), ForceXForm:$dst)>; 4580fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 12)), ForceXForm:$dst), 4581fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), ForceXForm:$dst)>; 4582fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 13)), ForceXForm:$dst), 4583fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 11)), VSRC), ForceXForm:$dst)>; 4584fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 14)), ForceXForm:$dst), 4585fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>; 4586fe6060f1SDimitry Andricdef : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 15)), ForceXForm:$dst), 4587fe6060f1SDimitry Andric (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 9)), VSRC), ForceXForm:$dst)>; 45885ffd83dbSDimitry Andric 45895ffd83dbSDimitry Andric// Scalar stores of i16 4590fe6060f1SDimitry Andricdef : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 0)), ForceXForm:$dst), 4591fe6060f1SDimitry Andric (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), ForceXForm:$dst)>; 4592fe6060f1SDimitry Andricdef : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 1)), ForceXForm:$dst), 4593fe6060f1SDimitry Andric (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), ForceXForm:$dst)>; 4594fe6060f1SDimitry Andricdef : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 2)), ForceXForm:$dst), 4595fe6060f1SDimitry Andric (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), ForceXForm:$dst)>; 4596fe6060f1SDimitry Andricdef : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 3)), ForceXForm:$dst), 4597fe6060f1SDimitry Andric (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), ForceXForm:$dst)>; 4598fe6060f1SDimitry Andricdef : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 4)), ForceXForm:$dst), 4599fe6060f1SDimitry Andric (STXSIHXv (COPY_TO_REGCLASS $S, VSRC), ForceXForm:$dst)>; 4600fe6060f1SDimitry Andricdef : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 5)), ForceXForm:$dst), 4601fe6060f1SDimitry Andric (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), ForceXForm:$dst)>; 4602fe6060f1SDimitry Andricdef : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 6)), ForceXForm:$dst), 4603fe6060f1SDimitry Andric (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), ForceXForm:$dst)>; 4604fe6060f1SDimitry Andricdef : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), ForceXForm:$dst), 4605fe6060f1SDimitry Andric (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>; 46065ffd83dbSDimitry Andric 46075ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 4608fe6060f1SDimitry Andric v2i64, (i64 (load DSForm:$src)), 4609fe6060f1SDimitry Andric (XXPERMDIs (DFLOADf64 DSForm:$src), 2), 4610fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>; 46115ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 4612fe6060f1SDimitry Andric v2i64, (i64 (load XForm:$src)), 4613fe6060f1SDimitry Andric (XXPERMDIs (XFLOADf64 XForm:$src), 2), 4614fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>; 46155ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 4616fe6060f1SDimitry Andric v2f64, (f64 (load DSForm:$src)), 4617fe6060f1SDimitry Andric (XXPERMDIs (DFLOADf64 DSForm:$src), 2), 4618fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>; 46195ffd83dbSDimitry Andricdefm : ScalToVecWPermute< 4620fe6060f1SDimitry Andric v2f64, (f64 (load XForm:$src)), 4621fe6060f1SDimitry Andric (XXPERMDIs (XFLOADf64 XForm:$src), 2), 4622fe6060f1SDimitry Andric (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>; 46235ffd83dbSDimitry Andric 4624fe6060f1SDimitry Andricdef : Pat<(store (i64 (extractelt v2i64:$A, 0)), XForm:$src), 46255ffd83dbSDimitry Andric (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4626fe6060f1SDimitry Andric sub_64), XForm:$src)>; 4627fe6060f1SDimitry Andricdef : Pat<(store (f64 (extractelt v2f64:$A, 0)), XForm:$src), 46285ffd83dbSDimitry Andric (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4629fe6060f1SDimitry Andric sub_64), XForm:$src)>; 4630fe6060f1SDimitry Andricdef : Pat<(store (i64 (extractelt v2i64:$A, 1)), XForm:$src), 4631fe6060f1SDimitry Andric (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), XForm:$src)>; 4632fe6060f1SDimitry Andricdef : Pat<(store (f64 (extractelt v2f64:$A, 1)), XForm:$src), 4633fe6060f1SDimitry Andric (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), XForm:$src)>; 4634fe6060f1SDimitry Andricdef : Pat<(store (i64 (extractelt v2i64:$A, 0)), DSForm:$src), 46355ffd83dbSDimitry Andric (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4636fe6060f1SDimitry Andric sub_64), DSForm:$src)>; 4637fe6060f1SDimitry Andricdef : Pat<(store (f64 (extractelt v2f64:$A, 0)), DSForm:$src), 46385ffd83dbSDimitry Andric (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), 4639fe6060f1SDimitry Andric DSForm:$src)>; 4640fe6060f1SDimitry Andricdef : Pat<(store (i64 (extractelt v2i64:$A, 1)), DSForm:$src), 4641fe6060f1SDimitry Andric (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), DSForm:$src)>; 4642fe6060f1SDimitry Andricdef : Pat<(store (f64 (extractelt v2f64:$A, 1)), DSForm:$src), 4643fe6060f1SDimitry Andric (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), DSForm:$src)>; 46445ffd83dbSDimitry Andric 46455ffd83dbSDimitry Andric// (Un)Signed DWord vector extract -> QP 46465ffd83dbSDimitry Andricdef : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))), 46475ffd83dbSDimitry Andric (f128 (XSCVSDQP 46485ffd83dbSDimitry Andric (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>; 46495ffd83dbSDimitry Andricdef : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))), 46505ffd83dbSDimitry Andric (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>; 46515ffd83dbSDimitry Andricdef : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))), 46525ffd83dbSDimitry Andric (f128 (XSCVUDQP 46535ffd83dbSDimitry Andric (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>; 46545ffd83dbSDimitry Andricdef : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))), 46555ffd83dbSDimitry Andric (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>; 46565ffd83dbSDimitry Andric 46575ffd83dbSDimitry Andric// (Un)Signed Word vector extract -> QP 46585ffd83dbSDimitry Andricforeach Idx = [[0,3],[1,2],[3,0]] in { 46595ffd83dbSDimitry Andric def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))), 46605ffd83dbSDimitry Andric (f128 (XSCVSDQP (EXTRACT_SUBREG 46615ffd83dbSDimitry Andric (VEXTSW2D (VSPLTW !head(!tail(Idx)), $src)), 46625ffd83dbSDimitry Andric sub_64)))>; 46635ffd83dbSDimitry Andric} 46645ffd83dbSDimitry Andricdef : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 2)))), 46655ffd83dbSDimitry Andric (f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>; 46665ffd83dbSDimitry Andric 46675ffd83dbSDimitry Andricforeach Idx = [[0,12],[1,8],[2,4],[3,0]] in { 46685ffd83dbSDimitry Andric def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))), 46695ffd83dbSDimitry Andric (f128 (XSCVUDQP (XXEXTRACTUW $src, !head(!tail(Idx)))))>; 46700b57cec5SDimitry Andric} 46710b57cec5SDimitry Andric 4672fe6060f1SDimitry Andric// (Un)Signed HWord vector extract -> QP/DP/SP 46735ffd83dbSDimitry Andric// The Nested foreach lists identifies the vector element and corresponding 46745ffd83dbSDimitry Andric// register byte location. 46755ffd83dbSDimitry Andricforeach Idx = [[0,14],[1,12],[2,10],[3,8],[4,6],[5,4],[6,2],[7,0]] in { 46765ffd83dbSDimitry Andric def : Pat<(f128 (sint_to_fp 46775ffd83dbSDimitry Andric (i32 (sext_inreg 46785ffd83dbSDimitry Andric (vector_extract v8i16:$src, !head(Idx)), i16)))), 46795ffd83dbSDimitry Andric (f128 (XSCVSDQP 46805ffd83dbSDimitry Andric (EXTRACT_SUBREG (VEXTSH2D 46815ffd83dbSDimitry Andric (VEXTRACTUH !head(!tail(Idx)), $src)), 46825ffd83dbSDimitry Andric sub_64)))>; 46835ffd83dbSDimitry Andric def : Pat<(f128 (uint_to_fp 46845ffd83dbSDimitry Andric (and (i32 (vector_extract v8i16:$src, !head(Idx))), 46855ffd83dbSDimitry Andric 65535))), 46865ffd83dbSDimitry Andric (f128 (XSCVUDQP (EXTRACT_SUBREG 46875ffd83dbSDimitry Andric (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>; 4688fe6060f1SDimitry Andric def : Pat<(f32 (PPCfcfidus 4689fe6060f1SDimitry Andric (f64 (PPCmtvsrz 4690fe6060f1SDimitry Andric (and (i32 (vector_extract v8i16:$src, !head(Idx))), 4691fe6060f1SDimitry Andric 65535))))), 4692fe6060f1SDimitry Andric (f32 (XSCVUXDSP (EXTRACT_SUBREG 4693fe6060f1SDimitry Andric (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>; 4694fe6060f1SDimitry Andric def : Pat<(f32 (PPCfcfids 4695fe6060f1SDimitry Andric (f64 (PPCmtvsra 4696fe6060f1SDimitry Andric (i32 (sext_inreg (vector_extract v8i16:$src, 4697fe6060f1SDimitry Andric !head(Idx)), i16)))))), 4698fe6060f1SDimitry Andric (f32 (XSCVSXDSP 4699fe6060f1SDimitry Andric (EXTRACT_SUBREG 4700fe6060f1SDimitry Andric (VEXTSH2D (VEXTRACTUH !head(!tail(Idx)), $src)), 4701fe6060f1SDimitry Andric sub_64)))>; 4702fe6060f1SDimitry Andric def : Pat<(f64 (PPCfcfidu 4703fe6060f1SDimitry Andric (f64 (PPCmtvsrz 4704fe6060f1SDimitry Andric (and (i32 (vector_extract v8i16:$src, !head(Idx))), 4705fe6060f1SDimitry Andric 65535))))), 4706fe6060f1SDimitry Andric (f64 (XSCVUXDDP (EXTRACT_SUBREG 4707fe6060f1SDimitry Andric (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>; 4708fe6060f1SDimitry Andric def : Pat<(f64 (PPCfcfid 4709fe6060f1SDimitry Andric (f64 (PPCmtvsra 4710fe6060f1SDimitry Andric (i32 (sext_inreg 4711fe6060f1SDimitry Andric (vector_extract v8i16:$src, !head(Idx)), i16)))))), 4712fe6060f1SDimitry Andric (f64 (XSCVSXDDP 4713fe6060f1SDimitry Andric (EXTRACT_SUBREG (VEXTSH2D 4714fe6060f1SDimitry Andric (VEXTRACTUH !head(!tail(Idx)), $src)), 4715fe6060f1SDimitry Andric sub_64)))>; 47160b57cec5SDimitry Andric} 47170b57cec5SDimitry Andric 4718fe6060f1SDimitry Andric// (Un)Signed Byte vector extract -> QP/DP/SP 47195ffd83dbSDimitry Andricforeach Idx = [[0,15],[1,14],[2,13],[3,12],[4,11],[5,10],[6,9],[7,8],[8,7], 47205ffd83dbSDimitry Andric [9,6],[10,5],[11,4],[12,3],[13,2],[14,1],[15,0]] in { 47215ffd83dbSDimitry Andric def : Pat<(f128 (sint_to_fp 47225ffd83dbSDimitry Andric (i32 (sext_inreg 47235ffd83dbSDimitry Andric (vector_extract v16i8:$src, !head(Idx)), i8)))), 47245ffd83dbSDimitry Andric (f128 (XSCVSDQP 47255ffd83dbSDimitry Andric (EXTRACT_SUBREG 47265ffd83dbSDimitry Andric (VEXTSB2D (VEXTRACTUB !head(!tail(Idx)), $src)), 47275ffd83dbSDimitry Andric sub_64)))>; 47285ffd83dbSDimitry Andric def : Pat<(f128 (uint_to_fp 47295ffd83dbSDimitry Andric (and (i32 (vector_extract v16i8:$src, !head(Idx))), 47305ffd83dbSDimitry Andric 255))), 47315ffd83dbSDimitry Andric (f128 (XSCVUDQP 47325ffd83dbSDimitry Andric (EXTRACT_SUBREG 47335ffd83dbSDimitry Andric (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>; 4734fe6060f1SDimitry Andric 4735fe6060f1SDimitry Andric def : Pat<(f32 (PPCfcfidus 4736fe6060f1SDimitry Andric (f64 (PPCmtvsrz 4737fe6060f1SDimitry Andric (and (i32 (vector_extract v16i8:$src, !head(Idx))), 4738fe6060f1SDimitry Andric 255))))), 4739fe6060f1SDimitry Andric (f32 (XSCVUXDSP (EXTRACT_SUBREG 4740fe6060f1SDimitry Andric (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>; 4741fe6060f1SDimitry Andric def : Pat<(f32 (PPCfcfids 4742fe6060f1SDimitry Andric (f64 (PPCmtvsra 4743fe6060f1SDimitry Andric (i32 (sext_inreg 4744fe6060f1SDimitry Andric (vector_extract v16i8:$src, !head(Idx)), i8)))))), 4745fe6060f1SDimitry Andric (f32 (XSCVSXDSP 4746fe6060f1SDimitry Andric (EXTRACT_SUBREG (VEXTSH2D 4747fe6060f1SDimitry Andric (VEXTRACTUB !head(!tail(Idx)), $src)), 4748fe6060f1SDimitry Andric sub_64)))>; 4749fe6060f1SDimitry Andric def : Pat<(f64 (PPCfcfidu 4750fe6060f1SDimitry Andric (f64 (PPCmtvsrz 4751fe6060f1SDimitry Andric (and (i32 4752fe6060f1SDimitry Andric (vector_extract v16i8:$src, !head(Idx))), 255))))), 4753fe6060f1SDimitry Andric (f64 (XSCVUXDDP (EXTRACT_SUBREG 4754fe6060f1SDimitry Andric (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>; 4755fe6060f1SDimitry Andric def : Pat<(f64 (PPCfcfidu 4756fe6060f1SDimitry Andric (f64 (PPCmtvsra 4757fe6060f1SDimitry Andric (i32 (sext_inreg 4758fe6060f1SDimitry Andric (vector_extract v16i8:$src, !head(Idx)), i8)))))), 4759fe6060f1SDimitry Andric (f64 (XSCVSXDDP 4760fe6060f1SDimitry Andric (EXTRACT_SUBREG (VEXTSH2D 4761fe6060f1SDimitry Andric (VEXTRACTUB !head(!tail(Idx)), $src)), 4762fe6060f1SDimitry Andric sub_64)))>; 4763fe6060f1SDimitry Andric 4764fe6060f1SDimitry Andric def : Pat<(f64 (PPCfcfid 4765fe6060f1SDimitry Andric (f64 (PPCmtvsra 4766fe6060f1SDimitry Andric (i32 (sext_inreg 4767fe6060f1SDimitry Andric (vector_extract v16i8:$src, !head(Idx)), i8)))))), 4768fe6060f1SDimitry Andric (f64 (XSCVSXDDP 4769fe6060f1SDimitry Andric (EXTRACT_SUBREG (VEXTSH2D 4770fe6060f1SDimitry Andric (VEXTRACTUH !head(!tail(Idx)), $src)), 4771fe6060f1SDimitry Andric sub_64)))>; 47725ffd83dbSDimitry Andric} 47735ffd83dbSDimitry Andric 47745ffd83dbSDimitry Andric// Unsiged int in vsx register -> QP 47755ffd83dbSDimitry Andricdef : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))), 47765ffd83dbSDimitry Andric (f128 (XSCVUDQP 47775ffd83dbSDimitry Andric (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 8)))>; 47785ffd83dbSDimitry Andric} // HasVSX, HasP9Vector, IsLittleEndian 47795ffd83dbSDimitry Andric 47805ffd83dbSDimitry Andric// Any Power9 VSX subtarget that supports Power9 Altivec. 47815ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasP9Altivec] in { 4782881fc203SDimitry Andric// Unsigned absolute-difference. 4783881fc203SDimitry Andricdef : Pat<(v4i32 (abdu v4i32:$A, v4i32:$B)), 47840b57cec5SDimitry Andric (v4i32 (VABSDUW $A, $B))>; 47850b57cec5SDimitry Andric 4786881fc203SDimitry Andricdef : Pat<(v8i16 (abdu v8i16:$A, v8i16:$B)), 47870b57cec5SDimitry Andric (v8i16 (VABSDUH $A, $B))>; 47880b57cec5SDimitry Andric 4789881fc203SDimitry Andricdef : Pat<(v16i8 (abdu v16i8:$A, v16i8:$B)), 47900b57cec5SDimitry Andric (v16i8 (VABSDUB $A, $B))>; 47910b57cec5SDimitry Andric 4792881fc203SDimitry Andric// Signed absolute-difference. 4793881fc203SDimitry Andric// Power9 VABSD* instructions are designed to support unsigned integer 4794881fc203SDimitry Andric// vectors (byte/halfword/word), if we want to make use of them for signed 4795881fc203SDimitry Andric// integer vectors, we have to flip their sign bits first. To flip sign bit 4796881fc203SDimitry Andric// for byte/halfword integer vector would become inefficient, but for word 4797881fc203SDimitry Andric// integer vector, we can leverage XVNEGSP to make it efficiently. 4798881fc203SDimitry Andricdef : Pat<(v4i32 (abds v4i32:$A, v4i32:$B)), 47990b57cec5SDimitry Andric (v4i32 (VABSDUW (XVNEGSP $A), (XVNEGSP $B)))>; 48005ffd83dbSDimitry Andric} // HasVSX, HasP9Altivec 48015ffd83dbSDimitry Andric 4802e8d8bef9SDimitry Andric// Big endian Power9 64Bit VSX subtargets with P9 Altivec support. 4803e8d8bef9SDimitry Andriclet Predicates = [HasVSX, HasP9Altivec, IsBigEndian, IsPPC64] in { 48045ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v16i8:$S, i64:$Idx)))), 48055ffd83dbSDimitry Andric (VEXTUBLX $Idx, $S)>; 48065ffd83dbSDimitry Andric 48075ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, i64:$Idx)))), 48085ffd83dbSDimitry Andric (VEXTUHLX (RLWINM8 $Idx, 1, 28, 30), $S)>; 48095ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 0)))), 48105ffd83dbSDimitry Andric (VEXTUHLX (LI8 0), $S)>; 48115ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 1)))), 48125ffd83dbSDimitry Andric (VEXTUHLX (LI8 2), $S)>; 48135ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 2)))), 48145ffd83dbSDimitry Andric (VEXTUHLX (LI8 4), $S)>; 48155ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 3)))), 48165ffd83dbSDimitry Andric (VEXTUHLX (LI8 6), $S)>; 48175ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 4)))), 48185ffd83dbSDimitry Andric (VEXTUHLX (LI8 8), $S)>; 48195ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 5)))), 48205ffd83dbSDimitry Andric (VEXTUHLX (LI8 10), $S)>; 48215ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 6)))), 48225ffd83dbSDimitry Andric (VEXTUHLX (LI8 12), $S)>; 48235ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 7)))), 48245ffd83dbSDimitry Andric (VEXTUHLX (LI8 14), $S)>; 48255ffd83dbSDimitry Andric 48265ffd83dbSDimitry Andricdef : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, i64:$Idx)))), 48275ffd83dbSDimitry Andric (VEXTUWLX (RLWINM8 $Idx, 2, 28, 29), $S)>; 48285ffd83dbSDimitry Andricdef : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 0)))), 48295ffd83dbSDimitry Andric (VEXTUWLX (LI8 0), $S)>; 48305ffd83dbSDimitry Andric 48315ffd83dbSDimitry Andric// For extracting BE word 1, MFVSRWZ is better than VEXTUWLX 48325ffd83dbSDimitry Andricdef : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 1)))), 48335ffd83dbSDimitry Andric (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 48345ffd83dbSDimitry Andric (i32 VectorExtractions.LE_WORD_2), sub_32)>; 48355ffd83dbSDimitry Andricdef : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 2)))), 48365ffd83dbSDimitry Andric (VEXTUWLX (LI8 8), $S)>; 48375ffd83dbSDimitry Andricdef : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 3)))), 48385ffd83dbSDimitry Andric (VEXTUWLX (LI8 12), $S)>; 48395ffd83dbSDimitry Andric 48405ffd83dbSDimitry Andricdef : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, i64:$Idx)))), 48415ffd83dbSDimitry Andric (EXTSW (VEXTUWLX (RLWINM8 $Idx, 2, 28, 29), $S))>; 48425ffd83dbSDimitry Andricdef : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 0)))), 48435ffd83dbSDimitry Andric (EXTSW (VEXTUWLX (LI8 0), $S))>; 48445ffd83dbSDimitry Andric// For extracting BE word 1, MFVSRWZ is better than VEXTUWLX 48455ffd83dbSDimitry Andricdef : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 1)))), 48465ffd83dbSDimitry Andric (EXTSW (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 48475ffd83dbSDimitry Andric (i32 VectorExtractions.LE_WORD_2), sub_32))>; 48485ffd83dbSDimitry Andricdef : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 2)))), 48495ffd83dbSDimitry Andric (EXTSW (VEXTUWLX (LI8 8), $S))>; 48505ffd83dbSDimitry Andricdef : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 3)))), 48515ffd83dbSDimitry Andric (EXTSW (VEXTUWLX (LI8 12), $S))>; 48525ffd83dbSDimitry Andric 48535ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)), 48545ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBLX $Idx, $S), sub_32))>; 48555ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 0)), 48565ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 0), $S), sub_32))>; 48575ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 1)), 48585ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 1), $S), sub_32))>; 48595ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 2)), 48605ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 2), $S), sub_32))>; 48615ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 3)), 48625ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 3), $S), sub_32))>; 48635ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 4)), 48645ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 4), $S), sub_32))>; 48655ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 5)), 48665ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 5), $S), sub_32))>; 48675ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 6)), 48685ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 6), $S), sub_32))>; 48695ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 7)), 48705ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 7), $S), sub_32))>; 48715ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 8)), 48725ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 8), $S), sub_32))>; 48735ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 9)), 48745ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 9), $S), sub_32))>; 48755ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 10)), 48765ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 10), $S), sub_32))>; 48775ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 11)), 48785ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 11), $S), sub_32))>; 48795ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 12)), 48805ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 12), $S), sub_32))>; 48815ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 13)), 48825ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 13), $S), sub_32))>; 48835ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 14)), 48845ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 14), $S), sub_32))>; 48855ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 15)), 48865ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 15), $S), sub_32))>; 48875ffd83dbSDimitry Andric 48885ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)), 48895ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHLX 48905ffd83dbSDimitry Andric (RLWINM8 $Idx, 1, 28, 30), $S), sub_32))>; 48915ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 0)), 48925ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 0), $S), sub_32))>; 48935ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 1)), 48945ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 2), $S), sub_32))>; 48955ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 2)), 48965ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 4), $S), sub_32))>; 48975ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 3)), 48985ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 6), $S), sub_32))>; 48995ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 4)), 49005ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 8), $S), sub_32))>; 49015ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 5)), 49025ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 10), $S), sub_32))>; 49035ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 6)), 49045ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 12), $S), sub_32))>; 49055ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 6)), 49065ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 14), $S), sub_32))>; 49075ffd83dbSDimitry Andric 49085ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)), 49095ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUWLX 49105ffd83dbSDimitry Andric (RLWINM8 $Idx, 2, 28, 29), $S), sub_32))>; 49115ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, 0)), 49125ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 0), $S), sub_32))>; 49135ffd83dbSDimitry Andric// For extracting BE word 1, MFVSRWZ is better than VEXTUWLX 49145ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, 1)), 49155ffd83dbSDimitry Andric (i32 VectorExtractions.LE_WORD_2)>; 49165ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, 2)), 49175ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 8), $S), sub_32))>; 49185ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, 3)), 49195ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 12), $S), sub_32))>; 49205ffd83dbSDimitry Andric 49215ffd83dbSDimitry Andric// P9 Altivec instructions that can be used to build vectors. 49225ffd83dbSDimitry Andric// Adding them to PPCInstrVSX.td rather than PPCAltivecVSX.td to compete 49235ffd83dbSDimitry Andric// with complexities of existing build vector patterns in this file. 49245ffd83dbSDimitry Andricdef : Pat<(v2i64 (build_vector WordToDWord.BE_A0, WordToDWord.BE_A1)), 49255ffd83dbSDimitry Andric (v2i64 (VEXTSW2D $A))>; 49265ffd83dbSDimitry Andricdef : Pat<(v2i64 (build_vector HWordToDWord.BE_A0, HWordToDWord.BE_A1)), 49275ffd83dbSDimitry Andric (v2i64 (VEXTSH2D $A))>; 49285ffd83dbSDimitry Andricdef : Pat<(v4i32 (build_vector HWordToWord.BE_A0, HWordToWord.BE_A1, 49295ffd83dbSDimitry Andric HWordToWord.BE_A2, HWordToWord.BE_A3)), 49305ffd83dbSDimitry Andric (v4i32 (VEXTSH2W $A))>; 49315ffd83dbSDimitry Andricdef : Pat<(v4i32 (build_vector ByteToWord.BE_A0, ByteToWord.BE_A1, 49325ffd83dbSDimitry Andric ByteToWord.BE_A2, ByteToWord.BE_A3)), 49335ffd83dbSDimitry Andric (v4i32 (VEXTSB2W $A))>; 49345ffd83dbSDimitry Andricdef : Pat<(v2i64 (build_vector ByteToDWord.BE_A0, ByteToDWord.BE_A1)), 49355ffd83dbSDimitry Andric (v2i64 (VEXTSB2D $A))>; 4936e8d8bef9SDimitry Andric} // HasVSX, HasP9Altivec, IsBigEndian, IsPPC64 49375ffd83dbSDimitry Andric 49385ffd83dbSDimitry Andric// Little endian Power9 VSX subtargets with P9 Altivec support. 49395ffd83dbSDimitry Andriclet Predicates = [HasVSX, HasP9Altivec, IsLittleEndian] in { 49405ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v16i8:$S, i64:$Idx)))), 49415ffd83dbSDimitry Andric (VEXTUBRX $Idx, $S)>; 49425ffd83dbSDimitry Andric 49435ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, i64:$Idx)))), 49445ffd83dbSDimitry Andric (VEXTUHRX (RLWINM8 $Idx, 1, 28, 30), $S)>; 49455ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 0)))), 49465ffd83dbSDimitry Andric (VEXTUHRX (LI8 0), $S)>; 49475ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 1)))), 49485ffd83dbSDimitry Andric (VEXTUHRX (LI8 2), $S)>; 49495ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 2)))), 49505ffd83dbSDimitry Andric (VEXTUHRX (LI8 4), $S)>; 49515ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 3)))), 49525ffd83dbSDimitry Andric (VEXTUHRX (LI8 6), $S)>; 49535ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 4)))), 49545ffd83dbSDimitry Andric (VEXTUHRX (LI8 8), $S)>; 49555ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 5)))), 49565ffd83dbSDimitry Andric (VEXTUHRX (LI8 10), $S)>; 49575ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 6)))), 49585ffd83dbSDimitry Andric (VEXTUHRX (LI8 12), $S)>; 49595ffd83dbSDimitry Andricdef : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 7)))), 49605ffd83dbSDimitry Andric (VEXTUHRX (LI8 14), $S)>; 49615ffd83dbSDimitry Andric 49625ffd83dbSDimitry Andricdef : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, i64:$Idx)))), 49635ffd83dbSDimitry Andric (VEXTUWRX (RLWINM8 $Idx, 2, 28, 29), $S)>; 49645ffd83dbSDimitry Andricdef : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 0)))), 49655ffd83dbSDimitry Andric (VEXTUWRX (LI8 0), $S)>; 49665ffd83dbSDimitry Andricdef : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 1)))), 49675ffd83dbSDimitry Andric (VEXTUWRX (LI8 4), $S)>; 49685ffd83dbSDimitry Andric// For extracting LE word 2, MFVSRWZ is better than VEXTUWRX 49695ffd83dbSDimitry Andricdef : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 2)))), 49705ffd83dbSDimitry Andric (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 49715ffd83dbSDimitry Andric (i32 VectorExtractions.LE_WORD_2), sub_32)>; 49725ffd83dbSDimitry Andricdef : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 3)))), 49735ffd83dbSDimitry Andric (VEXTUWRX (LI8 12), $S)>; 49745ffd83dbSDimitry Andric 49755ffd83dbSDimitry Andricdef : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, i64:$Idx)))), 49765ffd83dbSDimitry Andric (EXTSW (VEXTUWRX (RLWINM8 $Idx, 2, 28, 29), $S))>; 49775ffd83dbSDimitry Andricdef : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 0)))), 49785ffd83dbSDimitry Andric (EXTSW (VEXTUWRX (LI8 0), $S))>; 49795ffd83dbSDimitry Andricdef : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 1)))), 49805ffd83dbSDimitry Andric (EXTSW (VEXTUWRX (LI8 4), $S))>; 49815ffd83dbSDimitry Andric// For extracting LE word 2, MFVSRWZ is better than VEXTUWRX 49825ffd83dbSDimitry Andricdef : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 2)))), 49835ffd83dbSDimitry Andric (EXTSW (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 49845ffd83dbSDimitry Andric (i32 VectorExtractions.LE_WORD_2), sub_32))>; 49855ffd83dbSDimitry Andricdef : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 3)))), 49865ffd83dbSDimitry Andric (EXTSW (VEXTUWRX (LI8 12), $S))>; 49875ffd83dbSDimitry Andric 49885ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)), 49895ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBRX $Idx, $S), sub_32))>; 49905ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 0)), 49915ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 0), $S), sub_32))>; 49925ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 1)), 49935ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 1), $S), sub_32))>; 49945ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 2)), 49955ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 2), $S), sub_32))>; 49965ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 3)), 49975ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 3), $S), sub_32))>; 49985ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 4)), 49995ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 4), $S), sub_32))>; 50005ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 5)), 50015ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 5), $S), sub_32))>; 50025ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 6)), 50035ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 6), $S), sub_32))>; 50045ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 7)), 50055ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 7), $S), sub_32))>; 50065ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 8)), 50075ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 8), $S), sub_32))>; 50085ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 9)), 50095ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 9), $S), sub_32))>; 50105ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 10)), 50115ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 10), $S), sub_32))>; 50125ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 11)), 50135ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 11), $S), sub_32))>; 50145ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 12)), 50155ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 12), $S), sub_32))>; 50165ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 13)), 50175ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 13), $S), sub_32))>; 50185ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 14)), 50195ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 14), $S), sub_32))>; 50205ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v16i8:$S, 15)), 50215ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 15), $S), sub_32))>; 50225ffd83dbSDimitry Andric 50235ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)), 50245ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHRX 50255ffd83dbSDimitry Andric (RLWINM8 $Idx, 1, 28, 30), $S), sub_32))>; 50265ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 0)), 50275ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 0), $S), sub_32))>; 50285ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 1)), 50295ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 2), $S), sub_32))>; 50305ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 2)), 50315ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 4), $S), sub_32))>; 50325ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 3)), 50335ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 6), $S), sub_32))>; 50345ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 4)), 50355ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 8), $S), sub_32))>; 50365ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 5)), 50375ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 10), $S), sub_32))>; 50385ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 6)), 50395ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 12), $S), sub_32))>; 50405ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v8i16:$S, 6)), 50415ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 14), $S), sub_32))>; 50425ffd83dbSDimitry Andric 50435ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)), 50445ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUWRX 50455ffd83dbSDimitry Andric (RLWINM8 $Idx, 2, 28, 29), $S), sub_32))>; 50465ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, 0)), 50475ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 0), $S), sub_32))>; 50485ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, 1)), 50495ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 4), $S), sub_32))>; 50505ffd83dbSDimitry Andric// For extracting LE word 2, MFVSRWZ is better than VEXTUWRX 50515ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, 2)), 50525ffd83dbSDimitry Andric (i32 VectorExtractions.LE_WORD_2)>; 50535ffd83dbSDimitry Andricdef : Pat<(i32 (vector_extract v4i32:$S, 3)), 50545ffd83dbSDimitry Andric (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 12), $S), sub_32))>; 50555ffd83dbSDimitry Andric 50565ffd83dbSDimitry Andric// P9 Altivec instructions that can be used to build vectors. 50575ffd83dbSDimitry Andric// Adding them to PPCInstrVSX.td rather than PPCAltivecVSX.td to compete 50585ffd83dbSDimitry Andric// with complexities of existing build vector patterns in this file. 50595ffd83dbSDimitry Andricdef : Pat<(v2i64 (build_vector WordToDWord.LE_A0, WordToDWord.LE_A1)), 50605ffd83dbSDimitry Andric (v2i64 (VEXTSW2D $A))>; 50615ffd83dbSDimitry Andricdef : Pat<(v2i64 (build_vector HWordToDWord.LE_A0, HWordToDWord.LE_A1)), 50625ffd83dbSDimitry Andric (v2i64 (VEXTSH2D $A))>; 50635ffd83dbSDimitry Andricdef : Pat<(v4i32 (build_vector HWordToWord.LE_A0, HWordToWord.LE_A1, 50645ffd83dbSDimitry Andric HWordToWord.LE_A2, HWordToWord.LE_A3)), 50655ffd83dbSDimitry Andric (v4i32 (VEXTSH2W $A))>; 50665ffd83dbSDimitry Andricdef : Pat<(v4i32 (build_vector ByteToWord.LE_A0, ByteToWord.LE_A1, 50675ffd83dbSDimitry Andric ByteToWord.LE_A2, ByteToWord.LE_A3)), 50685ffd83dbSDimitry Andric (v4i32 (VEXTSB2W $A))>; 50695ffd83dbSDimitry Andricdef : Pat<(v2i64 (build_vector ByteToDWord.LE_A0, ByteToDWord.LE_A1)), 50705ffd83dbSDimitry Andric (v2i64 (VEXTSB2D $A))>; 50715ffd83dbSDimitry Andric} // HasVSX, HasP9Altivec, IsLittleEndian 50725ffd83dbSDimitry Andric 5073e8d8bef9SDimitry Andric// Big endian 64Bit VSX subtarget that supports additional direct moves from 5074e8d8bef9SDimitry Andric// ISA3.0. 5075e8d8bef9SDimitry Andriclet Predicates = [HasVSX, IsISA3_0, HasDirectMove, IsBigEndian, IsPPC64] in { 50765ffd83dbSDimitry Andricdef : Pat<(i64 (extractelt v2i64:$A, 1)), 50775ffd83dbSDimitry Andric (i64 (MFVSRLD $A))>; 50785ffd83dbSDimitry Andric// Better way to build integer vectors if we have MTVSRDD. Big endian. 50795ffd83dbSDimitry Andricdef : Pat<(v2i64 (build_vector i64:$rB, i64:$rA)), 50805ffd83dbSDimitry Andric (v2i64 (MTVSRDD $rB, $rA))>; 50815ffd83dbSDimitry Andricdef : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)), 50825ffd83dbSDimitry Andric (MTVSRDD 50835ffd83dbSDimitry Andric (RLDIMI AnyExts.B, AnyExts.A, 32, 0), 50845ffd83dbSDimitry Andric (RLDIMI AnyExts.D, AnyExts.C, 32, 0))>; 50855ffd83dbSDimitry Andric 50865ffd83dbSDimitry Andricdef : Pat<(f128 (PPCbuild_fp128 i64:$rB, i64:$rA)), 50875ffd83dbSDimitry Andric (f128 (COPY_TO_REGCLASS (MTVSRDD $rB, $rA), VRRC))>; 5088e8d8bef9SDimitry Andric} // HasVSX, IsISA3_0, HasDirectMove, IsBigEndian, IsPPC64 50895ffd83dbSDimitry Andric 50905ffd83dbSDimitry Andric// Little endian VSX subtarget that supports direct moves from ISA3.0. 50915ffd83dbSDimitry Andriclet Predicates = [HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian] in { 50925ffd83dbSDimitry Andricdef : Pat<(i64 (extractelt v2i64:$A, 0)), 50935ffd83dbSDimitry Andric (i64 (MFVSRLD $A))>; 50945ffd83dbSDimitry Andric// Better way to build integer vectors if we have MTVSRDD. Little endian. 50955ffd83dbSDimitry Andricdef : Pat<(v2i64 (build_vector i64:$rA, i64:$rB)), 50965ffd83dbSDimitry Andric (v2i64 (MTVSRDD $rB, $rA))>; 50975ffd83dbSDimitry Andricdef : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)), 50985ffd83dbSDimitry Andric (MTVSRDD 50995ffd83dbSDimitry Andric (RLDIMI AnyExts.C, AnyExts.D, 32, 0), 51005ffd83dbSDimitry Andric (RLDIMI AnyExts.A, AnyExts.B, 32, 0))>; 51015ffd83dbSDimitry Andric 51025ffd83dbSDimitry Andricdef : Pat<(f128 (PPCbuild_fp128 i64:$rA, i64:$rB)), 51035ffd83dbSDimitry Andric (f128 (COPY_TO_REGCLASS (MTVSRDD $rB, $rA), VRRC))>; 51045ffd83dbSDimitry Andric} // HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian 51055ffd83dbSDimitry Andric} // AddedComplexity = 400 51065ffd83dbSDimitry Andric 51075ffd83dbSDimitry Andric//---------------------------- Instruction aliases ---------------------------// 51085ffd83dbSDimitry Andricdef : InstAlias<"xvmovdp $XT, $XB", 51095ffd83dbSDimitry Andric (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)>; 51105ffd83dbSDimitry Andricdef : InstAlias<"xvmovsp $XT, $XB", 51115ffd83dbSDimitry Andric (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB)>; 51125ffd83dbSDimitry Andric 5113e8d8bef9SDimitry Andric// Certain versions of the AIX assembler may missassemble these mnemonics. 5114e8d8bef9SDimitry Andriclet Predicates = [ModernAs] in { 51155ffd83dbSDimitry Andric def : InstAlias<"xxspltd $XT, $XB, 0", 51165ffd83dbSDimitry Andric (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0)>; 51175ffd83dbSDimitry Andric def : InstAlias<"xxspltd $XT, $XB, 1", 51185ffd83dbSDimitry Andric (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3)>; 5119e8d8bef9SDimitry Andric def : InstAlias<"xxspltd $XT, $XB, 0", 5120e8d8bef9SDimitry Andric (XXPERMDIs vsrc:$XT, vsfrc:$XB, 0)>; 5121e8d8bef9SDimitry Andric def : InstAlias<"xxspltd $XT, $XB, 1", 5122e8d8bef9SDimitry Andric (XXPERMDIs vsrc:$XT, vsfrc:$XB, 3)>; 5123e8d8bef9SDimitry Andric} 5124e8d8bef9SDimitry Andric 51255ffd83dbSDimitry Andricdef : InstAlias<"xxmrghd $XT, $XA, $XB", 51265ffd83dbSDimitry Andric (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0)>; 51275ffd83dbSDimitry Andricdef : InstAlias<"xxmrgld $XT, $XA, $XB", 51285ffd83dbSDimitry Andric (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3)>; 51295ffd83dbSDimitry Andricdef : InstAlias<"xxswapd $XT, $XB", 51305ffd83dbSDimitry Andric (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>; 51315ffd83dbSDimitry Andricdef : InstAlias<"xxswapd $XT, $XB", 51325ffd83dbSDimitry Andric (XXPERMDIs vsrc:$XT, vsfrc:$XB, 2)>; 51335ffd83dbSDimitry Andricdef : InstAlias<"mfvrd $rA, $XT", 51345ffd83dbSDimitry Andric (MFVRD g8rc:$rA, vrrc:$XT), 0>; 51355ffd83dbSDimitry Andricdef : InstAlias<"mffprd $rA, $src", 51365ffd83dbSDimitry Andric (MFVSRD g8rc:$rA, f8rc:$src)>; 51375ffd83dbSDimitry Andricdef : InstAlias<"mtvrd $XT, $rA", 51385ffd83dbSDimitry Andric (MTVRD vrrc:$XT, g8rc:$rA), 0>; 51395ffd83dbSDimitry Andricdef : InstAlias<"mtfprd $dst, $rA", 51405ffd83dbSDimitry Andric (MTVSRD f8rc:$dst, g8rc:$rA)>; 51415ffd83dbSDimitry Andricdef : InstAlias<"mfvrwz $rA, $XT", 51425ffd83dbSDimitry Andric (MFVRWZ gprc:$rA, vrrc:$XT), 0>; 51435ffd83dbSDimitry Andricdef : InstAlias<"mffprwz $rA, $src", 51445ffd83dbSDimitry Andric (MFVSRWZ gprc:$rA, f8rc:$src)>; 51455ffd83dbSDimitry Andricdef : InstAlias<"mtvrwa $XT, $rA", 51465ffd83dbSDimitry Andric (MTVRWA vrrc:$XT, gprc:$rA), 0>; 51475ffd83dbSDimitry Andricdef : InstAlias<"mtfprwa $dst, $rA", 51485ffd83dbSDimitry Andric (MTVSRWA f8rc:$dst, gprc:$rA)>; 51495ffd83dbSDimitry Andricdef : InstAlias<"mtvrwz $XT, $rA", 51505ffd83dbSDimitry Andric (MTVRWZ vrrc:$XT, gprc:$rA), 0>; 51515ffd83dbSDimitry Andricdef : InstAlias<"mtfprwz $dst, $rA", 51525ffd83dbSDimitry Andric (MTVSRWZ f8rc:$dst, gprc:$rA)>; 5153