1 //===-- PPCMachineFunctionInfo.h - Private data used for PowerPC --*- C++ -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the PowerPC specific subclass of MachineFunctionInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H
15 
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/TargetCallingConv.h"
19 
20 namespace llvm {
21 
22 /// PPCFunctionInfo - This class is derived from MachineFunction private
23 /// PowerPC target-specific information for each MachineFunction.
24 class PPCFunctionInfo : public MachineFunctionInfo {
25 public:
26   enum ParamType {
27     FixedType,
28     ShortFloatingPoint,
29     LongFloatingPoint,
30     VectorChar,
31     VectorShort,
32     VectorInt,
33     VectorFloat
34   };
35 
36 private:
37   virtual void anchor();
38 
39   /// FramePointerSaveIndex - Frame index of where the old frame pointer is
40   /// stored.  Also used as an anchor for instructions that need to be altered
41   /// when using frame pointers (dyna_add, dyna_sub.)
42   int FramePointerSaveIndex = 0;
43 
44   /// ReturnAddrSaveIndex - Frame index of where the return address is stored.
45   ///
46   int ReturnAddrSaveIndex = 0;
47 
48   /// Frame index where the old base pointer is stored.
49   int BasePointerSaveIndex = 0;
50 
51   /// Frame index where the old PIC base pointer is stored.
52   int PICBasePointerSaveIndex = 0;
53 
54   /// Frame index where the ROP Protection Hash is stored.
55   int ROPProtectionHashSaveIndex = 0;
56 
57   /// MustSaveLR - Indicates whether LR is defined (or clobbered) in the current
58   /// function.  This is only valid after the initial scan of the function by
59   /// PEI.
60   bool MustSaveLR = false;
61 
62   /// MustSaveTOC - Indicates that the TOC save needs to be performed in the
63   /// prologue of the function. This is typically the case when there are
64   /// indirect calls in the function and it is more profitable to save the
65   /// TOC pointer in the prologue than in the block(s) containing the call(s).
66   bool MustSaveTOC = false;
67 
68   /// Do we have to disable shrink-wrapping? This has to be set if we emit any
69   /// instructions that clobber LR in the entry block because discovering this
70   /// in PEI is too late (happens after shrink-wrapping);
71   bool ShrinkWrapDisabled = false;
72 
73   /// Does this function have any stack spills.
74   bool HasSpills = false;
75 
76   /// Does this function spill using instructions with only r+r (not r+i)
77   /// forms.
78   bool HasNonRISpills = false;
79 
80   /// SpillsCR - Indicates whether CR is spilled in the current function.
81   bool SpillsCR = false;
82 
83   /// DisableNonVolatileCR - Indicates whether non-volatile CR fields would be
84   /// disabled.
85   bool DisableNonVolatileCR = false;
86 
87   /// LRStoreRequired - The bool indicates whether there is some explicit use of
88   /// the LR/LR8 stack slot that is not obvious from scanning the code.  This
89   /// requires that the code generator produce a store of LR to the stack on
90   /// entry, even though LR may otherwise apparently not be used.
91   bool LRStoreRequired = false;
92 
93   /// This function makes use of the PPC64 ELF TOC base pointer (register r2).
94   bool UsesTOCBasePtr = false;
95 
96   /// MinReservedArea - This is the frame size that is at least reserved in a
97   /// potential caller (parameter+linkage area).
98   unsigned MinReservedArea = 0;
99 
100   /// TailCallSPDelta - Stack pointer delta used when tail calling. Maximum
101   /// amount the stack pointer is adjusted to make the frame bigger for tail
102   /// calls. Used for creating an area before the register spill area.
103   int TailCallSPDelta = 0;
104 
105   /// HasFastCall - Does this function contain a fast call. Used to determine
106   /// how the caller's stack pointer should be calculated (epilog/dynamicalloc).
107   bool HasFastCall = false;
108 
109   /// VarArgsFrameIndex - FrameIndex for start of varargs area.
110   int VarArgsFrameIndex = 0;
111 
112   /// VarArgsStackOffset - StackOffset for start of stack
113   /// arguments.
114 
115   int VarArgsStackOffset = 0;
116 
117   /// VarArgsNumGPR - Index of the first unused integer
118   /// register for parameter passing.
119   unsigned VarArgsNumGPR = 0;
120 
121   /// VarArgsNumFPR - Index of the first unused double
122   /// register for parameter passing.
123   unsigned VarArgsNumFPR = 0;
124 
125   /// FixedParmsNum - The number of fixed parameters.
126   unsigned FixedParmsNum = 0;
127 
128   /// FloatingParmsNum - The number of floating parameters.
129   unsigned FloatingParmsNum = 0;
130 
131   /// VectorParmsNum - The number of vector parameters.
132   unsigned VectorParmsNum = 0;
133 
134   /// ParamtersType - Store all the parameter's type that are saved on
135   /// registers.
136   SmallVector<ParamType, 32> ParamtersType;
137 
138   /// CRSpillFrameIndex - FrameIndex for CR spill slot for 32-bit SVR4.
139   int CRSpillFrameIndex = 0;
140 
141   /// If any of CR[2-4] need to be saved in the prologue and restored in the
142   /// epilogue then they are added to this array. This is used for the
143   /// 64-bit SVR4 ABI.
144   SmallVector<Register, 3> MustSaveCRs;
145 
146   /// Whether this uses the PIC Base register or not.
147   bool UsesPICBase = false;
148 
149   /// We keep track attributes for each live-in virtual registers
150   /// to use SExt/ZExt flags in later optimization.
151   std::vector<std::pair<Register, ISD::ArgFlagsTy>> LiveInAttrs;
152 
153 public:
154   explicit PPCFunctionInfo(const Function &F, const TargetSubtargetInfo *STI);
155 
156   MachineFunctionInfo *
157   clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
158         const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
159       const override;
160 
161   int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
162   void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; }
163 
164   int getReturnAddrSaveIndex() const { return ReturnAddrSaveIndex; }
165   void setReturnAddrSaveIndex(int idx) { ReturnAddrSaveIndex = idx; }
166 
167   int getBasePointerSaveIndex() const { return BasePointerSaveIndex; }
168   void setBasePointerSaveIndex(int Idx) { BasePointerSaveIndex = Idx; }
169 
170   int getPICBasePointerSaveIndex() const { return PICBasePointerSaveIndex; }
171   void setPICBasePointerSaveIndex(int Idx) { PICBasePointerSaveIndex = Idx; }
172 
173   int getROPProtectionHashSaveIndex() const {
174     return ROPProtectionHashSaveIndex;
175   }
176   void setROPProtectionHashSaveIndex(int Idx) {
177     ROPProtectionHashSaveIndex = Idx;
178   }
179 
180   unsigned getMinReservedArea() const { return MinReservedArea; }
181   void setMinReservedArea(unsigned size) { MinReservedArea = size; }
182 
183   int getTailCallSPDelta() const { return TailCallSPDelta; }
184   void setTailCallSPDelta(int size) { TailCallSPDelta = size; }
185 
186   /// MustSaveLR - This is set when the prolog/epilog inserter does its initial
187   /// scan of the function. It is true if the LR/LR8 register is ever explicitly
188   /// defined/clobbered in the machine function (e.g. by calls and movpctolr,
189   /// which is used in PIC generation), or if the LR stack slot is explicitly
190   /// referenced by builtin_return_address.
191   void setMustSaveLR(bool U) { MustSaveLR = U; }
192   bool mustSaveLR() const    { return MustSaveLR; }
193 
194   void setMustSaveTOC(bool U) { MustSaveTOC = U; }
195   bool mustSaveTOC() const    { return MustSaveTOC; }
196 
197   /// We certainly don't want to shrink wrap functions if we've emitted a
198   /// MovePCtoLR8 as that has to go into the entry, so the prologue definitely
199   /// has to go into the entry block.
200   void setShrinkWrapDisabled(bool U) { ShrinkWrapDisabled = U; }
201   bool shrinkWrapDisabled() const { return ShrinkWrapDisabled; }
202 
203   void setHasSpills()      { HasSpills = true; }
204   bool hasSpills() const   { return HasSpills; }
205 
206   void setHasNonRISpills()    { HasNonRISpills = true; }
207   bool hasNonRISpills() const { return HasNonRISpills; }
208 
209   void setSpillsCR()       { SpillsCR = true; }
210   bool isCRSpilled() const { return SpillsCR; }
211 
212   void setDisableNonVolatileCR() { DisableNonVolatileCR = true; }
213   bool isNonVolatileCRDisabled() const { return DisableNonVolatileCR; }
214 
215   void setLRStoreRequired() { LRStoreRequired = true; }
216   bool isLRStoreRequired() const { return LRStoreRequired; }
217 
218   void setUsesTOCBasePtr()    { UsesTOCBasePtr = true; }
219   bool usesTOCBasePtr() const { return UsesTOCBasePtr; }
220 
221   void setHasFastCall() { HasFastCall = true; }
222   bool hasFastCall() const { return HasFastCall;}
223 
224   int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
225   void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
226 
227   int getVarArgsStackOffset() const { return VarArgsStackOffset; }
228   void setVarArgsStackOffset(int Offset) { VarArgsStackOffset = Offset; }
229 
230   unsigned getVarArgsNumGPR() const { return VarArgsNumGPR; }
231   void setVarArgsNumGPR(unsigned Num) { VarArgsNumGPR = Num; }
232 
233   unsigned getFixedParmsNum() const { return FixedParmsNum; }
234   unsigned getFloatingPointParmsNum() const { return FloatingParmsNum; }
235   unsigned getVectorParmsNum() const { return VectorParmsNum; }
236   bool hasVectorParms() const { return VectorParmsNum != 0; }
237 
238   uint32_t getParmsType() const;
239 
240   uint32_t getVecExtParmsType() const;
241 
242   void appendParameterType(ParamType Type);
243 
244   unsigned getVarArgsNumFPR() const { return VarArgsNumFPR; }
245   void setVarArgsNumFPR(unsigned Num) { VarArgsNumFPR = Num; }
246 
247   /// This function associates attributes for each live-in virtual register.
248   void addLiveInAttr(Register VReg, ISD::ArgFlagsTy Flags) {
249     LiveInAttrs.push_back(std::make_pair(VReg, Flags));
250   }
251 
252   /// This function returns true if the specified vreg is
253   /// a live-in register and sign-extended.
254   bool isLiveInSExt(Register VReg) const;
255 
256   /// This function returns true if the specified vreg is
257   /// a live-in register and zero-extended.
258   bool isLiveInZExt(Register VReg) const;
259 
260   int getCRSpillFrameIndex() const { return CRSpillFrameIndex; }
261   void setCRSpillFrameIndex(int idx) { CRSpillFrameIndex = idx; }
262 
263   const SmallVectorImpl<Register> &
264     getMustSaveCRs() const { return MustSaveCRs; }
265   void addMustSaveCR(Register Reg) { MustSaveCRs.push_back(Reg); }
266 
267   void setUsesPICBase(bool uses) { UsesPICBase = uses; }
268   bool usesPICBase() const { return UsesPICBase; }
269 
270   MCSymbol *getPICOffsetSymbol(MachineFunction &MF) const;
271 
272   MCSymbol *getGlobalEPSymbol(MachineFunction &MF) const;
273   MCSymbol *getLocalEPSymbol(MachineFunction &MF) const;
274   MCSymbol *getTOCOffsetSymbol(MachineFunction &MF) const;
275 };
276 
277 } // end namespace llvm
278 
279 #endif // LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H
280