1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the PowerPC implementation of the TargetRegisterInfo 10 // class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCRegisterInfo.h" 15 #include "PPCFrameLowering.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "PPCSubtarget.h" 19 #include "PPCTargetMachine.h" 20 #include "llvm/ADT/BitVector.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/ADT/Statistic.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineModuleInfo.h" 27 #include "llvm/CodeGen/MachineRegisterInfo.h" 28 #include "llvm/CodeGen/RegisterScavenging.h" 29 #include "llvm/CodeGen/TargetFrameLowering.h" 30 #include "llvm/CodeGen/TargetInstrInfo.h" 31 #include "llvm/IR/CallingConv.h" 32 #include "llvm/IR/Constants.h" 33 #include "llvm/IR/Function.h" 34 #include "llvm/IR/Type.h" 35 #include "llvm/Support/CommandLine.h" 36 #include "llvm/Support/Debug.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/MathExtras.h" 39 #include "llvm/Support/raw_ostream.h" 40 #include "llvm/Target/TargetMachine.h" 41 #include "llvm/Target/TargetOptions.h" 42 #include <cstdlib> 43 44 using namespace llvm; 45 46 #define DEBUG_TYPE "reginfo" 47 48 #define GET_REGINFO_TARGET_DESC 49 #include "PPCGenRegisterInfo.inc" 50 51 STATISTIC(InflateGPRC, "Number of gprc inputs for getLargestLegalClass"); 52 STATISTIC(InflateGP8RC, "Number of g8rc inputs for getLargestLegalClass"); 53 54 static cl::opt<bool> 55 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), 56 cl::desc("Enable use of a base pointer for complex stack frames")); 57 58 static cl::opt<bool> 59 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), 60 cl::desc("Force the use of a base pointer in every function")); 61 62 static cl::opt<bool> 63 EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false), 64 cl::desc("Enable spills from gpr to vsr rather than stack")); 65 66 static cl::opt<bool> 67 StackPtrConst("ppc-stack-ptr-caller-preserved", 68 cl::desc("Consider R1 caller preserved so stack saves of " 69 "caller preserved registers can be LICM candidates"), 70 cl::init(true), cl::Hidden); 71 72 static cl::opt<unsigned> 73 MaxCRBitSpillDist("ppc-max-crbit-spill-dist", 74 cl::desc("Maximum search distance for definition of CR bit " 75 "spill on ppc"), 76 cl::Hidden, cl::init(100)); 77 78 // Copies/moves of physical accumulators are expensive operations 79 // that should be avoided whenever possible. MMA instructions are 80 // meant to be used in performance-sensitive computational kernels. 81 // This option is provided, at least for the time being, to give the 82 // user a tool to detect this expensive operation and either rework 83 // their code or report a compiler bug if that turns out to be the 84 // cause. 85 #ifndef NDEBUG 86 static cl::opt<bool> 87 ReportAccMoves("ppc-report-acc-moves", 88 cl::desc("Emit information about accumulator register spills " 89 "and copies"), 90 cl::Hidden, cl::init(false)); 91 #endif 92 93 static unsigned offsetMinAlignForOpcode(unsigned OpC); 94 95 PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM) 96 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR, 97 TM.isPPC64() ? 0 : 1, 98 TM.isPPC64() ? 0 : 1), 99 TM(TM) { 100 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 101 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 102 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 103 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 104 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 105 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 106 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 107 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 108 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; 109 110 // 64-bit 111 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 112 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 113 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 114 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 115 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 116 117 // VSX 118 ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX; 119 ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX; 120 ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX; 121 ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX; 122 ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX; 123 ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX; 124 ImmToIdxMap[PPC::LXV] = PPC::LXVX; 125 ImmToIdxMap[PPC::LXSD] = PPC::LXSDX; 126 ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX; 127 ImmToIdxMap[PPC::STXV] = PPC::STXVX; 128 ImmToIdxMap[PPC::STXSD] = PPC::STXSDX; 129 ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX; 130 131 // SPE 132 ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX; 133 ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX; 134 ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX; 135 ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX; 136 137 // Power10 138 ImmToIdxMap[PPC::PLBZ] = PPC::LBZX; ImmToIdxMap[PPC::PLBZ8] = PPC::LBZX8; 139 ImmToIdxMap[PPC::PLHZ] = PPC::LHZX; ImmToIdxMap[PPC::PLHZ8] = PPC::LHZX8; 140 ImmToIdxMap[PPC::PLHA] = PPC::LHAX; ImmToIdxMap[PPC::PLHA8] = PPC::LHAX8; 141 ImmToIdxMap[PPC::PLWZ] = PPC::LWZX; ImmToIdxMap[PPC::PLWZ8] = PPC::LWZX8; 142 ImmToIdxMap[PPC::PLWA] = PPC::LWAX; ImmToIdxMap[PPC::PLWA8] = PPC::LWAX; 143 ImmToIdxMap[PPC::PLD] = PPC::LDX; ImmToIdxMap[PPC::PSTD] = PPC::STDX; 144 145 ImmToIdxMap[PPC::PSTB] = PPC::STBX; ImmToIdxMap[PPC::PSTB8] = PPC::STBX8; 146 ImmToIdxMap[PPC::PSTH] = PPC::STHX; ImmToIdxMap[PPC::PSTH8] = PPC::STHX8; 147 ImmToIdxMap[PPC::PSTW] = PPC::STWX; ImmToIdxMap[PPC::PSTW8] = PPC::STWX8; 148 149 ImmToIdxMap[PPC::PLFS] = PPC::LFSX; ImmToIdxMap[PPC::PSTFS] = PPC::STFSX; 150 ImmToIdxMap[PPC::PLFD] = PPC::LFDX; ImmToIdxMap[PPC::PSTFD] = PPC::STFDX; 151 ImmToIdxMap[PPC::PLXSSP] = PPC::LXSSPX; ImmToIdxMap[PPC::PSTXSSP] = PPC::STXSSPX; 152 ImmToIdxMap[PPC::PLXSD] = PPC::LXSDX; ImmToIdxMap[PPC::PSTXSD] = PPC::STXSDX; 153 ImmToIdxMap[PPC::PLXV] = PPC::LXVX; ImmToIdxMap[PPC::PSTXV] = PPC::STXVX; 154 155 ImmToIdxMap[PPC::LXVP] = PPC::LXVPX; 156 ImmToIdxMap[PPC::STXVP] = PPC::STXVPX; 157 ImmToIdxMap[PPC::PLXVP] = PPC::LXVPX; 158 ImmToIdxMap[PPC::PSTXVP] = PPC::STXVPX; 159 } 160 161 /// getPointerRegClass - Return the register class to use to hold pointers. 162 /// This is used for addressing modes. 163 const TargetRegisterClass * 164 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 165 const { 166 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value 167 // when it checks for ZERO folding. 168 if (Kind == 1) { 169 if (TM.isPPC64()) 170 return &PPC::G8RC_NOX0RegClass; 171 return &PPC::GPRC_NOR0RegClass; 172 } 173 174 if (TM.isPPC64()) 175 return &PPC::G8RCRegClass; 176 return &PPC::GPRCRegClass; 177 } 178 179 const MCPhysReg* 180 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 181 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); 182 if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) { 183 if (!TM.isPPC64() && Subtarget.isAIXABI()) 184 report_fatal_error("AnyReg unimplemented on 32-bit AIX."); 185 if (Subtarget.hasVSX()) { 186 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) 187 return CSR_64_AllRegs_AIX_Dflt_VSX_SaveList; 188 return CSR_64_AllRegs_VSX_SaveList; 189 } 190 if (Subtarget.hasAltivec()) { 191 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) 192 return CSR_64_AllRegs_AIX_Dflt_Altivec_SaveList; 193 return CSR_64_AllRegs_Altivec_SaveList; 194 } 195 return CSR_64_AllRegs_SaveList; 196 } 197 198 // On PPC64, we might need to save r2 (but only if it is not reserved). 199 // We do not need to treat R2 as callee-saved when using PC-Relative calls 200 // because any direct uses of R2 will cause it to be reserved. If the function 201 // is a leaf or the only uses of R2 are implicit uses for calls, the calls 202 // will use the @notoc relocation which will cause this function to set the 203 // st_other bit to 1, thereby communicating to its caller that it arbitrarily 204 // clobbers the TOC. 205 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2) && 206 !Subtarget.isUsingPCRelativeCalls(); 207 208 // Cold calling convention CSRs. 209 if (MF->getFunction().getCallingConv() == CallingConv::Cold) { 210 if (Subtarget.isAIXABI()) 211 report_fatal_error("Cold calling unimplemented on AIX."); 212 if (TM.isPPC64()) { 213 if (Subtarget.hasAltivec()) 214 return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList 215 : CSR_SVR64_ColdCC_Altivec_SaveList; 216 return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList 217 : CSR_SVR64_ColdCC_SaveList; 218 } 219 // 32-bit targets. 220 if (Subtarget.hasAltivec()) 221 return CSR_SVR32_ColdCC_Altivec_SaveList; 222 else if (Subtarget.hasSPE()) 223 return CSR_SVR32_ColdCC_SPE_SaveList; 224 return CSR_SVR32_ColdCC_SaveList; 225 } 226 // Standard calling convention CSRs. 227 if (TM.isPPC64()) { 228 if (Subtarget.hasAltivec() && 229 (!Subtarget.isAIXABI() || TM.getAIXExtendedAltivecABI())) { 230 return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList 231 : CSR_PPC64_Altivec_SaveList; 232 } 233 return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList; 234 } 235 // 32-bit targets. 236 if (Subtarget.isAIXABI()) { 237 if (Subtarget.hasAltivec()) 238 return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_Altivec_SaveList 239 : CSR_AIX32_SaveList; 240 return CSR_AIX32_SaveList; 241 } 242 if (Subtarget.hasAltivec()) 243 return CSR_SVR432_Altivec_SaveList; 244 else if (Subtarget.hasSPE()) 245 return CSR_SVR432_SPE_SaveList; 246 return CSR_SVR432_SaveList; 247 } 248 249 const uint32_t * 250 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, 251 CallingConv::ID CC) const { 252 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 253 if (CC == CallingConv::AnyReg) { 254 if (Subtarget.hasVSX()) { 255 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) 256 return CSR_64_AllRegs_AIX_Dflt_VSX_RegMask; 257 return CSR_64_AllRegs_VSX_RegMask; 258 } 259 if (Subtarget.hasAltivec()) { 260 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) 261 return CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask; 262 return CSR_64_AllRegs_Altivec_RegMask; 263 } 264 return CSR_64_AllRegs_RegMask; 265 } 266 267 if (Subtarget.isAIXABI()) { 268 return TM.isPPC64() 269 ? ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI()) 270 ? CSR_PPC64_Altivec_RegMask 271 : CSR_PPC64_RegMask) 272 : ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI()) 273 ? CSR_AIX32_Altivec_RegMask 274 : CSR_AIX32_RegMask); 275 } 276 277 if (CC == CallingConv::Cold) { 278 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask 279 : CSR_SVR64_ColdCC_RegMask) 280 : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask 281 : (Subtarget.hasSPE() 282 ? CSR_SVR32_ColdCC_SPE_RegMask 283 : CSR_SVR32_ColdCC_RegMask)); 284 } 285 286 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_PPC64_Altivec_RegMask 287 : CSR_PPC64_RegMask) 288 : (Subtarget.hasAltivec() 289 ? CSR_SVR432_Altivec_RegMask 290 : (Subtarget.hasSPE() ? CSR_SVR432_SPE_RegMask 291 : CSR_SVR432_RegMask)); 292 } 293 294 const uint32_t* 295 PPCRegisterInfo::getNoPreservedMask() const { 296 return CSR_NoRegs_RegMask; 297 } 298 299 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const { 300 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM}) 301 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32)); 302 } 303 304 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 305 BitVector Reserved(getNumRegs()); 306 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 307 const PPCFrameLowering *TFI = getFrameLowering(MF); 308 309 // The ZERO register is not really a register, but the representation of r0 310 // when used in instructions that treat r0 as the constant 0. 311 markSuperRegs(Reserved, PPC::ZERO); 312 313 // The FP register is also not really a register, but is the representation 314 // of the frame pointer register used by ISD::FRAMEADDR. 315 markSuperRegs(Reserved, PPC::FP); 316 317 // The BP register is also not really a register, but is the representation 318 // of the base pointer register used by setjmp. 319 markSuperRegs(Reserved, PPC::BP); 320 321 // The counter registers must be reserved so that counter-based loops can 322 // be correctly formed (and the mtctr instructions are not DCE'd). 323 markSuperRegs(Reserved, PPC::CTR); 324 markSuperRegs(Reserved, PPC::CTR8); 325 326 markSuperRegs(Reserved, PPC::R1); 327 markSuperRegs(Reserved, PPC::LR); 328 markSuperRegs(Reserved, PPC::LR8); 329 markSuperRegs(Reserved, PPC::RM); 330 331 markSuperRegs(Reserved, PPC::VRSAVE); 332 333 // The SVR4 ABI reserves r2 and r13 334 if (Subtarget.isSVR4ABI()) { 335 // We only reserve r2 if we need to use the TOC pointer. If we have no 336 // explicit uses of the TOC pointer (meaning we're a leaf function with 337 // no constant-pool loads, etc.) and we have no potential uses inside an 338 // inline asm block, then we can treat r2 has an ordinary callee-saved 339 // register. 340 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 341 if (!TM.isPPC64() || FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm()) 342 markSuperRegs(Reserved, PPC::R2); // System-reserved register 343 markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register 344 } 345 346 // Always reserve r2 on AIX for now. 347 // TODO: Make r2 allocatable on AIX/XCOFF for some leaf functions. 348 if (Subtarget.isAIXABI()) 349 markSuperRegs(Reserved, PPC::R2); // System-reserved register 350 351 // On PPC64, r13 is the thread pointer. Never allocate this register. 352 if (TM.isPPC64()) 353 markSuperRegs(Reserved, PPC::R13); 354 355 if (TFI->needsFP(MF)) 356 markSuperRegs(Reserved, PPC::R31); 357 358 bool IsPositionIndependent = TM.isPositionIndependent(); 359 if (hasBasePointer(MF)) { 360 if (Subtarget.is32BitELFABI() && IsPositionIndependent) 361 markSuperRegs(Reserved, PPC::R29); 362 else 363 markSuperRegs(Reserved, PPC::R30); 364 } 365 366 if (Subtarget.is32BitELFABI() && IsPositionIndependent) 367 markSuperRegs(Reserved, PPC::R30); 368 369 // Reserve Altivec registers when Altivec is unavailable. 370 if (!Subtarget.hasAltivec()) 371 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(), 372 IE = PPC::VRRCRegClass.end(); I != IE; ++I) 373 markSuperRegs(Reserved, *I); 374 375 if (Subtarget.isAIXABI() && Subtarget.hasAltivec() && 376 !TM.getAIXExtendedAltivecABI()) { 377 // In the AIX default Altivec ABI, vector registers VR20-VR31 are reserved 378 // and cannot be used. 379 for (auto Reg : CSR_Altivec_SaveList) { 380 if (Reg == 0) 381 break; 382 markSuperRegs(Reserved, Reg); 383 for (MCRegAliasIterator AS(Reg, this, true); AS.isValid(); ++AS) { 384 Reserved.set(*AS); 385 } 386 } 387 } 388 389 assert(checkAllSuperRegsMarked(Reserved)); 390 return Reserved; 391 } 392 393 bool PPCRegisterInfo::isAsmClobberable(const MachineFunction &MF, 394 MCRegister PhysReg) const { 395 // We cannot use getReservedRegs() to find the registers that are not asm 396 // clobberable because there are some reserved registers which can be 397 // clobbered by inline asm. For example, when LR is clobbered, the register is 398 // saved and restored. We will hardcode the registers that are not asm 399 // cloberable in this function. 400 401 // The stack pointer (R1/X1) is not clobberable by inline asm 402 return PhysReg != PPC::R1 && PhysReg != PPC::X1; 403 } 404 405 bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const { 406 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 407 const PPCInstrInfo *InstrInfo = Subtarget.getInstrInfo(); 408 const MachineFrameInfo &MFI = MF.getFrameInfo(); 409 const std::vector<CalleeSavedInfo> &Info = MFI.getCalleeSavedInfo(); 410 411 LLVM_DEBUG(dbgs() << "requiresFrameIndexScavenging for " << MF.getName() 412 << ".\n"); 413 // If the callee saved info is invalid we have to default to true for safety. 414 if (!MFI.isCalleeSavedInfoValid()) { 415 LLVM_DEBUG(dbgs() << "TRUE - Invalid callee saved info.\n"); 416 return true; 417 } 418 419 // We will require the use of X-Forms because the frame is larger than what 420 // can be represented in signed 16 bits that fit in the immediate of a D-Form. 421 // If we need an X-Form then we need a register to store the address offset. 422 unsigned FrameSize = MFI.getStackSize(); 423 // Signed 16 bits means that the FrameSize cannot be more than 15 bits. 424 if (FrameSize & ~0x7FFF) { 425 LLVM_DEBUG(dbgs() << "TRUE - Frame size is too large for D-Form.\n"); 426 return true; 427 } 428 429 // The callee saved info is valid so it can be traversed. 430 // Checking for registers that need saving that do not have load or store 431 // forms where the address offset is an immediate. 432 for (unsigned i = 0; i < Info.size(); i++) { 433 // If the spill is to a register no scavenging is required. 434 if (Info[i].isSpilledToReg()) 435 continue; 436 437 int FrIdx = Info[i].getFrameIdx(); 438 Register Reg = Info[i].getReg(); 439 440 const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg); 441 unsigned Opcode = InstrInfo->getStoreOpcodeForSpill(RC); 442 if (!MFI.isFixedObjectIndex(FrIdx)) { 443 // This is not a fixed object. If it requires alignment then we may still 444 // need to use the XForm. 445 if (offsetMinAlignForOpcode(Opcode) > 1) { 446 LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode) 447 << " for register " << printReg(Reg, this) << ".\n"); 448 LLVM_DEBUG(dbgs() << "TRUE - Not fixed frame object that requires " 449 << "alignment.\n"); 450 return true; 451 } 452 } 453 454 // This is eiher: 455 // 1) A fixed frame index object which we know are aligned so 456 // as long as we have a valid DForm/DSForm/DQForm (non XForm) we don't 457 // need to consider the alignment here. 458 // 2) A not fixed object but in that case we now know that the min required 459 // alignment is no more than 1 based on the previous check. 460 if (InstrInfo->isXFormMemOp(Opcode)) { 461 LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode) 462 << " for register " << printReg(Reg, this) << ".\n"); 463 LLVM_DEBUG(dbgs() << "TRUE - Memory operand is X-Form.\n"); 464 return true; 465 } 466 } 467 LLVM_DEBUG(dbgs() << "FALSE - Scavenging is not required.\n"); 468 return false; 469 } 470 471 bool PPCRegisterInfo::requiresVirtualBaseRegisters( 472 const MachineFunction &MF) const { 473 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 474 // Do not use virtual base registers when ROP protection is turned on. 475 // Virtual base registers break the layout of the local variable space and may 476 // push the ROP Hash location past the 512 byte range of the ROP store 477 // instruction. 478 return !Subtarget.hasROPProtect(); 479 } 480 481 bool PPCRegisterInfo::isCallerPreservedPhysReg(MCRegister PhysReg, 482 const MachineFunction &MF) const { 483 assert(Register::isPhysicalRegister(PhysReg)); 484 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 485 const MachineFrameInfo &MFI = MF.getFrameInfo(); 486 487 if (!Subtarget.is64BitELFABI() && !Subtarget.isAIXABI()) 488 return false; 489 if (PhysReg == Subtarget.getTOCPointerRegister()) 490 // X2/R2 is guaranteed to be preserved within a function if it is reserved. 491 // The reason it's reserved is that it's the TOC pointer (and the function 492 // uses the TOC). In functions where it isn't reserved (i.e. leaf functions 493 // with no TOC access), we can't claim that it is preserved. 494 return (getReservedRegs(MF).test(PhysReg)); 495 if (StackPtrConst && PhysReg == Subtarget.getStackPointerRegister() && 496 !MFI.hasVarSizedObjects() && !MFI.hasOpaqueSPAdjustment()) 497 // The value of the stack pointer does not change within a function after 498 // the prologue and before the epilogue if there are no dynamic allocations 499 // and no inline asm which clobbers X1/R1. 500 return true; 501 return false; 502 } 503 504 bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg, 505 ArrayRef<MCPhysReg> Order, 506 SmallVectorImpl<MCPhysReg> &Hints, 507 const MachineFunction &MF, 508 const VirtRegMap *VRM, 509 const LiveRegMatrix *Matrix) const { 510 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 511 512 // Call the base implementation first to set any hints based on the usual 513 // heuristics and decide what the return value should be. We want to return 514 // the same value returned by the base implementation. If the base 515 // implementation decides to return true and force the allocation then we 516 // will leave it as such. On the other hand if the base implementation 517 // decides to return false the following code will not force the allocation 518 // as we are just looking to provide a hint. 519 bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints( 520 VirtReg, Order, Hints, MF, VRM, Matrix); 521 // We are interested in instructions that copy values to ACC/UACC. 522 // The copy into UACC will be simply a COPY to a subreg so we 523 // want to allocate the corresponding physical subreg for the source. 524 // The copy into ACC will be a BUILD_UACC so we want to allocate 525 // the same number UACC for the source. 526 for (MachineInstr &Use : MRI->reg_nodbg_instructions(VirtReg)) { 527 const MachineOperand *ResultOp = nullptr; 528 Register ResultReg; 529 switch (Use.getOpcode()) { 530 case TargetOpcode::COPY: { 531 ResultOp = &Use.getOperand(0); 532 ResultReg = ResultOp->getReg(); 533 if (Register::isVirtualRegister(ResultReg) && 534 MRI->getRegClass(ResultReg)->contains(PPC::UACC0) && 535 VRM->hasPhys(ResultReg)) { 536 Register UACCPhys = VRM->getPhys(ResultReg); 537 Register HintReg = getSubReg(UACCPhys, ResultOp->getSubReg()); 538 // Ensure that the hint is a VSRp register. 539 if (HintReg >= PPC::VSRp0 && HintReg <= PPC::VSRp31) 540 Hints.push_back(HintReg); 541 } 542 break; 543 } 544 case PPC::BUILD_UACC: { 545 ResultOp = &Use.getOperand(0); 546 ResultReg = ResultOp->getReg(); 547 if (MRI->getRegClass(ResultReg)->contains(PPC::ACC0) && 548 VRM->hasPhys(ResultReg)) { 549 Register ACCPhys = VRM->getPhys(ResultReg); 550 assert((ACCPhys >= PPC::ACC0 && ACCPhys <= PPC::ACC7) && 551 "Expecting an ACC register for BUILD_UACC."); 552 Register HintReg = PPC::UACC0 + (ACCPhys - PPC::ACC0); 553 Hints.push_back(HintReg); 554 } 555 break; 556 } 557 } 558 } 559 return BaseImplRetVal; 560 } 561 562 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 563 MachineFunction &MF) const { 564 const PPCFrameLowering *TFI = getFrameLowering(MF); 565 const unsigned DefaultSafety = 1; 566 567 switch (RC->getID()) { 568 default: 569 return 0; 570 case PPC::G8RC_NOX0RegClassID: 571 case PPC::GPRC_NOR0RegClassID: 572 case PPC::SPERCRegClassID: 573 case PPC::G8RCRegClassID: 574 case PPC::GPRCRegClassID: { 575 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 576 return 32 - FP - DefaultSafety; 577 } 578 case PPC::F4RCRegClassID: 579 case PPC::F8RCRegClassID: 580 case PPC::VSLRCRegClassID: 581 return 32 - DefaultSafety; 582 case PPC::VFRCRegClassID: 583 case PPC::VRRCRegClassID: { 584 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 585 // Vector registers VR20-VR31 are reserved and cannot be used in the default 586 // Altivec ABI on AIX. 587 if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI()) 588 return 20 - DefaultSafety; 589 } 590 return 32 - DefaultSafety; 591 case PPC::VSFRCRegClassID: 592 case PPC::VSSRCRegClassID: 593 case PPC::VSRCRegClassID: { 594 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 595 if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI()) 596 // Vector registers VR20-VR31 are reserved and cannot be used in the 597 // default Altivec ABI on AIX. 598 return 52 - DefaultSafety; 599 } 600 return 64 - DefaultSafety; 601 case PPC::CRRCRegClassID: 602 return 8 - DefaultSafety; 603 } 604 } 605 606 const TargetRegisterClass * 607 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, 608 const MachineFunction &MF) const { 609 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 610 const auto *DefaultSuperclass = 611 TargetRegisterInfo::getLargestLegalSuperClass(RC, MF); 612 if (Subtarget.hasVSX()) { 613 // With VSX, we can inflate various sub-register classes to the full VSX 614 // register set. 615 616 // For Power9 we allow the user to enable GPR to vector spills. 617 // FIXME: Currently limited to spilling GP8RC. A follow on patch will add 618 // support to spill GPRC. 619 if (TM.isELFv2ABI() || Subtarget.isAIXABI()) { 620 if (Subtarget.hasP9Vector() && EnableGPRToVecSpills && 621 RC == &PPC::G8RCRegClass) { 622 InflateGP8RC++; 623 return &PPC::SPILLTOVSRRCRegClass; 624 } 625 if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills) 626 InflateGPRC++; 627 } 628 629 for (const auto *I = RC->getSuperClasses(); *I; ++I) { 630 if (getRegSizeInBits(**I) != getRegSizeInBits(*RC)) 631 continue; 632 633 switch ((*I)->getID()) { 634 case PPC::VSSRCRegClassID: 635 return Subtarget.hasP8Vector() ? *I : DefaultSuperclass; 636 case PPC::VSFRCRegClassID: 637 case PPC::VSRCRegClassID: 638 return *I; 639 case PPC::VSRpRCRegClassID: 640 return Subtarget.pairedVectorMemops() ? *I : DefaultSuperclass; 641 case PPC::ACCRCRegClassID: 642 case PPC::UACCRCRegClassID: 643 return Subtarget.hasMMA() ? *I : DefaultSuperclass; 644 } 645 } 646 } 647 648 return DefaultSuperclass; 649 } 650 651 //===----------------------------------------------------------------------===// 652 // Stack Frame Processing methods 653 //===----------------------------------------------------------------------===// 654 655 /// lowerDynamicAlloc - Generate the code for allocating an object in the 656 /// current frame. The sequence of code will be in the general form 657 /// 658 /// addi R0, SP, \#frameSize ; get the address of the previous frame 659 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 660 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 661 /// 662 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 663 // Get the instruction. 664 MachineInstr &MI = *II; 665 // Get the instruction's basic block. 666 MachineBasicBlock &MBB = *MI.getParent(); 667 // Get the basic block's function. 668 MachineFunction &MF = *MBB.getParent(); 669 // Get the frame info. 670 MachineFrameInfo &MFI = MF.getFrameInfo(); 671 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 672 // Get the instruction info. 673 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 674 // Determine whether 64-bit pointers are used. 675 bool LP64 = TM.isPPC64(); 676 DebugLoc dl = MI.getDebugLoc(); 677 678 // Get the maximum call stack size. 679 unsigned maxCallFrameSize = MFI.getMaxCallFrameSize(); 680 Align MaxAlign = MFI.getMaxAlign(); 681 assert(isAligned(MaxAlign, maxCallFrameSize) && 682 "Maximum call-frame size not sufficiently aligned"); 683 (void)MaxAlign; 684 685 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 686 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 687 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 688 bool KillNegSizeReg = MI.getOperand(1).isKill(); 689 Register NegSizeReg = MI.getOperand(1).getReg(); 690 691 prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, Reg); 692 // Grow the stack and update the stack pointer link, then determine the 693 // address of new allocated space. 694 if (LP64) { 695 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 696 .addReg(Reg, RegState::Kill) 697 .addReg(PPC::X1) 698 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 699 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 700 .addReg(PPC::X1) 701 .addImm(maxCallFrameSize); 702 } else { 703 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 704 .addReg(Reg, RegState::Kill) 705 .addReg(PPC::R1) 706 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 707 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 708 .addReg(PPC::R1) 709 .addImm(maxCallFrameSize); 710 } 711 712 // Discard the DYNALLOC instruction. 713 MBB.erase(II); 714 } 715 716 /// To accomplish dynamic stack allocation, we have to calculate exact size 717 /// subtracted from the stack pointer according alignment information and get 718 /// previous frame pointer. 719 void PPCRegisterInfo::prepareDynamicAlloca(MachineBasicBlock::iterator II, 720 Register &NegSizeReg, 721 bool &KillNegSizeReg, 722 Register &FramePointer) const { 723 // Get the instruction. 724 MachineInstr &MI = *II; 725 // Get the instruction's basic block. 726 MachineBasicBlock &MBB = *MI.getParent(); 727 // Get the basic block's function. 728 MachineFunction &MF = *MBB.getParent(); 729 // Get the frame info. 730 MachineFrameInfo &MFI = MF.getFrameInfo(); 731 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 732 // Get the instruction info. 733 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 734 // Determine whether 64-bit pointers are used. 735 bool LP64 = TM.isPPC64(); 736 DebugLoc dl = MI.getDebugLoc(); 737 // Get the total frame size. 738 unsigned FrameSize = MFI.getStackSize(); 739 740 // Get stack alignments. 741 const PPCFrameLowering *TFI = getFrameLowering(MF); 742 Align TargetAlign = TFI->getStackAlign(); 743 Align MaxAlign = MFI.getMaxAlign(); 744 745 // Determine the previous frame's address. If FrameSize can't be 746 // represented as 16 bits or we need special alignment, then we load the 747 // previous frame's address from 0(SP). Why not do an addis of the hi? 748 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 749 // Constructing the constant and adding would take 3 instructions. 750 // Fortunately, a frame greater than 32K is rare. 751 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 752 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 753 754 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 755 if (LP64) 756 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), FramePointer) 757 .addReg(PPC::X31) 758 .addImm(FrameSize); 759 else 760 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), FramePointer) 761 .addReg(PPC::R31) 762 .addImm(FrameSize); 763 } else if (LP64) { 764 BuildMI(MBB, II, dl, TII.get(PPC::LD), FramePointer) 765 .addImm(0) 766 .addReg(PPC::X1); 767 } else { 768 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), FramePointer) 769 .addImm(0) 770 .addReg(PPC::R1); 771 } 772 // Determine the actual NegSizeReg according to alignment info. 773 if (LP64) { 774 if (MaxAlign > TargetAlign) { 775 unsigned UnalNegSizeReg = NegSizeReg; 776 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 777 778 // Unfortunately, there is no andi, only andi., and we can't insert that 779 // here because we might clobber cr0 while it is live. 780 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) 781 .addImm(~(MaxAlign.value() - 1)); 782 783 unsigned NegSizeReg1 = NegSizeReg; 784 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 785 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) 786 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 787 .addReg(NegSizeReg1, RegState::Kill); 788 KillNegSizeReg = true; 789 } 790 } else { 791 if (MaxAlign > TargetAlign) { 792 unsigned UnalNegSizeReg = NegSizeReg; 793 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 794 795 // Unfortunately, there is no andi, only andi., and we can't insert that 796 // here because we might clobber cr0 while it is live. 797 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) 798 .addImm(~(MaxAlign.value() - 1)); 799 800 unsigned NegSizeReg1 = NegSizeReg; 801 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 802 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) 803 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 804 .addReg(NegSizeReg1, RegState::Kill); 805 KillNegSizeReg = true; 806 } 807 } 808 } 809 810 void PPCRegisterInfo::lowerPrepareProbedAlloca( 811 MachineBasicBlock::iterator II) const { 812 MachineInstr &MI = *II; 813 // Get the instruction's basic block. 814 MachineBasicBlock &MBB = *MI.getParent(); 815 // Get the basic block's function. 816 MachineFunction &MF = *MBB.getParent(); 817 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 818 // Get the instruction info. 819 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 820 // Determine whether 64-bit pointers are used. 821 bool LP64 = TM.isPPC64(); 822 DebugLoc dl = MI.getDebugLoc(); 823 Register FramePointer = MI.getOperand(0).getReg(); 824 const Register ActualNegSizeReg = MI.getOperand(1).getReg(); 825 bool KillNegSizeReg = MI.getOperand(2).isKill(); 826 Register NegSizeReg = MI.getOperand(2).getReg(); 827 const MCInstrDesc &CopyInst = TII.get(LP64 ? PPC::OR8 : PPC::OR); 828 // RegAllocator might allocate FramePointer and NegSizeReg in the same phyreg. 829 if (FramePointer == NegSizeReg) { 830 assert(KillNegSizeReg && "FramePointer is a def and NegSizeReg is an use, " 831 "NegSizeReg should be killed"); 832 // FramePointer is clobbered earlier than the use of NegSizeReg in 833 // prepareDynamicAlloca, save NegSizeReg in ActualNegSizeReg to avoid 834 // misuse. 835 BuildMI(MBB, II, dl, CopyInst, ActualNegSizeReg) 836 .addReg(NegSizeReg) 837 .addReg(NegSizeReg); 838 NegSizeReg = ActualNegSizeReg; 839 KillNegSizeReg = false; 840 } 841 prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, FramePointer); 842 // NegSizeReg might be updated in prepareDynamicAlloca if MaxAlign > 843 // TargetAlign. 844 if (NegSizeReg != ActualNegSizeReg) 845 BuildMI(MBB, II, dl, CopyInst, ActualNegSizeReg) 846 .addReg(NegSizeReg) 847 .addReg(NegSizeReg); 848 MBB.erase(II); 849 } 850 851 void PPCRegisterInfo::lowerDynamicAreaOffset( 852 MachineBasicBlock::iterator II) const { 853 // Get the instruction. 854 MachineInstr &MI = *II; 855 // Get the instruction's basic block. 856 MachineBasicBlock &MBB = *MI.getParent(); 857 // Get the basic block's function. 858 MachineFunction &MF = *MBB.getParent(); 859 // Get the frame info. 860 MachineFrameInfo &MFI = MF.getFrameInfo(); 861 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 862 // Get the instruction info. 863 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 864 865 unsigned maxCallFrameSize = MFI.getMaxCallFrameSize(); 866 bool is64Bit = TM.isPPC64(); 867 DebugLoc dl = MI.getDebugLoc(); 868 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), 869 MI.getOperand(0).getReg()) 870 .addImm(maxCallFrameSize); 871 MBB.erase(II); 872 } 873 874 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 875 /// reserving a whole register (R0), we scrounge for one here. This generates 876 /// code like this: 877 /// 878 /// mfcr rA ; Move the conditional register into GPR rA. 879 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 880 /// stw rA, FI ; Store rA to the frame. 881 /// 882 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 883 unsigned FrameIndex) const { 884 // Get the instruction. 885 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 886 // Get the instruction's basic block. 887 MachineBasicBlock &MBB = *MI.getParent(); 888 MachineFunction &MF = *MBB.getParent(); 889 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 890 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 891 DebugLoc dl = MI.getDebugLoc(); 892 893 bool LP64 = TM.isPPC64(); 894 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 895 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 896 897 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 898 Register SrcReg = MI.getOperand(0).getReg(); 899 900 // We need to store the CR in the low 4-bits of the saved value. First, issue 901 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg. 902 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 903 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 904 905 // If the saved register wasn't CR0, shift the bits left so that they are in 906 // CR0's slot. 907 if (SrcReg != PPC::CR0) { 908 Register Reg1 = Reg; 909 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 910 911 // rlwinm rA, rA, ShiftBits, 0, 31. 912 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 913 .addReg(Reg1, RegState::Kill) 914 .addImm(getEncodingValue(SrcReg) * 4) 915 .addImm(0) 916 .addImm(31); 917 } 918 919 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 920 .addReg(Reg, RegState::Kill), 921 FrameIndex); 922 923 // Discard the pseudo instruction. 924 MBB.erase(II); 925 } 926 927 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 928 unsigned FrameIndex) const { 929 // Get the instruction. 930 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 931 // Get the instruction's basic block. 932 MachineBasicBlock &MBB = *MI.getParent(); 933 MachineFunction &MF = *MBB.getParent(); 934 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 935 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 936 DebugLoc dl = MI.getDebugLoc(); 937 938 bool LP64 = TM.isPPC64(); 939 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 940 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 941 942 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 943 Register DestReg = MI.getOperand(0).getReg(); 944 assert(MI.definesRegister(DestReg) && 945 "RESTORE_CR does not define its destination"); 946 947 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 948 Reg), FrameIndex); 949 950 // If the reloaded register isn't CR0, shift the bits right so that they are 951 // in the right CR's slot. 952 if (DestReg != PPC::CR0) { 953 Register Reg1 = Reg; 954 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 955 956 unsigned ShiftBits = getEncodingValue(DestReg)*4; 957 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 958 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 959 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 960 .addImm(31); 961 } 962 963 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) 964 .addReg(Reg, RegState::Kill); 965 966 // Discard the pseudo instruction. 967 MBB.erase(II); 968 } 969 970 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II, 971 unsigned FrameIndex) const { 972 // Get the instruction. 973 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset> 974 // Get the instruction's basic block. 975 MachineBasicBlock &MBB = *MI.getParent(); 976 MachineFunction &MF = *MBB.getParent(); 977 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 978 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 979 const TargetRegisterInfo* TRI = Subtarget.getRegisterInfo(); 980 DebugLoc dl = MI.getDebugLoc(); 981 982 bool LP64 = TM.isPPC64(); 983 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 984 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 985 986 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 987 Register SrcReg = MI.getOperand(0).getReg(); 988 989 // Search up the BB to find the definition of the CR bit. 990 MachineBasicBlock::reverse_iterator Ins = MI; 991 MachineBasicBlock::reverse_iterator Rend = MBB.rend(); 992 ++Ins; 993 unsigned CRBitSpillDistance = 0; 994 bool SeenUse = false; 995 for (; Ins != Rend; ++Ins) { 996 // Definition found. 997 if (Ins->modifiesRegister(SrcReg, TRI)) 998 break; 999 // Use found. 1000 if (Ins->readsRegister(SrcReg, TRI)) 1001 SeenUse = true; 1002 // Unable to find CR bit definition within maximum search distance. 1003 if (CRBitSpillDistance == MaxCRBitSpillDist) { 1004 Ins = MI; 1005 break; 1006 } 1007 // Skip debug instructions when counting CR bit spill distance. 1008 if (!Ins->isDebugInstr()) 1009 CRBitSpillDistance++; 1010 } 1011 1012 // Unable to find the definition of the CR bit in the MBB. 1013 if (Ins == MBB.rend()) 1014 Ins = MI; 1015 1016 bool SpillsKnownBit = false; 1017 // There is no need to extract the CR bit if its value is already known. 1018 switch (Ins->getOpcode()) { 1019 case PPC::CRUNSET: 1020 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LI8 : PPC::LI), Reg) 1021 .addImm(0); 1022 SpillsKnownBit = true; 1023 break; 1024 case PPC::CRSET: 1025 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LIS8 : PPC::LIS), Reg) 1026 .addImm(-32768); 1027 SpillsKnownBit = true; 1028 break; 1029 default: 1030 // On Power10, we can use SETNBC to spill all CR bits. SETNBC will set all 1031 // bits (specifically, it produces a -1 if the CR bit is set). Ultimately, 1032 // the bit that is of importance to us is bit 32 (bit 0 of a 32-bit 1033 // register), and SETNBC will set this. 1034 if (Subtarget.isISA3_1()) { 1035 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETNBC8 : PPC::SETNBC), Reg) 1036 .addReg(SrcReg, RegState::Undef); 1037 break; 1038 } 1039 1040 // On Power9, we can use SETB to extract the LT bit. This only works for 1041 // the LT bit since SETB produces -1/1/0 for LT/GT/<neither>. So the value 1042 // of the bit we care about (32-bit sign bit) will be set to the value of 1043 // the LT bit (regardless of the other bits in the CR field). 1044 if (Subtarget.isISA3_0()) { 1045 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR1LT || 1046 SrcReg == PPC::CR2LT || SrcReg == PPC::CR3LT || 1047 SrcReg == PPC::CR4LT || SrcReg == PPC::CR5LT || 1048 SrcReg == PPC::CR6LT || SrcReg == PPC::CR7LT) { 1049 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETB8 : PPC::SETB), Reg) 1050 .addReg(getCRFromCRBit(SrcReg), RegState::Undef); 1051 break; 1052 } 1053 } 1054 1055 // We need to move the CR field that contains the CR bit we are spilling. 1056 // The super register may not be explicitly defined (i.e. it can be defined 1057 // by a CR-logical that only defines the subreg) so we state that the CR 1058 // field is undef. Also, in order to preserve the kill flag on the CR bit, 1059 // we add it as an implicit use. 1060 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 1061 .addReg(getCRFromCRBit(SrcReg), RegState::Undef) 1062 .addReg(SrcReg, 1063 RegState::Implicit | getKillRegState(MI.getOperand(0).isKill())); 1064 1065 // If the saved register wasn't CR0LT, shift the bits left so that the bit 1066 // to store is the first one. Mask all but that bit. 1067 Register Reg1 = Reg; 1068 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 1069 1070 // rlwinm rA, rA, ShiftBits, 0, 0. 1071 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 1072 .addReg(Reg1, RegState::Kill) 1073 .addImm(getEncodingValue(SrcReg)) 1074 .addImm(0).addImm(0); 1075 } 1076 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 1077 .addReg(Reg, RegState::Kill), 1078 FrameIndex); 1079 1080 bool KillsCRBit = MI.killsRegister(SrcReg, TRI); 1081 // Discard the pseudo instruction. 1082 MBB.erase(II); 1083 if (SpillsKnownBit && KillsCRBit && !SeenUse) { 1084 Ins->setDesc(TII.get(PPC::UNENCODED_NOP)); 1085 Ins->RemoveOperand(0); 1086 } 1087 } 1088 1089 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II, 1090 unsigned FrameIndex) const { 1091 // Get the instruction. 1092 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset> 1093 // Get the instruction's basic block. 1094 MachineBasicBlock &MBB = *MI.getParent(); 1095 MachineFunction &MF = *MBB.getParent(); 1096 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 1097 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1098 DebugLoc dl = MI.getDebugLoc(); 1099 1100 bool LP64 = TM.isPPC64(); 1101 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1102 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1103 1104 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 1105 Register DestReg = MI.getOperand(0).getReg(); 1106 assert(MI.definesRegister(DestReg) && 1107 "RESTORE_CRBIT does not define its destination"); 1108 1109 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 1110 Reg), FrameIndex); 1111 1112 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg); 1113 1114 Register RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 1115 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) 1116 .addReg(getCRFromCRBit(DestReg)); 1117 1118 unsigned ShiftBits = getEncodingValue(DestReg); 1119 // rlwimi r11, r10, 32-ShiftBits, ..., ... 1120 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO) 1121 .addReg(RegO, RegState::Kill) 1122 .addReg(Reg, RegState::Kill) 1123 .addImm(ShiftBits ? 32 - ShiftBits : 0) 1124 .addImm(ShiftBits) 1125 .addImm(ShiftBits); 1126 1127 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), 1128 getCRFromCRBit(DestReg)) 1129 .addReg(RegO, RegState::Kill) 1130 // Make sure we have a use dependency all the way through this 1131 // sequence of instructions. We can't have the other bits in the CR 1132 // modified in between the mfocrf and the mtocrf. 1133 .addReg(getCRFromCRBit(DestReg), RegState::Implicit); 1134 1135 // Discard the pseudo instruction. 1136 MBB.erase(II); 1137 } 1138 1139 void PPCRegisterInfo::emitAccCopyInfo(MachineBasicBlock &MBB, 1140 MCRegister DestReg, MCRegister SrcReg) { 1141 #ifdef NDEBUG 1142 return; 1143 #else 1144 if (ReportAccMoves) { 1145 std::string Dest = PPC::ACCRCRegClass.contains(DestReg) ? "acc" : "uacc"; 1146 std::string Src = PPC::ACCRCRegClass.contains(SrcReg) ? "acc" : "uacc"; 1147 dbgs() << "Emitting copy from " << Src << " to " << Dest << ":\n"; 1148 MBB.dump(); 1149 } 1150 #endif 1151 } 1152 1153 static void emitAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsPrimed, 1154 bool IsRestore) { 1155 #ifdef NDEBUG 1156 return; 1157 #else 1158 if (ReportAccMoves) { 1159 dbgs() << "Emitting " << (IsPrimed ? "acc" : "uacc") << " register " 1160 << (IsRestore ? "restore" : "spill") << ":\n"; 1161 MBB.dump(); 1162 } 1163 #endif 1164 } 1165 1166 /// lowerACCSpilling - Generate the code for spilling the accumulator register. 1167 /// Similarly to other spills/reloads that use pseudo-ops, we do not actually 1168 /// eliminate the FrameIndex here nor compute the stack offset. We simply 1169 /// create a real instruction with an FI and rely on eliminateFrameIndex to 1170 /// handle the FI elimination. 1171 void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II, 1172 unsigned FrameIndex) const { 1173 MachineInstr &MI = *II; // SPILL_ACC <SrcReg>, <offset> 1174 MachineBasicBlock &MBB = *MI.getParent(); 1175 MachineFunction &MF = *MBB.getParent(); 1176 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 1177 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1178 DebugLoc DL = MI.getDebugLoc(); 1179 Register SrcReg = MI.getOperand(0).getReg(); 1180 bool IsKilled = MI.getOperand(0).isKill(); 1181 1182 bool IsPrimed = PPC::ACCRCRegClass.contains(SrcReg); 1183 Register Reg = 1184 PPC::VSRp0 + (SrcReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2; 1185 bool IsLittleEndian = Subtarget.isLittleEndian(); 1186 1187 emitAccSpillRestoreInfo(MBB, IsPrimed, false); 1188 1189 // De-prime the register being spilled, create two stores for the pair 1190 // subregisters accounting for endianness and then re-prime the register if 1191 // it isn't killed. This uses the Offset parameter to addFrameReference() to 1192 // adjust the offset of the store that is within the 64-byte stack slot. 1193 if (IsPrimed) 1194 BuildMI(MBB, II, DL, TII.get(PPC::XXMFACC), SrcReg).addReg(SrcReg); 1195 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP)) 1196 .addReg(Reg, getKillRegState(IsKilled)), 1197 FrameIndex, IsLittleEndian ? 32 : 0); 1198 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP)) 1199 .addReg(Reg + 1, getKillRegState(IsKilled)), 1200 FrameIndex, IsLittleEndian ? 0 : 32); 1201 if (IsPrimed && !IsKilled) 1202 BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), SrcReg).addReg(SrcReg); 1203 1204 // Discard the pseudo instruction. 1205 MBB.erase(II); 1206 } 1207 1208 /// lowerACCRestore - Generate the code to restore the accumulator register. 1209 void PPCRegisterInfo::lowerACCRestore(MachineBasicBlock::iterator II, 1210 unsigned FrameIndex) const { 1211 MachineInstr &MI = *II; // <DestReg> = RESTORE_ACC <offset> 1212 MachineBasicBlock &MBB = *MI.getParent(); 1213 MachineFunction &MF = *MBB.getParent(); 1214 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 1215 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1216 DebugLoc DL = MI.getDebugLoc(); 1217 1218 Register DestReg = MI.getOperand(0).getReg(); 1219 assert(MI.definesRegister(DestReg) && 1220 "RESTORE_ACC does not define its destination"); 1221 1222 bool IsPrimed = PPC::ACCRCRegClass.contains(DestReg); 1223 Register Reg = 1224 PPC::VSRp0 + (DestReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2; 1225 bool IsLittleEndian = Subtarget.isLittleEndian(); 1226 1227 emitAccSpillRestoreInfo(MBB, IsPrimed, true); 1228 1229 // Create two loads for the pair subregisters accounting for endianness and 1230 // then prime the accumulator register being restored. 1231 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), Reg), 1232 FrameIndex, IsLittleEndian ? 32 : 0); 1233 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), Reg + 1), 1234 FrameIndex, IsLittleEndian ? 0 : 32); 1235 if (IsPrimed) 1236 BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), DestReg).addReg(DestReg); 1237 1238 // Discard the pseudo instruction. 1239 MBB.erase(II); 1240 } 1241 1242 /// lowerQuadwordSpilling - Generate code to spill paired general register. 1243 void PPCRegisterInfo::lowerQuadwordSpilling(MachineBasicBlock::iterator II, 1244 unsigned FrameIndex) const { 1245 MachineInstr &MI = *II; 1246 MachineBasicBlock &MBB = *MI.getParent(); 1247 MachineFunction &MF = *MBB.getParent(); 1248 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 1249 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1250 DebugLoc DL = MI.getDebugLoc(); 1251 1252 Register SrcReg = MI.getOperand(0).getReg(); 1253 bool IsKilled = MI.getOperand(0).isKill(); 1254 1255 Register Reg = PPC::X0 + (SrcReg - PPC::G8p0) * 2; 1256 bool IsLittleEndian = Subtarget.isLittleEndian(); 1257 1258 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STD)) 1259 .addReg(Reg, getKillRegState(IsKilled)), 1260 FrameIndex, IsLittleEndian ? 8 : 0); 1261 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STD)) 1262 .addReg(Reg + 1, getKillRegState(IsKilled)), 1263 FrameIndex, IsLittleEndian ? 0 : 8); 1264 1265 // Discard the pseudo instruction. 1266 MBB.erase(II); 1267 } 1268 1269 /// lowerQuadwordRestore - Generate code to restore paired general register. 1270 void PPCRegisterInfo::lowerQuadwordRestore(MachineBasicBlock::iterator II, 1271 unsigned FrameIndex) const { 1272 MachineInstr &MI = *II; 1273 MachineBasicBlock &MBB = *MI.getParent(); 1274 MachineFunction &MF = *MBB.getParent(); 1275 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 1276 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1277 DebugLoc DL = MI.getDebugLoc(); 1278 1279 Register DestReg = MI.getOperand(0).getReg(); 1280 assert(MI.definesRegister(DestReg) && 1281 "RESTORE_QUADWORD does not define its destination"); 1282 1283 Register Reg = PPC::X0 + (DestReg - PPC::G8p0) * 2; 1284 bool IsLittleEndian = Subtarget.isLittleEndian(); 1285 1286 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LD), Reg), FrameIndex, 1287 IsLittleEndian ? 8 : 0); 1288 addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LD), Reg + 1), FrameIndex, 1289 IsLittleEndian ? 0 : 8); 1290 1291 // Discard the pseudo instruction. 1292 MBB.erase(II); 1293 } 1294 1295 bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 1296 Register Reg, int &FrameIdx) const { 1297 // For the nonvolatile condition registers (CR2, CR3, CR4) return true to 1298 // prevent allocating an additional frame slot. 1299 // For 64-bit ELF and AIX, the CR save area is in the linkage area at SP+8, 1300 // for 32-bit AIX the CR save area is in the linkage area at SP+4. 1301 // We have created a FrameIndex to that spill slot to keep the CalleSaveInfos 1302 // valid. 1303 // For 32-bit ELF, we have previously created the stack slot if needed, so 1304 // return its FrameIdx. 1305 if (PPC::CR2 <= Reg && Reg <= PPC::CR4) { 1306 FrameIdx = MF.getInfo<PPCFunctionInfo>()->getCRSpillFrameIndex(); 1307 return true; 1308 } 1309 return false; 1310 } 1311 1312 // If the offset must be a multiple of some value, return what that value is. 1313 static unsigned offsetMinAlignForOpcode(unsigned OpC) { 1314 switch (OpC) { 1315 default: 1316 return 1; 1317 case PPC::LWA: 1318 case PPC::LWA_32: 1319 case PPC::LD: 1320 case PPC::LDU: 1321 case PPC::STD: 1322 case PPC::STDU: 1323 case PPC::DFLOADf32: 1324 case PPC::DFLOADf64: 1325 case PPC::DFSTOREf32: 1326 case PPC::DFSTOREf64: 1327 case PPC::LXSD: 1328 case PPC::LXSSP: 1329 case PPC::STXSD: 1330 case PPC::STXSSP: 1331 case PPC::STQ: 1332 return 4; 1333 case PPC::EVLDD: 1334 case PPC::EVSTDD: 1335 return 8; 1336 case PPC::LXV: 1337 case PPC::STXV: 1338 case PPC::LQ: 1339 case PPC::LXVP: 1340 case PPC::STXVP: 1341 return 16; 1342 } 1343 } 1344 1345 // If the offset must be a multiple of some value, return what that value is. 1346 static unsigned offsetMinAlign(const MachineInstr &MI) { 1347 unsigned OpC = MI.getOpcode(); 1348 return offsetMinAlignForOpcode(OpC); 1349 } 1350 1351 // Return the OffsetOperandNo given the FIOperandNum (and the instruction). 1352 static unsigned getOffsetONFromFION(const MachineInstr &MI, 1353 unsigned FIOperandNum) { 1354 // Take into account whether it's an add or mem instruction 1355 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 1356 if (MI.isInlineAsm()) 1357 OffsetOperandNo = FIOperandNum - 1; 1358 else if (MI.getOpcode() == TargetOpcode::STACKMAP || 1359 MI.getOpcode() == TargetOpcode::PATCHPOINT) 1360 OffsetOperandNo = FIOperandNum + 1; 1361 1362 return OffsetOperandNo; 1363 } 1364 1365 void 1366 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 1367 int SPAdj, unsigned FIOperandNum, 1368 RegScavenger *RS) const { 1369 assert(SPAdj == 0 && "Unexpected"); 1370 1371 // Get the instruction. 1372 MachineInstr &MI = *II; 1373 // Get the instruction's basic block. 1374 MachineBasicBlock &MBB = *MI.getParent(); 1375 // Get the basic block's function. 1376 MachineFunction &MF = *MBB.getParent(); 1377 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 1378 // Get the instruction info. 1379 const PPCInstrInfo &TII = *Subtarget.getInstrInfo(); 1380 // Get the frame info. 1381 MachineFrameInfo &MFI = MF.getFrameInfo(); 1382 DebugLoc dl = MI.getDebugLoc(); 1383 1384 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 1385 1386 // Get the frame index. 1387 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 1388 1389 // Get the frame pointer save index. Users of this index are primarily 1390 // DYNALLOC instructions. 1391 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1392 int FPSI = FI->getFramePointerSaveIndex(); 1393 // Get the instruction opcode. 1394 unsigned OpC = MI.getOpcode(); 1395 1396 if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) { 1397 lowerDynamicAreaOffset(II); 1398 return; 1399 } 1400 1401 // Special case for dynamic alloca. 1402 if (FPSI && FrameIndex == FPSI && 1403 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 1404 lowerDynamicAlloc(II); 1405 return; 1406 } 1407 1408 if (FPSI && FrameIndex == FPSI && 1409 (OpC == PPC::PREPARE_PROBED_ALLOCA_64 || 1410 OpC == PPC::PREPARE_PROBED_ALLOCA_32 || 1411 OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 || 1412 OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32)) { 1413 lowerPrepareProbedAlloca(II); 1414 return; 1415 } 1416 1417 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. 1418 if (OpC == PPC::SPILL_CR) { 1419 lowerCRSpilling(II, FrameIndex); 1420 return; 1421 } else if (OpC == PPC::RESTORE_CR) { 1422 lowerCRRestore(II, FrameIndex); 1423 return; 1424 } else if (OpC == PPC::SPILL_CRBIT) { 1425 lowerCRBitSpilling(II, FrameIndex); 1426 return; 1427 } else if (OpC == PPC::RESTORE_CRBIT) { 1428 lowerCRBitRestore(II, FrameIndex); 1429 return; 1430 } else if (OpC == PPC::SPILL_ACC || OpC == PPC::SPILL_UACC) { 1431 lowerACCSpilling(II, FrameIndex); 1432 return; 1433 } else if (OpC == PPC::RESTORE_ACC || OpC == PPC::RESTORE_UACC) { 1434 lowerACCRestore(II, FrameIndex); 1435 return; 1436 } else if (OpC == PPC::SPILL_QUADWORD) { 1437 lowerQuadwordSpilling(II, FrameIndex); 1438 return; 1439 } else if (OpC == PPC::RESTORE_QUADWORD) { 1440 lowerQuadwordRestore(II, FrameIndex); 1441 return; 1442 } 1443 1444 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 1445 MI.getOperand(FIOperandNum).ChangeToRegister( 1446 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false); 1447 1448 // If the instruction is not present in ImmToIdxMap, then it has no immediate 1449 // form (and must be r+r). 1450 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP && 1451 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC); 1452 1453 // Now add the frame object offset to the offset from r1. 1454 int Offset = MFI.getObjectOffset(FrameIndex); 1455 Offset += MI.getOperand(OffsetOperandNo).getImm(); 1456 1457 // If we're not using a Frame Pointer that has been set to the value of the 1458 // SP before having the stack size subtracted from it, then add the stack size 1459 // to Offset to get the correct offset. 1460 // Naked functions have stack size 0, although getStackSize may not reflect 1461 // that because we didn't call all the pieces that compute it for naked 1462 // functions. 1463 if (!MF.getFunction().hasFnAttribute(Attribute::Naked)) { 1464 if (!(hasBasePointer(MF) && FrameIndex < 0)) 1465 Offset += MFI.getStackSize(); 1466 } 1467 1468 // If we encounter an LXVP/STXVP with an offset that doesn't fit, we can 1469 // transform it to the prefixed version so we don't have to use the XForm. 1470 if ((OpC == PPC::LXVP || OpC == PPC::STXVP) && 1471 (!isInt<16>(Offset) || (Offset % offsetMinAlign(MI)) != 0) && 1472 Subtarget.hasPrefixInstrs()) { 1473 unsigned NewOpc = OpC == PPC::LXVP ? PPC::PLXVP : PPC::PSTXVP; 1474 MI.setDesc(TII.get(NewOpc)); 1475 OpC = NewOpc; 1476 } 1477 1478 // If we can, encode the offset directly into the instruction. If this is a 1479 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 1480 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 1481 // clear can be encoded. This is extremely uncommon, because normally you 1482 // only "std" to a stack slot that is at least 4-byte aligned, but it can 1483 // happen in invalid code. 1484 assert(OpC != PPC::DBG_VALUE && 1485 "This should be handled in a target-independent way"); 1486 // FIXME: This should be factored out to a separate function as prefixed 1487 // instructions add a number of opcodes for which we can use 34-bit imm. 1488 bool OffsetFitsMnemonic = (OpC == PPC::EVSTDD || OpC == PPC::EVLDD) ? 1489 isUInt<8>(Offset) : 1490 isInt<16>(Offset); 1491 if (TII.isPrefixed(MI.getOpcode())) 1492 OffsetFitsMnemonic = isInt<34>(Offset); 1493 if (!noImmForm && ((OffsetFitsMnemonic && 1494 ((Offset % offsetMinAlign(MI)) == 0)) || 1495 OpC == TargetOpcode::STACKMAP || 1496 OpC == TargetOpcode::PATCHPOINT)) { 1497 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 1498 return; 1499 } 1500 1501 // The offset doesn't fit into a single register, scavenge one to build the 1502 // offset in. 1503 1504 bool is64Bit = TM.isPPC64(); 1505 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1506 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1507 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; 1508 Register SRegHi = MF.getRegInfo().createVirtualRegister(RC), 1509 SReg = MF.getRegInfo().createVirtualRegister(RC); 1510 1511 // Insert a set of rA with the full offset value before the ld, st, or add 1512 if (isInt<16>(Offset)) 1513 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg) 1514 .addImm(Offset); 1515 else { 1516 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) 1517 .addImm(Offset >> 16); 1518 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 1519 .addReg(SRegHi, RegState::Kill) 1520 .addImm(Offset); 1521 } 1522 1523 // Convert into indexed form of the instruction: 1524 // 1525 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 1526 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 1527 unsigned OperandBase; 1528 1529 if (noImmForm) 1530 OperandBase = 1; 1531 else if (OpC != TargetOpcode::INLINEASM && 1532 OpC != TargetOpcode::INLINEASM_BR) { 1533 assert(ImmToIdxMap.count(OpC) && 1534 "No indexed form of load or store available!"); 1535 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 1536 MI.setDesc(TII.get(NewOpcode)); 1537 OperandBase = 1; 1538 } else { 1539 OperandBase = OffsetOperandNo; 1540 } 1541 1542 Register StackReg = MI.getOperand(FIOperandNum).getReg(); 1543 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 1544 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 1545 } 1546 1547 Register PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 1548 const PPCFrameLowering *TFI = getFrameLowering(MF); 1549 1550 if (!TM.isPPC64()) 1551 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 1552 else 1553 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 1554 } 1555 1556 Register PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const { 1557 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 1558 if (!hasBasePointer(MF)) 1559 return getFrameRegister(MF); 1560 1561 if (TM.isPPC64()) 1562 return PPC::X30; 1563 1564 if (Subtarget.isSVR4ABI() && TM.isPositionIndependent()) 1565 return PPC::R29; 1566 1567 return PPC::R30; 1568 } 1569 1570 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 1571 if (!EnableBasePointer) 1572 return false; 1573 if (AlwaysBasePointer) 1574 return true; 1575 1576 // If we need to realign the stack, then the stack pointer can no longer 1577 // serve as an offset into the caller's stack space. As a result, we need a 1578 // base pointer. 1579 return hasStackRealignment(MF); 1580 } 1581 1582 /// Returns true if the instruction's frame index 1583 /// reference would be better served by a base register other than FP 1584 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 1585 /// references it should create new base registers for. 1586 bool PPCRegisterInfo:: 1587 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 1588 assert(Offset < 0 && "Local offset must be negative"); 1589 1590 // It's the load/store FI references that cause issues, as it can be difficult 1591 // to materialize the offset if it won't fit in the literal field. Estimate 1592 // based on the size of the local frame and some conservative assumptions 1593 // about the rest of the stack frame (note, this is pre-regalloc, so 1594 // we don't know everything for certain yet) whether this offset is likely 1595 // to be out of range of the immediate. Return true if so. 1596 1597 // We only generate virtual base registers for loads and stores that have 1598 // an r+i form. Return false for everything else. 1599 unsigned OpC = MI->getOpcode(); 1600 if (!ImmToIdxMap.count(OpC)) 1601 return false; 1602 1603 // Don't generate a new virtual base register just to add zero to it. 1604 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && 1605 MI->getOperand(2).getImm() == 0) 1606 return false; 1607 1608 MachineBasicBlock &MBB = *MI->getParent(); 1609 MachineFunction &MF = *MBB.getParent(); 1610 const PPCFrameLowering *TFI = getFrameLowering(MF); 1611 unsigned StackEst = TFI->determineFrameLayout(MF, true); 1612 1613 // If we likely don't need a stack frame, then we probably don't need a 1614 // virtual base register either. 1615 if (!StackEst) 1616 return false; 1617 1618 // Estimate an offset from the stack pointer. 1619 // The incoming offset is relating to the SP at the start of the function, 1620 // but when we access the local it'll be relative to the SP after local 1621 // allocation, so adjust our SP-relative offset by that allocation size. 1622 Offset += StackEst; 1623 1624 // The frame pointer will point to the end of the stack, so estimate the 1625 // offset as the difference between the object offset and the FP location. 1626 return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset); 1627 } 1628 1629 /// Insert defining instruction(s) for BaseReg to 1630 /// be a pointer to FrameIdx at the beginning of the basic block. 1631 Register PPCRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, 1632 int FrameIdx, 1633 int64_t Offset) const { 1634 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI; 1635 1636 MachineBasicBlock::iterator Ins = MBB->begin(); 1637 DebugLoc DL; // Defaults to "unknown" 1638 if (Ins != MBB->end()) 1639 DL = Ins->getDebugLoc(); 1640 1641 const MachineFunction &MF = *MBB->getParent(); 1642 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 1643 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1644 const MCInstrDesc &MCID = TII.get(ADDriOpc); 1645 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 1646 const TargetRegisterClass *RC = getPointerRegClass(MF); 1647 Register BaseReg = MRI.createVirtualRegister(RC); 1648 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 1649 1650 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 1651 .addFrameIndex(FrameIdx).addImm(Offset); 1652 1653 return BaseReg; 1654 } 1655 1656 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, 1657 int64_t Offset) const { 1658 unsigned FIOperandNum = 0; 1659 while (!MI.getOperand(FIOperandNum).isFI()) { 1660 ++FIOperandNum; 1661 assert(FIOperandNum < MI.getNumOperands() && 1662 "Instr doesn't have FrameIndex operand!"); 1663 } 1664 1665 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false); 1666 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 1667 Offset += MI.getOperand(OffsetOperandNo).getImm(); 1668 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 1669 1670 MachineBasicBlock &MBB = *MI.getParent(); 1671 MachineFunction &MF = *MBB.getParent(); 1672 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 1673 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1674 const MCInstrDesc &MCID = MI.getDesc(); 1675 MachineRegisterInfo &MRI = MF.getRegInfo(); 1676 MRI.constrainRegClass(BaseReg, 1677 TII.getRegClass(MCID, FIOperandNum, this, MF)); 1678 } 1679 1680 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 1681 Register BaseReg, 1682 int64_t Offset) const { 1683 unsigned FIOperandNum = 0; 1684 while (!MI->getOperand(FIOperandNum).isFI()) { 1685 ++FIOperandNum; 1686 assert(FIOperandNum < MI->getNumOperands() && 1687 "Instr doesn't have FrameIndex operand!"); 1688 } 1689 1690 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum); 1691 Offset += MI->getOperand(OffsetOperandNo).getImm(); 1692 1693 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 1694 MI->getOpcode() == TargetOpcode::STACKMAP || 1695 MI->getOpcode() == TargetOpcode::PATCHPOINT || 1696 (isInt<16>(Offset) && (Offset % offsetMinAlign(*MI)) == 0); 1697 } 1698