1//===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12let Namespace = "PPC" in { 13def sub_lt : SubRegIndex<1>; 14def sub_gt : SubRegIndex<1, 1>; 15def sub_eq : SubRegIndex<1, 2>; 16def sub_un : SubRegIndex<1, 3>; 17def sub_32 : SubRegIndex<32>; 18def sub_64 : SubRegIndex<64>; 19def sub_vsx0 : SubRegIndex<128>; 20def sub_vsx1 : SubRegIndex<128, 128>; 21def sub_gp8_x0 : SubRegIndex<64>; 22def sub_gp8_x1 : SubRegIndex<64, 64>; 23} 24 25 26class PPCReg<string n> : Register<n> { 27 let Namespace = "PPC"; 28} 29 30// We identify all our registers with a 5-bit ID, for consistency's sake. 31 32// GPR - One of the 32 32-bit general-purpose registers 33class GPR<bits<5> num, string n> : PPCReg<n> { 34 let HWEncoding{4-0} = num; 35} 36 37// GP8 - One of the 32 64-bit general-purpose registers 38class GP8<GPR SubReg, string n> : PPCReg<n> { 39 let HWEncoding = SubReg.HWEncoding; 40 let SubRegs = [SubReg]; 41 let SubRegIndices = [sub_32]; 42} 43 44// SPE - One of the 32 64-bit general-purpose registers (SPE) 45class SPE<GPR SubReg, string n> : PPCReg<n> { 46 let HWEncoding = SubReg.HWEncoding; 47 let SubRegs = [SubReg]; 48 let SubRegIndices = [sub_32]; 49} 50 51// SPR - One of the 32-bit special-purpose registers 52class SPR<bits<10> num, string n> : PPCReg<n> { 53 let HWEncoding{9-0} = num; 54} 55 56// FPR - One of the 32 64-bit floating-point registers 57class FPR<bits<5> num, string n> : PPCReg<n> { 58 let HWEncoding{4-0} = num; 59} 60 61// VF - One of the 32 64-bit floating-point subregisters of the vector 62// registers (used by VSX). 63class VF<bits<5> num, string n> : PPCReg<n> { 64 let HWEncoding{4-0} = num; 65 let HWEncoding{5} = 1; 66} 67 68// VR - One of the 32 128-bit vector registers 69class VR<VF SubReg, string n> : PPCReg<n> { 70 let HWEncoding{4-0} = SubReg.HWEncoding{4-0}; 71 let HWEncoding{5} = 0; 72 let SubRegs = [SubReg]; 73 let SubRegIndices = [sub_64]; 74} 75 76// VSRL - One of the 32 128-bit VSX registers that overlap with the scalar 77// floating-point registers. 78class VSRL<FPR SubReg, string n> : PPCReg<n> { 79 let HWEncoding = SubReg.HWEncoding; 80 let SubRegs = [SubReg]; 81 let SubRegIndices = [sub_64]; 82} 83 84// VSXReg - One of the VSX registers in the range vs32-vs63 with numbering 85// and encoding to match. 86class VSXReg<bits<6> num, string n> : PPCReg<n> { 87 let HWEncoding{5-0} = num; 88} 89 90// CR - One of the 8 4-bit condition registers 91class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> { 92 let HWEncoding{2-0} = num; 93 let SubRegs = subregs; 94} 95 96// CRBIT - One of the 32 1-bit condition register fields 97class CRBIT<bits<5> num, string n> : PPCReg<n> { 98 let HWEncoding{4-0} = num; 99} 100 101// VSR Pairs - One of the 32 paired even-odd consecutive VSRs. 102class VSRPair<bits<5> num, string n, list<Register> subregs> : PPCReg<n> { 103 let HWEncoding{4-0} = num; 104 let SubRegs = subregs; 105} 106 107// GP8Pair - Consecutive even-odd paired GP8. 108class GP8Pair<string n, bits<5> EvenIndex> : PPCReg<n> { 109 assert !eq(EvenIndex{0}, 0), "Index should be even."; 110 let HWEncoding{4-0} = EvenIndex; 111 let SubRegs = [!cast<GP8>("X"#EvenIndex), !cast<GP8>("X"#!add(EvenIndex, 1))]; 112 let DwarfNumbers = [-1, -1]; 113 let SubRegIndices = [sub_gp8_x0, sub_gp8_x1]; 114} 115 116// General-purpose registers 117foreach Index = 0-31 in { 118 def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>; 119} 120 121// 64-bit General-purpose registers 122foreach Index = 0-31 in { 123 def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>, 124 DwarfRegNum<[Index, -2]>; 125} 126 127// SPE registers 128foreach Index = 0-31 in { 129 def S#Index : SPE<!cast<GPR>("R"#Index), "r"#Index>, 130 DwarfRegNum<[!add(Index, 1200), !add(Index, 1200)]>; 131} 132 133// Floating-point registers 134foreach Index = 0-31 in { 135 def F#Index : FPR<Index, "f"#Index>, 136 DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>; 137} 138 139// 64-bit Floating-point subregisters of Altivec registers 140// Note: the register names are v0-v31 or vs32-vs63 depending on the use. 141// Custom C++ code is used to produce the correct name and encoding. 142foreach Index = 0-31 in { 143 def VF#Index : VF<Index, "v" #Index>, 144 DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>; 145} 146 147// Vector registers 148foreach Index = 0-31 in { 149 def V#Index : VR<!cast<VF>("VF"#Index), "v"#Index>, 150 DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>; 151} 152 153// VSX registers 154foreach Index = 0-31 in { 155 def VSL#Index : VSRL<!cast<FPR>("F"#Index), "vs"#Index>, 156 DwarfRegAlias<!cast<FPR>("F"#Index)>; 157} 158 159// Dummy VSX registers, this defines string: "vs32"-"vs63", and is only used for 160// asm printing. 161foreach Index = 32-63 in { 162 def VSX#Index : VSXReg<Index, "vs"#Index>; 163} 164 165let SubRegIndices = [sub_vsx0, sub_vsx1] in { 166 // VSR pairs 0 - 15 (corresponding to VSRs 0 - 30 paired with 1 - 31). 167 foreach Index = { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 } in { 168 def VSRp#!srl(Index, 1) : VSRPair<!srl(Index, 1), "vsp"#Index, 169 [!cast<VSRL>("VSL"#Index), !cast<VSRL>("VSL"#!add(Index, 1))]>, 170 DwarfRegNum<[-1, -1]>; 171 } 172 173 // VSR pairs 16 - 31 (corresponding to VSRs 32 - 62 paired with 33 - 63). 174 foreach Index = { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 } in { 175 def VSRp#!add(!srl(Index, 1), 16) : 176 VSRPair<!add(!srl(Index, 1), 16), "vsp"#!add(Index, 32), 177 [!cast<VR>("V"#Index), !cast<VR>("V"#!add(Index, 1))]>, 178 DwarfRegNum<[-1, -1]>; 179 } 180} 181 182// 16 paired even-odd consecutive GP8s. 183foreach Index = { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 } in { 184 def G8p#!srl(Index, 1) : GP8Pair<"r"#Index, Index>; 185} 186 187// The representation of r0 when treated as the constant 0. 188let isConstant = true in { 189def ZERO : GPR<0, "0">, DwarfRegAlias<R0>; 190def ZERO8 : GP8<ZERO, "0">, DwarfRegAlias<X0>; 191} // isConstant = true 192 193// Representations of the frame pointer used by ISD::FRAMEADDR. 194def FP : GPR<0 /* arbitrary */, "**FRAME POINTER**">; 195def FP8 : GP8<FP, "**FRAME POINTER**">; 196 197// Representations of the base pointer used by setjmp. 198def BP : GPR<0 /* arbitrary */, "**BASE POINTER**">; 199def BP8 : GP8<BP, "**BASE POINTER**">; 200 201// Condition register bits 202def CR0LT : CRBIT< 0, "0">; 203def CR0GT : CRBIT< 1, "1">; 204def CR0EQ : CRBIT< 2, "2">; 205def CR0UN : CRBIT< 3, "3">; 206def CR1LT : CRBIT< 4, "4">; 207def CR1GT : CRBIT< 5, "5">; 208def CR1EQ : CRBIT< 6, "6">; 209def CR1UN : CRBIT< 7, "7">; 210def CR2LT : CRBIT< 8, "8">; 211def CR2GT : CRBIT< 9, "9">; 212def CR2EQ : CRBIT<10, "10">; 213def CR2UN : CRBIT<11, "11">; 214def CR3LT : CRBIT<12, "12">; 215def CR3GT : CRBIT<13, "13">; 216def CR3EQ : CRBIT<14, "14">; 217def CR3UN : CRBIT<15, "15">; 218def CR4LT : CRBIT<16, "16">; 219def CR4GT : CRBIT<17, "17">; 220def CR4EQ : CRBIT<18, "18">; 221def CR4UN : CRBIT<19, "19">; 222def CR5LT : CRBIT<20, "20">; 223def CR5GT : CRBIT<21, "21">; 224def CR5EQ : CRBIT<22, "22">; 225def CR5UN : CRBIT<23, "23">; 226def CR6LT : CRBIT<24, "24">; 227def CR6GT : CRBIT<25, "25">; 228def CR6EQ : CRBIT<26, "26">; 229def CR6UN : CRBIT<27, "27">; 230def CR7LT : CRBIT<28, "28">; 231def CR7GT : CRBIT<29, "29">; 232def CR7EQ : CRBIT<30, "30">; 233def CR7UN : CRBIT<31, "31">; 234 235// Condition registers 236let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in { 237def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>; 238def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>; 239def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>; 240def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>; 241def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>; 242def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>; 243def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>; 244def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>; 245} 246 247// Link register 248def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 249//let Aliases = [LR] in 250def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 251 252// Count register 253def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 254def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; 255 256// VRsave register 257def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; 258 259// SPE extra registers 260def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>; 261 262def XER: SPR<1, "xer">, DwarfRegNum<[76]>; 263 264// Carry bit. In the architecture this is really bit 0 of the XER register 265// (which really is SPR register 1); this is the only bit interesting to a 266// compiler. 267def CARRY: SPR<1, "xer">, DwarfRegNum<[76]> { 268 let Aliases = [XER]; 269} 270 271// FP rounding mode: bits 30 and 31 of the FP status and control register 272// This is not allocated as a normal register; it appears only in 273// Uses and Defs. The ABI says it needs to be preserved by a function, 274// but this is not achieved by saving and restoring it as with 275// most registers, it has to be done in code; to make this work all the 276// return and call instructions are described as Uses of RM, so instructions 277// that do nothing but change RM will not get deleted. 278def RM: PPCReg<"**ROUNDING MODE**">; 279 280/// Register classes 281// Allocate volatiles first 282// then nonvolatiles in reverse order since stmw/lmw save from rN to r31 283def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12), 284 (sequence "R%u", 30, 13), 285 R31, R0, R1, FP, BP)> { 286 // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so 287 // put it at the end of the list. 288 // On AIX, CSRs are allocated starting from R31 according to: 289 // https://www.ibm.com/docs/en/ssw_aix_72/assembler/assembler_pdf.pdf. 290 // This also helps setting the correct `NumOfGPRsSaved' in traceback table. 291 let AltOrders = [(add (sub GPRC, R2), R2), 292 (add (sequence "R%u", 2, 12), 293 (sequence "R%u", 31, 13), R0, R1, FP, BP)]; 294 let AltOrderSelect = [{ 295 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx(); 296 }]; 297} 298 299def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12), 300 (sequence "X%u", 30, 14), 301 X31, X13, X0, X1, FP8, BP8)> { 302 // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so 303 // put it at the end of the list. 304 let AltOrders = [(add (sub G8RC, X2), X2), 305 (add (sequence "X%u", 2, 12), 306 (sequence "X%u", 31, 13), X0, X1, FP8, BP8)]; 307 let AltOrderSelect = [{ 308 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx(); 309 }]; 310} 311 312// For some instructions r0 is special (representing the value 0 instead of 313// the value in the r0 register), and we use these register subclasses to 314// prevent r0 from being allocated for use by those instructions. 315def GPRC_NOR0 : RegisterClass<"PPC", [i32,f32], 32, (add (sub GPRC, R0), ZERO)> { 316 // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so 317 // put it at the end of the list. 318 let AltOrders = [(add (sub GPRC_NOR0, R2), R2), 319 (add (sequence "R%u", 2, 12), 320 (sequence "R%u", 31, 13), R1, FP, BP, ZERO)]; 321 let AltOrderSelect = [{ 322 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx(); 323 }]; 324} 325 326def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)> { 327 // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so 328 // put it at the end of the list. 329 let AltOrders = [(add (sub G8RC_NOX0, X2), X2), 330 (add (sequence "X%u", 2, 12), 331 (sequence "X%u", 31, 13), X1, FP8, BP8, ZERO8)]; 332 let AltOrderSelect = [{ 333 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx(); 334 }]; 335} 336 337def SPERC : RegisterClass<"PPC", [f64], 64, (add (sequence "S%u", 2, 12), 338 (sequence "S%u", 30, 13), 339 S31, S0, S1)>; 340 341// Allocate volatiles first, then non-volatiles in reverse order. With the SVR4 342// ABI the size of the Floating-point register save area is determined by the 343// allocated non-volatile register with the lowest register number, as FP 344// register N is spilled to offset 8 * (32 - N) below the back chain word of the 345// previous stack frame. By allocating non-volatiles in reverse order we make 346// sure that the Floating-point register save area is always as small as 347// possible because there aren't any unused spill slots. 348def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13), 349 (sequence "F%u", 31, 14))>; 350def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>; 351 352def VRRC : RegisterClass<"PPC", 353 [v16i8,v8i16,v4i32,v2i64,v1i128,v4f32,v2f64, f128], 354 128, 355 (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11, 356 V12, V13, V14, V15, V16, V17, V18, V19, V31, V30, 357 V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>; 358 359// VSX register classes (the allocation order mirrors that of the corresponding 360// subregister classes). 361def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128, 362 (add (sequence "VSL%u", 0, 13), 363 (sequence "VSL%u", 31, 14))>; 364def VSRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128, 365 (add VSLRC, VRRC)>; 366 367// Register classes for the 64-bit "scalar" VSX subregisters. 368def VFRC : RegisterClass<"PPC", [f64], 64, 369 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7, 370 VF8, VF9, VF10, VF11, VF12, VF13, VF14, 371 VF15, VF16, VF17, VF18, VF19, VF31, VF30, 372 VF29, VF28, VF27, VF26, VF25, VF24, VF23, 373 VF22, VF21, VF20)>; 374def VSFRC : RegisterClass<"PPC", [f64], 64, (add F8RC, VFRC)>; 375 376// Allow spilling GPR's into caller-saved VSR's. 377def SPILLTOVSRRC : RegisterClass<"PPC", [i64, f64], 64, (add G8RC, (sub VSFRC, 378 (sequence "VF%u", 31, 20), 379 (sequence "F%u", 31, 14)))>; 380 381// Register class for single precision scalars in VSX registers 382def VSSRC : RegisterClass<"PPC", [f32], 32, (add VSFRC)>; 383 384def CRBITRC : RegisterClass<"PPC", [i1], 32, 385 (add CR2LT, CR2GT, CR2EQ, CR2UN, 386 CR3LT, CR3GT, CR3EQ, CR3UN, 387 CR4LT, CR4GT, CR4EQ, CR4UN, 388 CR5LT, CR5GT, CR5EQ, CR5UN, 389 CR6LT, CR6GT, CR6EQ, CR6UN, 390 CR7LT, CR7GT, CR7EQ, CR7UN, 391 CR1LT, CR1GT, CR1EQ, CR1UN, 392 CR0LT, CR0GT, CR0EQ, CR0UN)> { 393 let Size = 32; 394 let AltOrders = [(sub CRBITRC, CR2LT, CR2GT, CR2EQ, CR2UN, CR3LT, CR3GT, 395 CR3EQ, CR3UN, CR4LT, CR4GT, CR4EQ, CR4UN)]; 396 let AltOrderSelect = [{ 397 return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() && 398 MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled(); 399 }]; 400} 401 402def CRRC : RegisterClass<"PPC", [i32], 32, 403 (add CR0, CR1, CR5, CR6, 404 CR7, CR2, CR3, CR4)> { 405 let AltOrders = [(sub CRRC, CR2, CR3, CR4)]; 406 let AltOrderSelect = [{ 407 return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() && 408 MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled(); 409 }]; 410} 411// The CTR registers are not allocatable because they're used by the 412// decrement-and-branch instructions, and thus need to stay live across 413// multiple basic blocks. 414def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> { 415 let isAllocatable = 0; 416} 417def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> { 418 let isAllocatable = 0; 419} 420 421def LRRC : RegisterClass<"PPC", [i32], 32, (add LR)> { 422 let isAllocatable = 0; 423} 424def LR8RC : RegisterClass<"PPC", [i64], 64, (add LR8)> { 425 let isAllocatable = 0; 426} 427 428def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>; 429def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY, XER)> { 430 let CopyCost = -1; 431} 432 433// Make AllocationOrder as similar as G8RC's to avoid potential spilling. 434// Similarly, we have an AltOrder for 64-bit ELF ABI which r2 is allocated 435// at last. 436def G8pRC : 437 RegisterClass<"PPC", [i128], 128, 438 (add (sequence "G8p%u", 1, 5), 439 (sequence "G8p%u", 14, 7), 440 G8p15, G8p6, G8p0)> { 441 let AltOrders = [(add (sub G8pRC, G8p1), G8p1)]; 442 let AltOrderSelect = [{ 443 return MF.getSubtarget<PPCSubtarget>().is64BitELFABI(); 444 }]; 445 let Size = 128; 446} 447 448include "PPCRegisterInfoMMA.td" 449include "PPCRegisterInfoDMR.td" 450 451//===----------------------------------------------------------------------===// 452// PowerPC Operand Definitions. 453 454// In the default PowerPC assembler syntax, registers are specified simply 455// by number, so they cannot be distinguished from immediate values (without 456// looking at the opcode). This means that the default operand matching logic 457// for the asm parser does not work, and we need to specify custom matchers. 458// Since those can only be specified with RegisterOperand classes and not 459// directly on the RegisterClass, all instructions patterns used by the asm 460// parser need to use a RegisterOperand (instead of a RegisterClass) for 461// all their register operands. 462// For this purpose, we define one RegisterOperand for each RegisterClass, 463// using the same name as the class, just in lower case. 464 465def PPCRegGPRCAsmOperand : AsmOperandClass { 466 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber"; 467} 468def gprc : RegisterOperand<GPRC> { 469 let ParserMatchClass = PPCRegGPRCAsmOperand; 470} 471def PPCRegG8RCAsmOperand : AsmOperandClass { 472 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber"; 473} 474def g8rc : RegisterOperand<G8RC> { 475 let ParserMatchClass = PPCRegG8RCAsmOperand; 476} 477def PPCRegG8pRCAsmOperand : AsmOperandClass { 478 let Name = "RegG8pRC"; let PredicateMethod = "isEvenRegNumber"; 479} 480def g8prc : RegisterOperand<G8pRC> { 481 let ParserMatchClass = PPCRegG8pRCAsmOperand; 482} 483def PPCRegGPRCNoR0AsmOperand : AsmOperandClass { 484 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber"; 485} 486def gprc_nor0 : RegisterOperand<GPRC_NOR0> { 487 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand; 488} 489def PPCRegG8RCNoX0AsmOperand : AsmOperandClass { 490 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber"; 491} 492def g8rc_nox0 : RegisterOperand<G8RC_NOX0> { 493 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand; 494} 495def PPCRegF8RCAsmOperand : AsmOperandClass { 496 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber"; 497} 498def f8rc : RegisterOperand<F8RC> { 499 let ParserMatchClass = PPCRegF8RCAsmOperand; 500} 501def PPCRegF4RCAsmOperand : AsmOperandClass { 502 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber"; 503} 504def f4rc : RegisterOperand<F4RC> { 505 let ParserMatchClass = PPCRegF4RCAsmOperand; 506} 507def PPCRegVRRCAsmOperand : AsmOperandClass { 508 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber"; 509} 510def vrrc : RegisterOperand<VRRC> { 511 let ParserMatchClass = PPCRegVRRCAsmOperand; 512} 513def PPCRegVFRCAsmOperand : AsmOperandClass { 514 let Name = "RegVFRC"; let PredicateMethod = "isRegNumber"; 515} 516def vfrc : RegisterOperand<VFRC> { 517 let ParserMatchClass = PPCRegVFRCAsmOperand; 518} 519def PPCRegCRBITRCAsmOperand : AsmOperandClass { 520 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber"; 521} 522def crbitrc : RegisterOperand<CRBITRC> { 523 let ParserMatchClass = PPCRegCRBITRCAsmOperand; 524} 525def PPCRegCRRCAsmOperand : AsmOperandClass { 526 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber"; 527} 528def crrc : RegisterOperand<CRRC> { 529 let ParserMatchClass = PPCRegCRRCAsmOperand; 530} 531def PPCRegSPERCAsmOperand : AsmOperandClass { 532 let Name = "RegSPERC"; let PredicateMethod = "isRegNumber"; 533} 534def sperc : RegisterOperand<SPERC> { 535 let ParserMatchClass = PPCRegSPERCAsmOperand; 536} 537def PPCRegSPE4RCAsmOperand : AsmOperandClass { 538 let Name = "RegSPE4RC"; let PredicateMethod = "isRegNumber"; 539} 540def spe4rc : RegisterOperand<GPRC> { 541 let ParserMatchClass = PPCRegSPE4RCAsmOperand; 542} 543 544def PPCU1ImmAsmOperand : AsmOperandClass { 545 let Name = "U1Imm"; let PredicateMethod = "isU1Imm"; 546 let RenderMethod = "addImmOperands"; 547} 548def u1imm : Operand<i32> { 549 let PrintMethod = "printU1ImmOperand"; 550 let ParserMatchClass = PPCU1ImmAsmOperand; 551 let OperandType = "OPERAND_IMMEDIATE"; 552} 553 554def PPCU2ImmAsmOperand : AsmOperandClass { 555 let Name = "U2Imm"; let PredicateMethod = "isU2Imm"; 556 let RenderMethod = "addImmOperands"; 557} 558def u2imm : Operand<i32> { 559 let PrintMethod = "printU2ImmOperand"; 560 let ParserMatchClass = PPCU2ImmAsmOperand; 561 let OperandType = "OPERAND_IMMEDIATE"; 562} 563 564def PPCATBitsAsHintAsmOperand : AsmOperandClass { 565 let Name = "ATBitsAsHint"; let PredicateMethod = "isATBitsAsHint"; 566 let RenderMethod = "addImmOperands"; // Irrelevant, predicate always fails. 567} 568def atimm : Operand<i32> { 569 let PrintMethod = "printATBitsAsHint"; 570 let ParserMatchClass = PPCATBitsAsHintAsmOperand; 571 let OperandType = "OPERAND_IMMEDIATE"; 572} 573 574def PPCU3ImmAsmOperand : AsmOperandClass { 575 let Name = "U3Imm"; let PredicateMethod = "isU3Imm"; 576 let RenderMethod = "addImmOperands"; 577} 578def u3imm : Operand<i32> { 579 let PrintMethod = "printU3ImmOperand"; 580 let ParserMatchClass = PPCU3ImmAsmOperand; 581 let OperandType = "OPERAND_IMMEDIATE"; 582} 583 584def PPCU4ImmAsmOperand : AsmOperandClass { 585 let Name = "U4Imm"; let PredicateMethod = "isU4Imm"; 586 let RenderMethod = "addImmOperands"; 587} 588def u4imm : Operand<i32> { 589 let PrintMethod = "printU4ImmOperand"; 590 let ParserMatchClass = PPCU4ImmAsmOperand; 591 let OperandType = "OPERAND_IMMEDIATE"; 592} 593def PPCS5ImmAsmOperand : AsmOperandClass { 594 let Name = "S5Imm"; let PredicateMethod = "isS5Imm"; 595 let RenderMethod = "addImmOperands"; 596} 597def s5imm : Operand<i32> { 598 let PrintMethod = "printS5ImmOperand"; 599 let ParserMatchClass = PPCS5ImmAsmOperand; 600 let DecoderMethod = "decodeSImmOperand<5>"; 601 let OperandType = "OPERAND_IMMEDIATE"; 602} 603def PPCU5ImmAsmOperand : AsmOperandClass { 604 let Name = "U5Imm"; let PredicateMethod = "isU5Imm"; 605 let RenderMethod = "addImmOperands"; 606} 607def u5imm : Operand<i32> { 608 let PrintMethod = "printU5ImmOperand"; 609 let ParserMatchClass = PPCU5ImmAsmOperand; 610 let DecoderMethod = "decodeUImmOperand<5>"; 611 let OperandType = "OPERAND_IMMEDIATE"; 612} 613def PPCU6ImmAsmOperand : AsmOperandClass { 614 let Name = "U6Imm"; let PredicateMethod = "isU6Imm"; 615 let RenderMethod = "addImmOperands"; 616} 617def u6imm : Operand<i32> { 618 let PrintMethod = "printU6ImmOperand"; 619 let ParserMatchClass = PPCU6ImmAsmOperand; 620 let DecoderMethod = "decodeUImmOperand<6>"; 621 let OperandType = "OPERAND_IMMEDIATE"; 622} 623def PPCU7ImmAsmOperand : AsmOperandClass { 624 let Name = "U7Imm"; let PredicateMethod = "isU7Imm"; 625 let RenderMethod = "addImmOperands"; 626} 627def u7imm : Operand<i32> { 628 let PrintMethod = "printU7ImmOperand"; 629 let ParserMatchClass = PPCU7ImmAsmOperand; 630 let DecoderMethod = "decodeUImmOperand<7>"; 631 let OperandType = "OPERAND_IMMEDIATE"; 632} 633def PPCU8ImmAsmOperand : AsmOperandClass { 634 let Name = "U8Imm"; let PredicateMethod = "isU8Imm"; 635 let RenderMethod = "addImmOperands"; 636} 637def u8imm : Operand<i32> { 638 let PrintMethod = "printU8ImmOperand"; 639 let ParserMatchClass = PPCU8ImmAsmOperand; 640 let DecoderMethod = "decodeUImmOperand<8>"; 641 let OperandType = "OPERAND_IMMEDIATE"; 642} 643def PPCU10ImmAsmOperand : AsmOperandClass { 644 let Name = "U10Imm"; let PredicateMethod = "isU10Imm"; 645 let RenderMethod = "addImmOperands"; 646} 647def u10imm : Operand<i32> { 648 let PrintMethod = "printU10ImmOperand"; 649 let ParserMatchClass = PPCU10ImmAsmOperand; 650 let DecoderMethod = "decodeUImmOperand<10>"; 651 let OperandType = "OPERAND_IMMEDIATE"; 652} 653def PPCU12ImmAsmOperand : AsmOperandClass { 654 let Name = "U12Imm"; let PredicateMethod = "isU12Imm"; 655 let RenderMethod = "addImmOperands"; 656} 657def u12imm : Operand<i32> { 658 let PrintMethod = "printU12ImmOperand"; 659 let ParserMatchClass = PPCU12ImmAsmOperand; 660 let DecoderMethod = "decodeUImmOperand<12>"; 661 let OperandType = "OPERAND_IMMEDIATE"; 662} 663def PPCS16ImmAsmOperand : AsmOperandClass { 664 let Name = "S16Imm"; let PredicateMethod = "isS16Imm"; 665 let RenderMethod = "addS16ImmOperands"; 666} 667def s16imm : Operand<i32> { 668 let PrintMethod = "printS16ImmOperand"; 669 let EncoderMethod = "getImm16Encoding"; 670 let ParserMatchClass = PPCS16ImmAsmOperand; 671 let DecoderMethod = "decodeSImmOperand<16>"; 672 let OperandType = "OPERAND_IMMEDIATE"; 673} 674def PPCU16ImmAsmOperand : AsmOperandClass { 675 let Name = "U16Imm"; let PredicateMethod = "isU16Imm"; 676 let RenderMethod = "addU16ImmOperands"; 677} 678def u16imm : Operand<i32> { 679 let PrintMethod = "printU16ImmOperand"; 680 let EncoderMethod = "getImm16Encoding"; 681 let ParserMatchClass = PPCU16ImmAsmOperand; 682 let DecoderMethod = "decodeUImmOperand<16>"; 683 let OperandType = "OPERAND_IMMEDIATE"; 684} 685def PPCS17ImmAsmOperand : AsmOperandClass { 686 let Name = "S17Imm"; let PredicateMethod = "isS17Imm"; 687 let RenderMethod = "addS16ImmOperands"; 688} 689def s17imm : Operand<i32> { 690 // This operand type is used for addis/lis to allow the assembler parser 691 // to accept immediates in the range -65536..65535 for compatibility with 692 // the GNU assembler. The operand is treated as 16-bit otherwise. 693 let PrintMethod = "printS16ImmOperand"; 694 let EncoderMethod = "getImm16Encoding"; 695 let ParserMatchClass = PPCS17ImmAsmOperand; 696 let DecoderMethod = "decodeSImmOperand<16>"; 697 let OperandType = "OPERAND_IMMEDIATE"; 698} 699def PPCS34ImmAsmOperand : AsmOperandClass { 700 let Name = "S34Imm"; 701 let PredicateMethod = "isS34Imm"; 702 let RenderMethod = "addImmOperands"; 703} 704def s34imm : Operand<i64> { 705 let PrintMethod = "printS34ImmOperand"; 706 let EncoderMethod = "getImm34EncodingNoPCRel"; 707 let ParserMatchClass = PPCS34ImmAsmOperand; 708 let DecoderMethod = "decodeSImmOperand<34>"; 709 let OperandType = "OPERAND_IMMEDIATE"; 710} 711def s34imm_pcrel : Operand<i64> { 712 let PrintMethod = "printS34ImmOperand"; 713 let EncoderMethod = "getImm34EncodingPCRel"; 714 let ParserMatchClass = PPCS34ImmAsmOperand; 715 let DecoderMethod = "decodeSImmOperand<34>"; 716 let OperandType = "OPERAND_IMMEDIATE"; 717} 718def PPCImmZeroAsmOperand : AsmOperandClass { 719 let Name = "ImmZero"; 720 let PredicateMethod = "isImmZero"; 721 let RenderMethod = "addImmOperands"; 722} 723def immZero : Operand<i32> { 724 let PrintMethod = "printImmZeroOperand"; 725 let ParserMatchClass = PPCImmZeroAsmOperand; 726 let DecoderMethod = "decodeImmZeroOperand"; 727 let OperandType = "OPERAND_IMMEDIATE"; 728} 729 730def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; 731def fpimm0neg : PatLeaf<(fpimm), [{return N->isExactlyValue(-0.0);}]>; 732 733def PPCDirectBrAsmOperand : AsmOperandClass { 734 let Name = "DirectBr"; let PredicateMethod = "isDirectBr"; 735 let RenderMethod = "addBranchTargetOperands"; 736} 737def directbrtarget : Operand<OtherVT> { 738 let PrintMethod = "printBranchOperand"; 739 let EncoderMethod = "getDirectBrEncoding"; 740 let DecoderMethod = "decodeDirectBrTarget"; 741 let ParserMatchClass = PPCDirectBrAsmOperand; 742 let OperandType = "OPERAND_PCREL"; 743} 744def absdirectbrtarget : Operand<OtherVT> { 745 let PrintMethod = "printAbsBranchOperand"; 746 let EncoderMethod = "getAbsDirectBrEncoding"; 747 let ParserMatchClass = PPCDirectBrAsmOperand; 748} 749def PPCCondBrAsmOperand : AsmOperandClass { 750 let Name = "CondBr"; let PredicateMethod = "isCondBr"; 751 let RenderMethod = "addBranchTargetOperands"; 752} 753def condbrtarget : Operand<OtherVT> { 754 let PrintMethod = "printBranchOperand"; 755 let EncoderMethod = "getCondBrEncoding"; 756 let DecoderMethod = "decodeCondBrTarget"; 757 let ParserMatchClass = PPCCondBrAsmOperand; 758 let OperandType = "OPERAND_PCREL"; 759} 760def abscondbrtarget : Operand<OtherVT> { 761 let PrintMethod = "printAbsBranchOperand"; 762 let EncoderMethod = "getAbsCondBrEncoding"; 763 let ParserMatchClass = PPCCondBrAsmOperand; 764} 765def calltarget : Operand<iPTR> { 766 let PrintMethod = "printBranchOperand"; 767 let EncoderMethod = "getDirectBrEncoding"; 768 let DecoderMethod = "decodeDirectBrTarget"; 769 let ParserMatchClass = PPCDirectBrAsmOperand; 770 let OperandType = "OPERAND_PCREL"; 771} 772def abscalltarget : Operand<iPTR> { 773 let PrintMethod = "printAbsBranchOperand"; 774 let EncoderMethod = "getAbsDirectBrEncoding"; 775 let ParserMatchClass = PPCDirectBrAsmOperand; 776} 777def PPCCRBitMaskOperand : AsmOperandClass { 778 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask"; 779} 780def crbitm: Operand<i8> { 781 let PrintMethod = "printcrbitm"; 782 let EncoderMethod = "get_crbitm_encoding"; 783 let DecoderMethod = "decodeCRBitMOperand"; 784 let ParserMatchClass = PPCCRBitMaskOperand; 785} 786// Address operands 787// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode). 788def PPCRegGxRCNoR0Operand : AsmOperandClass { 789 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; 790} 791def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> { 792 let ParserMatchClass = PPCRegGxRCNoR0Operand; 793} 794 795// New addressing modes with 34 bit immediates. 796def PPCDispRI34Operand : AsmOperandClass { 797 let Name = "DispRI34"; let PredicateMethod = "isS34Imm"; 798 let RenderMethod = "addImmOperands"; 799} 800def dispRI34 : Operand<iPTR> { 801 let ParserMatchClass = PPCDispRI34Operand; 802} 803def memri34 : Operand<iPTR> { // memri, imm is a 34-bit value. 804 let PrintMethod = "printMemRegImm34"; 805 let MIOperandInfo = (ops dispRI34:$imm, ptr_rc_nor0:$reg); 806 let EncoderMethod = "getMemRI34Encoding"; 807 let DecoderMethod = "decodeMemRI34Operands"; 808} 809// memri, imm is a 34-bit value for pc-relative instructions where 810// base register is set to zero. 811def memri34_pcrel : Operand<iPTR> { // memri, imm is a 34-bit value. 812 let PrintMethod = "printMemRegImm34PCRel"; 813 let MIOperandInfo = (ops dispRI34:$imm, immZero:$reg); 814 let EncoderMethod = "getMemRI34PCRelEncoding"; 815 let DecoderMethod = "decodeMemRI34PCRelOperands"; 816} 817 818// A version of ptr_rc usable with the asm parser. 819def PPCRegGxRCOperand : AsmOperandClass { 820 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber"; 821} 822def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> { 823 let ParserMatchClass = PPCRegGxRCOperand; 824} 825 826def PPCDispRIOperand : AsmOperandClass { 827 let Name = "DispRI"; let PredicateMethod = "isS16Imm"; 828 let RenderMethod = "addS16ImmOperands"; 829} 830def dispRI : Operand<iPTR> { 831 let ParserMatchClass = PPCDispRIOperand; 832} 833def PPCDispRIXOperand : AsmOperandClass { 834 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4"; 835 let RenderMethod = "addS16ImmOperands"; 836} 837def dispRIX : Operand<iPTR> { 838 let ParserMatchClass = PPCDispRIXOperand; 839} 840def PPCDispRIHashOperand : AsmOperandClass { 841 let Name = "DispRIHash"; let PredicateMethod = "isHashImmX8"; 842 let RenderMethod = "addImmOperands"; 843} 844def dispRIHash : Operand<iPTR> { 845 let ParserMatchClass = PPCDispRIHashOperand; 846} 847def PPCDispRIX16Operand : AsmOperandClass { 848 let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16"; 849 let RenderMethod = "addS16ImmOperands"; 850} 851def dispRIX16 : Operand<iPTR> { 852 let ParserMatchClass = PPCDispRIX16Operand; 853} 854def PPCDispSPE8Operand : AsmOperandClass { 855 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8"; 856 let RenderMethod = "addImmOperands"; 857} 858def dispSPE8 : Operand<iPTR> { 859 let ParserMatchClass = PPCDispSPE8Operand; 860} 861def PPCDispSPE4Operand : AsmOperandClass { 862 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4"; 863 let RenderMethod = "addImmOperands"; 864} 865def dispSPE4 : Operand<iPTR> { 866 let ParserMatchClass = PPCDispSPE4Operand; 867} 868def PPCDispSPE2Operand : AsmOperandClass { 869 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2"; 870 let RenderMethod = "addImmOperands"; 871} 872def dispSPE2 : Operand<iPTR> { 873 let ParserMatchClass = PPCDispSPE2Operand; 874} 875 876def memri : Operand<iPTR> { 877 let PrintMethod = "printMemRegImm"; 878 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 879 let EncoderMethod = "getMemRIEncoding"; 880 let DecoderMethod = "decodeMemRIOperands"; 881 let OperandType = "OPERAND_MEMORY"; 882} 883def memrr : Operand<iPTR> { 884 let PrintMethod = "printMemRegReg"; 885 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg); 886 let OperandType = "OPERAND_MEMORY"; 887} 888def memrix : Operand<iPTR> { // memri where the imm is 4-aligned. 889 let PrintMethod = "printMemRegImm"; 890 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 891 let EncoderMethod = "getMemRIXEncoding"; 892 let DecoderMethod = "decodeMemRIXOperands"; 893 let OperandType = "OPERAND_MEMORY"; 894} 895def memrihash : Operand<iPTR> { 896 // memrihash 8-aligned for ROP Protection Instructions. 897 let PrintMethod = "printMemRegImmHash"; 898 let MIOperandInfo = (ops dispRIHash:$imm, ptr_rc_nor0:$reg); 899 let EncoderMethod = "getMemRIHashEncoding"; 900 let DecoderMethod = "decodeMemRIHashOperands"; 901 let OperandType = "OPERAND_MEMORY"; 902} 903def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27} 904 let PrintMethod = "printMemRegImm"; 905 let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); 906 let EncoderMethod = "getMemRIX16Encoding"; 907 let DecoderMethod = "decodeMemRIX16Operands"; 908 let OperandType = "OPERAND_MEMORY"; 909} 910def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned. 911 let PrintMethod = "printMemRegImm"; 912 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); 913 let EncoderMethod = "getSPE8DisEncoding"; 914 let DecoderMethod = "decodeSPE8Operands"; 915 let OperandType = "OPERAND_MEMORY"; 916} 917def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned. 918 let PrintMethod = "printMemRegImm"; 919 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); 920 let EncoderMethod = "getSPE4DisEncoding"; 921 let DecoderMethod = "decodeSPE4Operands"; 922 let OperandType = "OPERAND_MEMORY"; 923} 924def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned. 925 let PrintMethod = "printMemRegImm"; 926 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); 927 let EncoderMethod = "getSPE2DisEncoding"; 928 let DecoderMethod = "decodeSPE2Operands"; 929 let OperandType = "OPERAND_MEMORY"; 930} 931 932// A single-register address. This is used with the SjLj 933// pseudo-instructions which translates to LD/LWZ. These instructions requires 934// G8RC_NOX0 registers. 935def memr : Operand<iPTR> { 936 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg); 937 let OperandType = "OPERAND_MEMORY"; 938} 939def PPCTLSRegOperand : AsmOperandClass { 940 let Name = "TLSReg"; let PredicateMethod = "isTLSReg"; 941 let RenderMethod = "addTLSRegOperands"; 942} 943def tlsreg32 : Operand<i32> { 944 let EncoderMethod = "getTLSRegEncoding"; 945 let ParserMatchClass = PPCTLSRegOperand; 946} 947def tlsgd32 : Operand<i32> {} 948def tlscall32 : Operand<i32> { 949 let PrintMethod = "printTLSCall"; 950 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym); 951 let EncoderMethod = "getTLSCallEncoding"; 952} 953 954// PowerPC Predicate operand. 955def pred : Operand<OtherVT> { 956 let PrintMethod = "printPredicateOperand"; 957 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg); 958} 959 960def PPCRegVSRCAsmOperand : AsmOperandClass { 961 let Name = "RegVSRC"; let PredicateMethod = "isVSRegNumber"; 962} 963def vsrc : RegisterOperand<VSRC> { 964 let ParserMatchClass = PPCRegVSRCAsmOperand; 965} 966 967def PPCRegVSFRCAsmOperand : AsmOperandClass { 968 let Name = "RegVSFRC"; let PredicateMethod = "isVSRegNumber"; 969} 970def vsfrc : RegisterOperand<VSFRC> { 971 let ParserMatchClass = PPCRegVSFRCAsmOperand; 972} 973 974def PPCRegVSSRCAsmOperand : AsmOperandClass { 975 let Name = "RegVSSRC"; let PredicateMethod = "isVSRegNumber"; 976} 977def vssrc : RegisterOperand<VSSRC> { 978 let ParserMatchClass = PPCRegVSSRCAsmOperand; 979} 980 981def PPCRegSPILLTOVSRRCAsmOperand : AsmOperandClass { 982 let Name = "RegSPILLTOVSRRC"; let PredicateMethod = "isVSRegNumber"; 983} 984 985def spilltovsrrc : RegisterOperand<SPILLTOVSRRC> { 986 let ParserMatchClass = PPCRegSPILLTOVSRRCAsmOperand; 987} 988 989def PPCRegVSRpRCAsmOperand : AsmOperandClass { 990 let Name = "RegVSRpRC"; let PredicateMethod = "isVSRpEvenRegNumber"; 991} 992 993def vsrprc : RegisterOperand<VSRpRC> { 994 let ParserMatchClass = PPCRegVSRpRCAsmOperand; 995} 996 997def PPCRegVSRpEvenRCAsmOperand : AsmOperandClass { 998 let Name = "RegVSRpEvenRC"; let PredicateMethod = "isVSRpEvenRegNumber"; 999} 1000 1001def vsrpevenrc : RegisterOperand<VSRpRC> { 1002 let ParserMatchClass = PPCRegVSRpEvenRCAsmOperand; 1003 let EncoderMethod = "getVSRpEvenEncoding"; 1004 let DecoderMethod = "decodeVSRpEvenOperands"; 1005} 1006 1007def PPCRegACCRCAsmOperand : AsmOperandClass { 1008 let Name = "RegACCRC"; let PredicateMethod = "isACCRegNumber"; 1009} 1010 1011def acc : RegisterOperand<ACCRC> { 1012 let ParserMatchClass = PPCRegACCRCAsmOperand; 1013} 1014 1015def uacc : RegisterOperand<UACCRC> { 1016 let ParserMatchClass = PPCRegACCRCAsmOperand; 1017} 1018 1019// DMR Register Operands 1020def PPCRegDMRROWRCAsmOperand : AsmOperandClass { 1021 let Name = "RegDMRROWRC"; 1022 let PredicateMethod = "isDMRROWRegNumber"; 1023} 1024 1025def dmrrow : RegisterOperand<DMRROWRC> { 1026 let ParserMatchClass = PPCRegDMRROWRCAsmOperand; 1027} 1028 1029def PPCRegDMRROWpRCAsmOperand : AsmOperandClass { 1030 let Name = "RegDMRROWpRC"; 1031 let PredicateMethod = "isDMRROWpRegNumber"; 1032} 1033 1034def dmrrowp : RegisterOperand<DMRROWpRC> { 1035 let ParserMatchClass = PPCRegDMRROWpRCAsmOperand; 1036} 1037 1038def wacc : RegisterOperand<WACCRC> { 1039 let ParserMatchClass = PPCRegACCRCAsmOperand; 1040} 1041 1042def wacc_hi : RegisterOperand<WACC_HIRC> { 1043 let ParserMatchClass = PPCRegACCRCAsmOperand; 1044} 1045 1046def PPCRegDMRRCAsmOperand : AsmOperandClass { 1047 let Name = "RegDMRRC"; 1048 let PredicateMethod = "isDMRRegNumber"; 1049} 1050 1051def dmr : RegisterOperand<DMRRC> { 1052 let ParserMatchClass = PPCRegDMRRCAsmOperand; 1053} 1054 1055def PPCRegDMRpRCAsmOperand : AsmOperandClass { 1056 let Name = "RegDMRpRC"; 1057 let PredicateMethod = "isDMRpRegNumber"; 1058} 1059 1060def dmrp : RegisterOperand<DMRpRC> { 1061 let ParserMatchClass = PPCRegDMRpRCAsmOperand; 1062} 1063