1//===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12let Namespace = "PPC" in { 13def sub_lt : SubRegIndex<1>; 14def sub_gt : SubRegIndex<1, 1>; 15def sub_eq : SubRegIndex<1, 2>; 16def sub_un : SubRegIndex<1, 3>; 17def sub_32 : SubRegIndex<32>; 18def sub_32_hi_phony : SubRegIndex<32,32>; 19def sub_64 : SubRegIndex<64>; 20def sub_vsx0 : SubRegIndex<128>; 21def sub_vsx1 : SubRegIndex<128, 128>; 22def sub_gp8_x0 : SubRegIndex<64>; 23def sub_gp8_x1 : SubRegIndex<64, 64>; 24def sub_fp0 : SubRegIndex<64>; 25def sub_fp1 : SubRegIndex<64, 64>; 26} 27 28 29class PPCReg<string n> : Register<n> { 30 let Namespace = "PPC"; 31} 32 33// We identify all our registers with a 5-bit ID, for consistency's sake. 34 35// GPR - One of the 32 32-bit general-purpose registers 36class GPR<bits<5> num, string n> : PPCReg<n> { 37 let HWEncoding{4-0} = num; 38} 39 40// GP8 - One of the 32 64-bit general-purpose registers 41class GP8<GPR SubReg, string n> : PPCReg<n> { 42 let HWEncoding = SubReg.HWEncoding; 43 let SubRegs = [SubReg]; 44 let SubRegIndices = [sub_32]; 45} 46 47class SPE<string n, bits<5> Enc, list<Register> subregs = []> : PPCReg<n> { 48 let HWEncoding{4-0} = Enc; 49 let SubRegs = subregs; 50 let SubRegIndices = [sub_32, sub_32_hi_phony]; 51 let CoveredBySubRegs = 1; 52} 53// SPR - One of the 32-bit special-purpose registers 54class SPR<bits<10> num, string n> : PPCReg<n> { 55 let HWEncoding{9-0} = num; 56} 57 58// FPR - One of the 32 64-bit floating-point registers 59class FPR<bits<5> num, string n> : PPCReg<n> { 60 let HWEncoding{4-0} = num; 61} 62 63// FPPair - A pair of 64-bit floating-point registers. 64class FPPair<string n, bits<5> EvenIndex> : PPCReg<n> { 65 assert !eq(EvenIndex{0}, 0), "Index should be even."; 66 let HWEncoding{4-0} = EvenIndex; 67 let SubRegs = [!cast<FPR>("F"#EvenIndex), !cast<FPR>("F"#!add(EvenIndex, 1))]; 68 let DwarfNumbers = [-1, -1]; 69 let SubRegIndices = [sub_fp0, sub_fp1]; 70} 71 72// VF - One of the 32 64-bit floating-point subregisters of the vector 73// registers (used by VSX). 74class VF<bits<5> num, string n> : PPCReg<n> { 75 let HWEncoding{4-0} = num; 76 let HWEncoding{5} = 1; 77} 78 79// VR - One of the 32 128-bit vector registers 80class VR<VF SubReg, string n> : PPCReg<n> { 81 let HWEncoding{4-0} = SubReg.HWEncoding{4-0}; 82 let HWEncoding{5} = 0; 83 let SubRegs = [SubReg]; 84 let SubRegIndices = [sub_64]; 85} 86 87// VSRL - One of the 32 128-bit VSX registers that overlap with the scalar 88// floating-point registers. 89class VSRL<FPR SubReg, string n> : PPCReg<n> { 90 let HWEncoding = SubReg.HWEncoding; 91 let SubRegs = [SubReg]; 92 let SubRegIndices = [sub_64]; 93} 94 95// VSXReg - One of the VSX registers in the range vs32-vs63 with numbering 96// and encoding to match. 97class VSXReg<bits<6> num, string n> : PPCReg<n> { 98 let HWEncoding{5-0} = num; 99} 100 101// CR - One of the 8 4-bit condition registers 102class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> { 103 let HWEncoding{2-0} = num; 104 let SubRegs = subregs; 105} 106 107// CRBIT - One of the 32 1-bit condition register fields 108class CRBIT<bits<5> num, string n> : PPCReg<n> { 109 let HWEncoding{4-0} = num; 110} 111 112// VSR Pairs - One of the 32 paired even-odd consecutive VSRs. 113class VSRPair<bits<5> num, string n, list<Register> subregs> : PPCReg<n> { 114 let HWEncoding{4-0} = num; 115 let SubRegs = subregs; 116} 117 118// GP8Pair - Consecutive even-odd paired GP8. 119class GP8Pair<string n, bits<5> EvenIndex> : PPCReg<n> { 120 assert !eq(EvenIndex{0}, 0), "Index should be even."; 121 let HWEncoding{4-0} = EvenIndex; 122 let SubRegs = [!cast<GP8>("X"#EvenIndex), !cast<GP8>("X"#!add(EvenIndex, 1))]; 123 let DwarfNumbers = [-1, -1]; 124 let SubRegIndices = [sub_gp8_x0, sub_gp8_x1]; 125} 126 127// General-purpose registers 128foreach Index = 0-31 in { 129 def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>; 130} 131 132let isArtificial = 1 in { 133 foreach Index = 0-31 in { 134 def H#Index : GPR<-1,"">; 135 } 136} 137 138// 64-bit General-purpose registers 139foreach Index = 0-31 in { 140 def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>, 141 DwarfRegNum<[Index, -2]>; 142} 143 144// SPE registers 145foreach Index = 0-31 in { 146 def S#Index : SPE<"r"#Index, Index, [!cast<GPR>("R"#Index), !cast<GPR>("H"#Index)]>, 147 DwarfRegNum<[!add(Index, 1200), !add(Index, 1200)]>; 148 149} 150 151 152// Floating-point registers 153foreach Index = 0-31 in { 154 def F#Index : FPR<Index, "f"#Index>, 155 DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>; 156} 157 158// Floating-point pair registers 159foreach Index = { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 } in { 160 def Fpair#Index : FPPair<"fp"#Index, Index>; 161} 162 163// 64-bit Floating-point subregisters of Altivec registers 164// Note: the register names are v0-v31 or vs32-vs63 depending on the use. 165// Custom C++ code is used to produce the correct name and encoding. 166foreach Index = 0-31 in { 167 def VF#Index : VF<Index, "v" #Index>, 168 DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>; 169} 170 171// Vector registers 172foreach Index = 0-31 in { 173 def V#Index : VR<!cast<VF>("VF"#Index), "v"#Index>, 174 DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>; 175} 176 177// VSX registers 178foreach Index = 0-31 in { 179 def VSL#Index : VSRL<!cast<FPR>("F"#Index), "vs"#Index>, 180 DwarfRegAlias<!cast<FPR>("F"#Index)>; 181} 182 183// Dummy VSX registers, this defines string: "vs32"-"vs63", and is only used for 184// asm printing. 185foreach Index = 32-63 in { 186 def VSX#Index : VSXReg<Index, "vs"#Index>; 187} 188 189let SubRegIndices = [sub_vsx0, sub_vsx1] in { 190 // VSR pairs 0 - 15 (corresponding to VSRs 0 - 30 paired with 1 - 31). 191 foreach Index = { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 } in { 192 def VSRp#!srl(Index, 1) : VSRPair<!srl(Index, 1), "vsp"#Index, 193 [!cast<VSRL>("VSL"#Index), !cast<VSRL>("VSL"#!add(Index, 1))]>, 194 DwarfRegNum<[-1, -1]>; 195 } 196 197 // VSR pairs 16 - 31 (corresponding to VSRs 32 - 62 paired with 33 - 63). 198 foreach Index = { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 } in { 199 def VSRp#!add(!srl(Index, 1), 16) : 200 VSRPair<!add(!srl(Index, 1), 16), "vsp"#!add(Index, 32), 201 [!cast<VR>("V"#Index), !cast<VR>("V"#!add(Index, 1))]>, 202 DwarfRegNum<[-1, -1]>; 203 } 204} 205 206// 16 paired even-odd consecutive GP8s. 207foreach Index = { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 } in { 208 def G8p#!srl(Index, 1) : GP8Pair<"r"#Index, Index>; 209} 210 211// The representation of r0 when treated as the constant 0. 212let isConstant = true in { 213def ZERO : GPR<0, "0">, DwarfRegAlias<R0>; 214def ZERO8 : GP8<ZERO, "0">, DwarfRegAlias<X0>; 215} // isConstant = true 216 217// Representations of the frame pointer used by ISD::FRAMEADDR. 218def FP : GPR<0 /* arbitrary */, "**FRAME POINTER**">; 219def FP8 : GP8<FP, "**FRAME POINTER**">; 220 221// Representations of the base pointer used by setjmp. 222def BP : GPR<0 /* arbitrary */, "**BASE POINTER**">; 223def BP8 : GP8<BP, "**BASE POINTER**">; 224 225// Condition register bits 226def CR0LT : CRBIT< 0, "0">; 227def CR0GT : CRBIT< 1, "1">; 228def CR0EQ : CRBIT< 2, "2">; 229def CR0UN : CRBIT< 3, "3">; 230def CR1LT : CRBIT< 4, "4">; 231def CR1GT : CRBIT< 5, "5">; 232def CR1EQ : CRBIT< 6, "6">; 233def CR1UN : CRBIT< 7, "7">; 234def CR2LT : CRBIT< 8, "8">; 235def CR2GT : CRBIT< 9, "9">; 236def CR2EQ : CRBIT<10, "10">; 237def CR2UN : CRBIT<11, "11">; 238def CR3LT : CRBIT<12, "12">; 239def CR3GT : CRBIT<13, "13">; 240def CR3EQ : CRBIT<14, "14">; 241def CR3UN : CRBIT<15, "15">; 242def CR4LT : CRBIT<16, "16">; 243def CR4GT : CRBIT<17, "17">; 244def CR4EQ : CRBIT<18, "18">; 245def CR4UN : CRBIT<19, "19">; 246def CR5LT : CRBIT<20, "20">; 247def CR5GT : CRBIT<21, "21">; 248def CR5EQ : CRBIT<22, "22">; 249def CR5UN : CRBIT<23, "23">; 250def CR6LT : CRBIT<24, "24">; 251def CR6GT : CRBIT<25, "25">; 252def CR6EQ : CRBIT<26, "26">; 253def CR6UN : CRBIT<27, "27">; 254def CR7LT : CRBIT<28, "28">; 255def CR7GT : CRBIT<29, "29">; 256def CR7EQ : CRBIT<30, "30">; 257def CR7UN : CRBIT<31, "31">; 258 259// Condition registers 260let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in { 261def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>; 262def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>; 263def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>; 264def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>; 265def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>; 266def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>; 267def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>; 268def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>; 269} 270 271// Link register 272def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 273//let Aliases = [LR] in 274def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 275 276// Count register 277def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 278def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; 279 280// VRsave register 281def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; 282 283// SPE extra registers 284def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>; 285 286def XER: SPR<1, "xer">, DwarfRegNum<[76]>; 287 288// Carry bit. In the architecture this is really bit 0 of the XER register 289// (which really is SPR register 1); this is the only bit interesting to a 290// compiler. 291def CARRY: SPR<1, "xer">, DwarfRegNum<[76]> { 292 let Aliases = [XER]; 293} 294 295// FP rounding mode: bits 30 and 31 of the FP status and control register 296// This is not allocated as a normal register; it appears only in 297// Uses and Defs. The ABI says it needs to be preserved by a function, 298// but this is not achieved by saving and restoring it as with 299// most registers, it has to be done in code; to make this work all the 300// return and call instructions are described as Uses of RM, so instructions 301// that do nothing but change RM will not get deleted. 302def RM: PPCReg<"**ROUNDING MODE**">; 303 304let isAllocatable = 0 in 305def GPRC32 : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "H%u", 2, 12), 306 (sequence "H%u", 30, 13), 307 H31, H0, H1)>; 308 309/// Register classes 310// Allocate volatiles first 311// then nonvolatiles in reverse order since stmw/lmw save from rN to r31 312def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12), 313 (sequence "R%u", 30, 13), 314 R31, R0, R1, FP, BP)> { 315 // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so 316 // put it at the end of the list. 317 // On AIX, CSRs are allocated starting from R31 according to: 318 // https://www.ibm.com/docs/en/ssw_aix_72/assembler/assembler_pdf.pdf. 319 // This also helps setting the correct `NumOfGPRsSaved' in traceback table. 320 let AltOrders = [(add (sub GPRC, R2), R2), 321 (add (sequence "R%u", 2, 12), 322 (sequence "R%u", 31, 13), R0, R1, FP, BP)]; 323 let AltOrderSelect = [{ 324 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx(); 325 }]; 326} 327 328def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12), 329 (sequence "X%u", 30, 14), 330 X31, X13, X0, X1, FP8, BP8)> { 331 // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so 332 // put it at the end of the list. 333 let AltOrders = [(add (sub G8RC, X2), X2), 334 (add (sequence "X%u", 2, 12), 335 (sequence "X%u", 31, 13), X0, X1, FP8, BP8)]; 336 let AltOrderSelect = [{ 337 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx(); 338 }]; 339} 340 341// For some instructions r0 is special (representing the value 0 instead of 342// the value in the r0 register), and we use these register subclasses to 343// prevent r0 from being allocated for use by those instructions. 344def GPRC_NOR0 : RegisterClass<"PPC", [i32,f32], 32, (add (sub GPRC, R0), ZERO)> { 345 // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so 346 // put it at the end of the list. 347 let AltOrders = [(add (sub GPRC_NOR0, R2), R2), 348 (add (sequence "R%u", 2, 12), 349 (sequence "R%u", 31, 13), R1, FP, BP, ZERO)]; 350 let AltOrderSelect = [{ 351 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx(); 352 }]; 353} 354 355def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)> { 356 // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so 357 // put it at the end of the list. 358 let AltOrders = [(add (sub G8RC_NOX0, X2), X2), 359 (add (sequence "X%u", 2, 12), 360 (sequence "X%u", 31, 13), X1, FP8, BP8, ZERO8)]; 361 let AltOrderSelect = [{ 362 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx(); 363 }]; 364} 365 366def SPERC : RegisterClass<"PPC", [f64], 64, (add (sequence "S%u", 2, 12), 367 (sequence "S%u", 30, 13), 368 S31, S0, S1)>; 369 370// Allocate volatiles first, then non-volatiles in reverse order. With the SVR4 371// ABI the size of the Floating-point register save area is determined by the 372// allocated non-volatile register with the lowest register number, as FP 373// register N is spilled to offset 8 * (32 - N) below the back chain word of the 374// previous stack frame. By allocating non-volatiles in reverse order we make 375// sure that the Floating-point register save area is always as small as 376// possible because there aren't any unused spill slots. 377def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13), 378 (sequence "F%u", 31, 14))>; 379def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>; 380 381// Floating point pair registers. 382// Note that the type used for this register class is ppcf128. This is not 383// completely correct. However, since we are not pattern matching any 384// instructions for these registers and we are not register allocating or 385// scheduling any of these instructions it should be safe to do this. 386// The reason we didn't use the correct type (Decimal Floating Point) is that 387// at the time of this implementation the correct type was not available. 388def FpRC : 389 RegisterClass<"PPC", [ppcf128], 128, 390 (add Fpair0, Fpair2, Fpair4, Fpair6, Fpair8, Fpair10, Fpair12, 391 Fpair14, Fpair16, Fpair18, Fpair20, Fpair22, Fpair24, 392 Fpair26, Fpair28, Fpair30)> { 393 let Size = 128; 394} 395 396def VRRC : RegisterClass<"PPC", 397 [v16i8,v8i16,v4i32,v2i64,v1i128,v4f32,v2f64, f128], 398 128, 399 (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11, 400 V12, V13, V14, V15, V16, V17, V18, V19, V31, V30, 401 V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>; 402 403// VSX register classes (the allocation order mirrors that of the corresponding 404// subregister classes). 405def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128, 406 (add (sequence "VSL%u", 0, 13), 407 (sequence "VSL%u", 31, 14))>; 408def VSRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128, 409 (add VSLRC, VRRC)>; 410 411// Register classes for the 64-bit "scalar" VSX subregisters. 412def VFRC : RegisterClass<"PPC", [f64], 64, 413 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7, 414 VF8, VF9, VF10, VF11, VF12, VF13, VF14, 415 VF15, VF16, VF17, VF18, VF19, VF31, VF30, 416 VF29, VF28, VF27, VF26, VF25, VF24, VF23, 417 VF22, VF21, VF20)>; 418def VSFRC : RegisterClass<"PPC", [f64], 64, (add F8RC, VFRC)>; 419 420// Allow spilling GPR's into caller-saved VSR's. 421def SPILLTOVSRRC : RegisterClass<"PPC", [i64, f64], 64, (add G8RC, (sub VSFRC, 422 (sequence "VF%u", 31, 20), 423 (sequence "F%u", 31, 14)))>; 424 425// Register class for single precision scalars in VSX registers 426def VSSRC : RegisterClass<"PPC", [f32], 32, (add VSFRC)>; 427 428def CRBITRC : RegisterClass<"PPC", [i1], 32, 429 (add CR2LT, CR2GT, CR2EQ, CR2UN, 430 CR3LT, CR3GT, CR3EQ, CR3UN, 431 CR4LT, CR4GT, CR4EQ, CR4UN, 432 CR5LT, CR5GT, CR5EQ, CR5UN, 433 CR6LT, CR6GT, CR6EQ, CR6UN, 434 CR7LT, CR7GT, CR7EQ, CR7UN, 435 CR1LT, CR1GT, CR1EQ, CR1UN, 436 CR0LT, CR0GT, CR0EQ, CR0UN)> { 437 let Size = 32; 438 let AltOrders = [(sub CRBITRC, CR2LT, CR2GT, CR2EQ, CR2UN, CR3LT, CR3GT, 439 CR3EQ, CR3UN, CR4LT, CR4GT, CR4EQ, CR4UN)]; 440 let AltOrderSelect = [{ 441 return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() && 442 MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled(); 443 }]; 444} 445 446def CRRC : RegisterClass<"PPC", [i32], 32, 447 (add CR0, CR1, CR5, CR6, 448 CR7, CR2, CR3, CR4)> { 449 let AltOrders = [(sub CRRC, CR2, CR3, CR4)]; 450 let AltOrderSelect = [{ 451 return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() && 452 MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled(); 453 }]; 454} 455// The CTR registers are not allocatable because they're used by the 456// decrement-and-branch instructions, and thus need to stay live across 457// multiple basic blocks. 458def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> { 459 let isAllocatable = 0; 460} 461def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> { 462 let isAllocatable = 0; 463} 464 465def LRRC : RegisterClass<"PPC", [i32], 32, (add LR)> { 466 let isAllocatable = 0; 467} 468def LR8RC : RegisterClass<"PPC", [i64], 64, (add LR8)> { 469 let isAllocatable = 0; 470} 471 472def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>; 473def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY, XER)> { 474 let CopyCost = -1; 475} 476 477// Make AllocationOrder as similar as G8RC's to avoid potential spilling. 478// Similarly, we have an AltOrder for 64-bit ELF ABI which r2 is allocated 479// at last. 480def G8pRC : 481 RegisterClass<"PPC", [i128], 128, 482 (add (sequence "G8p%u", 1, 5), 483 (sequence "G8p%u", 14, 7), 484 G8p15, G8p6, G8p0)> { 485 let AltOrders = [(add (sub G8pRC, G8p1), G8p1)]; 486 let AltOrderSelect = [{ 487 return MF.getSubtarget<PPCSubtarget>().is64BitELFABI(); 488 }]; 489 let Size = 128; 490} 491 492include "PPCRegisterInfoMMA.td" 493include "PPCRegisterInfoDMR.td" 494 495//===----------------------------------------------------------------------===// 496// PowerPC Operand Definitions. 497 498// In the default PowerPC assembler syntax, registers are specified simply 499// by number, so they cannot be distinguished from immediate values (without 500// looking at the opcode). This means that the default operand matching logic 501// for the asm parser does not work, and we need to specify custom matchers. 502// Since those can only be specified with RegisterOperand classes and not 503// directly on the RegisterClass, all instructions patterns used by the asm 504// parser need to use a RegisterOperand (instead of a RegisterClass) for 505// all their register operands. 506// For this purpose, we define one RegisterOperand for each RegisterClass, 507// using the same name as the class, just in lower case. 508 509def PPCRegGPRCAsmOperand : AsmOperandClass { 510 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber"; 511} 512def gprc : RegisterOperand<GPRC> { 513 let ParserMatchClass = PPCRegGPRCAsmOperand; 514} 515def PPCRegG8RCAsmOperand : AsmOperandClass { 516 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber"; 517} 518def g8rc : RegisterOperand<G8RC> { 519 let ParserMatchClass = PPCRegG8RCAsmOperand; 520} 521def PPCRegG8pRCAsmOperand : AsmOperandClass { 522 let Name = "RegG8pRC"; let PredicateMethod = "isEvenRegNumber"; 523} 524def g8prc : RegisterOperand<G8pRC> { 525 let ParserMatchClass = PPCRegG8pRCAsmOperand; 526} 527def PPCRegGPRCNoR0AsmOperand : AsmOperandClass { 528 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber"; 529} 530def gprc_nor0 : RegisterOperand<GPRC_NOR0> { 531 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand; 532} 533def PPCRegG8RCNoX0AsmOperand : AsmOperandClass { 534 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber"; 535} 536def g8rc_nox0 : RegisterOperand<G8RC_NOX0> { 537 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand; 538} 539def PPCRegF8RCAsmOperand : AsmOperandClass { 540 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber"; 541} 542def f8rc : RegisterOperand<F8RC> { 543 let ParserMatchClass = PPCRegF8RCAsmOperand; 544} 545def PPCRegF4RCAsmOperand : AsmOperandClass { 546 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber"; 547} 548def f4rc : RegisterOperand<F4RC> { 549 let ParserMatchClass = PPCRegF4RCAsmOperand; 550} 551def PPCRegFpRCAsmOperand : AsmOperandClass { 552 let Name = "RegFpRC"; let PredicateMethod = "isEvenRegNumber"; 553} 554def fpairrc : RegisterOperand<FpRC> { 555 let ParserMatchClass = PPCRegFpRCAsmOperand; 556} 557def PPCRegVRRCAsmOperand : AsmOperandClass { 558 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber"; 559} 560def vrrc : RegisterOperand<VRRC> { 561 let ParserMatchClass = PPCRegVRRCAsmOperand; 562} 563def PPCRegVFRCAsmOperand : AsmOperandClass { 564 let Name = "RegVFRC"; let PredicateMethod = "isRegNumber"; 565} 566def vfrc : RegisterOperand<VFRC> { 567 let ParserMatchClass = PPCRegVFRCAsmOperand; 568} 569def PPCRegCRBITRCAsmOperand : AsmOperandClass { 570 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber"; 571} 572def crbitrc : RegisterOperand<CRBITRC> { 573 let ParserMatchClass = PPCRegCRBITRCAsmOperand; 574} 575def PPCRegCRRCAsmOperand : AsmOperandClass { 576 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber"; 577} 578def crrc : RegisterOperand<CRRC> { 579 let ParserMatchClass = PPCRegCRRCAsmOperand; 580} 581def PPCRegSPERCAsmOperand : AsmOperandClass { 582 let Name = "RegSPERC"; let PredicateMethod = "isRegNumber"; 583} 584def sperc : RegisterOperand<SPERC> { 585 let ParserMatchClass = PPCRegSPERCAsmOperand; 586} 587def PPCRegSPE4RCAsmOperand : AsmOperandClass { 588 let Name = "RegSPE4RC"; let PredicateMethod = "isRegNumber"; 589} 590def spe4rc : RegisterOperand<GPRC> { 591 let ParserMatchClass = PPCRegSPE4RCAsmOperand; 592} 593 594def PPCU1ImmAsmOperand : AsmOperandClass { 595 let Name = "U1Imm"; let PredicateMethod = "isU1Imm"; 596 let RenderMethod = "addImmOperands"; 597} 598def u1imm : Operand<i32> { 599 let PrintMethod = "printU1ImmOperand"; 600 let ParserMatchClass = PPCU1ImmAsmOperand; 601 let DecoderMethod = "decodeUImmOperand<1>"; 602 let OperandType = "OPERAND_IMMEDIATE"; 603} 604 605def PPCU2ImmAsmOperand : AsmOperandClass { 606 let Name = "U2Imm"; let PredicateMethod = "isU2Imm"; 607 let RenderMethod = "addImmOperands"; 608} 609def u2imm : Operand<i32> { 610 let PrintMethod = "printU2ImmOperand"; 611 let ParserMatchClass = PPCU2ImmAsmOperand; 612 let DecoderMethod = "decodeUImmOperand<2>"; 613 let OperandType = "OPERAND_IMMEDIATE"; 614} 615 616def PPCATBitsAsHintAsmOperand : AsmOperandClass { 617 let Name = "ATBitsAsHint"; let PredicateMethod = "isATBitsAsHint"; 618 let RenderMethod = "addImmOperands"; // Irrelevant, predicate always fails. 619} 620def atimm : Operand<i32> { 621 let PrintMethod = "printATBitsAsHint"; 622 let ParserMatchClass = PPCATBitsAsHintAsmOperand; 623 let OperandType = "OPERAND_IMMEDIATE"; 624} 625 626def PPCU3ImmAsmOperand : AsmOperandClass { 627 let Name = "U3Imm"; let PredicateMethod = "isU3Imm"; 628 let RenderMethod = "addImmOperands"; 629} 630def u3imm : Operand<i32> { 631 let PrintMethod = "printU3ImmOperand"; 632 let ParserMatchClass = PPCU3ImmAsmOperand; 633 let DecoderMethod = "decodeUImmOperand<3>"; 634 let OperandType = "OPERAND_IMMEDIATE"; 635} 636 637def PPCU4ImmAsmOperand : AsmOperandClass { 638 let Name = "U4Imm"; let PredicateMethod = "isU4Imm"; 639 let RenderMethod = "addImmOperands"; 640} 641def u4imm : Operand<i32> { 642 let PrintMethod = "printU4ImmOperand"; 643 let ParserMatchClass = PPCU4ImmAsmOperand; 644 let DecoderMethod = "decodeUImmOperand<4>"; 645 let OperandType = "OPERAND_IMMEDIATE"; 646} 647def PPCS5ImmAsmOperand : AsmOperandClass { 648 let Name = "S5Imm"; let PredicateMethod = "isS5Imm"; 649 let RenderMethod = "addImmOperands"; 650} 651def s5imm : Operand<i32> { 652 let PrintMethod = "printS5ImmOperand"; 653 let ParserMatchClass = PPCS5ImmAsmOperand; 654 let DecoderMethod = "decodeSImmOperand<5>"; 655 let OperandType = "OPERAND_IMMEDIATE"; 656} 657def PPCU5ImmAsmOperand : AsmOperandClass { 658 let Name = "U5Imm"; let PredicateMethod = "isU5Imm"; 659 let RenderMethod = "addImmOperands"; 660} 661def u5imm : Operand<i32> { 662 let PrintMethod = "printU5ImmOperand"; 663 let ParserMatchClass = PPCU5ImmAsmOperand; 664 let DecoderMethod = "decodeUImmOperand<5>"; 665 let OperandType = "OPERAND_IMMEDIATE"; 666} 667def PPCU6ImmAsmOperand : AsmOperandClass { 668 let Name = "U6Imm"; let PredicateMethod = "isU6Imm"; 669 let RenderMethod = "addImmOperands"; 670} 671def u6imm : Operand<i32> { 672 let PrintMethod = "printU6ImmOperand"; 673 let ParserMatchClass = PPCU6ImmAsmOperand; 674 let DecoderMethod = "decodeUImmOperand<6>"; 675 let OperandType = "OPERAND_IMMEDIATE"; 676} 677def PPCU7ImmAsmOperand : AsmOperandClass { 678 let Name = "U7Imm"; let PredicateMethod = "isU7Imm"; 679 let RenderMethod = "addImmOperands"; 680} 681def u7imm : Operand<i32> { 682 let PrintMethod = "printU7ImmOperand"; 683 let ParserMatchClass = PPCU7ImmAsmOperand; 684 let DecoderMethod = "decodeUImmOperand<7>"; 685 let OperandType = "OPERAND_IMMEDIATE"; 686} 687def PPCU8ImmAsmOperand : AsmOperandClass { 688 let Name = "U8Imm"; let PredicateMethod = "isU8Imm"; 689 let RenderMethod = "addImmOperands"; 690} 691def u8imm : Operand<i32> { 692 let PrintMethod = "printU8ImmOperand"; 693 let ParserMatchClass = PPCU8ImmAsmOperand; 694 let DecoderMethod = "decodeUImmOperand<8>"; 695 let OperandType = "OPERAND_IMMEDIATE"; 696} 697def PPCU10ImmAsmOperand : AsmOperandClass { 698 let Name = "U10Imm"; let PredicateMethod = "isU10Imm"; 699 let RenderMethod = "addImmOperands"; 700} 701def u10imm : Operand<i32> { 702 let PrintMethod = "printU10ImmOperand"; 703 let ParserMatchClass = PPCU10ImmAsmOperand; 704 let DecoderMethod = "decodeUImmOperand<10>"; 705 let OperandType = "OPERAND_IMMEDIATE"; 706} 707def PPCU12ImmAsmOperand : AsmOperandClass { 708 let Name = "U12Imm"; let PredicateMethod = "isU12Imm"; 709 let RenderMethod = "addImmOperands"; 710} 711def u12imm : Operand<i32> { 712 let PrintMethod = "printU12ImmOperand"; 713 let ParserMatchClass = PPCU12ImmAsmOperand; 714 let DecoderMethod = "decodeUImmOperand<12>"; 715 let OperandType = "OPERAND_IMMEDIATE"; 716} 717def PPCS16ImmAsmOperand : AsmOperandClass { 718 let Name = "S16Imm"; let PredicateMethod = "isS16Imm"; 719 let RenderMethod = "addS16ImmOperands"; 720} 721def s16imm : Operand<i32> { 722 let PrintMethod = "printS16ImmOperand"; 723 let EncoderMethod = "getImm16Encoding"; 724 let ParserMatchClass = PPCS16ImmAsmOperand; 725 let DecoderMethod = "decodeSImmOperand<16>"; 726 let OperandType = "OPERAND_IMMEDIATE"; 727} 728def PPCU16ImmAsmOperand : AsmOperandClass { 729 let Name = "U16Imm"; let PredicateMethod = "isU16Imm"; 730 let RenderMethod = "addU16ImmOperands"; 731} 732def u16imm : Operand<i32> { 733 let PrintMethod = "printU16ImmOperand"; 734 let EncoderMethod = "getImm16Encoding"; 735 let ParserMatchClass = PPCU16ImmAsmOperand; 736 let DecoderMethod = "decodeUImmOperand<16>"; 737 let OperandType = "OPERAND_IMMEDIATE"; 738} 739def PPCS17ImmAsmOperand : AsmOperandClass { 740 let Name = "S17Imm"; let PredicateMethod = "isS17Imm"; 741 let RenderMethod = "addS16ImmOperands"; 742} 743def s17imm : Operand<i32> { 744 // This operand type is used for addis/lis to allow the assembler parser 745 // to accept immediates in the range -65536..65535 for compatibility with 746 // the GNU assembler. The operand is treated as 16-bit otherwise. 747 let PrintMethod = "printS16ImmOperand"; 748 let EncoderMethod = "getImm16Encoding"; 749 let ParserMatchClass = PPCS17ImmAsmOperand; 750 let DecoderMethod = "decodeSImmOperand<16>"; 751 let OperandType = "OPERAND_IMMEDIATE"; 752} 753def PPCS34ImmAsmOperand : AsmOperandClass { 754 let Name = "S34Imm"; 755 let PredicateMethod = "isS34Imm"; 756 let RenderMethod = "addImmOperands"; 757} 758def s34imm : Operand<i64> { 759 let PrintMethod = "printS34ImmOperand"; 760 let EncoderMethod = "getImm34EncodingNoPCRel"; 761 let ParserMatchClass = PPCS34ImmAsmOperand; 762 let DecoderMethod = "decodeSImmOperand<34>"; 763 let OperandType = "OPERAND_IMMEDIATE"; 764} 765def s34imm_pcrel : Operand<i64> { 766 let PrintMethod = "printS34ImmOperand"; 767 let EncoderMethod = "getImm34EncodingPCRel"; 768 let ParserMatchClass = PPCS34ImmAsmOperand; 769 let DecoderMethod = "decodeSImmOperand<34>"; 770 let OperandType = "OPERAND_IMMEDIATE"; 771} 772def PPCImmZeroAsmOperand : AsmOperandClass { 773 let Name = "ImmZero"; 774 let PredicateMethod = "isImmZero"; 775 let RenderMethod = "addImmOperands"; 776} 777def immZero : Operand<i32> { 778 let PrintMethod = "printImmZeroOperand"; 779 let ParserMatchClass = PPCImmZeroAsmOperand; 780 let DecoderMethod = "decodeImmZeroOperand"; 781 let OperandType = "OPERAND_IMMEDIATE"; 782} 783 784def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; 785def fpimm0neg : PatLeaf<(fpimm), [{return N->isExactlyValue(-0.0);}]>; 786 787def PPCDirectBrAsmOperand : AsmOperandClass { 788 let Name = "DirectBr"; let PredicateMethod = "isDirectBr"; 789 let RenderMethod = "addBranchTargetOperands"; 790} 791def directbrtarget : Operand<OtherVT> { 792 let PrintMethod = "printBranchOperand"; 793 let EncoderMethod = "getDirectBrEncoding"; 794 let DecoderMethod = "decodeDirectBrTarget"; 795 let ParserMatchClass = PPCDirectBrAsmOperand; 796 let OperandType = "OPERAND_PCREL"; 797} 798def absdirectbrtarget : Operand<OtherVT> { 799 let PrintMethod = "printAbsBranchOperand"; 800 let EncoderMethod = "getAbsDirectBrEncoding"; 801 let ParserMatchClass = PPCDirectBrAsmOperand; 802} 803def PPCCondBrAsmOperand : AsmOperandClass { 804 let Name = "CondBr"; let PredicateMethod = "isCondBr"; 805 let RenderMethod = "addBranchTargetOperands"; 806} 807def condbrtarget : Operand<OtherVT> { 808 let PrintMethod = "printBranchOperand"; 809 let EncoderMethod = "getCondBrEncoding"; 810 let DecoderMethod = "decodeCondBrTarget"; 811 let ParserMatchClass = PPCCondBrAsmOperand; 812 let OperandType = "OPERAND_PCREL"; 813} 814def abscondbrtarget : Operand<OtherVT> { 815 let PrintMethod = "printAbsBranchOperand"; 816 let EncoderMethod = "getAbsCondBrEncoding"; 817 let ParserMatchClass = PPCCondBrAsmOperand; 818} 819def calltarget : Operand<iPTR> { 820 let PrintMethod = "printBranchOperand"; 821 let EncoderMethod = "getDirectBrEncoding"; 822 let DecoderMethod = "decodeDirectBrTarget"; 823 let ParserMatchClass = PPCDirectBrAsmOperand; 824 let OperandType = "OPERAND_PCREL"; 825} 826def abscalltarget : Operand<iPTR> { 827 let PrintMethod = "printAbsBranchOperand"; 828 let EncoderMethod = "getAbsDirectBrEncoding"; 829 let ParserMatchClass = PPCDirectBrAsmOperand; 830} 831def PPCCRBitMaskOperand : AsmOperandClass { 832 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask"; 833} 834def crbitm: Operand<i8> { 835 let PrintMethod = "printcrbitm"; 836 let EncoderMethod = "get_crbitm_encoding"; 837 let DecoderMethod = "decodeCRBitMOperand"; 838 let ParserMatchClass = PPCCRBitMaskOperand; 839} 840// Address operands 841// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode). 842def PPCRegGxRCNoR0Operand : AsmOperandClass { 843 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; 844} 845def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> { 846 let ParserMatchClass = PPCRegGxRCNoR0Operand; 847} 848 849// New addressing modes with 34 bit immediates. 850def PPCDispRI34Operand : AsmOperandClass { 851 let Name = "DispRI34"; let PredicateMethod = "isS34Imm"; 852 let RenderMethod = "addImmOperands"; 853} 854def dispRI34 : Operand<iPTR> { 855 let ParserMatchClass = PPCDispRI34Operand; 856 let EncoderMethod = "getDispRI34Encoding"; 857 let DecoderMethod = "decodeSImmOperand<34>"; 858} 859def dispRI34_pcrel : Operand<iPTR> { 860 let ParserMatchClass = PPCDispRI34Operand; 861 let EncoderMethod = "getDispRI34PCRelEncoding"; 862 let DecoderMethod = "decodeSImmOperand<34>"; 863} 864def memri34 : Operand<iPTR> { // memri, imm is a 34-bit value. 865 let PrintMethod = "printMemRegImm34"; 866 let MIOperandInfo = (ops dispRI34:$imm, ptr_rc_nor0:$reg); 867} 868// memri, imm is a 34-bit value for pc-relative instructions where 869// base register is set to zero. 870def memri34_pcrel : Operand<iPTR> { // memri, imm is a 34-bit value. 871 let PrintMethod = "printMemRegImm34PCRel"; 872 let MIOperandInfo = (ops dispRI34_pcrel:$imm, immZero:$reg); 873} 874 875// A version of ptr_rc usable with the asm parser. 876def PPCRegGxRCOperand : AsmOperandClass { 877 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber"; 878} 879def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> { 880 let ParserMatchClass = PPCRegGxRCOperand; 881} 882 883def PPCDispRIOperand : AsmOperandClass { 884 let Name = "DispRI"; let PredicateMethod = "isS16Imm"; 885 let RenderMethod = "addS16ImmOperands"; 886} 887def dispRI : Operand<iPTR> { 888 let ParserMatchClass = PPCDispRIOperand; 889 let EncoderMethod = "getDispRIEncoding"; 890} 891def PPCDispRIXOperand : AsmOperandClass { 892 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4"; 893 let RenderMethod = "addS16ImmOperands"; 894} 895def dispRIX : Operand<iPTR> { 896 let ParserMatchClass = PPCDispRIXOperand; 897 let EncoderMethod = "getDispRIXEncoding"; 898 let DecoderMethod = "decodeDispRIXOperand"; 899} 900def PPCDispRIHashOperand : AsmOperandClass { 901 let Name = "DispRIHash"; let PredicateMethod = "isHashImmX8"; 902 let RenderMethod = "addImmOperands"; 903} 904def dispRIHash : Operand<iPTR> { 905 let ParserMatchClass = PPCDispRIHashOperand; 906 let EncoderMethod = "getDispRIHashEncoding"; 907 let DecoderMethod = "decodeDispRIHashOperand"; 908} 909def PPCDispRIX16Operand : AsmOperandClass { 910 let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16"; 911 let RenderMethod = "addS16ImmOperands"; 912} 913def dispRIX16 : Operand<iPTR> { 914 let ParserMatchClass = PPCDispRIX16Operand; 915 let EncoderMethod = "getDispRIX16Encoding"; 916 let DecoderMethod = "decodeDispRIX16Operand"; 917 918} 919def PPCDispSPE8Operand : AsmOperandClass { 920 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8"; 921 let RenderMethod = "addImmOperands"; 922} 923def dispSPE8 : Operand<iPTR> { 924 let ParserMatchClass = PPCDispSPE8Operand; 925 let DecoderMethod = "decodeDispSPE8Operand"; 926 let EncoderMethod = "getDispSPE8Encoding"; 927} 928def PPCDispSPE4Operand : AsmOperandClass { 929 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4"; 930 let RenderMethod = "addImmOperands"; 931} 932def dispSPE4 : Operand<iPTR> { 933 let ParserMatchClass = PPCDispSPE4Operand; 934 let DecoderMethod = "decodeDispSPE4Operand"; 935 let EncoderMethod = "getDispSPE4Encoding"; 936} 937def PPCDispSPE2Operand : AsmOperandClass { 938 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2"; 939 let RenderMethod = "addImmOperands"; 940} 941def dispSPE2 : Operand<iPTR> { 942 let ParserMatchClass = PPCDispSPE2Operand; 943 let DecoderMethod = "decodeDispSPE2Operand"; 944 let EncoderMethod = "getDispSPE2Encoding"; 945} 946 947def memri : Operand<iPTR> { 948 let PrintMethod = "printMemRegImm"; 949 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 950 let OperandType = "OPERAND_MEMORY"; 951} 952def memrr : Operand<iPTR> { 953 let PrintMethod = "printMemRegReg"; 954 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg); 955 let OperandType = "OPERAND_MEMORY"; 956} 957def memrix : Operand<iPTR> { // memri where the imm is 4-aligned. 958 let PrintMethod = "printMemRegImm"; 959 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 960 let OperandType = "OPERAND_MEMORY"; 961} 962def memrihash : Operand<iPTR> { 963 // memrihash 8-aligned for ROP Protection Instructions. 964 let PrintMethod = "printMemRegImmHash"; 965 let MIOperandInfo = (ops dispRIHash:$imm, ptr_rc_nor0:$reg); 966 let OperandType = "OPERAND_MEMORY"; 967} 968def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27} 969 let PrintMethod = "printMemRegImm"; 970 let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); 971 let OperandType = "OPERAND_MEMORY"; 972} 973def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned. 974 let PrintMethod = "printMemRegImm"; 975 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); 976 let OperandType = "OPERAND_MEMORY"; 977} 978def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned. 979 let PrintMethod = "printMemRegImm"; 980 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); 981 let OperandType = "OPERAND_MEMORY"; 982} 983def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned. 984 let PrintMethod = "printMemRegImm"; 985 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); 986 let OperandType = "OPERAND_MEMORY"; 987} 988 989// A single-register address. This is used with the SjLj 990// pseudo-instructions which translates to LD/LWZ. These instructions requires 991// G8RC_NOX0 registers. 992def memr : Operand<iPTR> { 993 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg); 994 let OperandType = "OPERAND_MEMORY"; 995} 996def PPCTLSRegOperand : AsmOperandClass { 997 let Name = "TLSReg"; let PredicateMethod = "isTLSReg"; 998 let RenderMethod = "addTLSRegOperands"; 999} 1000def tlsreg32 : Operand<i32> { 1001 let EncoderMethod = "getTLSRegEncoding"; 1002 let ParserMatchClass = PPCTLSRegOperand; 1003} 1004def tlsgd32 : Operand<i32> {} 1005def tlscall32 : Operand<i32> { 1006 let PrintMethod = "printTLSCall"; 1007 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym); 1008 let EncoderMethod = "getTLSCallEncoding"; 1009} 1010 1011// PowerPC Predicate operand. 1012def pred : Operand<OtherVT> { 1013 let PrintMethod = "printPredicateOperand"; 1014 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg); 1015} 1016 1017def PPCRegVSRCAsmOperand : AsmOperandClass { 1018 let Name = "RegVSRC"; let PredicateMethod = "isVSRegNumber"; 1019} 1020def vsrc : RegisterOperand<VSRC> { 1021 let ParserMatchClass = PPCRegVSRCAsmOperand; 1022} 1023 1024def PPCRegVSFRCAsmOperand : AsmOperandClass { 1025 let Name = "RegVSFRC"; let PredicateMethod = "isVSRegNumber"; 1026} 1027def vsfrc : RegisterOperand<VSFRC> { 1028 let ParserMatchClass = PPCRegVSFRCAsmOperand; 1029} 1030 1031def PPCRegVSSRCAsmOperand : AsmOperandClass { 1032 let Name = "RegVSSRC"; let PredicateMethod = "isVSRegNumber"; 1033} 1034def vssrc : RegisterOperand<VSSRC> { 1035 let ParserMatchClass = PPCRegVSSRCAsmOperand; 1036} 1037 1038def PPCRegSPILLTOVSRRCAsmOperand : AsmOperandClass { 1039 let Name = "RegSPILLTOVSRRC"; let PredicateMethod = "isVSRegNumber"; 1040} 1041 1042def spilltovsrrc : RegisterOperand<SPILLTOVSRRC> { 1043 let ParserMatchClass = PPCRegSPILLTOVSRRCAsmOperand; 1044} 1045 1046def PPCRegVSRpRCAsmOperand : AsmOperandClass { 1047 let Name = "RegVSRpRC"; let PredicateMethod = "isVSRpEvenRegNumber"; 1048} 1049 1050def vsrprc : RegisterOperand<VSRpRC> { 1051 let ParserMatchClass = PPCRegVSRpRCAsmOperand; 1052} 1053 1054def PPCRegVSRpEvenRCAsmOperand : AsmOperandClass { 1055 let Name = "RegVSRpEvenRC"; let PredicateMethod = "isVSRpEvenRegNumber"; 1056} 1057 1058def vsrpevenrc : RegisterOperand<VSRpRC> { 1059 let ParserMatchClass = PPCRegVSRpEvenRCAsmOperand; 1060 let EncoderMethod = "getVSRpEvenEncoding"; 1061 let DecoderMethod = "decodeVSRpEvenOperands"; 1062} 1063 1064def PPCRegACCRCAsmOperand : AsmOperandClass { 1065 let Name = "RegACCRC"; let PredicateMethod = "isACCRegNumber"; 1066} 1067 1068def acc : RegisterOperand<ACCRC> { 1069 let ParserMatchClass = PPCRegACCRCAsmOperand; 1070} 1071 1072def uacc : RegisterOperand<UACCRC> { 1073 let ParserMatchClass = PPCRegACCRCAsmOperand; 1074} 1075 1076// DMR Register Operands 1077def PPCRegDMRROWRCAsmOperand : AsmOperandClass { 1078 let Name = "RegDMRROWRC"; 1079 let PredicateMethod = "isDMRROWRegNumber"; 1080} 1081 1082def dmrrow : RegisterOperand<DMRROWRC> { 1083 let ParserMatchClass = PPCRegDMRROWRCAsmOperand; 1084} 1085 1086def PPCRegDMRROWpRCAsmOperand : AsmOperandClass { 1087 let Name = "RegDMRROWpRC"; 1088 let PredicateMethod = "isDMRROWpRegNumber"; 1089} 1090 1091def dmrrowp : RegisterOperand<DMRROWpRC> { 1092 let ParserMatchClass = PPCRegDMRROWpRCAsmOperand; 1093} 1094 1095def wacc : RegisterOperand<WACCRC> { 1096 let ParserMatchClass = PPCRegACCRCAsmOperand; 1097} 1098 1099def wacc_hi : RegisterOperand<WACC_HIRC> { 1100 let ParserMatchClass = PPCRegACCRCAsmOperand; 1101} 1102 1103def PPCRegDMRRCAsmOperand : AsmOperandClass { 1104 let Name = "RegDMRRC"; 1105 let PredicateMethod = "isDMRRegNumber"; 1106} 1107 1108def dmr : RegisterOperand<DMRRC> { 1109 let ParserMatchClass = PPCRegDMRRCAsmOperand; 1110} 1111 1112def PPCRegDMRpRCAsmOperand : AsmOperandClass { 1113 let Name = "RegDMRpRC"; 1114 let PredicateMethod = "isDMRpRegNumber"; 1115} 1116 1117def dmrp : RegisterOperand<DMRpRC> { 1118 let ParserMatchClass = PPCRegDMRpRCAsmOperand; 1119} 1120