1//===-- PPCScheduleP7.td - PPC P7 Scheduling Definitions ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the SchedModel for the POWER7 processor. 10// 11//===----------------------------------------------------------------------===// 12 13def P7Model : SchedMachineModel { 14 let IssueWidth = 6; // 4 (non-branch) instructions are dispatched per cycle. 15 // Note that the dispatch bundle size is 6 (including 16 // branches), but the total internal issue bandwidth per 17 // cycle (from all queues) is 8. 18 19 let LoadLatency = 3; // Optimistic load latency assuming bypass. 20 // This is overriden by OperandCycles if the 21 // Itineraries are queried instead. 22 let MispredictPenalty = 16; 23 24 let MicroOpBufferSize = 44; 25 26 // Try to make sure we have at least 10 dispatch groups in a loop. 27 let LoopMicroOpBufferSize = 40; 28 29 let CompleteModel = 0; 30 31 let UnsupportedFeatures = [HasSPE, PrefixInstrs, MMA, 32 PairedVectorMemops, IsISA3_0, IsISA2_07, 33 PCRelativeMemops, IsISA3_1, IsISAFuture]; 34} 35 36let SchedModel = P7Model in { 37 def P7_LSU_FXU: ProcResource<4>; 38 def P7_LSU: ProcResource<2> { 39 let Super = P7_LSU_FXU; 40 } 41 def P7_FXU: ProcResource<2> { 42 let Super = P7_LSU_FXU; 43 } 44 // Implemented as two 2-way SIMD operations for double- and single-precision. 45 def P7_FPU: ProcResource<4>; 46 // Scalar binary floating point instructions can only use two FPUs. 47 def P7_ScalarFPU: ProcResource<2> { 48 let Super = P7_FPU; 49 } 50 def P7_VectorFPU: ProcResource<2> { 51 let Super = P7_FPU; 52 } 53 // Executing simple FX, complex FX, permute and 4-way SIMD single-precision FP ops 54 def P7_VMX: ProcResource<1>; 55 def P7_VPM: ProcResource<1> { 56 let Super = P7_VMX; 57 let BufferSize = 1; 58 } 59 def P7_VXS: ProcResource<1> { 60 let Super = P7_VMX; 61 } 62 def P7_DFU: ProcResource<1>; 63 def P7_BRU: ProcResource<1>; 64 def P7_CRU: ProcResource<1>; 65 66 def P7_PORT_LS : ProcResource<2>; 67 def P7_PORT_FX : ProcResource<2>; 68 def P7_PORT_FP : ProcResource<2>; 69 def P7_PORT_BR : ProcResource<1>; 70 def P7_PORT_CR : ProcResource<1>; 71 72 def P7_DISP_LS : SchedWriteRes<[P7_PORT_LS]>; 73 def P7_DISP_FX : SchedWriteRes<[P7_PORT_FX]>; 74 def P7_DISP_FP : SchedWriteRes<[P7_PORT_FP]>; 75 def P7_DISP_BR : SchedWriteRes<[P7_PORT_BR]>; 76 def P7_DISP_CR : SchedWriteRes<[P7_PORT_CR]>; 77 78 def P7_BRU_NONE : SchedWriteRes<[P7_BRU]>; 79 def P7_BRU_3C : SchedWriteRes<[P7_BRU]> { let Latency = 3; } 80 def P7_BRU_4C : SchedWriteRes<[P7_BRU]> { let Latency = 4; } 81 def P7_CRU_NONE : SchedWriteRes<[P7_CRU]>; 82 def P7_CRU_3C : SchedWriteRes<[P7_CRU]> { let Latency = 3; } 83 def P7_CRU_6C : SchedWriteRes<[P7_CRU]> { let Latency = 6; } 84 def P7_LSU_NONE : SchedWriteRes<[P7_LSU]>; 85 def P7_LSU_2C : SchedWriteRes<[P7_LSU]> { let Latency = 2; } 86 def P7_LSU_3C : SchedWriteRes<[P7_LSU]> { let Latency = 3; } 87 def P7_LSU_4C : SchedWriteRes<[P7_LSU]> { let Latency = 4; } 88 def P7_FXU_NONE : SchedWriteRes<[P7_FXU]>; 89 def P7_FXU_2C : SchedWriteRes<[P7_FXU]> { let Latency = 2; } 90 def P7_FXU_3C : SchedWriteRes<[P7_FXU]> { let Latency = 3; } 91 def P7_FXU_4C : SchedWriteRes<[P7_FXU]> { let Latency = 4; } 92 def P7_FXU_5C : SchedWriteRes<[P7_FXU]> { let Latency = 5; } 93 def P7_FXU_38C : SchedWriteRes<[P7_FXU]> { let Latency = 38; } 94 def P7_FXU_69C : SchedWriteRes<[P7_FXU]> { let Latency = 69; } 95 def P7_LSU_FXU_2C : SchedWriteRes<[P7_LSU_FXU]> { let Latency = 2; } 96 def P7_FPU_NONE : SchedWriteRes<[P7_FPU]>; 97 def P7_VectorFPU_6C : SchedWriteRes<[P7_VectorFPU]> { let Latency = 6; } 98 def P7_VectorFPU_25C : SchedWriteRes<[P7_VectorFPU]> { let Latency = 25; } 99 def P7_VectorFPU_30C : SchedWriteRes<[P7_VectorFPU]> { let Latency = 30; } 100 def P7_VectorFPU_31C : SchedWriteRes<[P7_VectorFPU]> { let Latency = 31; } 101 def P7_VectorFPU_42C : SchedWriteRes<[P7_VectorFPU]> { let Latency = 42; } 102 def P7_ScalarFPU_6C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 6; } 103 def P7_ScalarFPU_8C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 8; } 104 def P7_ScalarFPU_27C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 27; } 105 def P7_ScalarFPU_31C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 31; } 106 def P7_ScalarFPU_32C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 32; } 107 def P7_ScalarFPU_33C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 33; } 108 def P7_ScalarFPU_42C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 42; } 109 def P7_ScalarFPU_44C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 44; } 110 def P7_VXS_2C : SchedWriteRes<[P7_VXS]> { let Latency = 2; } 111 def P7_VPM_3C : SchedWriteRes<[P7_VPM]> { let Latency = 3; } 112 113 // Instruction of BRU pipeline 114 115 def : InstRW<[P7_BRU_NONE, P7_DISP_BR], 116 (instregex "^B(L)?(A)?(8)?(_NOP|_NOTOC)?(_TLS|_RM)?(_)?$")>; 117 118 def : InstRW<[P7_BRU_3C, P7_DISP_BR], (instrs 119 BDZLRLp, BDZLRm, BDZLRp, BDZLm, BDZLp, BDZm, BDZp, 120 BDNZ, BDNZ8, BDNZA, BDNZAm, BDNZAp, BDNZL, BDNZLA, BDNZLAm, BDNZLAp, BDNZLR, 121 BDNZLR8, BDNZLRL, BDNZLRLm, BDNZLRLp, BDNZLRm, BDNZLRp, BDNZLm, BDNZLp, 122 BDNZm, BDNZp, BDZ, BDZ8, BDZA, BDZAm, BDZAp, BDZL, BDZLA, BDZLAm, BDZLAp, 123 BDZLR, BDZLR8, BDZLRL, BDZLRLm, BLR, BLR8, BLRL, BCL, BCLR, BCLRL, BCLRLn, 124 BCLRn, BCLalways, BCLn, BCTR, BCTR8, BCTRL, BCTRL8, BCTRL8_LDinto_toc, 125 BCTRL8_LDinto_toc_RM, BCTRL8_RM, BCTRL_LWZinto_toc, BCTRL_LWZinto_toc_RM, 126 BCTRL_RM, BCn, BC, BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, 127 BCCLA, BCCLR, BCCLRL, BCCTR, BCCTR8, BCCTR8n, BCCTRL, BCCTRL8, 128 BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCCLRL, BCCTR, 129 BCCTR8, BCCTR8n, BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, BCCTRn, gBC, gBCA, 130 gBCAat, gBCCTR, gBCCTRL, gBCL, gBCLA, gBCLAat, gBCLR, gBCLRL, gBCLat, gBCat, 131 MFCTR, MFCTR8, MFLR, MFLR8 132 )>; 133 134 def : InstRW<[P7_BRU_4C], (instrs MTLR, MTLR8, MTCTR, MTCTR8, MTCTR8loop, MTCTRloop)>; 135 136 // Instructions of CRU pipeline 137 138 def : InstRW<[P7_CRU_NONE], (instrs MFCR, MFCR8)>; 139 def : InstRW<[P7_CRU_3C], (instrs MCRF)>; 140 def : InstRW<[P7_CRU_6C, P7_DISP_CR], (instrs 141 CR6SET, CR6UNSET, CRSET, CRUNSET, 142 CRAND, CRANDC, CREQV, CRNAND, CRNOR, CRNOT, CROR, CRORC 143 )>; 144 145 // Instructions of LSU and FXU pipelines 146 147 def : InstRW<[P7_LSU_NONE, P7_DISP_LS], (instrs LMW, LWARX, LWARXL, LDARX, LDARXL)>; 148 def : InstRW<[P7_LSU_2C, P7_DISP_LS], (instrs LHBRX, LHBRX8, LWBRX, LWBRX8)>; 149 def : InstRW<[P7_LSU_3C], (instrs MFSR, MFSRIN)>; 150 151 def : InstRW<[P7_LSU_3C, P7_DISP_LS], (instrs 152 LFS, LFSX, LFSXTLS, LFSXTLS_, LFD, LFDX, LFDXTLS, LFDXTLS_, LXSDX, LXVD2X, 153 LXVW4X, LXVDSX 154 )>; 155 156 def : InstRW<[P7_LSU_3C, P7_FXU_3C, P7_DISP_LS], (instrs 157 LFSU, LFSUX, LFDU, LFDUX)>; 158 159 def : InstRW<[P7_LSU_NONE, P7_FPU_NONE, P7_DISP_LS], (instrs 160 STXSDX, STXVD2X, STXVW4X)>; 161 162 def : InstRW<[P7_LSU_4C, P7_FXU_4C, P7_DISP_LS], (instrs 163 LBARX, LBZCIX, LDBRX, LDCIX, LFIWAX, LFIWZX, LHARX, LHZCIX, LSWI, LVEBX, 164 LVEHX, LVEWX, LVSL, LVSR, LVX, LVXL, LWZCIX, 165 STFD, STFDU, STFDUX, STFDX, STFIWX, STFS, STFSU, STFSUX, STFSX, 166 STHCIX, STSWI, STVEBX, STVEHX, STVEWX, STVX, STVXL, STWCIX, 167 LHA, LHA8, LHAX, LHAX8, LWA, LWAX, LWAX_32, LWA_32, LHAU, LHAU8, 168 LHAUX, LHAUX8, LWAUX 169 )>; 170 171 def : InstRW<[P7_LSU_NONE, P7_FXU_NONE, P7_DISP_LS], (instrs 172 STB, STB8, STH, STH8, STW, STW8, STD, STBX, STBX8, STHX, STHX8, STWX, 173 STWX8, STDX, STHBRX, STWBRX, STMW, STWCX, STDCX, STDU, STHU, STHU8, 174 STBU, STBU8, STWU, STWU8, STDUX, STWUX, STWUX8, STHUX, STHUX8, STBUX, STBUX8 175 )>; 176 177 def : InstRW<[P7_LSU_2C, P7_FXU_2C, P7_DISP_LS], (instrs 178 LWZU, LWZU8, LHZU, LHZU8, LBZU, LBZU8, LDU, 179 LWZUX, LWZUX8, LHZUX, LHZUX8, LBZUX, LBZUX8, LDUX 180 )>; 181 182 def : InstRW<[P7_LSU_FXU_2C, P7_DISP_FX], (instrs 183 (instregex "^(ADD|L)I(S)?(8)?$"), 184 (instregex "^(ADD|SUBF)(4|8)(TLS)?(_)?(_rec)?$"), 185 (instregex "^(X)?ORI(S)?(8)?$"), 186 (instregex "^(X)OR(8)?(_rec)?$"), 187 ADDIC, ADDIC8, SUBFIC, SUBFIC8, SUBFZE, SUBFZE8, 188 ADDE, ADDE8, ADDME, ADDME8, SUBFME, SUBFME8, 189 NEG, NEG8, NEG8_rec, NEG_rec, NEG8O, NEGO, 190 ANDI_rec, ANDIS_rec, AND, AND8, AND_rec, AND8_rec, 191 NAND, NAND8, NAND_rec, NAND8_rec, NOR, NOR8, NOR_rec, NOR8_rec, 192 EQV, EQV8, EQV_rec, EQV8_rec, ANDC, ANDC8, ANDC_rec, ANDC8_rec, 193 ORC, ORC8, ORC_rec, ORC8_rec 194 )>; 195 196 def : InstRW<[P7_FXU_2C, P7_DISP_FX], (instrs 197 CMPD, CMPDI, CMPLD, CMPLDI, CMPLW, CMPLWI, CMPW, CMPWI, 198 EXTSB8_32_64, EXTSB8_rec, EXTSH8_32_64, EXTSH8_rec, EXTSW_32, 199 EXTSW_32_64, EXTSW_32_64_rec, POPCNTB, POPCNTB8, POPCNTD, POPCNTW, 200 ADDPCIS, ANDI8_rec, ANDIS8_rec, SUBFUS, SUBFUS_rec, 201 ADD4O, ADD8O, ADDC, ADDC8, SUBFO, SUBF8O, SUBFC, SUBFC8, 202 ADDIC_rec, ADDE8_rec, ADDE_rec, SUBFE8_rec, SUBFE_rec, 203 ADDME8_rec, ADDME_rec, SUBFME8_rec, SUBFME_rec, ADDZE8_rec, ADDZE_rec, 204 SUBFZE_rec, SUBFZE8_rec, ADD8O_rec, SUBFO_rec, SUBF8O_rec, ADD4O_rec, 205 ADD8O_rec, SUBF8O_rec, SUBFO_rec, ADDE8O, ADDEO, SUBFE8O, SUBFEO, ADDME8O, 206 ADDMEO, SUBFME8O, SUBFMEO, ADDZE8O, ADDZEO, SUBFZE8O, SUBFZEO, NEG8O_rec, 207 NEGO_rec, ADDEO, ADDE8O, SUBFEO, SUBFE8O, ADDMEO, SUBFMEO, SUBFME8O, ADDME8O, 208 ADDZEO, ADDZE8O, SUBFZEO, SUBFZE8O, NEG8O_rec, NEGO_rec, 209 ADDE8O_rec, ADDEO_rec, ADDMEO_rec, ADDME8O_rec, SUBFMEO_rec, SUBFME8O_rec, 210 ADDZEO_rec, ADDZE8O_rec, SUBFZEO_rec, SUBFZE8O_rec, 211 ADDC8_rec, ADDC_rec, ADDCO, ADDCO_rec, ADDC8O, ADDC8O_rec, 212 SUBFC8_rec, SUBFC_rec, SUBFCO, SUBFC8O, SUBFCO_rec, SUBFC8O_rec, 213 EXTSB, EXTSB8, EXTSB_rec, EXTSH, EXTSH8, EXTSH_rec, EXTSW, EXTSW_rec, 214 RLDICL, RLDICL_rec, RLDICR, RLDICR_rec, RLDIC, RLDIC_rec, 215 RLWINM, RLWINM8, RLWINM_rec, RLDCL, RLDCL_rec, RLDCR, RLDCR_rec, 216 RLWNM, RLWNM8, RLWNM_rec, RLDIMI, RLDIMI_rec, 217 RLDICL_32, RLDICL_32_64, RLDICL_32_rec, RLDICR_32, RLWINM8_rec, RLWNM8_rec, 218 SLD, SLD_rec, SLW, SLW8, SLW_rec, SLW8_rec, SRD, SRD_rec, SRW, SRW8, SRW_rec, 219 SRW8_rec, SRADI, SRADI_rec, SRAWI, SRAWI_rec, SRAD, SRAD_rec, SRAW, SRAW_rec, 220 SRADI_32, SUBFE, SUBFE8, SUBFE8O_rec, SUBFEO_rec 221 )>; 222 223 def : InstRW<[P7_FXU_3C, P7_DISP_FX], (instregex "^CNT(L|T)Z(D|W)(8)?(M)?(_rec)?$")>; 224 225 def : InstRW<[P7_FXU_5C, P7_DISP_FX], (instrs 226 MULLI, MULLI8, MULLW, MULHW, MULHWU, MULLD, MULHD, MULHDU, MULLWO, MULLDO, 227 MULLW_rec, MULLD_rec, MULHD_rec, MULHW_rec, MULHDU_rec, MULHWU_rec, MULLWO_rec, 228 MULLDO_rec 229 )>; 230 231 def : InstRW<[P7_FXU_38C, P7_DISP_FX], (instrs 232 DIVDE, DIVDEO, DIVDEO_rec, DIVDEU, DIVDEUO, DIVDEUO_rec, DIVDEU_rec, DIVDE_rec, 233 DIVWE, DIVWEO, DIVWEO_rec, DIVWEU, DIVWEUO, DIVWEUO_rec, DIVWEU_rec, DIVWE_rec, 234 DIVW, DIVWU, DIVWU_rec, DIVWO, DIVWO_rec, DIVWUO, DIVWUO_rec, DIVW_rec 235 )>; 236 237 def : InstRW<[P7_FXU_69C, P7_DISP_FX], (instrs 238 DIVD, DIVDU, DIVDO, DIVDO_rec, DIVDUO, DIVDUO_rec, DIVDU_rec, DIVD_rec)>; 239 240 // Instructions of FPU and VMX pipeline 241 242 def : InstRW<[P7_ScalarFPU_6C, P7_DISP_FP], (instrs 243 (instregex "^F(N)?(M)?(R|ADD|SUB|ABS|NEG|NABS|UL)(D|S)?(_rec)?$"), 244 (instregex "^FC(T|F)I(D|W)(U)?(S)?(Z)?(_rec)?$"), 245 (instregex "^XS(N)?M(SUB|ADD)(A|M)(D|S)P$"), 246 (instregex "^XS(NEG|ABS|NABS|ADD|SUB|MUL)(D|S)P(s)?$"), 247 FRE, FRES_rec, FRE_rec, FRSP_rec, FTDIV, FTSQRT, 248 FRSP, FRES, FRSQRTE, FRSQRTES, FRSQRTES_rec, FRSQRTE_rec, FSELD, FSELS, 249 FSELD_rec, FSELS_rec, FCPSGND, FCPSGND_rec, FCPSGNS, FCPSGNS_rec, 250 FRIMD, FRIMD_rec, FRIMS, FRIMS_rec, FRIND, FRIND_rec, FRINS, FRINS_rec, 251 FRIPD, FRIPD_rec, FRIPS, FRIPS_rec, FRIZD, FRIZD_rec, FRIZS, FRIZS_rec, 252 XSCPSGNDP, XSCVDPSP, XSCVDPSXDS, XSCVDPSXDSs, XSCVDPSXWS, XSCVDPSXWSs, 253 XSCVDPUXDS, XSCVDPUXDSs, XSCVDPUXWS, XSCVDPUXWSs, XSCVSPDP, XSCVSXDDP, 254 XSCVUXDDP, XSMAXDP, XSMINDP, XSRDPI, XSRDPIC, XSRDPIM, XSRDPIP, XSRDPIZ, 255 XSREDP, XSRSQRTEDP, XSTDIVDP, XSTSQRTDP, XSCMPODP, XSCMPUDP 256 )>; 257 258 def : InstRW<[P7_VectorFPU_6C, P7_DISP_FP], (instrs 259 (instregex "^XV(N)?(M)?(ADD|SUB)(A|M)?(D|S)P$"), 260 (instregex "^XV(MAX|MIN|MUL|NEG|ABS|ADD|NABS)(D|S)P$"), 261 XVCMPEQDP, XVCMPEQDP_rec, XVCMPGEDP, XVCMPGEDP_rec, XVCMPGTDP, XVCMPGTDP_rec, 262 XVCPSGNDP, XVCVDPSXDS, XVCVDPSXWS, XVCVDPUXDS, XVCVDPUXWS, XVCVSPSXDS, 263 XVCVSPSXWS, XVCVSPUXDS, XVCVSPUXWS, XVCVSXDDP, XVCVSXWDP, XVCVUXDDP, 264 XVCVUXWDP, XVRDPI, XVRDPIC, XVRDPIM, XVRDPIP, XVRDPIZ, XVREDP, 265 XVRSPI, XVRSPIC, XVRSPIM, XVRSPIP, XVRSPIZ, XVRSQRTEDP, XVTDIVDP, 266 XVTSQRTDP 267 )>; 268 269 // TODO: Altivec instructions are not listed in Book IV. 270 def : InstRW<[P7_VPM_3C, P7_DISP_FP], (instrs 271 (instregex "^VPK(S|U)(H|W)(S|U)(S|M)$"), 272 (instregex "^VUPK(H|L)(S|P)(X|B|H)$"), 273 VPERM, XXMRGHW, XXMRGLW, XXPERMDI, XXPERMDIs, XXSLDWI, XXSLDWIs, 274 VSPLTB, VSPLTBs, VSPLTH, VSPLTHs, VSPLTISB, VSPLTISH, VSPLTISW, VSPLTW, 275 XXSPLTW, XXSPLTWs, VSEL, XXSEL, VPKPX 276 )>; 277 278 def : InstRW<[P7_VXS_2C, P7_DISP_FP], (instrs 279 (instregex "^VADD(U|S)(B|H|W)(S|M)$"), 280 (instregex "^V(MAX|MIN)(S|U)(B|H|W)$"), 281 (instregex "^V(MRG)(L|H)(B|H|W)$"), 282 XXLORf, XXLXORdpz, XXLXORspz, XXLXORz, XVRSQRTESP, XVRESP, 283 XVTDIVSP, XVTSQRTSP, XVCMPEQSP, XVCMPEQSP_rec, XVCMPGESP, XVCMPGESP_rec, 284 XVCMPGTSP, XVCMPGTSP_rec, XVCVSXDSP, XVCVSXWSP, XVCVUXDSP, XVCVUXWSP, 285 XVCPSGNSP, XVCVDPSP, VADDCUW, VADDFP, VAND, VANDC, VAVGSB, VAVGSH, 286 VAVGSW, VAVGUB, VAVGUH, VAVGUW, VCFSX, VCFUX, VCMPBFP, VCMPBFP_rec, 287 VCMPEQFP, VCMPEQFP_rec, VCMPEQUB, VCMPEQUB_rec, VCMPEQUH, VCMPEQUH_rec, 288 VCMPEQUW, VCMPEQUW_rec, VCMPGEFP, VCMPGEFP_rec, VCMPGTFP, VCMPGTFP_rec, 289 VCMPGTSB, VCMPGTSB_rec, VCMPGTSH, VCMPGTSH_rec, VCMPGTSW, VCMPGTSW_rec, 290 VCMPGTUB, VCMPGTUB_rec, VCMPGTUH, VCMPGTUH_rec, VCMPGTUW, VCMPGTUW_rec, 291 VCTSXS, VCTUXS, VEXPTEFP, VLOGEFP, VNOR, VOR, 292 VMADDFP, VMHADDSHS, VMHRADDSHS, VMLADDUHM, VNMSUBFP, VMAXFP, VMINFP, 293 VMSUMMBM, VMSUMSHM, VMSUMSHS, VMSUMUBM, VMSUMUDM, VMSUMUHM, VMSUMUHS, 294 VMULESB, VMULESH, VMULEUB, VMULEUH, VMULOSB, VMULOSH, VMULOUB, VMULOUH, 295 VREFP, VRFIM, VRFIN, VRFIP, VRFIZ, VRLB, VRLH, VRLW, VRSQRTEFP, 296 VSR, VSRAB, VSRAH, VSRAW, VSRB, VSRH, VSRO, VSRW, VSUBCUW, VSL, VSLB, 297 VSLDOI, VSLH, VSLO, VSLW, VSUBFP, VSUBSBS, VSUBSHS, VSUBSWS, VSUBUBM, 298 VSUBUBS, VSUBUHM, VSUBUHS, VSUBUWM, VSUBUWS, VSUM2SWS, VSUM4SBS, VSUM4SHS, 299 VSUM4UBS, VSUMSWS, VXOR, XXLAND, XXLANDC, XXLNOR, XXLOR, XXLXOR 300 )>; 301 302 def : InstRW<[P7_ScalarFPU_8C, P7_DISP_FP], 303 (instrs FCMPOD, FCMPOS, FCMPUD, FCMPUS)>; 304 def : InstRW<[P7_ScalarFPU_27C, P7_DISP_FP], (instrs FDIVS, FDIVS_rec)>; 305 def : InstRW<[P7_ScalarFPU_31C, P7_DISP_FP], (instrs XSDIVDP)>; 306 def : InstRW<[P7_ScalarFPU_32C, P7_DISP_FP], (instrs FSQRTS, XSSQRTSP, FSQRTS_rec)>; 307 def : InstRW<[P7_ScalarFPU_33C, P7_DISP_FP], (instrs FDIV, FDIV_rec)>; 308 def : InstRW<[P7_ScalarFPU_42C, P7_DISP_FP], (instrs XSSQRTDP)>; 309 def : InstRW<[P7_ScalarFPU_44C, P7_DISP_FP], (instrs FSQRT, FSQRT_rec)>; 310 311 def : InstRW<[P7_VectorFPU_25C, P7_DISP_FP], (instrs XVDIVSP)>; 312 def : InstRW<[P7_VectorFPU_30C, P7_DISP_FP], (instrs XVSQRTSP)>; 313 def : InstRW<[P7_VectorFPU_31C, P7_DISP_FP], (instrs XVDIVDP)>; 314 def : InstRW<[P7_VectorFPU_42C, P7_DISP_FP], (instrs XVSQRTDP)>; 315} 316