10b57cec5SDimitry Andric//===-- PPCScheduleP8.td - PPC P8 Scheduling Definitions ---*- tablegen -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 95f757f3fSDimitry Andric// This file defines the SchedModel for the POWER8 processor. 100b57cec5SDimitry Andric// 110b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andricdef P8Model : SchedMachineModel { 145f757f3fSDimitry Andric let IssueWidth = 8; 155f757f3fSDimitry Andric let LoadLatency = 3; 160b57cec5SDimitry Andric let MispredictPenalty = 16; 170b57cec5SDimitry Andric let LoopMicroOpBufferSize = 60; 185f757f3fSDimitry Andric let MicroOpBufferSize = 64; 195f757f3fSDimitry Andric // TODO: Due to limitation of instruction definitions, non-P8 instructions 205f757f3fSDimitry Andric // are required to be listed here. Change this after it got fixed. 210b57cec5SDimitry Andric let CompleteModel = 0; 225f757f3fSDimitry Andric let UnsupportedFeatures = [HasSPE, PrefixInstrs, MMA, 235f757f3fSDimitry Andric PairedVectorMemops, PCRelativeMemops, 245f757f3fSDimitry Andric IsISA3_0, IsISA3_1, IsISAFuture]; 250b57cec5SDimitry Andric} 260b57cec5SDimitry Andric 275f757f3fSDimitry Andriclet SchedModel = P8Model in { 285f757f3fSDimitry Andric // Power8 Pipeline Units: 295f757f3fSDimitry Andric 305f757f3fSDimitry Andric def P8_LU_LS_FX : ProcResource<6>; 315f757f3fSDimitry Andric def P8_LU_LS : ProcResource<4> { let Super = P8_LU_LS_FX; } 325f757f3fSDimitry Andric def P8_LS : ProcResource<2> { let Super = P8_LU_LS; } 335f757f3fSDimitry Andric def P8_LU : ProcResource<2> { let Super = P8_LU_LS; } 345f757f3fSDimitry Andric def P8_FX : ProcResource<2> { let Super = P8_LU_LS_FX; } 355f757f3fSDimitry Andric def P8_DFU : ProcResource<1>; 365f757f3fSDimitry Andric def P8_BR : ProcResource<1> { let BufferSize = 16; } 375f757f3fSDimitry Andric def P8_CY : ProcResource<1>; 385f757f3fSDimitry Andric def P8_CRL : ProcResource<1>; 395f757f3fSDimitry Andric def P8_VMX : ProcResource<2>; 405f757f3fSDimitry Andric def P8_PM : ProcResource<2> { 415f757f3fSDimitry Andric // This is workaround for scheduler to respect latency of long permute chain. 425f757f3fSDimitry Andric let BufferSize = 1; 435f757f3fSDimitry Andric let Super = P8_VMX; 445f757f3fSDimitry Andric } 455f757f3fSDimitry Andric def P8_XS : ProcResource<2> { let Super = P8_VMX; } 465f757f3fSDimitry Andric def P8_VX : ProcResource<2> { let Super = P8_VMX; } 475f757f3fSDimitry Andric def P8_FPU : ProcResource<4>; 485f757f3fSDimitry Andric // Units for scalar, 2xDouble and 4xSingle 495f757f3fSDimitry Andric def P8_FP_Scal : ProcResource<2> { let Super = P8_FPU; } 505f757f3fSDimitry Andric def P8_FP_2x64 : ProcResource<2> { let Super = P8_FPU; } 515f757f3fSDimitry Andric def P8_FP_4x32 : ProcResource<2> { let Super = P8_FPU; } 525f757f3fSDimitry Andric 535f757f3fSDimitry Andric // Power8 Dispatch Ports: 545f757f3fSDimitry Andric // Two ports to do loads or fixed-point operations. 555f757f3fSDimitry Andric // Two ports to do stores, fixed-point loads, or fixed-point operations. 565f757f3fSDimitry Andric // Two ports for fixed-point operations. 575f757f3fSDimitry Andric // Two issue ports shared by 2 DFP/2 VSX/2 VMX/1 CY/1 DFP operations. 585f757f3fSDimitry Andric // One for branch operations. 595f757f3fSDimitry Andric // One for condition register operations. 605f757f3fSDimitry Andric 615f757f3fSDimitry Andric // TODO: Model dispatch of cracked instructions. 625f757f3fSDimitry Andric 635f757f3fSDimitry Andric // Six ports in total are available for fixed-point operations. 645f757f3fSDimitry Andric def P8_PORT_ALLFX : ProcResource<6>; 655f757f3fSDimitry Andric // Four ports in total are available for fixed-point load operations. 665f757f3fSDimitry Andric def P8_PORT_FXLD : ProcResource<4> { let Super = P8_PORT_ALLFX; } 675f757f3fSDimitry Andric // Two ports to do loads or fixed-point operations. 685f757f3fSDimitry Andric def P8_PORT_LD_FX : ProcResource<2> { let Super = P8_PORT_FXLD; } 695f757f3fSDimitry Andric // Two ports to do stores, fixed-point loads, or fixed-point operations. 705f757f3fSDimitry Andric def P8_PORT_ST_FXLD_FX : ProcResource<2> { let Super = P8_PORT_FXLD; } 715f757f3fSDimitry Andric // Two issue ports shared by two floating-point, two VSX, two VMX, one crypto, 725f757f3fSDimitry Andric // and one DFP operations. 735f757f3fSDimitry Andric def P8_PORT_VMX_FP : ProcResource<2>; 745f757f3fSDimitry Andric // One port for branch operation. 755f757f3fSDimitry Andric def P8_PORT_BR : ProcResource<1>; 765f757f3fSDimitry Andric // One port for condition register operation. 775f757f3fSDimitry Andric def P8_PORT_CR : ProcResource<1>; 785f757f3fSDimitry Andric 795f757f3fSDimitry Andric def P8_ISSUE_FX : SchedWriteRes<[P8_PORT_ALLFX]>; 805f757f3fSDimitry Andric def P8_ISSUE_FXLD : SchedWriteRes<[P8_PORT_FXLD]>; 815f757f3fSDimitry Andric def P8_ISSUE_LD : SchedWriteRes<[P8_PORT_LD_FX]>; 825f757f3fSDimitry Andric def P8_ISSUE_ST : SchedWriteRes<[P8_PORT_ST_FXLD_FX]>; 835f757f3fSDimitry Andric def P8_ISSUE_VSX : SchedWriteRes<[P8_PORT_VMX_FP]>; 845f757f3fSDimitry Andric def P8_ISSUE_BR : SchedWriteRes<[P8_PORT_BR]>; 855f757f3fSDimitry Andric def P8_ISSUE_CR : SchedWriteRes<[P8_PORT_CR]>; 865f757f3fSDimitry Andric 875f757f3fSDimitry Andric // Power8 Instruction Latency & Port Groups: 885f757f3fSDimitry Andric 895f757f3fSDimitry Andric def P8_LS_LU_NONE : SchedWriteRes<[P8_LU, P8_LS]>; 905f757f3fSDimitry Andric def P8_LS_FP_NONE : SchedWriteRes<[P8_LS, P8_FPU]>; 915f757f3fSDimitry Andric def P8_LU_or_LS_3C : SchedWriteRes<[P8_LU_LS]> { let Latency = 3; } 925f757f3fSDimitry Andric def P8_LS_FX_3C : SchedWriteRes<[P8_LS, P8_FX]> { let Latency = 3; } 935f757f3fSDimitry Andric def P8_LU_or_LS_or_FX_2C : SchedWriteRes<[P8_LU_LS_FX]> { let Latency = 2; } 945f757f3fSDimitry Andric def P8_LU_or_LS_FX_3C : SchedWriteRes<[P8_LU_LS, P8_FX]> { let Latency = 3; } 955f757f3fSDimitry Andric def P8_FX_NONE : SchedWriteRes<[P8_FX]>; 965f757f3fSDimitry Andric def P8_FX_1C : SchedWriteRes<[P8_FX]> { let Latency = 1; } 975f757f3fSDimitry Andric def P8_FX_2C : SchedWriteRes<[P8_FX]> { let Latency = 2; } 985f757f3fSDimitry Andric def P8_FX_3C : SchedWriteRes<[P8_FX]> { let Latency = 3; } 995f757f3fSDimitry Andric def P8_FX_5C : SchedWriteRes<[P8_FX]> { let Latency = 5; } 1005f757f3fSDimitry Andric def P8_FX_10C : SchedWriteRes<[P8_FX]> { let Latency = 10; } 1015f757f3fSDimitry Andric def P8_FX_23C : SchedWriteRes<[P8_FX]> { let Latency = 23; } 1025f757f3fSDimitry Andric def P8_FX_15C : SchedWriteRes<[P8_FX]> { let Latency = 15; } 1035f757f3fSDimitry Andric def P8_FX_41C : SchedWriteRes<[P8_FX]> { let Latency = 41; } 1045f757f3fSDimitry Andric def P8_BR_2C : SchedWriteRes<[P8_BR]> { let Latency = 2; } 1055f757f3fSDimitry Andric def P8_CR_NONE : SchedWriteRes<[P8_CRL]>; 1065f757f3fSDimitry Andric def P8_CR_3C : SchedWriteRes<[P8_CRL]> { let Latency = 3; } 1075f757f3fSDimitry Andric def P8_CR_5C : SchedWriteRes<[P8_CRL]> { let Latency = 5; } 1085f757f3fSDimitry Andric def P8_LU_5C : SchedWriteRes<[P8_LU]> { let Latency = 5; } 1095f757f3fSDimitry Andric def P8_LU_FX_5C : SchedWriteRes<[P8_LU, P8_FX]> { let Latency = 5; } 1105f757f3fSDimitry Andric def P8_LS_FP_FX_2C : SchedWriteRes<[P8_LS, P8_FPU, P8_FX]> { let Latency = 2; } 1115f757f3fSDimitry Andric def P8_LS_FP_FX_3C : SchedWriteRes<[P8_LS, P8_FPU, P8_FX]> { let Latency = 3; } 1125f757f3fSDimitry Andric def P8_LS_3C : SchedWriteRes<[P8_LS]> { let Latency = 3; } 1135f757f3fSDimitry Andric def P8_FP_3C : SchedWriteRes<[P8_FPU]> { let Latency = 3; } 1145f757f3fSDimitry Andric def P8_FP_Scal_6C : SchedWriteRes<[P8_FP_Scal]> { let Latency = 6; } 1155f757f3fSDimitry Andric def P8_FP_4x32_6C : SchedWriteRes<[P8_FP_4x32]> { let Latency = 6; } 1165f757f3fSDimitry Andric def P8_FP_2x64_6C : SchedWriteRes<[P8_FP_2x64]> { let Latency = 6; } 1175f757f3fSDimitry Andric def P8_FP_26C : SchedWriteRes<[P8_FP_Scal]> { let Latency = 26; } 1185f757f3fSDimitry Andric def P8_FP_28C : SchedWriteRes<[P8_FP_4x32]> { let Latency = 28; } 1195f757f3fSDimitry Andric def P8_FP_31C : SchedWriteRes<[P8_FP_Scal]> { let Latency = 31; } 1205f757f3fSDimitry Andric def P8_FP_Scal_32C : SchedWriteRes<[P8_FP_Scal]> { let Latency = 32; } 1215f757f3fSDimitry Andric def P8_FP_2x64_32C : SchedWriteRes<[P8_FP_2x64]> { let Latency = 32; } 1225f757f3fSDimitry Andric def P8_FP_4x32_32C : SchedWriteRes<[P8_FP_4x32]> { let Latency = 32; } 1235f757f3fSDimitry Andric def P8_FP_Scal_43C : SchedWriteRes<[P8_FP_Scal]> { let Latency = 43; } 1245f757f3fSDimitry Andric def P8_FP_2x64_43C : SchedWriteRes<[P8_FP_2x64]> { let Latency = 43; } 1255f757f3fSDimitry Andric def P8_XS_2C : SchedWriteRes<[P8_XS]> { let Latency = 2; } 1265f757f3fSDimitry Andric def P8_PM_2C : SchedWriteRes<[P8_PM]> { let Latency = 2; } 1275f757f3fSDimitry Andric def P8_XS_4C : SchedWriteRes<[P8_XS]> { let Latency = 4; } 1285f757f3fSDimitry Andric def P8_VX_7C : SchedWriteRes<[P8_VX]> { let Latency = 7; } 1295f757f3fSDimitry Andric def P8_XS_9C : SchedWriteRes<[P8_XS]> { let Latency = 9; } 1305f757f3fSDimitry Andric def P8_CY_6C : SchedWriteRes<[P8_CY]> { let Latency = 6; } 1315f757f3fSDimitry Andric def P8_DFU_13C : SchedWriteRes<[P8_DFU]> { let Latency = 13; } 1325f757f3fSDimitry Andric def P8_DFU_15C : SchedWriteRes<[P8_DFU]> { let Latency = 15; } 1335f757f3fSDimitry Andric def P8_DFU_17C : SchedWriteRes<[P8_DFU]> { let Latency = 17; } 1345f757f3fSDimitry Andric def P8_DFU_25C : SchedWriteRes<[P8_DFU]> { let Latency = 25; } 1355f757f3fSDimitry Andric def P8_DFU_32C : SchedWriteRes<[P8_DFU]> { let Latency = 32; } 1365f757f3fSDimitry Andric def P8_DFU_34C : SchedWriteRes<[P8_DFU]> { let Latency = 34; } 1375f757f3fSDimitry Andric def P8_DFU_40C : SchedWriteRes<[P8_DFU]> { let Latency = 40; } 1385f757f3fSDimitry Andric def P8_DFU_90C : SchedWriteRes<[P8_DFU]> { let Latency = 90; } 1395f757f3fSDimitry Andric def P8_DFU_96C : SchedWriteRes<[P8_DFU]> { let Latency = 96; } 1405f757f3fSDimitry Andric def P8_DFU_172C : SchedWriteRes<[P8_DFU]> { let Latency = 172; } 1415f757f3fSDimitry Andric // Direct move instructions 1425f757f3fSDimitry Andric def P8_DM_5C : SchedWriteRes<[]> { let Latency = 5; } 1435f757f3fSDimitry Andric 1445f757f3fSDimitry Andric // Instructions of CR pipeline 1455f757f3fSDimitry Andric 1465f757f3fSDimitry Andric def : InstRW<[P8_CR_NONE, P8_ISSUE_CR], (instrs MFCR, MFCR8)>; 1475f757f3fSDimitry Andric def : InstRW<[P8_CR_3C, P8_ISSUE_CR], (instrs MFOCRF, MFOCRF8)>; 1485f757f3fSDimitry Andric def : InstRW<[P8_CR_5C, P8_ISSUE_CR], (instrs MFLR, MFLR8, MFCTR, MFCTR8)>; 1495f757f3fSDimitry Andric 1505f757f3fSDimitry Andric // Instructions of CY pipeline 1515f757f3fSDimitry Andric 1525f757f3fSDimitry Andric def : InstRW<[P8_CY_6C, P8_ISSUE_VSX], (instrs 1535f757f3fSDimitry Andric VCIPHER, VCIPHERLAST, VNCIPHER, VNCIPHERLAST, VPMSUMB, VPMSUMD, VPMSUMH, VPMSUMW, VSBOX)>; 1545f757f3fSDimitry Andric 1555f757f3fSDimitry Andric // Instructions of FPU pipeline 1565f757f3fSDimitry Andric 1575f757f3fSDimitry Andric def : InstRW<[P8_FP_26C, P8_ISSUE_VSX], (instrs (instregex "^FDIVS(_rec)?$"), XSDIVSP)>; 1585f757f3fSDimitry Andric def : InstRW<[P8_FP_28C, P8_ISSUE_VSX], (instrs XVDIVSP)>; 1595f757f3fSDimitry Andric def : InstRW<[P8_FP_31C, P8_ISSUE_VSX], (instregex "^FSQRTS(_rec)?$")>; 1605f757f3fSDimitry Andric def : InstRW<[P8_FP_Scal_32C, P8_ISSUE_VSX], (instrs FDIV, FDIV_rec, XSDIVDP)>; 1615f757f3fSDimitry Andric def : InstRW<[P8_FP_2x64_32C, P8_ISSUE_VSX], (instrs XVDIVDP)>; 1625f757f3fSDimitry Andric def : InstRW<[P8_FP_4x32_32C, P8_ISSUE_VSX], (instrs XVSQRTSP)>; 1635f757f3fSDimitry Andric def : InstRW<[P8_FP_Scal_43C, P8_ISSUE_VSX], (instrs FSQRT, FSQRT_rec, XSSQRTDP)>; 1645f757f3fSDimitry Andric def : InstRW<[P8_FP_2x64_43C, P8_ISSUE_VSX], (instrs XVSQRTDP)>; 1655f757f3fSDimitry Andric 1665f757f3fSDimitry Andric def : InstRW<[P8_FP_3C, P8_ISSUE_VSX], (instrs 1675f757f3fSDimitry Andric MTFSFI_rec, MTFSF_rec, MTFSFI, MTFSFIb, MTFSF, MTFSFb, MTFSB0, MTFSB1)>; 1685f757f3fSDimitry Andric 1695f757f3fSDimitry Andric def : InstRW<[P8_FP_Scal_6C, P8_ISSUE_VSX], (instrs 1705f757f3fSDimitry Andric (instregex "^F(N)?M(ADD|SUB)(S)?(_rec)?$"), 1715f757f3fSDimitry Andric (instregex "^XS(N)?M(ADD|SUB)(A|M)(D|S)P$"), 1725f757f3fSDimitry Andric (instregex "^FC(F|T)I(D|W)(U)?(S|Z)?(_rec)?$"), 1735f757f3fSDimitry Andric (instregex "^(F|XS)(ABS|CPSGN|ADD|MUL|NABS|RE|NEG|SUB|SEL|RSQRTE)(D|S)?(P)?(s)?(_rec)?$"), 1745f757f3fSDimitry Andric (instregex "^FRI(M|N|P|Z)(D|S)(_rec)?$"), 1755f757f3fSDimitry Andric (instregex "^XSCVDP(S|U)X(W|D)S(s)?$"), 1765f757f3fSDimitry Andric (instregex "^XSCV(S|U)XD(D|S)P$"), 1775f757f3fSDimitry Andric (instregex "^XSCV(D|S)P(S|D)P(N)?$"), 1785f757f3fSDimitry Andric (instregex "^XSRDPI(C|M|P|Z)?$"), 1795f757f3fSDimitry Andric FMR, FRSP, FMR_rec, FRSP_rec, XSRSP)>; 1805f757f3fSDimitry Andric 1815f757f3fSDimitry Andric def : InstRW<[P8_FP_4x32_6C, P8_ISSUE_VSX], (instrs 1825f757f3fSDimitry Andric (instregex "^XV(N)?M(ADD|SUB)(A|M)SP$"), 1835f757f3fSDimitry Andric (instregex "^VRFI(M|N|P|Z)$"), 1845f757f3fSDimitry Andric XVRSQRTESP, XVSUBSP, VADDFP, VEXPTEFP, VLOGEFP, VMADDFP, VNMSUBFP, VREFP, 1855f757f3fSDimitry Andric VRSQRTEFP, VSUBFP, XVCVSXWSP, XVCVUXWSP, XVMULSP, XVNABSSP, XVNEGSP, XVRESP, 1865f757f3fSDimitry Andric XVCVDPSP, XVCVSXDSP, XVCVUXDSP, XVABSSP, XVADDSP, XVCPSGNSP)>; 1875f757f3fSDimitry Andric 1885f757f3fSDimitry Andric def : InstRW<[P8_FP_2x64_6C, P8_ISSUE_VSX], (instrs 1895f757f3fSDimitry Andric (instregex "^XVR(D|S)PI(C|M|P|Z)?$"), 1905f757f3fSDimitry Andric (instregex "^XVCV(S|U)X(D|W)DP$"), 1915f757f3fSDimitry Andric (instregex "^XVCV(D|W|S)P(S|U)X(D|W)S$"), 1925f757f3fSDimitry Andric (instregex "^XV(N)?(M)?(RSQRTE|CPSGN|SUB|ADD|ABS|UL|NEG|RE)(A|M)?DP$"), 1935f757f3fSDimitry Andric XVCVSPDP)>; 1945f757f3fSDimitry Andric 1955f757f3fSDimitry Andric // Instructions of FX, LU or LS pipeline 1965f757f3fSDimitry Andric 1975f757f3fSDimitry Andric def : InstRW<[P8_FX_NONE, P8_ISSUE_FX], (instrs TDI, TWI, TD, TW, MTCRF, MTCRF8, MTOCRF, MTOCRF8)>; 1985f757f3fSDimitry Andric def : InstRW<[P8_FX_1C, P8_ISSUE_FX], (instregex "^RLWIMI(8)?$")>; 1995f757f3fSDimitry Andric // TODO: Pipeline of logical instructions might be LS or FX 2005f757f3fSDimitry Andric def : InstRW<[P8_FX_2C, P8_ISSUE_FX], (instrs 2015f757f3fSDimitry Andric (instregex "^(N|X)?(EQV|AND|OR)(I)?(S|C)?(8)?(_rec)?$"), 2025f757f3fSDimitry Andric (instregex "^EXTS(B|H|W)(8)?(_32)?(_64)?(_rec)?$"), 2035f757f3fSDimitry Andric (instregex "^RL(D|W)(I)?(NM|C)(L|R)?(8)?(_32)?(_64)?(_rec)?$"), 2045f757f3fSDimitry Andric (instregex "^S(L|R)(A)?(W|D)(I)?(8)?(_rec|_32)?$"), 2055f757f3fSDimitry Andric (instregex "^(ADD|SUBF)(M|Z)?(C|E)?(4|8)?O(_rec)?$"), 2065f757f3fSDimitry Andric (instregex "^(ADD|SUBF)(M|Z)?E(8)?_rec$"), 2075f757f3fSDimitry Andric (instregex "^(ADD|SUBF|NEG)(4|8)?_rec$"), 2085f757f3fSDimitry Andric NOP, ADDG6S, ADDG6S8, ADDZE, ADDZE8, ADDIC_rec, NEGO_rec, ADDC, ADDC8, SUBFC, SUBFC8, 2095f757f3fSDimitry Andric ADDC_rec, ADDC8_rec, SUBFC_rec, SUBFC8_rec, COPY, NEG8O_rec, 2105f757f3fSDimitry Andric RLDIMI, RLDIMI_rec, RLWIMI8_rec, RLWIMI_rec)>; 2115f757f3fSDimitry Andric 2125f757f3fSDimitry Andric def : InstRW<[P8_FX_3C], (instregex "^(POP)?CNT(LZ)?(B|W|D)(8)?(_rec)?$")>; 2135f757f3fSDimitry Andric def : InstRW<[P8_FX_5C, P8_ISSUE_FX], (instrs 2145f757f3fSDimitry Andric (instregex "^MUL(H|L)(I|W|D)(8)?(U|O)?(_rec)?$"), 2155f757f3fSDimitry Andric CMPDI,CMPWI,CMPD,CMPW,CMPLDI,CMPLWI,CMPLD,CMPLW, 2165f757f3fSDimitry Andric ISEL, ISEL8, MTLR, MTLR8, MTCTR, MTCTR8, MTCTR8loop, MTCTRloop)>; 2175f757f3fSDimitry Andric 2185f757f3fSDimitry Andric def : InstRW<[P8_FX_10C, P8_ISSUE_VSX], (instregex "^MFTB(8)?$")>; 2195f757f3fSDimitry Andric def : InstRW<[P8_FX_15C, P8_ISSUE_FX], (instregex "^DIVW(U)?$")>; 2205f757f3fSDimitry Andric 2215f757f3fSDimitry Andric def : InstRW<[P8_FX_23C, P8_ISSUE_FX], (instregex "^DIV(D|WE)(U)?$")>; 2225f757f3fSDimitry Andric def : InstRW<[P8_FX_41C], (instrs 2235f757f3fSDimitry Andric (instregex "^DIV(D|W)(E)?(U)?O(_rec)?$"), 2245f757f3fSDimitry Andric (instregex "^DIV(D|W)(E)?(U)?_rec$"), 2255f757f3fSDimitry Andric DIVDE, DIVDEU)>; 2265f757f3fSDimitry Andric 2275f757f3fSDimitry Andric def : InstRW<[P8_LS_3C, P8_ISSUE_FX], (instrs MFSR, MFSRIN)>; 2285f757f3fSDimitry Andric 2295f757f3fSDimitry Andric def : InstRW<[P8_LU_5C, P8_ISSUE_LD], (instrs 2305f757f3fSDimitry Andric LFS, LFSX, LFD, LFDX, LFDXTLS, LFDXTLS_, LXVD2X, LXVW4X, LXVDSX, LVEBX, LVEHX, LVEWX, 2315f757f3fSDimitry Andric LVX, LVXL, LXSDX, LFIWAX, LFIWZX, LFSXTLS, LFSXTLS_, LXVB16X, LXVD2X, LXSIWZX, 2325f757f3fSDimitry Andric DFLOADf64, XFLOADf64, LIWZX)>; 2335f757f3fSDimitry Andric 2345f757f3fSDimitry Andric def : InstRW<[P8_LS_FX_3C, P8_ISSUE_FXLD], (instrs LQ)>; 2355f757f3fSDimitry Andric def : InstRW<[P8_LU_FX_5C, P8_ISSUE_LD], (instregex "^LF(D|S)U(X)?$")>; 2365f757f3fSDimitry Andric 2375f757f3fSDimitry Andric def : InstRW<[P8_LS_FP_NONE, P8_ISSUE_ST], (instrs 2385f757f3fSDimitry Andric STXSDX, STXVD2X, STXVW4X, STFIWX, STFS, STFSX, STFD, STFDX, 2395f757f3fSDimitry Andric STFDEPX, STFDXTLS, STFDXTLS_, STFSXTLS, STFSXTLS_, STXSIWX, STXSSP, STXSSPX)>; 2405f757f3fSDimitry Andric 2415f757f3fSDimitry Andric def : InstRW<[P8_LS_FP_FX_2C, P8_ISSUE_ST], (instrs STVEBX, STVEHX, STVEWX, STVX, STVXL)>; 2425f757f3fSDimitry Andric def : InstRW<[P8_LS_FP_FX_3C, P8_ISSUE_ST], (instregex "^STF(D|S)U(X)?$")>; 2435f757f3fSDimitry Andric 2445f757f3fSDimitry Andric def : InstRW<[P8_LS_LU_NONE, P8_ISSUE_ST], (instrs 2455f757f3fSDimitry Andric (instregex "^ST(B|H|W|D)(U)?(X)?(8|TLS)?(_)?(32)?$"), 2465f757f3fSDimitry Andric STBCIX, STBCX, STBEPX, STDBRX, STDCIX, STDCX, STHBRX, STHCIX, STHCX, STHEPX, 2475f757f3fSDimitry Andric STMW, STSWI, STWBRX, STWCIX, STWCX, STWEPX)>; 2485f757f3fSDimitry Andric 2495f757f3fSDimitry Andric def : InstRW<[P8_LU_or_LS_FX_3C, P8_ISSUE_FXLD], 2505f757f3fSDimitry Andric (instregex "^L(B|H|W|D)(A|Z)?(U)?(X)?(8|TLS)?(_)?(32)?$")>; 2515f757f3fSDimitry Andric 2525f757f3fSDimitry Andric def : InstRW<[P8_LU_or_LS_3C, P8_ISSUE_FXLD], (instrs 2535f757f3fSDimitry Andric LBARX, LBARXL, LBEPX, LBZCIX, LDARX, LDARXL, LDBRX, LDCIX, LFDEPX, LHARX, LHARXL, LHBRX, LXSIWAX, 2545f757f3fSDimitry Andric LHBRX8, LHEPX, LHZCIX, LMW, LSWI, LVSL, LVSR, LWARX, LWARXL, LWBRX, LWBRX8, LWEPX, LWZCIX)>; 2555f757f3fSDimitry Andric 2565f757f3fSDimitry Andric def : InstRW<[P8_LU_or_LS_or_FX_2C, P8_ISSUE_FX], (instrs 2575f757f3fSDimitry Andric (instregex "^ADDI(C)?(dtprel|tlsgd|toc)?(L)?(ADDR)?(32|8)?$"), 2585f757f3fSDimitry Andric (instregex "^ADDIS(dtprel|tlsgd|toc|gotTprel)?(HA)?(32|8)?$"), 2595f757f3fSDimitry Andric (instregex "^LI(S)?(8)?$"), 2605f757f3fSDimitry Andric (instregex "^ADD(M)?(E)?(4|8)?(TLS)?(_)?$"), 2615f757f3fSDimitry Andric (instregex "^SUBF(M|Z)?(E)?(IC)?(4|8)?$"), 2625f757f3fSDimitry Andric (instregex "^NEG(8)?(O)?$"))>; 2635f757f3fSDimitry Andric 2645f757f3fSDimitry Andric // Instructions of PM pipeline 2655f757f3fSDimitry Andric 2665f757f3fSDimitry Andric def : InstRW<[P8_PM_2C, P8_ISSUE_VSX], (instrs 2675f757f3fSDimitry Andric (instregex "^VPK(S|U)(H|W|D)(S|U)(M|S)$"), 2685f757f3fSDimitry Andric (instregex "^VUPK(H|L)(P|S)(H|B|W|X)$"), 2695f757f3fSDimitry Andric (instregex "^VSPLT(IS)?(B|H|W)(s)?$"), 2705f757f3fSDimitry Andric (instregex "^(XX|V)MRG(E|O|H|L)(B|H|W)$"), 2715f757f3fSDimitry Andric XXPERMDI, XXPERMDIs, XXSEL, XXSLDWI, XXSLDWIs, XXSPLTW, XXSPLTWs, VPERMXOR, 2725f757f3fSDimitry Andric VPKPX, VPERM, VBPERMQ, VGBBD, VSEL, VSL, VSLDOI, VSLO, VSR, VSRO)>; 2735f757f3fSDimitry Andric 2745f757f3fSDimitry Andric def : InstRW<[P8_XS_2C, P8_ISSUE_VSX], (instrs 2755f757f3fSDimitry Andric (instregex "^V(ADD|SUB)(S|U)(B|H|W|D)(M|S)$"), 2765f757f3fSDimitry Andric (instregex "^X(S|V)(MAX|MIN)(D|S)P$"), 2775f757f3fSDimitry Andric (instregex "^V(S)?(R)?(L)?(A)?(B|D|H|W)$"), 2785f757f3fSDimitry Andric (instregex "^VAVG(S|U)(B|H|W)$"), 2795f757f3fSDimitry Andric (instregex "^VM(AX|IN)(S|U)(B|H|W|D)$"), 2805f757f3fSDimitry Andric (instregex "^(XX|V)(L)?(N)?(X)?(AND|OR|EQV)(C)?$"), 2815f757f3fSDimitry Andric (instregex "^(X)?VCMP(EQ|GT|GE|B)(F|S|U)?(B|H|W|D|P|S)(P)?(_rec)?$"), 2825f757f3fSDimitry Andric (instregex "^VCLZ(B|H|W|D)$"), 2835f757f3fSDimitry Andric (instregex "^VPOPCNT(B|H|W)$"), 2845f757f3fSDimitry Andric XXLORf, XXLXORdpz, XXLXORspz, XXLXORz, VEQV, VMAXFP, VMINFP, 2855f757f3fSDimitry Andric VSHASIGMAD, VSHASIGMAW, VSUBCUW, VADDCUW, MFVSCR, MTVSCR)>; 2865f757f3fSDimitry Andric 2875f757f3fSDimitry Andric def : InstRW<[P8_XS_4C, P8_ISSUE_VSX], (instrs 2885f757f3fSDimitry Andric (instregex "^V(ADD|SUB)(E)?(C)?UQ(M)?$"), 2895f757f3fSDimitry Andric VPOPCNTD)>; 2905f757f3fSDimitry Andric 2915f757f3fSDimitry Andric def : InstRW<[P8_XS_9C, P8_ISSUE_CR], (instrs 2925f757f3fSDimitry Andric (instregex "^(F|XS)CMP(O|U)(D|S)(P)?$"), 2935f757f3fSDimitry Andric (instregex "^(F|XS|XV)T(DIV|SQRT)((D|S)P)?$"))>; 2945f757f3fSDimitry Andric 2955f757f3fSDimitry Andric // Instructions of VX pipeline 2965f757f3fSDimitry Andric 2975f757f3fSDimitry Andric def : InstRW<[P8_VX_7C, P8_ISSUE_VSX], (instrs 2985f757f3fSDimitry Andric (instregex "^V(M)?SUM(2|4)?(M|S|U)(B|H|W)(M|S)$"), 2995f757f3fSDimitry Andric (instregex "^VMUL(E|O)?(S|U)(B|H|W)(M)?$"), 3005f757f3fSDimitry Andric VMHADDSHS, VMHRADDSHS, VMLADDUHM)>; 3015f757f3fSDimitry Andric 3025f757f3fSDimitry Andric // Instructions of BR pipeline 3035f757f3fSDimitry Andric 3045f757f3fSDimitry Andric def : InstRW<[P8_BR_2C, P8_ISSUE_BR], (instrs 3055f757f3fSDimitry Andric (instregex "^(g)?B(C)?(C)?(CTR)?(L)?(A)?(R)?(L)?(8)?(_LD|_LWZ)?(always|into_toc|at)?(_RM)?(n)?$"), 3065f757f3fSDimitry Andric (instregex "^BD(N)?Z(L)?(R|A)?(L)?(m|p|8)?$"), 3075f757f3fSDimitry Andric (instregex "^BL(R|A)?(8)?(_NOP)?(_TLS)?(_)?(RM)?$"))>; 3085f757f3fSDimitry Andric 3095f757f3fSDimitry Andric // Instructions of DFP pipeline 3105f757f3fSDimitry Andric // DFP operations also use float/vector/crypto issue ports. 3115f757f3fSDimitry Andric def : InstRW<[P8_DFU_13C, P8_ISSUE_VSX], (instrs 3125f757f3fSDimitry Andric (instregex "^DTST(D|S)(C|F|G)(Q)?$"), 3135f757f3fSDimitry Andric (instregex "^D(Q|X)EX(Q)?(_rec)?$"), 3145f757f3fSDimitry Andric (instregex "^D(ADD|SUB|IEX|QUA|RRND|RINTX|RINTN|CTDP|DEDPD|ENBCD)(_rec)?$"), 3155f757f3fSDimitry Andric (instregex "^DSC(L|R)I(_rec)?$"), 3165f757f3fSDimitry Andric BCDADD_rec, BCDSUB_rec, DCMPO, DCMPU, DTSTEX, DQUAI)>; 3175f757f3fSDimitry Andric 3185f757f3fSDimitry Andric def : InstRW<[P8_DFU_15C, P8_ISSUE_VSX], (instrs 3195f757f3fSDimitry Andric (instregex "^DRINT(N|X)Q(_rec)?$"), 3205f757f3fSDimitry Andric DCMPOQ, DCMPUQ, DRRNDQ, DRRNDQ_rec, DIEXQ, DIEXQ_rec, DQUAIQ, DQUAIQ_rec, 3215f757f3fSDimitry Andric DTSTEXQ, DDEDPDQ, DDEDPDQ_rec, DENBCDQ, DENBCDQ_rec, DSCLIQ, DSCLIQ_rec, 3225f757f3fSDimitry Andric DSCRIQ, DSCRIQ_rec, DCTQPQ, DCTQPQ_rec)>; 3235f757f3fSDimitry Andric 3245f757f3fSDimitry Andric def : InstRW<[P8_DFU_17C, P8_ISSUE_VSX], (instregex "^D(ADD|SUB|QUA)Q(_rec)?$")>; 3255f757f3fSDimitry Andric def : InstRW<[P8_DFU_25C, P8_ISSUE_VSX], (instrs DRSP, DRSP_rec, DCTFIX, DCTFIX_rec)>; 3265f757f3fSDimitry Andric def : InstRW<[P8_DFU_32C, P8_ISSUE_VSX], (instrs DCFFIX, DCFFIX_rec)>; 3275f757f3fSDimitry Andric def : InstRW<[P8_DFU_34C, P8_ISSUE_VSX], (instrs DCFFIXQ, DCFFIXQ_rec)>; 3285f757f3fSDimitry Andric def : InstRW<[P8_DFU_40C, P8_ISSUE_VSX], (instrs DMUL, DMUL_rec)>; 3295f757f3fSDimitry Andric def : InstRW<[P8_DFU_90C, P8_ISSUE_VSX], (instrs DMULQ, DMULQ_rec)>; 3305f757f3fSDimitry Andric def : InstRW<[P8_DFU_96C, P8_ISSUE_VSX], (instrs DDIV, DDIV_rec)>; 3315f757f3fSDimitry Andric def : InstRW<[P8_DFU_172C, P8_ISSUE_VSX], (instrs DDIVQ, DDIVQ_rec)>; 3325f757f3fSDimitry Andric 3335f757f3fSDimitry Andric // Direct move instructions 3345f757f3fSDimitry Andric 3355f757f3fSDimitry Andric def : InstRW<[P8_DM_5C, P8_ISSUE_VSX], (instrs 3365f757f3fSDimitry Andric MFVRD, MFVSRD, MFVRWZ, MFVSRWZ, MTVRD, MTVSRD, MTVRWA, MTVSRWA, MTVRWZ, MTVSRWZ)>; 3375f757f3fSDimitry Andric} 338