10b57cec5SDimitry Andric//===-- PPCScheduleP9.td - PPC P9 Scheduling Definitions ---*- tablegen -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file defines the itinerary class data for the POWER9 processor. 100b57cec5SDimitry Andric// 110b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 120b57cec5SDimitry Andricdef P9Model : SchedMachineModel { 130b57cec5SDimitry Andric // The maximum number of instructions to be issued at the same time. 140b57cec5SDimitry Andric // While a value of 8 is technically correct since 8 instructions can be 150b57cec5SDimitry Andric // fetched from the instruction cache. However, only 6 instructions may be 160b57cec5SDimitry Andric // actually dispatched at a time. 170b57cec5SDimitry Andric let IssueWidth = 8; 180b57cec5SDimitry Andric 190b57cec5SDimitry Andric // Load latency is 4 or 5 cycles depending on the load. This latency assumes 200b57cec5SDimitry Andric // that we have a cache hit. For a cache miss the load latency will be more. 215ffd83dbSDimitry Andric // There are two instructions (lxvl, lxvll) that have a latency of 6 cycles. 220b57cec5SDimitry Andric // However it is not worth bumping this value up to 6 when the vast majority 230b57cec5SDimitry Andric // of instructions are 4 or 5 cycles. 240b57cec5SDimitry Andric let LoadLatency = 5; 250b57cec5SDimitry Andric 260b57cec5SDimitry Andric // A total of 16 cycles to recover from a branch mispredict. 270b57cec5SDimitry Andric let MispredictPenalty = 16; 280b57cec5SDimitry Andric 290b57cec5SDimitry Andric // Try to make sure we have at least 10 dispatch groups in a loop. 300b57cec5SDimitry Andric // A dispatch group is 6 instructions. 310b57cec5SDimitry Andric let LoopMicroOpBufferSize = 60; 320b57cec5SDimitry Andric 330b57cec5SDimitry Andric // As iops are dispatched to a slice, they are held in an independent slice 340b57cec5SDimitry Andric // issue queue until all register sources and other dependencies have been 350b57cec5SDimitry Andric // resolved and they can be issued. Each of four execution slices has an 360b57cec5SDimitry Andric // 11-entry iop issue queue. 370b57cec5SDimitry Andric let MicroOpBufferSize = 44; 380b57cec5SDimitry Andric 390b57cec5SDimitry Andric let CompleteModel = 1; 400b57cec5SDimitry Andric 41bdd1243dSDimitry Andric // Do not support SPE (Signal Processing Engine) or prefixed instructions on 42bdd1243dSDimitry Andric // Power 9, or MMA, or paired vector mem ops, or PC relative mem ops, or 43bdd1243dSDimitry Andric // instructions introduced after ISA 3.0. 44bdd1243dSDimitry Andric let UnsupportedFeatures = [HasSPE, PrefixInstrs, MMA, 458a4dda33SDimitry Andric PairedVectorMemops, IsBookE, 4681ad6265SDimitry Andric PCRelativeMemops, IsISA3_1, IsISAFuture]; 470b57cec5SDimitry Andric} 480b57cec5SDimitry Andric 490b57cec5SDimitry Andriclet SchedModel = P9Model in { 500b57cec5SDimitry Andric 510b57cec5SDimitry Andric // ***************** Processor Resources ***************** 520b57cec5SDimitry Andric 530b57cec5SDimitry Andric // Dispatcher slots: 540b57cec5SDimitry Andric // x0, x1, x2, and x3 are the dedicated slice dispatch ports, where each 550b57cec5SDimitry Andric // corresponds to one of the four execution slices. 560b57cec5SDimitry Andric def DISPx02 : ProcResource<2>; 570b57cec5SDimitry Andric def DISPx13 : ProcResource<2>; 580b57cec5SDimitry Andric // The xa and xb ports can be used to send an iop to either of the two slices 590b57cec5SDimitry Andric // of the superslice, but are restricted to iops with only two primary sources. 600b57cec5SDimitry Andric def DISPxab : ProcResource<2>; 610b57cec5SDimitry Andric // b0 and b1 are dedicated dispatch ports into the branch slice. 620b57cec5SDimitry Andric def DISPb01 : ProcResource<2>; 630b57cec5SDimitry Andric 640b57cec5SDimitry Andric // Any non BR dispatch ports 650b57cec5SDimitry Andric def DISP_NBR 660b57cec5SDimitry Andric : ProcResGroup<[ DISPx02, DISPx13, DISPxab]>; 670b57cec5SDimitry Andric def DISP_SS : ProcResGroup<[ DISPx02, DISPx13]>; 680b57cec5SDimitry Andric 690b57cec5SDimitry Andric // Issue Ports 700b57cec5SDimitry Andric // An instruction can go down one of two issue queues. 710b57cec5SDimitry Andric // Address Generation (AGEN) mainly for loads and stores. 720b57cec5SDimitry Andric // Execution (EXEC) for most other instructions. 730b57cec5SDimitry Andric // Some instructions cannot be run on just any issue queue and may require an 740b57cec5SDimitry Andric // Even or an Odd queue. The EXECE represents the even queues and the EXECO 750b57cec5SDimitry Andric // represents the odd queues. 760b57cec5SDimitry Andric def IP_AGEN : ProcResource<4>; 770b57cec5SDimitry Andric def IP_EXEC : ProcResource<4>; 780b57cec5SDimitry Andric def IP_EXECE : ProcResource<2> { 790b57cec5SDimitry Andric //Even Exec Ports 800b57cec5SDimitry Andric let Super = IP_EXEC; 810b57cec5SDimitry Andric } 820b57cec5SDimitry Andric def IP_EXECO : ProcResource<2> { 830b57cec5SDimitry Andric //Odd Exec Ports 840b57cec5SDimitry Andric let Super = IP_EXEC; 850b57cec5SDimitry Andric } 860b57cec5SDimitry Andric 870b57cec5SDimitry Andric // Pipeline Groups 880b57cec5SDimitry Andric // Four ALU (Fixed Point Arithmetic) units in total. Two even, two Odd. 890b57cec5SDimitry Andric def ALU : ProcResource<4>; 900b57cec5SDimitry Andric def ALUE : ProcResource<2> { 910b57cec5SDimitry Andric //Even ALU pipelines 920b57cec5SDimitry Andric let Super = ALU; 930b57cec5SDimitry Andric } 940b57cec5SDimitry Andric def ALUO : ProcResource<2> { 950b57cec5SDimitry Andric //Odd ALU pipelines 960b57cec5SDimitry Andric let Super = ALU; 970b57cec5SDimitry Andric } 980b57cec5SDimitry Andric 990b57cec5SDimitry Andric // Two DIV (Fixed Point Divide) units. 1000b57cec5SDimitry Andric def DIV : ProcResource<2>; 1010b57cec5SDimitry Andric 1020b57cec5SDimitry Andric // Four DP (Floating Point) units in total. Two even, two Odd. 1030b57cec5SDimitry Andric def DP : ProcResource<4>; 1040b57cec5SDimitry Andric def DPE : ProcResource<2> { 1050b57cec5SDimitry Andric //Even DP pipelines 1060b57cec5SDimitry Andric let Super = DP; 1070b57cec5SDimitry Andric } 1080b57cec5SDimitry Andric def DPO : ProcResource<2> { 1090b57cec5SDimitry Andric //Odd DP pipelines 1100b57cec5SDimitry Andric let Super = DP; 1110b57cec5SDimitry Andric } 1120b57cec5SDimitry Andric 1130b57cec5SDimitry Andric // Four LS (Load or Store) units. 1140b57cec5SDimitry Andric def LS : ProcResource<4>; 1150b57cec5SDimitry Andric 1160b57cec5SDimitry Andric // Two PM (Permute) units. 1170b57cec5SDimitry Andric def PM : ProcResource<2>; 1180b57cec5SDimitry Andric 1190b57cec5SDimitry Andric // Only one DFU (Decimal Floating Point and Quad Precision) unit. 1200b57cec5SDimitry Andric def DFU : ProcResource<1>; 1210b57cec5SDimitry Andric 1220b57cec5SDimitry Andric // Only one Branch unit. 1230b57cec5SDimitry Andric def BR : ProcResource<1> { 1240b57cec5SDimitry Andric let BufferSize = 16; 1250b57cec5SDimitry Andric } 1260b57cec5SDimitry Andric 1270b57cec5SDimitry Andric // Only one CY (Crypto) unit. 1280b57cec5SDimitry Andric def CY : ProcResource<1>; 1290b57cec5SDimitry Andric 1300b57cec5SDimitry Andric // ***************** SchedWriteRes Definitions ***************** 1310b57cec5SDimitry Andric 1320b57cec5SDimitry Andric // Dispatcher 1330b57cec5SDimitry Andric // Dispatch Rules: '-' or 'V' 1340b57cec5SDimitry Andric // Vector ('V') - vector iops (128-bit operand) take only one decode and 1350b57cec5SDimitry Andric // dispatch slot but are dispatched to both the even and odd slices of a 1360b57cec5SDimitry Andric // superslice. 1370b57cec5SDimitry Andric def DISP_1C : SchedWriteRes<[DISP_NBR]> { 1380b57cec5SDimitry Andric let NumMicroOps = 0; 1390b57cec5SDimitry Andric let Latency = 1; 1400b57cec5SDimitry Andric } 1410b57cec5SDimitry Andric // Dispatch Rules: 'E' 1420b57cec5SDimitry Andric // Even slice ('E')- certain operations must be sent only to an even slice. 1430b57cec5SDimitry Andric // Also consumes odd dispatch slice slot of the same superslice at dispatch 1440b57cec5SDimitry Andric def DISP_EVEN_1C : SchedWriteRes<[ DISPx02, DISPx13 ]> { 1450b57cec5SDimitry Andric let NumMicroOps = 0; 1460b57cec5SDimitry Andric let Latency = 1; 1470b57cec5SDimitry Andric } 1480b57cec5SDimitry Andric // Dispatch Rules: 'P' 1490b57cec5SDimitry Andric // Paired ('P') - certain cracked and expanded iops are paired such that they 1500b57cec5SDimitry Andric // must dispatch together to the same superslice. 1510b57cec5SDimitry Andric def DISP_PAIR_1C : SchedWriteRes<[ DISP_SS, DISP_SS]> { 1520b57cec5SDimitry Andric let NumMicroOps = 0; 1530b57cec5SDimitry Andric let Latency = 1; 1540b57cec5SDimitry Andric } 1550b57cec5SDimitry Andric // Tuple Restricted ('R') - certain iops preclude dispatching more than one 1560b57cec5SDimitry Andric // operation per slice for the super- slice to which they are dispatched 1570b57cec5SDimitry Andric def DISP_3SLOTS_1C : SchedWriteRes<[DISPx02, DISPx13, DISPxab]> { 1580b57cec5SDimitry Andric let NumMicroOps = 0; 1590b57cec5SDimitry Andric let Latency = 1; 1600b57cec5SDimitry Andric } 1610b57cec5SDimitry Andric // Each execution and branch slice can receive up to two iops per cycle 1620b57cec5SDimitry Andric def DISP_BR_1C : SchedWriteRes<[ DISPxab ]> { 1630b57cec5SDimitry Andric let NumMicroOps = 0; 1640b57cec5SDimitry Andric let Latency = 1; 1650b57cec5SDimitry Andric } 1660b57cec5SDimitry Andric 1670b57cec5SDimitry Andric // Issue Ports 1680b57cec5SDimitry Andric def IP_AGEN_1C : SchedWriteRes<[IP_AGEN]> { 1690b57cec5SDimitry Andric let NumMicroOps = 0; 1700b57cec5SDimitry Andric let Latency = 1; 1710b57cec5SDimitry Andric } 1720b57cec5SDimitry Andric 1730b57cec5SDimitry Andric def IP_EXEC_1C : SchedWriteRes<[IP_EXEC]> { 1740b57cec5SDimitry Andric let NumMicroOps = 0; 1750b57cec5SDimitry Andric let Latency = 1; 1760b57cec5SDimitry Andric } 1770b57cec5SDimitry Andric 1780b57cec5SDimitry Andric def IP_EXECE_1C : SchedWriteRes<[IP_EXECE]> { 1790b57cec5SDimitry Andric let NumMicroOps = 0; 1800b57cec5SDimitry Andric let Latency = 1; 1810b57cec5SDimitry Andric } 1820b57cec5SDimitry Andric 1830b57cec5SDimitry Andric def IP_EXECO_1C : SchedWriteRes<[IP_EXECO]> { 1840b57cec5SDimitry Andric let NumMicroOps = 0; 1850b57cec5SDimitry Andric let Latency = 1; 1860b57cec5SDimitry Andric } 1870b57cec5SDimitry Andric 1880b57cec5SDimitry Andric //Pipeline Groups 1890b57cec5SDimitry Andric 1900b57cec5SDimitry Andric // ALU Units 1910b57cec5SDimitry Andric // An ALU may take either 2 or 3 cycles to complete the operation. 1920b57cec5SDimitry Andric // However, the ALU unit is only ever busy for 1 cycle at a time and may 1930b57cec5SDimitry Andric // receive new instructions each cycle. 1940b57cec5SDimitry Andric def P9_ALU_2C : SchedWriteRes<[ALU]> { 1950b57cec5SDimitry Andric let Latency = 2; 1960b57cec5SDimitry Andric } 1970b57cec5SDimitry Andric 1980b57cec5SDimitry Andric def P9_ALUE_2C : SchedWriteRes<[ALUE]> { 1990b57cec5SDimitry Andric let Latency = 2; 2000b57cec5SDimitry Andric } 2010b57cec5SDimitry Andric 2020b57cec5SDimitry Andric def P9_ALUO_2C : SchedWriteRes<[ALUO]> { 2030b57cec5SDimitry Andric let Latency = 2; 2040b57cec5SDimitry Andric } 2050b57cec5SDimitry Andric 2060b57cec5SDimitry Andric def P9_ALU_3C : SchedWriteRes<[ALU]> { 2070b57cec5SDimitry Andric let Latency = 3; 2080b57cec5SDimitry Andric } 2090b57cec5SDimitry Andric 2100b57cec5SDimitry Andric def P9_ALUE_3C : SchedWriteRes<[ALUE]> { 2110b57cec5SDimitry Andric let Latency = 3; 2120b57cec5SDimitry Andric } 2130b57cec5SDimitry Andric 2140b57cec5SDimitry Andric def P9_ALUO_3C : SchedWriteRes<[ALUO]> { 2150b57cec5SDimitry Andric let Latency = 3; 2160b57cec5SDimitry Andric } 2170b57cec5SDimitry Andric 2180b57cec5SDimitry Andric // DIV Unit 2190b57cec5SDimitry Andric // A DIV unit may take from 5 to 40 cycles to complete. 2200b57cec5SDimitry Andric // Some DIV operations may keep the unit busy for up to 8 cycles. 2210b57cec5SDimitry Andric def P9_DIV_5C : SchedWriteRes<[DIV]> { 2220b57cec5SDimitry Andric let Latency = 5; 2230b57cec5SDimitry Andric } 2240b57cec5SDimitry Andric 2250b57cec5SDimitry Andric def P9_DIV_12C : SchedWriteRes<[DIV]> { 2260b57cec5SDimitry Andric let Latency = 12; 2270b57cec5SDimitry Andric } 2280b57cec5SDimitry Andric 2290b57cec5SDimitry Andric def P9_DIV_16C_8 : SchedWriteRes<[DIV]> { 2305f757f3fSDimitry Andric let ReleaseAtCycles = [8]; 2310b57cec5SDimitry Andric let Latency = 16; 2320b57cec5SDimitry Andric } 2330b57cec5SDimitry Andric 2340b57cec5SDimitry Andric def P9_DIV_24C_8 : SchedWriteRes<[DIV]> { 2355f757f3fSDimitry Andric let ReleaseAtCycles = [8]; 2360b57cec5SDimitry Andric let Latency = 24; 2370b57cec5SDimitry Andric } 2380b57cec5SDimitry Andric 2390b57cec5SDimitry Andric def P9_DIV_40C_8 : SchedWriteRes<[DIV]> { 2405f757f3fSDimitry Andric let ReleaseAtCycles = [8]; 2410b57cec5SDimitry Andric let Latency = 40; 2420b57cec5SDimitry Andric } 2430b57cec5SDimitry Andric 2440b57cec5SDimitry Andric // DP Unit 2450b57cec5SDimitry Andric // A DP unit may take from 2 to 36 cycles to complete. 2460b57cec5SDimitry Andric // Some DP operations keep the unit busy for up to 10 cycles. 2470b57cec5SDimitry Andric def P9_DP_5C : SchedWriteRes<[DP]> { 2480b57cec5SDimitry Andric let Latency = 5; 2490b57cec5SDimitry Andric } 2500b57cec5SDimitry Andric 2510b57cec5SDimitry Andric def P9_DP_7C : SchedWriteRes<[DP]> { 2520b57cec5SDimitry Andric let Latency = 7; 2530b57cec5SDimitry Andric } 2540b57cec5SDimitry Andric 2550b57cec5SDimitry Andric def P9_DPE_7C : SchedWriteRes<[DPE]> { 2560b57cec5SDimitry Andric let Latency = 7; 2570b57cec5SDimitry Andric } 2580b57cec5SDimitry Andric 2590b57cec5SDimitry Andric def P9_DPO_7C : SchedWriteRes<[DPO]> { 2600b57cec5SDimitry Andric let Latency = 7; 2610b57cec5SDimitry Andric } 2620b57cec5SDimitry Andric 2630b57cec5SDimitry Andric def P9_DP_22C_5 : SchedWriteRes<[DP]> { 2645f757f3fSDimitry Andric let ReleaseAtCycles = [5]; 2650b57cec5SDimitry Andric let Latency = 22; 2660b57cec5SDimitry Andric } 2670b57cec5SDimitry Andric 2680b57cec5SDimitry Andric def P9_DPO_24C_8 : SchedWriteRes<[DPO]> { 2695f757f3fSDimitry Andric let ReleaseAtCycles = [8]; 2700b57cec5SDimitry Andric let Latency = 24; 2710b57cec5SDimitry Andric } 2720b57cec5SDimitry Andric 2730b57cec5SDimitry Andric def P9_DPE_24C_8 : SchedWriteRes<[DPE]> { 2745f757f3fSDimitry Andric let ReleaseAtCycles = [8]; 2750b57cec5SDimitry Andric let Latency = 24; 2760b57cec5SDimitry Andric } 2770b57cec5SDimitry Andric 2780b57cec5SDimitry Andric def P9_DP_26C_5 : SchedWriteRes<[DP]> { 2795f757f3fSDimitry Andric let ReleaseAtCycles = [5]; 2800b57cec5SDimitry Andric let Latency = 22; 2810b57cec5SDimitry Andric } 2820b57cec5SDimitry Andric 2830b57cec5SDimitry Andric def P9_DPE_27C_10 : SchedWriteRes<[DP]> { 2845f757f3fSDimitry Andric let ReleaseAtCycles = [10]; 2850b57cec5SDimitry Andric let Latency = 27; 2860b57cec5SDimitry Andric } 2870b57cec5SDimitry Andric 2880b57cec5SDimitry Andric def P9_DPO_27C_10 : SchedWriteRes<[DP]> { 2895f757f3fSDimitry Andric let ReleaseAtCycles = [10]; 2900b57cec5SDimitry Andric let Latency = 27; 2910b57cec5SDimitry Andric } 2920b57cec5SDimitry Andric 2930b57cec5SDimitry Andric def P9_DP_33C_8 : SchedWriteRes<[DP]> { 2945f757f3fSDimitry Andric let ReleaseAtCycles = [8]; 2950b57cec5SDimitry Andric let Latency = 33; 2960b57cec5SDimitry Andric } 2970b57cec5SDimitry Andric 2980b57cec5SDimitry Andric def P9_DPE_33C_8 : SchedWriteRes<[DPE]> { 2995f757f3fSDimitry Andric let ReleaseAtCycles = [8]; 3000b57cec5SDimitry Andric let Latency = 33; 3010b57cec5SDimitry Andric } 3020b57cec5SDimitry Andric 3030b57cec5SDimitry Andric def P9_DPO_33C_8 : SchedWriteRes<[DPO]> { 3045f757f3fSDimitry Andric let ReleaseAtCycles = [8]; 3050b57cec5SDimitry Andric let Latency = 33; 3060b57cec5SDimitry Andric } 3070b57cec5SDimitry Andric 3080b57cec5SDimitry Andric def P9_DP_36C_10 : SchedWriteRes<[DP]> { 3095f757f3fSDimitry Andric let ReleaseAtCycles = [10]; 3100b57cec5SDimitry Andric let Latency = 36; 3110b57cec5SDimitry Andric } 3120b57cec5SDimitry Andric 3130b57cec5SDimitry Andric def P9_DPE_36C_10 : SchedWriteRes<[DP]> { 3145f757f3fSDimitry Andric let ReleaseAtCycles = [10]; 3150b57cec5SDimitry Andric let Latency = 36; 3160b57cec5SDimitry Andric } 3170b57cec5SDimitry Andric 3180b57cec5SDimitry Andric def P9_DPO_36C_10 : SchedWriteRes<[DP]> { 3195f757f3fSDimitry Andric let ReleaseAtCycles = [10]; 3200b57cec5SDimitry Andric let Latency = 36; 3210b57cec5SDimitry Andric } 3220b57cec5SDimitry Andric 3230b57cec5SDimitry Andric // PM Unit 3240b57cec5SDimitry Andric // Three cycle permute operations. 3250b57cec5SDimitry Andric def P9_PM_3C : SchedWriteRes<[PM]> { 3260b57cec5SDimitry Andric let Latency = 3; 3270b57cec5SDimitry Andric } 3280b57cec5SDimitry Andric 3290b57cec5SDimitry Andric // Load and Store Units 3300b57cec5SDimitry Andric // Loads can have 4, 5 or 6 cycles of latency. 3310b57cec5SDimitry Andric // Stores are listed as having a single cycle of latency. This is not 3320b57cec5SDimitry Andric // completely accurate since it takes more than 1 cycle to actually store 3330b57cec5SDimitry Andric // the value. However, since the store does not produce a result it can be 3340b57cec5SDimitry Andric // considered complete after one cycle. 3350b57cec5SDimitry Andric def P9_LS_1C : SchedWriteRes<[LS]> { 3360b57cec5SDimitry Andric let Latency = 1; 3370b57cec5SDimitry Andric } 3380b57cec5SDimitry Andric 3390b57cec5SDimitry Andric def P9_LS_4C : SchedWriteRes<[LS]> { 3400b57cec5SDimitry Andric let Latency = 4; 3410b57cec5SDimitry Andric } 3420b57cec5SDimitry Andric 3430b57cec5SDimitry Andric def P9_LS_5C : SchedWriteRes<[LS]> { 3440b57cec5SDimitry Andric let Latency = 5; 3450b57cec5SDimitry Andric } 3460b57cec5SDimitry Andric 3470b57cec5SDimitry Andric def P9_LS_6C : SchedWriteRes<[LS]> { 3480b57cec5SDimitry Andric let Latency = 6; 3490b57cec5SDimitry Andric } 3500b57cec5SDimitry Andric 3510b57cec5SDimitry Andric // DFU Unit 3520b57cec5SDimitry Andric // Some of the most expensive ops use the DFU. 3530b57cec5SDimitry Andric // Can take from 12 cycles to 76 cycles to obtain a result. 3540b57cec5SDimitry Andric // The unit may be busy for up to 62 cycles. 3550b57cec5SDimitry Andric def P9_DFU_12C : SchedWriteRes<[DFU]> { 3560b57cec5SDimitry Andric let Latency = 12; 3570b57cec5SDimitry Andric } 3580b57cec5SDimitry Andric 3590b57cec5SDimitry Andric def P9_DFU_23C : SchedWriteRes<[DFU]> { 3600b57cec5SDimitry Andric let Latency = 23; 3615f757f3fSDimitry Andric let ReleaseAtCycles = [11]; 3620b57cec5SDimitry Andric } 3630b57cec5SDimitry Andric 3640b57cec5SDimitry Andric def P9_DFU_24C : SchedWriteRes<[DFU]> { 3650b57cec5SDimitry Andric let Latency = 24; 3665f757f3fSDimitry Andric let ReleaseAtCycles = [12]; 3670b57cec5SDimitry Andric } 3680b57cec5SDimitry Andric 3690b57cec5SDimitry Andric def P9_DFU_37C : SchedWriteRes<[DFU]> { 3700b57cec5SDimitry Andric let Latency = 37; 3715f757f3fSDimitry Andric let ReleaseAtCycles = [25]; 3720b57cec5SDimitry Andric } 3730b57cec5SDimitry Andric 3740b57cec5SDimitry Andric def P9_DFU_58C : SchedWriteRes<[DFU]> { 3750b57cec5SDimitry Andric let Latency = 58; 3765f757f3fSDimitry Andric let ReleaseAtCycles = [44]; 3770b57cec5SDimitry Andric } 3780b57cec5SDimitry Andric 3790b57cec5SDimitry Andric def P9_DFU_76C : SchedWriteRes<[DFU]> { 3800b57cec5SDimitry Andric let Latency = 76; 3815f757f3fSDimitry Andric let ReleaseAtCycles = [62]; 3820b57cec5SDimitry Andric } 3830b57cec5SDimitry Andric 3840b57cec5SDimitry Andric // 2 or 5 cycle latencies for the branch unit. 3850b57cec5SDimitry Andric def P9_BR_2C : SchedWriteRes<[BR]> { 3860b57cec5SDimitry Andric let Latency = 2; 3870b57cec5SDimitry Andric } 3880b57cec5SDimitry Andric 3890b57cec5SDimitry Andric def P9_BR_5C : SchedWriteRes<[BR]> { 3900b57cec5SDimitry Andric let Latency = 5; 3910b57cec5SDimitry Andric } 3920b57cec5SDimitry Andric 3930b57cec5SDimitry Andric // 6 cycle latency for the crypto unit 3940b57cec5SDimitry Andric def P9_CY_6C : SchedWriteRes<[CY]> { 3950b57cec5SDimitry Andric let Latency = 6; 3960b57cec5SDimitry Andric } 3970b57cec5SDimitry Andric 3980b57cec5SDimitry Andric // ***************** WriteSeq Definitions ***************** 3990b57cec5SDimitry Andric 4000b57cec5SDimitry Andric // These are combinations of the resources listed above. 4010b57cec5SDimitry Andric // The idea is that some cracked instructions cannot be done in parallel and 4020b57cec5SDimitry Andric // so the latencies for their resources must be added. 4030b57cec5SDimitry Andric def P9_LoadAndALUOp_6C : WriteSequence<[P9_LS_4C, P9_ALU_2C]>; 4040b57cec5SDimitry Andric def P9_LoadAndALUOp_7C : WriteSequence<[P9_LS_5C, P9_ALU_2C]>; 4050b57cec5SDimitry Andric def P9_LoadAndALU2Op_7C : WriteSequence<[P9_LS_4C, P9_ALU_3C]>; 4060b57cec5SDimitry Andric def P9_LoadAndALU2Op_8C : WriteSequence<[P9_LS_5C, P9_ALU_3C]>; 4070b57cec5SDimitry Andric def P9_LoadAndPMOp_8C : WriteSequence<[P9_LS_5C, P9_PM_3C]>; 4080b57cec5SDimitry Andric def P9_IntDivAndALUOp_18C_8 : WriteSequence<[P9_DIV_16C_8, P9_ALU_2C]>; 4090b57cec5SDimitry Andric def P9_IntDivAndALUOp_26C_8 : WriteSequence<[P9_DIV_24C_8, P9_ALU_2C]>; 4100b57cec5SDimitry Andric def P9_IntDivAndALUOp_42C_8 : WriteSequence<[P9_DIV_40C_8, P9_ALU_2C]>; 4110b57cec5SDimitry Andric def P9_StoreAndALUOp_3C : WriteSequence<[P9_LS_1C, P9_ALU_2C]>; 4120b57cec5SDimitry Andric def P9_ALUOpAndALUOp_4C : WriteSequence<[P9_ALU_2C, P9_ALU_2C]>; 4130b57cec5SDimitry Andric def P9_ALU2OpAndALU2Op_6C : WriteSequence<[P9_ALU_3C, P9_ALU_3C]>; 4140b57cec5SDimitry Andric def P9_ALUOpAndALUOpAndALUOp_6C : 4150b57cec5SDimitry Andric WriteSequence<[P9_ALU_2C, P9_ALU_2C, P9_ALU_2C]>; 4160b57cec5SDimitry Andric def P9_DPOpAndALUOp_7C : WriteSequence<[P9_DP_5C, P9_ALU_2C]>; 4170b57cec5SDimitry Andric def P9_DPOpAndALU2Op_10C : WriteSequence<[P9_DP_7C, P9_ALU_3C]>; 4180b57cec5SDimitry Andric def P9_DPOpAndALU2Op_25C_5 : WriteSequence<[P9_DP_22C_5, P9_ALU_3C]>; 4190b57cec5SDimitry Andric def P9_DPOpAndALU2Op_29C_5 : WriteSequence<[P9_DP_26C_5, P9_ALU_3C]>; 4200b57cec5SDimitry Andric def P9_DPOpAndALU2Op_36C_8 : WriteSequence<[P9_DP_33C_8, P9_ALU_3C]>; 4210b57cec5SDimitry Andric def P9_DPOpAndALU2Op_39C_10 : WriteSequence<[P9_DP_36C_10, P9_ALU_3C]>; 4220b57cec5SDimitry Andric def P9_BROpAndALUOp_7C : WriteSequence<[P9_BR_5C, P9_ALU_2C]>; 4230b57cec5SDimitry Andric 4240b57cec5SDimitry Andric // Include the resource requirements of individual instructions. 4250b57cec5SDimitry Andric include "P9InstrResources.td" 4260b57cec5SDimitry Andric 4270b57cec5SDimitry Andric} 4280b57cec5SDimitry Andric 429