1//===-- PPCScheduleP9.td - PPC P9 Scheduling Definitions ---*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the itinerary class data for the POWER9 processor.
10//
11//===----------------------------------------------------------------------===//
12include "PPCInstrInfo.td"
13
14def P9Model : SchedMachineModel {
15  // The maximum number of instructions to be issued at the same time.
16  // While a value of 8 is technically correct since 8 instructions can be
17  // fetched from the instruction cache. However, only 6 instructions may be
18  // actually dispatched at a time.
19  let IssueWidth = 8;
20
21  // Load latency is 4 or 5 cycles depending on the load. This latency assumes
22  // that we have a cache hit. For a cache miss the load latency will be more.
23  // There are two instructions (lxvl, lxvll) that have a latency of 6 cycles.
24  // However it is not worth bumping this value up to 6 when the vast majority
25  // of instructions are 4 or 5 cycles.
26  let LoadLatency = 5;
27
28  // A total of 16 cycles to recover from a branch mispredict.
29  let MispredictPenalty = 16;
30
31  // Try to make sure we have at least 10 dispatch groups in a loop.
32  // A dispatch group is 6 instructions.
33  let LoopMicroOpBufferSize = 60;
34
35  // As iops are dispatched to a slice, they are held in an independent slice
36  // issue queue until all register sources and other dependencies have been
37  // resolved and they can be issued. Each of four execution slices has an
38  // 11-entry iop issue queue.
39  let MicroOpBufferSize = 44;
40
41  let CompleteModel = 1;
42
43  // Do not support SPE (Signal Processing Engine), prefixed instructions on
44  // Power 9, paired vector mem ops, MMA, PC relative mem ops, or instructions
45  // introduced in ISA 3.1.
46  let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops, MMA,
47                             PCRelativeMemops, IsISA3_1];
48}
49
50let SchedModel = P9Model in {
51
52  // ***************** Processor Resources *****************
53
54  // Dispatcher slots:
55  // x0, x1, x2, and x3 are the dedicated slice dispatch ports, where each
56  // corresponds to one of the four execution slices.
57  def DISPx02 : ProcResource<2>;
58  def DISPx13 : ProcResource<2>;
59  // The xa and xb ports can be used to send an iop to either of the two slices
60  // of the superslice, but are restricted to iops with only two primary sources.
61  def DISPxab : ProcResource<2>;
62  // b0 and b1 are dedicated dispatch ports into the branch slice.
63  def DISPb01 : ProcResource<2>;
64
65  // Any non BR dispatch ports
66  def DISP_NBR
67      : ProcResGroup<[ DISPx02, DISPx13, DISPxab]>;
68  def DISP_SS : ProcResGroup<[ DISPx02, DISPx13]>;
69
70  // Issue Ports
71  // An instruction can go down one of two issue queues.
72  // Address Generation (AGEN) mainly for loads and stores.
73  // Execution (EXEC) for most other instructions.
74  // Some instructions cannot be run on just any issue queue and may require an
75  // Even or an Odd queue. The EXECE represents the even queues and the EXECO
76  // represents the odd queues.
77  def IP_AGEN : ProcResource<4>;
78  def IP_EXEC : ProcResource<4>;
79  def IP_EXECE : ProcResource<2> {
80    //Even Exec Ports
81    let Super = IP_EXEC;
82  }
83  def IP_EXECO : ProcResource<2> {
84    //Odd Exec Ports
85    let Super = IP_EXEC;
86  }
87
88  // Pipeline Groups
89  // Four ALU (Fixed Point Arithmetic) units in total. Two even, two Odd.
90  def ALU : ProcResource<4>;
91  def ALUE : ProcResource<2> {
92    //Even ALU pipelines
93    let Super = ALU;
94  }
95  def ALUO : ProcResource<2> {
96    //Odd ALU pipelines
97    let Super = ALU;
98  }
99
100  // Two DIV (Fixed Point Divide) units.
101  def DIV : ProcResource<2>;
102
103  // Four DP (Floating Point) units in total. Two even, two Odd.
104  def DP : ProcResource<4>;
105  def DPE : ProcResource<2> {
106    //Even DP pipelines
107    let Super = DP;
108  }
109  def DPO : ProcResource<2> {
110    //Odd DP pipelines
111    let Super = DP;
112  }
113
114  // Four LS (Load or Store) units.
115  def LS : ProcResource<4>;
116
117  // Two PM (Permute) units.
118  def PM : ProcResource<2>;
119
120  // Only one DFU (Decimal Floating Point and Quad Precision) unit.
121  def DFU : ProcResource<1>;
122
123  // Only one Branch unit.
124  def BR : ProcResource<1> {
125    let BufferSize = 16;
126  }
127
128  // Only one CY (Crypto) unit.
129  def CY : ProcResource<1>;
130
131  // ***************** SchedWriteRes Definitions *****************
132
133  // Dispatcher
134  // Dispatch Rules: '-' or 'V'
135  // Vector ('V') - vector iops (128-bit operand) take only one decode and
136  // dispatch slot but are dispatched to both the even and odd slices of a
137  // superslice.
138  def DISP_1C : SchedWriteRes<[DISP_NBR]> {
139    let NumMicroOps = 0;
140    let Latency = 1;
141  }
142  // Dispatch Rules: 'E'
143  // Even slice ('E')- certain operations must be sent only to an even slice.
144  // Also consumes odd dispatch slice slot of the same superslice at dispatch
145  def DISP_EVEN_1C : SchedWriteRes<[ DISPx02, DISPx13 ]> {
146    let NumMicroOps = 0;
147    let Latency = 1;
148  }
149  // Dispatch Rules: 'P'
150  // Paired ('P') - certain cracked and expanded iops are paired such that they
151  // must dispatch together to the same superslice.
152  def DISP_PAIR_1C : SchedWriteRes<[ DISP_SS, DISP_SS]> {
153    let NumMicroOps = 0;
154    let Latency = 1;
155  }
156  // Tuple Restricted ('R') - certain iops preclude dispatching more than one
157  // operation per slice for the super- slice to which they are dispatched
158  def DISP_3SLOTS_1C : SchedWriteRes<[DISPx02, DISPx13, DISPxab]> {
159    let NumMicroOps = 0;
160    let Latency = 1;
161  }
162  // Each execution and branch slice can receive up to two iops per cycle
163  def DISP_BR_1C : SchedWriteRes<[ DISPxab ]> {
164    let NumMicroOps = 0;
165    let Latency = 1;
166  }
167
168  // Issue Ports
169  def IP_AGEN_1C : SchedWriteRes<[IP_AGEN]> {
170    let NumMicroOps = 0;
171    let Latency = 1;
172  }
173
174  def IP_EXEC_1C : SchedWriteRes<[IP_EXEC]> {
175    let NumMicroOps = 0;
176    let Latency = 1;
177  }
178
179  def IP_EXECE_1C : SchedWriteRes<[IP_EXECE]> {
180    let NumMicroOps = 0;
181    let Latency = 1;
182  }
183
184  def IP_EXECO_1C : SchedWriteRes<[IP_EXECO]> {
185    let NumMicroOps = 0;
186    let Latency = 1;
187  }
188
189  //Pipeline Groups
190
191  // ALU Units
192  // An ALU may take either 2 or 3 cycles to complete the operation.
193  // However, the ALU unit is only ever busy for 1 cycle at a time and may
194  // receive new instructions each cycle.
195  def P9_ALU_2C : SchedWriteRes<[ALU]> {
196    let Latency = 2;
197  }
198
199  def P9_ALUE_2C : SchedWriteRes<[ALUE]> {
200    let Latency = 2;
201  }
202
203  def P9_ALUO_2C : SchedWriteRes<[ALUO]> {
204    let Latency = 2;
205  }
206
207  def P9_ALU_3C : SchedWriteRes<[ALU]> {
208    let Latency = 3;
209  }
210
211  def P9_ALUE_3C : SchedWriteRes<[ALUE]> {
212    let Latency = 3;
213  }
214
215  def P9_ALUO_3C : SchedWriteRes<[ALUO]> {
216    let Latency = 3;
217  }
218
219  // DIV Unit
220  // A DIV unit may take from 5 to 40 cycles to complete.
221  // Some DIV operations may keep the unit busy for up to 8 cycles.
222  def P9_DIV_5C : SchedWriteRes<[DIV]> {
223    let Latency = 5;
224  }
225
226  def P9_DIV_12C : SchedWriteRes<[DIV]> {
227    let Latency = 12;
228  }
229
230  def P9_DIV_16C_8 : SchedWriteRes<[DIV]> {
231    let ResourceCycles = [8];
232    let Latency = 16;
233  }
234
235  def P9_DIV_24C_8 : SchedWriteRes<[DIV]> {
236    let ResourceCycles = [8];
237    let Latency = 24;
238  }
239
240  def P9_DIV_40C_8 : SchedWriteRes<[DIV]> {
241    let ResourceCycles = [8];
242    let Latency = 40;
243  }
244
245  // DP Unit
246  // A DP unit may take from 2 to 36 cycles to complete.
247  // Some DP operations keep the unit busy for up to 10 cycles.
248  def P9_DP_5C : SchedWriteRes<[DP]> {
249    let Latency = 5;
250  }
251
252  def P9_DP_7C : SchedWriteRes<[DP]> {
253    let Latency = 7;
254  }
255
256  def P9_DPE_7C : SchedWriteRes<[DPE]> {
257    let Latency = 7;
258  }
259
260  def P9_DPO_7C : SchedWriteRes<[DPO]> {
261    let Latency = 7;
262  }
263
264  def P9_DP_22C_5 : SchedWriteRes<[DP]> {
265    let ResourceCycles = [5];
266    let Latency = 22;
267  }
268
269  def P9_DPO_24C_8 : SchedWriteRes<[DPO]> {
270    let ResourceCycles = [8];
271    let Latency = 24;
272  }
273
274  def P9_DPE_24C_8 : SchedWriteRes<[DPE]> {
275    let ResourceCycles = [8];
276    let Latency = 24;
277  }
278
279  def P9_DP_26C_5 : SchedWriteRes<[DP]> {
280    let ResourceCycles = [5];
281    let Latency = 22;
282  }
283
284  def P9_DPE_27C_10 : SchedWriteRes<[DP]> {
285    let ResourceCycles = [10];
286    let Latency = 27;
287  }
288
289  def P9_DPO_27C_10 : SchedWriteRes<[DP]> {
290    let ResourceCycles = [10];
291    let Latency = 27;
292  }
293
294  def P9_DP_33C_8 : SchedWriteRes<[DP]> {
295    let ResourceCycles = [8];
296    let Latency = 33;
297  }
298
299  def P9_DPE_33C_8 : SchedWriteRes<[DPE]> {
300    let ResourceCycles = [8];
301    let Latency = 33;
302  }
303
304  def P9_DPO_33C_8 : SchedWriteRes<[DPO]> {
305    let ResourceCycles = [8];
306    let Latency = 33;
307  }
308
309  def P9_DP_36C_10 : SchedWriteRes<[DP]> {
310    let ResourceCycles = [10];
311    let Latency = 36;
312  }
313
314  def P9_DPE_36C_10 : SchedWriteRes<[DP]> {
315    let ResourceCycles = [10];
316    let Latency = 36;
317  }
318
319  def P9_DPO_36C_10 : SchedWriteRes<[DP]> {
320    let ResourceCycles = [10];
321    let Latency = 36;
322  }
323
324  // PM Unit
325  // Three cycle permute operations.
326  def P9_PM_3C : SchedWriteRes<[PM]> {
327    let Latency = 3;
328  }
329
330  // Load and Store Units
331  // Loads can have 4, 5 or 6 cycles of latency.
332  // Stores are listed as having a single cycle of latency. This is not
333  // completely accurate since it takes more than 1 cycle to actually store
334  // the value. However, since the store does not produce a result it can be
335  // considered complete after one cycle.
336  def P9_LS_1C : SchedWriteRes<[LS]> {
337    let Latency = 1;
338  }
339
340  def P9_LS_4C : SchedWriteRes<[LS]> {
341    let Latency = 4;
342  }
343
344  def P9_LS_5C : SchedWriteRes<[LS]> {
345    let Latency = 5;
346  }
347
348  def P9_LS_6C : SchedWriteRes<[LS]> {
349    let Latency = 6;
350  }
351
352  // DFU Unit
353  // Some of the most expensive ops use the DFU.
354  // Can take from 12 cycles to 76 cycles to obtain a result.
355  // The unit may be busy for up to 62 cycles.
356  def P9_DFU_12C : SchedWriteRes<[DFU]> {
357    let Latency = 12;
358  }
359
360  def P9_DFU_23C : SchedWriteRes<[DFU]> {
361    let Latency = 23;
362    let ResourceCycles = [11];
363  }
364
365  def P9_DFU_24C : SchedWriteRes<[DFU]> {
366    let Latency = 24;
367    let ResourceCycles = [12];
368  }
369
370  def P9_DFU_37C : SchedWriteRes<[DFU]> {
371    let Latency = 37;
372    let ResourceCycles = [25];
373  }
374
375  def P9_DFU_58C : SchedWriteRes<[DFU]> {
376    let Latency = 58;
377    let ResourceCycles = [44];
378  }
379
380  def P9_DFU_76C : SchedWriteRes<[DFU]> {
381    let Latency = 76;
382    let ResourceCycles = [62];
383  }
384
385  // 2 or 5 cycle latencies for the branch unit.
386  def P9_BR_2C : SchedWriteRes<[BR]> {
387    let Latency = 2;
388  }
389
390  def P9_BR_5C : SchedWriteRes<[BR]> {
391    let Latency = 5;
392  }
393
394  // 6 cycle latency for the crypto unit
395  def P9_CY_6C : SchedWriteRes<[CY]> {
396    let Latency = 6;
397  }
398
399  // ***************** WriteSeq Definitions *****************
400
401  // These are combinations of the resources listed above.
402  // The idea is that some cracked instructions cannot be done in parallel and
403  // so the latencies for their resources must be added.
404  def P9_LoadAndALUOp_6C : WriteSequence<[P9_LS_4C, P9_ALU_2C]>;
405  def P9_LoadAndALUOp_7C : WriteSequence<[P9_LS_5C, P9_ALU_2C]>;
406  def P9_LoadAndALU2Op_7C : WriteSequence<[P9_LS_4C, P9_ALU_3C]>;
407  def P9_LoadAndALU2Op_8C : WriteSequence<[P9_LS_5C, P9_ALU_3C]>;
408  def P9_LoadAndPMOp_8C : WriteSequence<[P9_LS_5C, P9_PM_3C]>;
409  def P9_LoadAndLoadOp_8C : WriteSequence<[P9_LS_4C, P9_LS_4C]>;
410  def P9_IntDivAndALUOp_18C_8 : WriteSequence<[P9_DIV_16C_8, P9_ALU_2C]>;
411  def P9_IntDivAndALUOp_26C_8 : WriteSequence<[P9_DIV_24C_8, P9_ALU_2C]>;
412  def P9_IntDivAndALUOp_42C_8 : WriteSequence<[P9_DIV_40C_8, P9_ALU_2C]>;
413  def P9_StoreAndALUOp_3C : WriteSequence<[P9_LS_1C, P9_ALU_2C]>;
414  def P9_ALUOpAndALUOp_4C : WriteSequence<[P9_ALU_2C, P9_ALU_2C]>;
415  def P9_ALU2OpAndALU2Op_6C : WriteSequence<[P9_ALU_3C, P9_ALU_3C]>;
416  def P9_ALUOpAndALUOpAndALUOp_6C :
417    WriteSequence<[P9_ALU_2C, P9_ALU_2C, P9_ALU_2C]>;
418  def P9_DPOpAndALUOp_7C : WriteSequence<[P9_DP_5C, P9_ALU_2C]>;
419  def P9_DPOpAndALU2Op_10C : WriteSequence<[P9_DP_7C, P9_ALU_3C]>;
420  def P9_DPOpAndALU2Op_25C_5 : WriteSequence<[P9_DP_22C_5, P9_ALU_3C]>;
421  def P9_DPOpAndALU2Op_29C_5 : WriteSequence<[P9_DP_26C_5, P9_ALU_3C]>;
422  def P9_DPOpAndALU2Op_36C_8 : WriteSequence<[P9_DP_33C_8, P9_ALU_3C]>;
423  def P9_DPOpAndALU2Op_39C_10 : WriteSequence<[P9_DP_36C_10, P9_ALU_3C]>;
424  def P9_BROpAndALUOp_7C : WriteSequence<[P9_BR_5C, P9_ALU_2C]>;
425
426  // Include the resource requirements of individual instructions.
427  include "P9InstrResources.td"
428
429}
430
431