1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the PPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCSubtarget.h"
14 #include "GISel/PPCCallLowering.h"
15 #include "GISel/PPCLegalizerInfo.h"
16 #include "GISel/PPCRegisterBankInfo.h"
17 #include "PPC.h"
18 #include "PPCRegisterInfo.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineScheduler.h"
24 #include "llvm/IR/Attributes.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalValue.h"
27 #include "llvm/MC/TargetRegistry.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include <cstdlib>
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "ppc-subtarget"
35 
36 #define GET_SUBTARGETINFO_TARGET_DESC
37 #define GET_SUBTARGETINFO_CTOR
38 #include "PPCGenSubtargetInfo.inc"
39 
40 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
41 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
42 
43 static cl::opt<bool>
44     EnableMachinePipeliner("ppc-enable-pipeliner",
45                            cl::desc("Enable Machine Pipeliner for PPC"),
46                            cl::init(false), cl::Hidden);
47 
48 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
49                                                             StringRef FS) {
50   initializeEnvironment();
51   initSubtargetFeatures(CPU, FS);
52   return *this;
53 }
54 
55 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
56                            const std::string &FS, const PPCTargetMachine &TM)
57     : PPCGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT),
58       IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
59               TargetTriple.getArch() == Triple::ppc64le),
60       TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
61       InstrInfo(*this), TLInfo(TM, *this) {
62   CallLoweringInfo.reset(new PPCCallLowering(*getTargetLowering()));
63   Legalizer.reset(new PPCLegalizerInfo(*this));
64   auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo());
65   RegBankInfo.reset(RBI);
66 
67   InstSelector.reset(createPPCInstructionSelector(
68       *static_cast<const PPCTargetMachine *>(&TM), *this, *RBI));
69 }
70 
71 void PPCSubtarget::initializeEnvironment() {
72   StackAlignment = Align(16);
73   CPUDirective = PPC::DIR_NONE;
74   HasMFOCRF = false;
75   Has64BitSupport = false;
76   Use64BitRegs = false;
77   UseCRBits = false;
78   HasHardFloat = false;
79   HasAltivec = false;
80   HasSPE = false;
81   HasEFPU2 = false;
82   HasFPU = false;
83   HasVSX = false;
84   NeedsTwoConstNR = false;
85   HasP8Vector = false;
86   HasP8Altivec = false;
87   HasP8Crypto = false;
88   HasP9Vector = false;
89   HasP9Altivec = false;
90   HasMMA = false;
91   HasROPProtect = false;
92   HasPrivileged = false;
93   HasP10Vector = false;
94   HasPrefixInstrs = false;
95   HasPCRelativeMemops = false;
96   HasFCPSGN = false;
97   HasFSQRT = false;
98   HasFRE = false;
99   HasFRES = false;
100   HasFRSQRTE = false;
101   HasFRSQRTES = false;
102   HasRecipPrec = false;
103   HasSTFIWX = false;
104   HasLFIWAX = false;
105   HasFPRND = false;
106   HasFPCVT = false;
107   HasISEL = false;
108   HasBPERMD = false;
109   HasExtDiv = false;
110   HasCMPB = false;
111   HasLDBRX = false;
112   IsBookE = false;
113   HasOnlyMSYNC = false;
114   IsPPC4xx = false;
115   IsPPC6xx = false;
116   IsE500 = false;
117   FeatureMFTB = false;
118   AllowsUnalignedFPAccess = false;
119   DeprecatedDST = false;
120   HasICBT = false;
121   HasInvariantFunctionDescriptors = false;
122   HasPartwordAtomics = false;
123   HasQuadwordAtomics = false;
124   HasDirectMove = false;
125   HasHTM = false;
126   HasFloat128 = false;
127   HasFusion = false;
128   HasStoreFusion = false;
129   HasAddiLoadFusion = false;
130   HasAddisLoadFusion = false;
131   HasArithAddFusion = false;
132   HasAddLogicalFusion = false;
133   HasLogicalAddFusion = false;
134   HasLogicalFusion = false;
135   HasSha3Fusion = false;
136   HasCompareFusion = false;
137   HasWideImmFusion = false;
138   HasZeroMoveFusion = false;
139   HasBack2BackFusion = false;
140   IsISA2_06 = false;
141   IsISA2_07 = false;
142   IsISA3_0 = false;
143   IsISA3_1 = false;
144   IsISAFuture = false;
145   UseLongCalls = false;
146   SecurePlt = false;
147   VectorsUseTwoUnits = false;
148   UsePPCPreRASchedStrategy = false;
149   UsePPCPostRASchedStrategy = false;
150   PairedVectorMemops = false;
151   PredictableSelectIsExpensive = false;
152   HasModernAIXAs = false;
153   IsAIX = false;
154 
155   HasPOPCNTD = POPCNTD_Unavailable;
156 }
157 
158 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
159   // Determine default and user specified characteristics
160   std::string CPUName = std::string(CPU);
161   if (CPUName.empty() || CPU == "generic") {
162     // If cross-compiling with -march=ppc64le without -mcpu
163     if (TargetTriple.getArch() == Triple::ppc64le)
164       CPUName = "ppc64le";
165     else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)
166       CPUName = "e500";
167     else
168       CPUName = "generic";
169   }
170 
171   // Initialize scheduling itinerary for the specified CPU.
172   InstrItins = getInstrItineraryForCPU(CPUName);
173 
174   // Parse features string.
175   ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
176 
177   // If the user requested use of 64-bit regs, but the cpu selected doesn't
178   // support it, ignore.
179   if (IsPPC64 && has64BitSupport())
180     Use64BitRegs = true;
181 
182   if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) ||
183       TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() ||
184       TargetTriple.isMusl())
185     SecurePlt = true;
186 
187   if (HasSPE && IsPPC64)
188     report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
189   if (HasSPE && (HasAltivec || HasVSX || HasFPU))
190     report_fatal_error(
191         "SPE and traditional floating point cannot both be enabled.\n", false);
192 
193   // If not SPE, set standard FPU
194   if (!HasSPE)
195     HasFPU = true;
196 
197   StackAlignment = getPlatformStackAlignment();
198 
199   // Determine endianness.
200   IsLittleEndian = TM.isLittleEndian();
201 }
202 
203 bool PPCSubtarget::enableMachineScheduler() const { return true; }
204 
205 bool PPCSubtarget::enableMachinePipeliner() const {
206   return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner;
207 }
208 
209 bool PPCSubtarget::useDFAforSMS() const { return false; }
210 
211 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
212 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
213 
214 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
215   return TargetSubtargetInfo::ANTIDEP_ALL;
216 }
217 
218 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
219   CriticalPathRCs.clear();
220   CriticalPathRCs.push_back(isPPC64() ?
221                             &PPC::G8RCRegClass : &PPC::GPRCRegClass);
222 }
223 
224 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
225                                        unsigned NumRegionInstrs) const {
226   // The GenericScheduler that we use defaults to scheduling bottom up only.
227   // We want to schedule from both the top and the bottom and so we set
228   // OnlyBottomUp to false.
229   // We want to do bi-directional scheduling since it provides a more balanced
230   // schedule leading to better performance.
231   Policy.OnlyBottomUp = false;
232   // Spilling is generally expensive on all PPC cores, so always enable
233   // register-pressure tracking.
234   Policy.ShouldTrackPressure = true;
235 }
236 
237 bool PPCSubtarget::useAA() const {
238   return true;
239 }
240 
241 bool PPCSubtarget::enableSubRegLiveness() const {
242   return UseSubRegLiveness;
243 }
244 
245 bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
246   // Large code model always uses the TOC even for local symbols.
247   if (TM.getCodeModel() == CodeModel::Large)
248     return true;
249   if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
250     return false;
251   return true;
252 }
253 
254 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
255 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
256 
257 bool PPCSubtarget::isUsingPCRelativeCalls() const {
258   return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() &&
259          CodeModel::Medium == getTargetMachine().getCodeModel();
260 }
261 
262 // GlobalISEL
263 const CallLowering *PPCSubtarget::getCallLowering() const {
264   return CallLoweringInfo.get();
265 }
266 
267 const RegisterBankInfo *PPCSubtarget::getRegBankInfo() const {
268   return RegBankInfo.get();
269 }
270 
271 const LegalizerInfo *PPCSubtarget::getLegalizerInfo() const {
272   return Legalizer.get();
273 }
274 
275 InstructionSelector *PPCSubtarget::getInstructionSelector() const {
276   return InstSelector.get();
277 }
278