1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the PPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCSubtarget.h"
14 #include "GISel/PPCCallLowering.h"
15 #include "GISel/PPCLegalizerInfo.h"
16 #include "GISel/PPCRegisterBankInfo.h"
17 #include "PPC.h"
18 #include "PPCRegisterInfo.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineScheduler.h"
23 #include "llvm/IR/Attributes.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/IR/GlobalValue.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include <cstdlib>
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "ppc-subtarget"
34 
35 #define GET_SUBTARGETINFO_TARGET_DESC
36 #define GET_SUBTARGETINFO_CTOR
37 #include "PPCGenSubtargetInfo.inc"
38 
39 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
40 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
41 
42 static cl::opt<bool>
43     EnableMachinePipeliner("ppc-enable-pipeliner",
44                            cl::desc("Enable Machine Pipeliner for PPC"),
45                            cl::init(false), cl::Hidden);
46 
47 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
48                                                             StringRef FS) {
49   initializeEnvironment();
50   initSubtargetFeatures(CPU, FS);
51   return *this;
52 }
53 
54 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
55                            const std::string &FS, const PPCTargetMachine &TM)
56     : PPCGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT),
57       IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
58               TargetTriple.getArch() == Triple::ppc64le),
59       TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
60       InstrInfo(*this), TLInfo(TM, *this) {
61   CallLoweringInfo.reset(new PPCCallLowering(*getTargetLowering()));
62   Legalizer.reset(new PPCLegalizerInfo(*this));
63   auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo());
64   RegBankInfo.reset(RBI);
65 
66   InstSelector.reset(createPPCInstructionSelector(
67       *static_cast<const PPCTargetMachine *>(&TM), *this, *RBI));
68 }
69 
70 void PPCSubtarget::initializeEnvironment() {
71   StackAlignment = Align(16);
72   CPUDirective = PPC::DIR_NONE;
73   HasMFOCRF = false;
74   Has64BitSupport = false;
75   Use64BitRegs = false;
76   UseCRBits = false;
77   HasHardFloat = false;
78   HasAltivec = false;
79   HasSPE = false;
80   HasEFPU2 = false;
81   HasFPU = false;
82   HasVSX = false;
83   NeedsTwoConstNR = false;
84   HasP8Vector = false;
85   HasP8Altivec = false;
86   HasP8Crypto = false;
87   HasP9Vector = false;
88   HasP9Altivec = false;
89   HasMMA = false;
90   HasROPProtect = false;
91   HasPrivileged = false;
92   HasP10Vector = false;
93   HasPrefixInstrs = false;
94   HasPCRelativeMemops = false;
95   HasFCPSGN = false;
96   HasFSQRT = false;
97   HasFRE = false;
98   HasFRES = false;
99   HasFRSQRTE = false;
100   HasFRSQRTES = false;
101   HasRecipPrec = false;
102   HasSTFIWX = false;
103   HasLFIWAX = false;
104   HasFPRND = false;
105   HasFPCVT = false;
106   HasISEL = false;
107   HasBPERMD = false;
108   HasExtDiv = false;
109   HasCMPB = false;
110   HasLDBRX = false;
111   IsBookE = false;
112   HasOnlyMSYNC = false;
113   IsPPC4xx = false;
114   IsPPC6xx = false;
115   IsE500 = false;
116   FeatureMFTB = false;
117   AllowsUnalignedFPAccess = false;
118   DeprecatedDST = false;
119   HasICBT = false;
120   HasInvariantFunctionDescriptors = false;
121   HasPartwordAtomics = false;
122   HasQuadwordAtomics = false;
123   HasDirectMove = false;
124   HasHTM = false;
125   HasFloat128 = false;
126   HasFusion = false;
127   HasStoreFusion = false;
128   HasAddiLoadFusion = false;
129   HasAddisLoadFusion = false;
130   IsISA2_07 = false;
131   IsISA3_0 = false;
132   IsISA3_1 = false;
133   UseLongCalls = false;
134   SecurePlt = false;
135   VectorsUseTwoUnits = false;
136   UsePPCPreRASchedStrategy = false;
137   UsePPCPostRASchedStrategy = false;
138   PairedVectorMemops = false;
139   PredictableSelectIsExpensive = false;
140   HasModernAIXAs = false;
141   IsAIX = false;
142 
143   HasPOPCNTD = POPCNTD_Unavailable;
144 }
145 
146 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
147   // Determine default and user specified characteristics
148   std::string CPUName = std::string(CPU);
149   if (CPUName.empty() || CPU == "generic") {
150     // If cross-compiling with -march=ppc64le without -mcpu
151     if (TargetTriple.getArch() == Triple::ppc64le)
152       CPUName = "ppc64le";
153     else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)
154       CPUName = "e500";
155     else
156       CPUName = "generic";
157   }
158 
159   // Initialize scheduling itinerary for the specified CPU.
160   InstrItins = getInstrItineraryForCPU(CPUName);
161 
162   // Parse features string.
163   ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
164 
165   // If the user requested use of 64-bit regs, but the cpu selected doesn't
166   // support it, ignore.
167   if (IsPPC64 && has64BitSupport())
168     Use64BitRegs = true;
169 
170   if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) ||
171       TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() ||
172       TargetTriple.isMusl())
173     SecurePlt = true;
174 
175   if (HasSPE && IsPPC64)
176     report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
177   if (HasSPE && (HasAltivec || HasVSX || HasFPU))
178     report_fatal_error(
179         "SPE and traditional floating point cannot both be enabled.\n", false);
180 
181   // If not SPE, set standard FPU
182   if (!HasSPE)
183     HasFPU = true;
184 
185   StackAlignment = getPlatformStackAlignment();
186 
187   // Determine endianness.
188   IsLittleEndian = TM.isLittleEndian();
189 }
190 
191 bool PPCSubtarget::enableMachineScheduler() const { return true; }
192 
193 bool PPCSubtarget::enableMachinePipeliner() const {
194   return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner;
195 }
196 
197 bool PPCSubtarget::useDFAforSMS() const { return false; }
198 
199 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
200 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
201 
202 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
203   return TargetSubtargetInfo::ANTIDEP_ALL;
204 }
205 
206 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
207   CriticalPathRCs.clear();
208   CriticalPathRCs.push_back(isPPC64() ?
209                             &PPC::G8RCRegClass : &PPC::GPRCRegClass);
210 }
211 
212 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
213                                        unsigned NumRegionInstrs) const {
214   // The GenericScheduler that we use defaults to scheduling bottom up only.
215   // We want to schedule from both the top and the bottom and so we set
216   // OnlyBottomUp to false.
217   // We want to do bi-directional scheduling since it provides a more balanced
218   // schedule leading to better performance.
219   Policy.OnlyBottomUp = false;
220   // Spilling is generally expensive on all PPC cores, so always enable
221   // register-pressure tracking.
222   Policy.ShouldTrackPressure = true;
223 }
224 
225 bool PPCSubtarget::useAA() const {
226   return true;
227 }
228 
229 bool PPCSubtarget::enableSubRegLiveness() const {
230   return UseSubRegLiveness;
231 }
232 
233 bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
234   // Large code model always uses the TOC even for local symbols.
235   if (TM.getCodeModel() == CodeModel::Large)
236     return true;
237   if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
238     return false;
239   return true;
240 }
241 
242 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
243 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
244 
245 bool PPCSubtarget::isUsingPCRelativeCalls() const {
246   return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() &&
247          CodeModel::Medium == getTargetMachine().getCodeModel();
248 }
249 
250 // GlobalISEL
251 const CallLowering *PPCSubtarget::getCallLowering() const {
252   return CallLoweringInfo.get();
253 }
254 
255 const RegisterBankInfo *PPCSubtarget::getRegBankInfo() const {
256   return RegBankInfo.get();
257 }
258 
259 const LegalizerInfo *PPCSubtarget::getLegalizerInfo() const {
260   return Legalizer.get();
261 }
262 
263 InstructionSelector *PPCSubtarget::getInstructionSelector() const {
264   return InstSelector.get();
265 }
266