1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares the PowerPC specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H 14 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H 15 16 #include "PPCFrameLowering.h" 17 #include "PPCISelLowering.h" 18 #include "PPCInstrInfo.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 21 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 22 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 23 #include "llvm/CodeGen/SelectionDAGTargetInfo.h" 24 #include "llvm/CodeGen/TargetSubtargetInfo.h" 25 #include "llvm/IR/DataLayout.h" 26 #include "llvm/MC/MCInstrItineraries.h" 27 #include <string> 28 29 #define GET_SUBTARGETINFO_HEADER 30 #include "PPCGenSubtargetInfo.inc" 31 32 // GCC #defines PPC on Linux but we use it as our namespace name 33 #undef PPC 34 35 namespace llvm { 36 class StringRef; 37 38 namespace PPC { 39 // -m directive values. 40 enum { 41 DIR_NONE, 42 DIR_32, 43 DIR_440, 44 DIR_601, 45 DIR_602, 46 DIR_603, 47 DIR_7400, 48 DIR_750, 49 DIR_970, 50 DIR_A2, 51 DIR_E500, 52 DIR_E500mc, 53 DIR_E5500, 54 DIR_PWR3, 55 DIR_PWR4, 56 DIR_PWR5, 57 DIR_PWR5X, 58 DIR_PWR6, 59 DIR_PWR6X, 60 DIR_PWR7, 61 DIR_PWR8, 62 DIR_PWR9, 63 DIR_PWR10, 64 DIR_PWR_FUTURE, 65 DIR_64 66 }; 67 } 68 69 class GlobalValue; 70 71 class PPCSubtarget : public PPCGenSubtargetInfo { 72 public: 73 enum POPCNTDKind { 74 POPCNTD_Unavailable, 75 POPCNTD_Slow, 76 POPCNTD_Fast 77 }; 78 79 protected: 80 /// TargetTriple - What processor and OS we're targeting. 81 Triple TargetTriple; 82 83 /// stackAlignment - The minimum alignment known to hold of the stack frame on 84 /// entry to the function and which must be maintained by every function. 85 Align StackAlignment; 86 87 /// Selected instruction itineraries (one entry per itinerary class.) 88 InstrItineraryData InstrItins; 89 90 /// Which cpu directive was used. 91 unsigned CPUDirective; 92 93 /// Used by the ISel to turn in optimizations for POWER4-derived architectures 94 bool HasMFOCRF; 95 bool Has64BitSupport; 96 bool Use64BitRegs; 97 bool UseCRBits; 98 bool HasHardFloat; 99 bool IsPPC64; 100 bool HasAltivec; 101 bool HasFPU; 102 bool HasSPE; 103 bool HasEFPU2; 104 bool HasVSX; 105 bool NeedsTwoConstNR; 106 bool HasP8Vector; 107 bool HasP8Altivec; 108 bool HasP8Crypto; 109 bool HasP9Vector; 110 bool HasP9Altivec; 111 bool HasP10Vector; 112 bool HasPrefixInstrs; 113 bool HasPCRelativeMemops; 114 bool HasMMA; 115 bool HasFCPSGN; 116 bool HasFSQRT; 117 bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES; 118 bool HasRecipPrec; 119 bool HasSTFIWX; 120 bool HasLFIWAX; 121 bool HasFPRND; 122 bool HasFPCVT; 123 bool HasISEL; 124 bool HasBPERMD; 125 bool HasExtDiv; 126 bool HasCMPB; 127 bool HasLDBRX; 128 bool IsBookE; 129 bool HasOnlyMSYNC; 130 bool IsE500; 131 bool IsPPC4xx; 132 bool IsPPC6xx; 133 bool FeatureMFTB; 134 bool AllowsUnalignedFPAccess; 135 bool DeprecatedDST; 136 bool IsLittleEndian; 137 bool HasICBT; 138 bool HasInvariantFunctionDescriptors; 139 bool HasPartwordAtomics; 140 bool HasDirectMove; 141 bool HasHTM; 142 bool HasFloat128; 143 bool HasFusion; 144 bool HasStoreFusion; 145 bool HasAddiLoadFusion; 146 bool HasAddisLoadFusion; 147 bool IsISA3_0; 148 bool IsISA3_1; 149 bool UseLongCalls; 150 bool SecurePlt; 151 bool VectorsUseTwoUnits; 152 bool UsePPCPreRASchedStrategy; 153 bool UsePPCPostRASchedStrategy; 154 bool PairedVectorMemops; 155 bool PredictableSelectIsExpensive; 156 bool HasModernAIXAs; 157 bool IsAIX; 158 159 POPCNTDKind HasPOPCNTD; 160 161 const PPCTargetMachine &TM; 162 PPCFrameLowering FrameLowering; 163 PPCInstrInfo InstrInfo; 164 PPCTargetLowering TLInfo; 165 SelectionDAGTargetInfo TSInfo; 166 167 /// GlobalISel related APIs. 168 std::unique_ptr<CallLowering> CallLoweringInfo; 169 std::unique_ptr<LegalizerInfo> Legalizer; 170 std::unique_ptr<RegisterBankInfo> RegBankInfo; 171 std::unique_ptr<InstructionSelector> InstSelector; 172 173 public: 174 /// This constructor initializes the data members to match that 175 /// of the specified triple. 176 /// 177 PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, 178 const PPCTargetMachine &TM); 179 180 /// ParseSubtargetFeatures - Parses features string setting specified 181 /// subtarget options. Definition of function is auto generated by tblgen. 182 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); 183 184 /// getStackAlignment - Returns the minimum alignment known to hold of the 185 /// stack frame on entry to the function and which must be maintained by every 186 /// function for this subtarget. 187 Align getStackAlignment() const { return StackAlignment; } 188 189 /// getCPUDirective - Returns the -m directive specified for the cpu. 190 /// 191 unsigned getCPUDirective() const { return CPUDirective; } 192 193 /// getInstrItins - Return the instruction itineraries based on subtarget 194 /// selection. 195 const InstrItineraryData *getInstrItineraryData() const override { 196 return &InstrItins; 197 } 198 199 const PPCFrameLowering *getFrameLowering() const override { 200 return &FrameLowering; 201 } 202 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; } 203 const PPCTargetLowering *getTargetLowering() const override { 204 return &TLInfo; 205 } 206 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { 207 return &TSInfo; 208 } 209 const PPCRegisterInfo *getRegisterInfo() const override { 210 return &getInstrInfo()->getRegisterInfo(); 211 } 212 const PPCTargetMachine &getTargetMachine() const { return TM; } 213 214 /// initializeSubtargetDependencies - Initializes using a CPU and feature string 215 /// so that we can use initializer lists for subtarget initialization. 216 PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); 217 218 private: 219 void initializeEnvironment(); 220 void initSubtargetFeatures(StringRef CPU, StringRef FS); 221 222 public: 223 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode. 224 /// 225 bool isPPC64() const; 226 227 /// has64BitSupport - Return true if the selected CPU supports 64-bit 228 /// instructions, regardless of whether we are in 32-bit or 64-bit mode. 229 bool has64BitSupport() const { return Has64BitSupport; } 230 // useSoftFloat - Return true if soft-float option is turned on. 231 bool useSoftFloat() const { 232 if (isAIXABI() && !HasHardFloat) 233 report_fatal_error("soft-float is not yet supported on AIX."); 234 return !HasHardFloat; 235 } 236 237 /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit 238 /// registers in 32-bit mode when possible. This can only true if 239 /// has64BitSupport() returns true. 240 bool use64BitRegs() const { return Use64BitRegs; } 241 242 /// useCRBits - Return true if we should store and manipulate i1 values in 243 /// the individual condition register bits. 244 bool useCRBits() const { return UseCRBits; } 245 246 // isLittleEndian - True if generating little-endian code 247 bool isLittleEndian() const { return IsLittleEndian; } 248 249 // Specific obvious features. 250 bool hasFCPSGN() const { return HasFCPSGN; } 251 bool hasFSQRT() const { return HasFSQRT; } 252 bool hasFRE() const { return HasFRE; } 253 bool hasFRES() const { return HasFRES; } 254 bool hasFRSQRTE() const { return HasFRSQRTE; } 255 bool hasFRSQRTES() const { return HasFRSQRTES; } 256 bool hasRecipPrec() const { return HasRecipPrec; } 257 bool hasSTFIWX() const { return HasSTFIWX; } 258 bool hasLFIWAX() const { return HasLFIWAX; } 259 bool hasFPRND() const { return HasFPRND; } 260 bool hasFPCVT() const { return HasFPCVT; } 261 bool hasAltivec() const { return HasAltivec; } 262 bool hasSPE() const { return HasSPE; } 263 bool hasEFPU2() const { return HasEFPU2; } 264 bool hasFPU() const { return HasFPU; } 265 bool hasVSX() const { return HasVSX; } 266 bool needsTwoConstNR() const { return NeedsTwoConstNR; } 267 bool hasP8Vector() const { return HasP8Vector; } 268 bool hasP8Altivec() const { return HasP8Altivec; } 269 bool hasP8Crypto() const { return HasP8Crypto; } 270 bool hasP9Vector() const { return HasP9Vector; } 271 bool hasP9Altivec() const { return HasP9Altivec; } 272 bool hasP10Vector() const { return HasP10Vector; } 273 bool hasPrefixInstrs() const { return HasPrefixInstrs; } 274 bool hasPCRelativeMemops() const { return HasPCRelativeMemops; } 275 bool hasMMA() const { return HasMMA; } 276 bool pairedVectorMemops() const { return PairedVectorMemops; } 277 bool hasMFOCRF() const { return HasMFOCRF; } 278 bool hasISEL() const { return HasISEL; } 279 bool hasBPERMD() const { return HasBPERMD; } 280 bool hasExtDiv() const { return HasExtDiv; } 281 bool hasCMPB() const { return HasCMPB; } 282 bool hasLDBRX() const { return HasLDBRX; } 283 bool isBookE() const { return IsBookE; } 284 bool hasOnlyMSYNC() const { return HasOnlyMSYNC; } 285 bool isPPC4xx() const { return IsPPC4xx; } 286 bool isPPC6xx() const { return IsPPC6xx; } 287 bool isSecurePlt() const {return SecurePlt; } 288 bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; } 289 bool isE500() const { return IsE500; } 290 bool isFeatureMFTB() const { return FeatureMFTB; } 291 bool allowsUnalignedFPAccess() const { return AllowsUnalignedFPAccess; } 292 bool isDeprecatedDST() const { return DeprecatedDST; } 293 bool hasICBT() const { return HasICBT; } 294 bool hasInvariantFunctionDescriptors() const { 295 return HasInvariantFunctionDescriptors; 296 } 297 bool usePPCPreRASchedStrategy() const { return UsePPCPreRASchedStrategy; } 298 bool usePPCPostRASchedStrategy() const { return UsePPCPostRASchedStrategy; } 299 bool hasPartwordAtomics() const { return HasPartwordAtomics; } 300 bool hasDirectMove() const { return HasDirectMove; } 301 302 Align getPlatformStackAlignment() const { 303 return Align(16); 304 } 305 306 unsigned getRedZoneSize() const { 307 if (isPPC64()) 308 // 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved) 309 return 288; 310 311 // AIX PPC32: 220 bytes = 18*8 (FPRs) + 19*4 (GPRs); 312 // PPC32 SVR4ABI has no redzone. 313 return isAIXABI() ? 220 : 0; 314 } 315 316 bool hasHTM() const { return HasHTM; } 317 bool hasFloat128() const { return HasFloat128; } 318 bool isISA3_0() const { return IsISA3_0; } 319 bool isISA3_1() const { return IsISA3_1; } 320 bool useLongCalls() const { return UseLongCalls; } 321 bool hasFusion() const { return HasFusion; } 322 bool hasStoreFusion() const { return HasStoreFusion; } 323 bool hasAddiLoadFusion() const { return HasAddiLoadFusion; } 324 bool hasAddisLoadFusion() const { return HasAddisLoadFusion; } 325 bool needsSwapsForVSXMemOps() const { 326 return hasVSX() && isLittleEndian() && !hasP9Vector(); 327 } 328 329 POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; } 330 331 const Triple &getTargetTriple() const { return TargetTriple; } 332 333 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } 334 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } 335 bool isTargetLinux() const { return TargetTriple.isOSLinux(); } 336 337 bool isAIXABI() const { return TargetTriple.isOSAIX(); } 338 bool isSVR4ABI() const { return !isAIXABI(); } 339 bool isELFv2ABI() const; 340 341 bool is64BitELFABI() const { return isSVR4ABI() && isPPC64(); } 342 bool is32BitELFABI() const { return isSVR4ABI() && !isPPC64(); } 343 bool isUsingPCRelativeCalls() const; 344 345 /// Originally, this function return hasISEL(). Now we always enable it, 346 /// but may expand the ISEL instruction later. 347 bool enableEarlyIfConversion() const override { return true; } 348 349 /// Scheduling customization. 350 bool enableMachineScheduler() const override; 351 /// Pipeliner customization. 352 bool enableMachinePipeliner() const override; 353 /// Machine Pipeliner customization 354 bool useDFAforSMS() const override; 355 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU. 356 bool enablePostRAScheduler() const override; 357 AntiDepBreakMode getAntiDepBreakMode() const override; 358 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override; 359 360 void overrideSchedPolicy(MachineSchedPolicy &Policy, 361 unsigned NumRegionInstrs) const override; 362 bool useAA() const override; 363 364 bool enableSubRegLiveness() const override; 365 366 /// True if the GV will be accessed via an indirect symbol. 367 bool isGVIndirectSymbol(const GlobalValue *GV) const; 368 369 /// True if the ABI is descriptor based. 370 bool usesFunctionDescriptors() const { 371 // Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit 372 // v1 ABI uses descriptors. 373 return isAIXABI() || (is64BitELFABI() && !isELFv2ABI()); 374 } 375 376 unsigned descriptorTOCAnchorOffset() const { 377 assert(usesFunctionDescriptors() && 378 "Should only be called when the target uses descriptors."); 379 return IsPPC64 ? 8 : 4; 380 } 381 382 unsigned descriptorEnvironmentPointerOffset() const { 383 assert(usesFunctionDescriptors() && 384 "Should only be called when the target uses descriptors."); 385 return IsPPC64 ? 16 : 8; 386 } 387 388 MCRegister getEnvironmentPointerRegister() const { 389 assert(usesFunctionDescriptors() && 390 "Should only be called when the target uses descriptors."); 391 return IsPPC64 ? PPC::X11 : PPC::R11; 392 } 393 394 MCRegister getTOCPointerRegister() const { 395 assert((is64BitELFABI() || isAIXABI()) && 396 "Should only be called when the target is a TOC based ABI."); 397 return IsPPC64 ? PPC::X2 : PPC::R2; 398 } 399 400 MCRegister getStackPointerRegister() const { 401 return IsPPC64 ? PPC::X1 : PPC::R1; 402 } 403 404 bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; } 405 406 bool isPredictableSelectIsExpensive() const { 407 return PredictableSelectIsExpensive; 408 } 409 410 // GlobalISEL 411 const CallLowering *getCallLowering() const override; 412 const RegisterBankInfo *getRegBankInfo() const override; 413 const LegalizerInfo *getLegalizerInfo() const override; 414 InstructionSelector *getInstructionSelector() const override; 415 }; 416 } // End llvm namespace 417 418 #endif 419