1 //===---------- PPCTLSDynamicCall.cpp - TLS Dynamic Call Fixup ------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This pass expands ADDItls{ld,gd}LADDR[32] machine instructions into 10 // separate ADDItls[gd]L[32] and GETtlsADDR[32] instructions, both of 11 // which define GPR3. A copy is added from GPR3 to the target virtual 12 // register of the original instruction. The GETtlsADDR[32] is really 13 // a call instruction, so its target register is constrained to be GPR3. 14 // This is not true of ADDItls[gd]L[32], but there is a legacy linker 15 // optimization bug that requires the target register of the addi of 16 // a local- or general-dynamic TLS access sequence to be GPR3. 17 // 18 // This is done in a late pass so that TLS variable accesses can be 19 // fully commoned by MachineCSE. 20 // 21 //===----------------------------------------------------------------------===// 22 23 #include "PPC.h" 24 #include "PPCInstrBuilder.h" 25 #include "PPCInstrInfo.h" 26 #include "PPCTargetMachine.h" 27 #include "llvm/CodeGen/LiveIntervals.h" 28 #include "llvm/CodeGen/MachineFunctionPass.h" 29 #include "llvm/CodeGen/MachineInstrBuilder.h" 30 #include "llvm/InitializePasses.h" 31 #include "llvm/Support/Debug.h" 32 #include "llvm/Support/raw_ostream.h" 33 34 using namespace llvm; 35 36 #define DEBUG_TYPE "ppc-tls-dynamic-call" 37 38 namespace { 39 struct PPCTLSDynamicCall : public MachineFunctionPass { 40 static char ID; 41 PPCTLSDynamicCall() : MachineFunctionPass(ID) { 42 initializePPCTLSDynamicCallPass(*PassRegistry::getPassRegistry()); 43 } 44 45 const PPCInstrInfo *TII; 46 LiveIntervals *LIS; 47 48 protected: 49 bool processBlock(MachineBasicBlock &MBB) { 50 bool Changed = false; 51 bool NeedFence = true; 52 bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64(); 53 bool IsPCREL = false; 54 55 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end(); 56 I != IE;) { 57 MachineInstr &MI = *I; 58 IsPCREL = isPCREL(MI); 59 60 if (MI.getOpcode() != PPC::ADDItlsgdLADDR && 61 MI.getOpcode() != PPC::ADDItlsldLADDR && 62 MI.getOpcode() != PPC::ADDItlsgdLADDR32 && 63 MI.getOpcode() != PPC::ADDItlsldLADDR32 && !IsPCREL) { 64 // Although we create ADJCALLSTACKDOWN and ADJCALLSTACKUP 65 // as scheduling fences, we skip creating fences if we already 66 // have existing ADJCALLSTACKDOWN/UP to avoid nesting, 67 // which causes verification error with -verify-machineinstrs. 68 if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN) 69 NeedFence = false; 70 else if (MI.getOpcode() == PPC::ADJCALLSTACKUP) 71 NeedFence = true; 72 73 ++I; 74 continue; 75 } 76 77 LLVM_DEBUG(dbgs() << "TLS Dynamic Call Fixup:\n " << MI); 78 79 Register OutReg = MI.getOperand(0).getReg(); 80 Register InReg = PPC::NoRegister; 81 Register GPR3 = Is64Bit ? PPC::X3 : PPC::R3; 82 SmallVector<Register, 3> OrigRegs = {OutReg, GPR3}; 83 if (!IsPCREL) { 84 InReg = MI.getOperand(1).getReg(); 85 OrigRegs.push_back(InReg); 86 } 87 DebugLoc DL = MI.getDebugLoc(); 88 89 unsigned Opc1, Opc2; 90 switch (MI.getOpcode()) { 91 default: 92 llvm_unreachable("Opcode inconsistency error"); 93 case PPC::ADDItlsgdLADDR: 94 Opc1 = PPC::ADDItlsgdL; 95 Opc2 = PPC::GETtlsADDR; 96 break; 97 case PPC::ADDItlsldLADDR: 98 Opc1 = PPC::ADDItlsldL; 99 Opc2 = PPC::GETtlsldADDR; 100 break; 101 case PPC::ADDItlsgdLADDR32: 102 Opc1 = PPC::ADDItlsgdL32; 103 Opc2 = PPC::GETtlsADDR32; 104 break; 105 case PPC::ADDItlsldLADDR32: 106 Opc1 = PPC::ADDItlsldL32; 107 Opc2 = PPC::GETtlsldADDR32; 108 break; 109 case PPC::PADDI8pc: 110 assert(IsPCREL && "Expecting General/Local Dynamic PCRel"); 111 Opc1 = PPC::PADDI8pc; 112 Opc2 = MI.getOperand(2).getTargetFlags() == 113 PPCII::MO_GOT_TLSGD_PCREL_FLAG 114 ? PPC::GETtlsADDRPCREL 115 : PPC::GETtlsldADDRPCREL; 116 } 117 118 // We create ADJCALLSTACKUP and ADJCALLSTACKDOWN around _tls_get_addr 119 // as scheduling fence to avoid it is scheduled before 120 // mflr in the prologue and the address in LR is clobbered (PR25839). 121 // We don't really need to save data to the stack - the clobbered 122 // registers are already saved when the SDNode (e.g. PPCaddiTlsgdLAddr) 123 // gets translated to the pseudo instruction (e.g. ADDItlsgdLADDR). 124 if (NeedFence) 125 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0) 126 .addImm(0); 127 128 MachineInstr *Addi; 129 if (IsPCREL) { 130 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addImm(0); 131 } else { 132 // Expand into two ops built prior to the existing instruction. 133 assert(InReg != PPC::NoRegister && "Operand must be a register"); 134 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addReg(InReg); 135 } 136 137 Addi->addOperand(MI.getOperand(2)); 138 139 // The ADDItls* instruction is the first instruction in the 140 // repair range. 141 MachineBasicBlock::iterator First = I; 142 --First; 143 144 MachineInstr *Call = (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3) 145 .addReg(GPR3)); 146 if (IsPCREL) 147 Call->addOperand(MI.getOperand(2)); 148 else 149 Call->addOperand(MI.getOperand(3)); 150 151 if (NeedFence) 152 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0); 153 154 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg) 155 .addReg(GPR3); 156 157 // The COPY is the last instruction in the repair range. 158 MachineBasicBlock::iterator Last = I; 159 --Last; 160 161 // Move past the original instruction and remove it. 162 ++I; 163 MI.removeFromParent(); 164 165 // Repair the live intervals. 166 LIS->repairIntervalsInRange(&MBB, First, Last, OrigRegs); 167 Changed = true; 168 } 169 170 return Changed; 171 } 172 173 public: 174 bool isPCREL(const MachineInstr &MI) { 175 return (MI.getOpcode() == PPC::PADDI8pc) && 176 (MI.getOperand(2).getTargetFlags() == 177 PPCII::MO_GOT_TLSGD_PCREL_FLAG || 178 MI.getOperand(2).getTargetFlags() == 179 PPCII::MO_GOT_TLSLD_PCREL_FLAG); 180 } 181 182 bool runOnMachineFunction(MachineFunction &MF) override { 183 TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo(); 184 LIS = &getAnalysis<LiveIntervals>(); 185 186 bool Changed = false; 187 188 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) { 189 MachineBasicBlock &B = *I++; 190 if (processBlock(B)) 191 Changed = true; 192 } 193 194 return Changed; 195 } 196 197 void getAnalysisUsage(AnalysisUsage &AU) const override { 198 AU.addRequired<LiveIntervals>(); 199 AU.addPreserved<LiveIntervals>(); 200 AU.addRequired<SlotIndexes>(); 201 AU.addPreserved<SlotIndexes>(); 202 MachineFunctionPass::getAnalysisUsage(AU); 203 } 204 }; 205 } 206 207 INITIALIZE_PASS_BEGIN(PPCTLSDynamicCall, DEBUG_TYPE, 208 "PowerPC TLS Dynamic Call Fixup", false, false) 209 INITIALIZE_PASS_DEPENDENCY(LiveIntervals) 210 INITIALIZE_PASS_DEPENDENCY(SlotIndexes) 211 INITIALIZE_PASS_END(PPCTLSDynamicCall, DEBUG_TYPE, 212 "PowerPC TLS Dynamic Call Fixup", false, false) 213 214 char PPCTLSDynamicCall::ID = 0; 215 FunctionPass* 216 llvm::createPPCTLSDynamicCallPass() { return new PPCTLSDynamicCall(); } 217