1 //===---------- PPCTLSDynamicCall.cpp - TLS Dynamic Call Fixup ------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This pass expands ADDItls{ld,gd}LADDR[32] machine instructions into 10 // separate ADDItls[gd]L[32] and GETtlsADDR[32] instructions, both of 11 // which define GPR3. A copy is added from GPR3 to the target virtual 12 // register of the original instruction. The GETtlsADDR[32] is really 13 // a call instruction, so its target register is constrained to be GPR3. 14 // This is not true of ADDItls[gd]L[32], but there is a legacy linker 15 // optimization bug that requires the target register of the addi of 16 // a local- or general-dynamic TLS access sequence to be GPR3. 17 // 18 // This is done in a late pass so that TLS variable accesses can be 19 // fully commoned by MachineCSE. 20 // 21 //===----------------------------------------------------------------------===// 22 23 #include "PPC.h" 24 #include "PPCInstrBuilder.h" 25 #include "PPCInstrInfo.h" 26 #include "PPCTargetMachine.h" 27 #include "llvm/CodeGen/LiveIntervals.h" 28 #include "llvm/CodeGen/MachineFunctionPass.h" 29 #include "llvm/CodeGen/MachineInstrBuilder.h" 30 #include "llvm/InitializePasses.h" 31 #include "llvm/Support/Debug.h" 32 #include "llvm/Support/raw_ostream.h" 33 34 using namespace llvm; 35 36 #define DEBUG_TYPE "ppc-tls-dynamic-call" 37 38 namespace { 39 struct PPCTLSDynamicCall : public MachineFunctionPass { 40 static char ID; 41 PPCTLSDynamicCall() : MachineFunctionPass(ID) { 42 initializePPCTLSDynamicCallPass(*PassRegistry::getPassRegistry()); 43 } 44 45 const PPCInstrInfo *TII; 46 LiveIntervals *LIS; 47 48 protected: 49 bool processBlock(MachineBasicBlock &MBB) { 50 bool Changed = false; 51 bool NeedFence = true; 52 bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64(); 53 bool IsAIX = MBB.getParent()->getSubtarget<PPCSubtarget>().isAIXABI(); 54 bool IsPCREL = false; 55 56 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end(); 57 I != IE;) { 58 MachineInstr &MI = *I; 59 IsPCREL = isPCREL(MI); 60 61 if (MI.getOpcode() != PPC::ADDItlsgdLADDR && 62 MI.getOpcode() != PPC::ADDItlsldLADDR && 63 MI.getOpcode() != PPC::ADDItlsgdLADDR32 && 64 MI.getOpcode() != PPC::ADDItlsldLADDR32 && 65 MI.getOpcode() != PPC::TLSGDAIX && 66 MI.getOpcode() != PPC::TLSGDAIX8 && !IsPCREL) { 67 // Although we create ADJCALLSTACKDOWN and ADJCALLSTACKUP 68 // as scheduling fences, we skip creating fences if we already 69 // have existing ADJCALLSTACKDOWN/UP to avoid nesting, 70 // which causes verification error with -verify-machineinstrs. 71 if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN) 72 NeedFence = false; 73 else if (MI.getOpcode() == PPC::ADJCALLSTACKUP) 74 NeedFence = true; 75 76 ++I; 77 continue; 78 } 79 80 LLVM_DEBUG(dbgs() << "TLS Dynamic Call Fixup:\n " << MI); 81 82 Register OutReg = MI.getOperand(0).getReg(); 83 Register InReg = PPC::NoRegister; 84 Register GPR3 = Is64Bit ? PPC::X3 : PPC::R3; 85 Register GPR4 = Is64Bit ? PPC::X4 : PPC::R4; 86 SmallVector<Register, 3> OrigRegs = {OutReg, GPR3}; 87 if (!IsPCREL) { 88 InReg = MI.getOperand(1).getReg(); 89 OrigRegs.push_back(InReg); 90 } 91 DebugLoc DL = MI.getDebugLoc(); 92 93 unsigned Opc1, Opc2; 94 switch (MI.getOpcode()) { 95 default: 96 llvm_unreachable("Opcode inconsistency error"); 97 case PPC::ADDItlsgdLADDR: 98 Opc1 = PPC::ADDItlsgdL; 99 Opc2 = PPC::GETtlsADDR; 100 break; 101 case PPC::ADDItlsldLADDR: 102 Opc1 = PPC::ADDItlsldL; 103 Opc2 = PPC::GETtlsldADDR; 104 break; 105 case PPC::ADDItlsgdLADDR32: 106 Opc1 = PPC::ADDItlsgdL32; 107 Opc2 = PPC::GETtlsADDR32; 108 break; 109 case PPC::ADDItlsldLADDR32: 110 Opc1 = PPC::ADDItlsldL32; 111 Opc2 = PPC::GETtlsldADDR32; 112 break; 113 case PPC::TLSGDAIX8: 114 // TLSGDAIX8 is expanded to two copies and GET_TLS_ADDR, so we only 115 // set Opc2 here. 116 Opc2 = PPC::GETtlsADDR64AIX; 117 break; 118 case PPC::TLSGDAIX: 119 // TLSGDAIX is expanded to two copies and GET_TLS_ADDR, so we only 120 // set Opc2 here. 121 Opc2 = PPC::GETtlsADDR32AIX; 122 break; 123 case PPC::PADDI8pc: 124 assert(IsPCREL && "Expecting General/Local Dynamic PCRel"); 125 Opc1 = PPC::PADDI8pc; 126 Opc2 = MI.getOperand(2).getTargetFlags() == 127 PPCII::MO_GOT_TLSGD_PCREL_FLAG 128 ? PPC::GETtlsADDRPCREL 129 : PPC::GETtlsldADDRPCREL; 130 } 131 132 // We create ADJCALLSTACKUP and ADJCALLSTACKDOWN around _tls_get_addr 133 // as scheduling fence to avoid it is scheduled before 134 // mflr in the prologue and the address in LR is clobbered (PR25839). 135 // We don't really need to save data to the stack - the clobbered 136 // registers are already saved when the SDNode (e.g. PPCaddiTlsgdLAddr) 137 // gets translated to the pseudo instruction (e.g. ADDItlsgdLADDR). 138 if (NeedFence) 139 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0) 140 .addImm(0); 141 142 // The ADDItls* instruction is the first instruction in the 143 // repair range. 144 MachineBasicBlock::iterator First = I; 145 --First; 146 147 if (IsAIX) { 148 // The variable offset and region handle are copied in r4 and r3. The 149 // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX. 150 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR4) 151 .addReg(MI.getOperand(1).getReg()); 152 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR3) 153 .addReg(MI.getOperand(2).getReg()); 154 BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3).addReg(GPR4); 155 } else { 156 MachineInstr *Addi; 157 if (IsPCREL) { 158 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addImm(0); 159 } else { 160 // Expand into two ops built prior to the existing instruction. 161 assert(InReg != PPC::NoRegister && "Operand must be a register"); 162 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addReg(InReg); 163 } 164 165 Addi->addOperand(MI.getOperand(2)); 166 167 MachineInstr *Call = 168 (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3)); 169 if (IsPCREL) 170 Call->addOperand(MI.getOperand(2)); 171 else 172 Call->addOperand(MI.getOperand(3)); 173 } 174 if (NeedFence) 175 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0); 176 177 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg) 178 .addReg(GPR3); 179 180 // The COPY is the last instruction in the repair range. 181 MachineBasicBlock::iterator Last = I; 182 --Last; 183 184 // Move past the original instruction and remove it. 185 ++I; 186 MI.removeFromParent(); 187 188 // Repair the live intervals. 189 LIS->repairIntervalsInRange(&MBB, First, Last, OrigRegs); 190 Changed = true; 191 } 192 193 return Changed; 194 } 195 196 public: 197 bool isPCREL(const MachineInstr &MI) { 198 return (MI.getOpcode() == PPC::PADDI8pc) && 199 (MI.getOperand(2).getTargetFlags() == 200 PPCII::MO_GOT_TLSGD_PCREL_FLAG || 201 MI.getOperand(2).getTargetFlags() == 202 PPCII::MO_GOT_TLSLD_PCREL_FLAG); 203 } 204 205 bool runOnMachineFunction(MachineFunction &MF) override { 206 TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo(); 207 LIS = &getAnalysis<LiveIntervals>(); 208 209 bool Changed = false; 210 211 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) { 212 MachineBasicBlock &B = *I++; 213 if (processBlock(B)) 214 Changed = true; 215 } 216 217 return Changed; 218 } 219 220 void getAnalysisUsage(AnalysisUsage &AU) const override { 221 AU.addRequired<LiveIntervals>(); 222 AU.addPreserved<LiveIntervals>(); 223 AU.addRequired<SlotIndexes>(); 224 AU.addPreserved<SlotIndexes>(); 225 MachineFunctionPass::getAnalysisUsage(AU); 226 } 227 }; 228 } 229 230 INITIALIZE_PASS_BEGIN(PPCTLSDynamicCall, DEBUG_TYPE, 231 "PowerPC TLS Dynamic Call Fixup", false, false) 232 INITIALIZE_PASS_DEPENDENCY(LiveIntervals) 233 INITIALIZE_PASS_DEPENDENCY(SlotIndexes) 234 INITIALIZE_PASS_END(PPCTLSDynamicCall, DEBUG_TYPE, 235 "PowerPC TLS Dynamic Call Fixup", false, false) 236 237 char PPCTLSDynamicCall::ID = 0; 238 FunctionPass* 239 llvm::createPPCTLSDynamicCallPass() { return new PPCTLSDynamicCall(); } 240