1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the PowerPC target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCTargetMachine.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "PPC.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCMachineScheduler.h"
18 #include "PPCMacroFusion.h"
19 #include "PPCSubtarget.h"
20 #include "PPCTargetObjectFile.h"
21 #include "PPCTargetTransformInfo.h"
22 #include "TargetInfo/PowerPCTargetInfo.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/Analysis/TargetTransformInfo.h"
27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
29 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
30 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
31 #include "llvm/CodeGen/GlobalISel/Localizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/MachineScheduler.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/CodeGen/TargetPassConfig.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/InitializePasses.h"
40 #include "llvm/MC/TargetRegistry.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Target/TargetLoweringObjectFile.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include <cassert>
48 #include <memory>
49 #include <optional>
50 #include <string>
51 
52 using namespace llvm;
53 
54 
55 static cl::opt<bool>
56     EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
57                            cl::desc("enable coalescing of duplicate branches for PPC"));
58 static cl::
59 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
60                         cl::desc("Disable CTR loops for PPC"));
61 
62 static cl::
63 opt<bool> DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden,
64                             cl::desc("Disable PPC loop instr form prep"));
65 
66 static cl::opt<bool>
67 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
68   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
69 
70 static cl::
71 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
72                                 cl::desc("Disable VSX Swap Removal for PPC"));
73 
74 static cl::
75 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
76                             cl::desc("Disable machine peepholes for PPC"));
77 
78 static cl::opt<bool>
79 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
80              cl::desc("Enable optimizations on complex GEPs"),
81              cl::init(true));
82 
83 static cl::opt<bool>
84 EnablePrefetch("enable-ppc-prefetching",
85                   cl::desc("enable software prefetching on PPC"),
86                   cl::init(false), cl::Hidden);
87 
88 static cl::opt<bool>
89 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
90                       cl::desc("Add extra TOC register dependencies"),
91                       cl::init(true), cl::Hidden);
92 
93 static cl::opt<bool>
94 EnableMachineCombinerPass("ppc-machine-combiner",
95                           cl::desc("Enable the machine combiner pass"),
96                           cl::init(true), cl::Hidden);
97 
98 static cl::opt<bool>
99   ReduceCRLogical("ppc-reduce-cr-logicals",
100                   cl::desc("Expand eligible cr-logical binary ops to branches"),
101                   cl::init(true), cl::Hidden);
102 
103 static cl::opt<bool> EnablePPCGenScalarMASSEntries(
104     "enable-ppc-gen-scalar-mass", cl::init(false),
105     cl::desc("Enable lowering math functions to their corresponding MASS "
106              "(scalar) entries"),
107     cl::Hidden);
108 
109 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget() {
110   // Register the targets
111   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
112   RegisterTargetMachine<PPCTargetMachine> B(getThePPC32LETarget());
113   RegisterTargetMachine<PPCTargetMachine> C(getThePPC64Target());
114   RegisterTargetMachine<PPCTargetMachine> D(getThePPC64LETarget());
115 
116   PassRegistry &PR = *PassRegistry::getPassRegistry();
117 #ifndef NDEBUG
118   initializePPCCTRLoopsVerifyPass(PR);
119 #endif
120   initializePPCLoopInstrFormPrepPass(PR);
121   initializePPCTOCRegDepsPass(PR);
122   initializePPCEarlyReturnPass(PR);
123   initializePPCVSXCopyPass(PR);
124   initializePPCVSXFMAMutatePass(PR);
125   initializePPCVSXSwapRemovalPass(PR);
126   initializePPCReduceCRLogicalsPass(PR);
127   initializePPCBSelPass(PR);
128   initializePPCBranchCoalescingPass(PR);
129   initializePPCBoolRetToIntPass(PR);
130   initializePPCExpandISELPass(PR);
131   initializePPCPreEmitPeepholePass(PR);
132   initializePPCTLSDynamicCallPass(PR);
133   initializePPCMIPeepholePass(PR);
134   initializePPCLowerMASSVEntriesPass(PR);
135   initializePPCGenScalarMASSEntriesPass(PR);
136   initializePPCExpandAtomicPseudoPass(PR);
137   initializeGlobalISel(PR);
138   initializePPCCTRLoopsPass(PR);
139   initializePPCDAGToDAGISelPass(PR);
140 }
141 
142 static bool isLittleEndianTriple(const Triple &T) {
143   return T.getArch() == Triple::ppc64le || T.getArch() == Triple::ppcle;
144 }
145 
146 /// Return the datalayout string of a subtarget.
147 static std::string getDataLayoutString(const Triple &T) {
148   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
149   std::string Ret;
150 
151   // Most PPC* platforms are big endian, PPC(64)LE is little endian.
152   if (isLittleEndianTriple(T))
153     Ret = "e";
154   else
155     Ret = "E";
156 
157   Ret += DataLayout::getManglingComponent(T);
158 
159   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
160   // pointers.
161   if (!is64Bit || T.getOS() == Triple::Lv2)
162     Ret += "-p:32:32";
163 
164   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
165   // documentation are wrong; these are correct (i.e. "what gcc does").
166   Ret += "-i64:64";
167 
168   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
169   if (is64Bit)
170     Ret += "-n32:64";
171   else
172     Ret += "-n32";
173 
174   // Specify the vector alignment explicitly. For v256i1 and v512i1, the
175   // calculated alignment would be 256*alignment(i1) and 512*alignment(i1),
176   // which is 256 and 512 bytes - way over aligned.
177   if (is64Bit && (T.isOSAIX() || T.isOSLinux()))
178     Ret += "-S128-v256:256:256-v512:512:512";
179 
180   return Ret;
181 }
182 
183 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
184                                       const Triple &TT) {
185   std::string FullFS = std::string(FS);
186 
187   // Make sure 64-bit features are available when CPUname is generic
188   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
189     if (!FullFS.empty())
190       FullFS = "+64bit," + FullFS;
191     else
192       FullFS = "+64bit";
193   }
194 
195   if (OL >= CodeGenOpt::Default) {
196     if (!FullFS.empty())
197       FullFS = "+crbits," + FullFS;
198     else
199       FullFS = "+crbits";
200   }
201 
202   if (OL != CodeGenOpt::None) {
203     if (!FullFS.empty())
204       FullFS = "+invariant-function-descriptors," + FullFS;
205     else
206       FullFS = "+invariant-function-descriptors";
207   }
208 
209   if (TT.isOSAIX()) {
210     if (!FullFS.empty())
211       FullFS = "+aix," + FullFS;
212     else
213       FullFS = "+aix";
214   }
215 
216   return FullFS;
217 }
218 
219 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
220   if (TT.isOSAIX())
221     return std::make_unique<TargetLoweringObjectFileXCOFF>();
222 
223   return std::make_unique<PPC64LinuxTargetObjectFile>();
224 }
225 
226 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
227                                                  const TargetOptions &Options) {
228   if (Options.MCOptions.getABIName().startswith("elfv1"))
229     return PPCTargetMachine::PPC_ABI_ELFv1;
230   else if (Options.MCOptions.getABIName().startswith("elfv2"))
231     return PPCTargetMachine::PPC_ABI_ELFv2;
232 
233   assert(Options.MCOptions.getABIName().empty() &&
234          "Unknown target-abi option!");
235 
236   switch (TT.getArch()) {
237   case Triple::ppc64le:
238     return PPCTargetMachine::PPC_ABI_ELFv2;
239   case Triple::ppc64:
240     if (TT.isPPC64ELFv2ABI())
241       return PPCTargetMachine::PPC_ABI_ELFv2;
242     else
243       return PPCTargetMachine::PPC_ABI_ELFv1;
244   default:
245     return PPCTargetMachine::PPC_ABI_UNKNOWN;
246   }
247 }
248 
249 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
250                                            std::optional<Reloc::Model> RM) {
251   assert((!TT.isOSAIX() || !RM || *RM == Reloc::PIC_) &&
252          "Invalid relocation model for AIX.");
253 
254   if (RM)
255     return *RM;
256 
257   // Big Endian PPC and AIX default to PIC.
258   if (TT.getArch() == Triple::ppc64 || TT.isOSAIX())
259     return Reloc::PIC_;
260 
261   // Rest are static by default.
262   return Reloc::Static;
263 }
264 
265 static CodeModel::Model
266 getEffectivePPCCodeModel(const Triple &TT, std::optional<CodeModel::Model> CM,
267                          bool JIT) {
268   if (CM) {
269     if (*CM == CodeModel::Tiny)
270       report_fatal_error("Target does not support the tiny CodeModel", false);
271     if (*CM == CodeModel::Kernel)
272       report_fatal_error("Target does not support the kernel CodeModel", false);
273     return *CM;
274   }
275 
276   if (JIT)
277     return CodeModel::Small;
278   if (TT.isOSAIX())
279     return CodeModel::Small;
280 
281   assert(TT.isOSBinFormatELF() && "All remaining PPC OSes are ELF based.");
282 
283   if (TT.isArch32Bit())
284     return CodeModel::Small;
285 
286   assert(TT.isArch64Bit() && "Unsupported PPC architecture.");
287   return CodeModel::Medium;
288 }
289 
290 
291 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
292   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
293   ScheduleDAGMILive *DAG =
294     new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
295                           std::make_unique<PPCPreRASchedStrategy>(C) :
296                           std::make_unique<GenericScheduler>(C));
297   // add DAG Mutations here.
298   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
299   if (ST.hasStoreFusion())
300     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
301   if (ST.hasFusion())
302     DAG->addMutation(createPowerPCMacroFusionDAGMutation());
303 
304   return DAG;
305 }
306 
307 static ScheduleDAGInstrs *createPPCPostMachineScheduler(
308   MachineSchedContext *C) {
309   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
310   ScheduleDAGMI *DAG =
311     new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
312                       std::make_unique<PPCPostRASchedStrategy>(C) :
313                       std::make_unique<PostGenericScheduler>(C), true);
314   // add DAG Mutations here.
315   if (ST.hasStoreFusion())
316     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
317   if (ST.hasFusion())
318     DAG->addMutation(createPowerPCMacroFusionDAGMutation());
319   return DAG;
320 }
321 
322 // The FeatureString here is a little subtle. We are modifying the feature
323 // string with what are (currently) non-function specific overrides as it goes
324 // into the LLVMTargetMachine constructor and then using the stored value in the
325 // Subtarget constructor below it.
326 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
327                                    StringRef CPU, StringRef FS,
328                                    const TargetOptions &Options,
329                                    std::optional<Reloc::Model> RM,
330                                    std::optional<CodeModel::Model> CM,
331                                    CodeGenOpt::Level OL, bool JIT)
332     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
333                         computeFSAdditions(FS, OL, TT), Options,
334                         getEffectiveRelocModel(TT, RM),
335                         getEffectivePPCCodeModel(TT, CM, JIT), OL),
336       TLOF(createTLOF(getTargetTriple())),
337       TargetABI(computeTargetABI(TT, Options)),
338       Endianness(isLittleEndianTriple(TT) ? Endian::LITTLE : Endian::BIG) {
339   initAsmInfo();
340 }
341 
342 PPCTargetMachine::~PPCTargetMachine() = default;
343 
344 const PPCSubtarget *
345 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
346   Attribute CPUAttr = F.getFnAttribute("target-cpu");
347   Attribute TuneAttr = F.getFnAttribute("tune-cpu");
348   Attribute FSAttr = F.getFnAttribute("target-features");
349 
350   std::string CPU =
351       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
352   std::string TuneCPU =
353       TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
354   std::string FS =
355       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
356 
357   // FIXME: This is related to the code below to reset the target options,
358   // we need to know whether or not the soft float flag is set on the
359   // function before we can generate a subtarget. We also need to use
360   // it as a key for the subtarget since that can be the only difference
361   // between two functions.
362   bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
363   // If the soft float attribute is set on the function turn on the soft float
364   // subtarget feature.
365   if (SoftFloat)
366     FS += FS.empty() ? "-hard-float" : ",-hard-float";
367 
368   auto &I = SubtargetMap[CPU + TuneCPU + FS];
369   if (!I) {
370     // This needs to be done before we create a new subtarget since any
371     // creation will depend on the TM and the code generation flags on the
372     // function that reside in TargetOptions.
373     resetTargetOptions(F);
374     I = std::make_unique<PPCSubtarget>(
375         TargetTriple, CPU, TuneCPU,
376         // FIXME: It would be good to have the subtarget additions here
377         // not necessary. Anything that turns them on/off (overrides) ends
378         // up being put at the end of the feature string, but the defaults
379         // shouldn't require adding them. Fixing this means pulling Feature64Bit
380         // out of most of the target cpus in the .td file and making it set only
381         // as part of initialization via the TargetTriple.
382         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
383   }
384   return I.get();
385 }
386 
387 //===----------------------------------------------------------------------===//
388 // Pass Pipeline Configuration
389 //===----------------------------------------------------------------------===//
390 
391 namespace {
392 
393 /// PPC Code Generator Pass Configuration Options.
394 class PPCPassConfig : public TargetPassConfig {
395 public:
396   PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
397     : TargetPassConfig(TM, PM) {
398     // At any optimization level above -O0 we use the Machine Scheduler and not
399     // the default Post RA List Scheduler.
400     if (TM.getOptLevel() != CodeGenOpt::None)
401       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
402   }
403 
404   PPCTargetMachine &getPPCTargetMachine() const {
405     return getTM<PPCTargetMachine>();
406   }
407 
408   void addIRPasses() override;
409   bool addPreISel() override;
410   bool addILPOpts() override;
411   bool addInstSelector() override;
412   void addMachineSSAOptimization() override;
413   void addPreRegAlloc() override;
414   void addPreSched2() override;
415   void addPreEmitPass() override;
416   void addPreEmitPass2() override;
417   // GlobalISEL
418   bool addIRTranslator() override;
419   bool addLegalizeMachineIR() override;
420   bool addRegBankSelect() override;
421   bool addGlobalInstructionSelect() override;
422 
423   ScheduleDAGInstrs *
424   createMachineScheduler(MachineSchedContext *C) const override {
425     return createPPCMachineScheduler(C);
426   }
427   ScheduleDAGInstrs *
428   createPostMachineScheduler(MachineSchedContext *C) const override {
429     return createPPCPostMachineScheduler(C);
430   }
431 };
432 
433 } // end anonymous namespace
434 
435 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
436   return new PPCPassConfig(*this, PM);
437 }
438 
439 void PPCPassConfig::addIRPasses() {
440   if (TM->getOptLevel() != CodeGenOpt::None)
441     addPass(createPPCBoolRetToIntPass());
442   addPass(createAtomicExpandPass());
443 
444   // Lower generic MASSV routines to PowerPC subtarget-specific entries.
445   addPass(createPPCLowerMASSVEntriesPass());
446 
447   // Generate PowerPC target-specific entries for scalar math functions
448   // that are available in IBM MASS (scalar) library.
449   if (TM->getOptLevel() == CodeGenOpt::Aggressive &&
450       EnablePPCGenScalarMASSEntries) {
451     TM->Options.PPCGenScalarMASSEntries = EnablePPCGenScalarMASSEntries;
452     addPass(createPPCGenScalarMASSEntriesPass());
453   }
454 
455   // If explicitly requested, add explicit data prefetch intrinsics.
456   if (EnablePrefetch.getNumOccurrences() > 0)
457     addPass(createLoopDataPrefetchPass());
458 
459   if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
460     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
461     // and lower a GEP with multiple indices to either arithmetic operations or
462     // multiple GEPs with single index.
463     addPass(createSeparateConstOffsetFromGEPPass(true));
464     // Call EarlyCSE pass to find and remove subexpressions in the lowered
465     // result.
466     addPass(createEarlyCSEPass());
467     // Do loop invariant code motion in case part of the lowered result is
468     // invariant.
469     addPass(createLICMPass());
470   }
471 
472   TargetPassConfig::addIRPasses();
473 }
474 
475 bool PPCPassConfig::addPreISel() {
476   if (!DisableInstrFormPrep && getOptLevel() != CodeGenOpt::None)
477     addPass(createPPCLoopInstrFormPrepPass(getPPCTargetMachine()));
478 
479   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
480     addPass(createHardwareLoopsPass());
481 
482   return false;
483 }
484 
485 bool PPCPassConfig::addILPOpts() {
486   addPass(&EarlyIfConverterID);
487 
488   if (EnableMachineCombinerPass)
489     addPass(&MachineCombinerID);
490 
491   return true;
492 }
493 
494 bool PPCPassConfig::addInstSelector() {
495   // Install an instruction selector.
496   addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
497 
498 #ifndef NDEBUG
499   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
500     addPass(createPPCCTRLoopsVerify());
501 #endif
502 
503   addPass(createPPCVSXCopyPass());
504   return false;
505 }
506 
507 void PPCPassConfig::addMachineSSAOptimization() {
508   // Run CTR loops pass before any cfg modification pass to prevent the
509   // canonical form of hardware loop from being destroied.
510   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
511     addPass(createPPCCTRLoopsPass());
512 
513   // PPCBranchCoalescingPass need to be done before machine sinking
514   // since it merges empty blocks.
515   if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
516     addPass(createPPCBranchCoalescingPass());
517   TargetPassConfig::addMachineSSAOptimization();
518   // For little endian, remove where possible the vector swap instructions
519   // introduced at code generation to normalize vector element order.
520   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
521       !DisableVSXSwapRemoval)
522     addPass(createPPCVSXSwapRemovalPass());
523   // Reduce the number of cr-logical ops.
524   if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
525     addPass(createPPCReduceCRLogicalsPass());
526   // Target-specific peephole cleanups performed after instruction
527   // selection.
528   if (!DisableMIPeephole) {
529     addPass(createPPCMIPeepholePass());
530     addPass(&DeadMachineInstructionElimID);
531   }
532 }
533 
534 void PPCPassConfig::addPreRegAlloc() {
535   if (getOptLevel() != CodeGenOpt::None) {
536     initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
537     insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
538                &PPCVSXFMAMutateID);
539   }
540 
541   // FIXME: We probably don't need to run these for -fPIE.
542   if (getPPCTargetMachine().isPositionIndependent()) {
543     // FIXME: LiveVariables should not be necessary here!
544     // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
545     // LiveVariables. This (unnecessary) dependency has been removed now,
546     // however a stage-2 clang build fails without LiveVariables computed here.
547     addPass(&LiveVariablesID);
548     addPass(createPPCTLSDynamicCallPass());
549   }
550   if (EnableExtraTOCRegDeps)
551     addPass(createPPCTOCRegDepsPass());
552 
553   if (getOptLevel() != CodeGenOpt::None)
554     addPass(&MachinePipelinerID);
555 }
556 
557 void PPCPassConfig::addPreSched2() {
558   if (getOptLevel() != CodeGenOpt::None)
559     addPass(&IfConverterID);
560 }
561 
562 void PPCPassConfig::addPreEmitPass() {
563   addPass(createPPCPreEmitPeepholePass());
564   addPass(createPPCExpandISELPass());
565 
566   if (getOptLevel() != CodeGenOpt::None)
567     addPass(createPPCEarlyReturnPass());
568 }
569 
570 void PPCPassConfig::addPreEmitPass2() {
571   // Schedule the expansion of AMOs at the last possible moment, avoiding the
572   // possibility for other passes to break the requirements for forward
573   // progress in the LL/SC block.
574   addPass(createPPCExpandAtomicPseudoPass());
575   // Must run branch selection immediately preceding the asm printer.
576   addPass(createPPCBranchSelectionPass());
577 }
578 
579 TargetTransformInfo
580 PPCTargetMachine::getTargetTransformInfo(const Function &F) const {
581   return TargetTransformInfo(PPCTTIImpl(this, F));
582 }
583 
584 bool PPCTargetMachine::isLittleEndian() const {
585   assert(Endianness != Endian::NOT_DETECTED &&
586          "Unable to determine endianness");
587   return Endianness == Endian::LITTLE;
588 }
589 
590 MachineFunctionInfo *PPCTargetMachine::createMachineFunctionInfo(
591     BumpPtrAllocator &Allocator, const Function &F,
592     const TargetSubtargetInfo *STI) const {
593   return PPCFunctionInfo::create<PPCFunctionInfo>(Allocator, F, STI);
594 }
595 
596 static MachineSchedRegistry
597 PPCPreRASchedRegistry("ppc-prera",
598                       "Run PowerPC PreRA specific scheduler",
599                       createPPCMachineScheduler);
600 
601 static MachineSchedRegistry
602 PPCPostRASchedRegistry("ppc-postra",
603                        "Run PowerPC PostRA specific scheduler",
604                        createPPCPostMachineScheduler);
605 
606 // Global ISEL
607 bool PPCPassConfig::addIRTranslator() {
608   addPass(new IRTranslator());
609   return false;
610 }
611 
612 bool PPCPassConfig::addLegalizeMachineIR() {
613   addPass(new Legalizer());
614   return false;
615 }
616 
617 bool PPCPassConfig::addRegBankSelect() {
618   addPass(new RegBankSelect());
619   return false;
620 }
621 
622 bool PPCPassConfig::addGlobalInstructionSelect() {
623   addPass(new InstructionSelect(getOptLevel()));
624   return false;
625 }
626