1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the PowerPC target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCTargetMachine.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "PPC.h"
16 #include "PPCMachineScheduler.h"
17 #include "PPCSubtarget.h"
18 #include "PPCTargetObjectFile.h"
19 #include "PPCTargetTransformInfo.h"
20 #include "TargetInfo/PowerPCTargetInfo.h"
21 #include "llvm/ADT/Optional.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/Triple.h"
25 #include "llvm/Analysis/TargetTransformInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/TargetPassConfig.h"
28 #include "llvm/CodeGen/MachineScheduler.h"
29 #include "llvm/IR/Attributes.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/Pass.h"
33 #include "llvm/Support/CodeGen.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/TargetRegistry.h"
36 #include "llvm/Target/TargetLoweringObjectFile.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Transforms/Scalar.h"
39 #include <cassert>
40 #include <memory>
41 #include <string>
42 
43 using namespace llvm;
44 
45 
46 static cl::opt<bool>
47     EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
48                            cl::desc("enable coalescing of duplicate branches for PPC"));
49 static cl::
50 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
51                         cl::desc("Disable CTR loops for PPC"));
52 
53 static cl::
54 opt<bool> DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden,
55                             cl::desc("Disable PPC loop instr form prep"));
56 
57 static cl::opt<bool>
58 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
59   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
60 
61 static cl::
62 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
63                                 cl::desc("Disable VSX Swap Removal for PPC"));
64 
65 static cl::
66 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
67                               cl::desc("Disable QPX load splat simplification"));
68 
69 static cl::
70 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
71                             cl::desc("Disable machine peepholes for PPC"));
72 
73 static cl::opt<bool>
74 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
75              cl::desc("Enable optimizations on complex GEPs"),
76              cl::init(true));
77 
78 static cl::opt<bool>
79 EnablePrefetch("enable-ppc-prefetching",
80                   cl::desc("enable software prefetching on PPC"),
81                   cl::init(false), cl::Hidden);
82 
83 static cl::opt<bool>
84 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
85                       cl::desc("Add extra TOC register dependencies"),
86                       cl::init(true), cl::Hidden);
87 
88 static cl::opt<bool>
89 EnableMachineCombinerPass("ppc-machine-combiner",
90                           cl::desc("Enable the machine combiner pass"),
91                           cl::init(true), cl::Hidden);
92 
93 static cl::opt<bool>
94   ReduceCRLogical("ppc-reduce-cr-logicals",
95                   cl::desc("Expand eligible cr-logical binary ops to branches"),
96                   cl::init(true), cl::Hidden);
97 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget() {
98   // Register the targets
99   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
100   RegisterTargetMachine<PPCTargetMachine> B(getThePPC64Target());
101   RegisterTargetMachine<PPCTargetMachine> C(getThePPC64LETarget());
102 
103   PassRegistry &PR = *PassRegistry::getPassRegistry();
104 #ifndef NDEBUG
105   initializePPCCTRLoopsVerifyPass(PR);
106 #endif
107   initializePPCLoopInstrFormPrepPass(PR);
108   initializePPCTOCRegDepsPass(PR);
109   initializePPCEarlyReturnPass(PR);
110   initializePPCVSXCopyPass(PR);
111   initializePPCVSXFMAMutatePass(PR);
112   initializePPCVSXSwapRemovalPass(PR);
113   initializePPCReduceCRLogicalsPass(PR);
114   initializePPCBSelPass(PR);
115   initializePPCBranchCoalescingPass(PR);
116   initializePPCQPXLoadSplatPass(PR);
117   initializePPCBoolRetToIntPass(PR);
118   initializePPCExpandISELPass(PR);
119   initializePPCPreEmitPeepholePass(PR);
120   initializePPCTLSDynamicCallPass(PR);
121   initializePPCMIPeepholePass(PR);
122   initializePPCLowerMASSVEntriesPass(PR);
123 }
124 
125 /// Return the datalayout string of a subtarget.
126 static std::string getDataLayoutString(const Triple &T) {
127   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
128   std::string Ret;
129 
130   // Most PPC* platforms are big endian, PPC64LE is little endian.
131   if (T.getArch() == Triple::ppc64le)
132     Ret = "e";
133   else
134     Ret = "E";
135 
136   Ret += DataLayout::getManglingComponent(T);
137 
138   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
139   // pointers.
140   if (!is64Bit || T.getOS() == Triple::Lv2)
141     Ret += "-p:32:32";
142 
143   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
144   // documentation are wrong; these are correct (i.e. "what gcc does").
145   if (is64Bit || !T.isOSDarwin())
146     Ret += "-i64:64";
147   else
148     Ret += "-f64:32:64";
149 
150   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
151   if (is64Bit)
152     Ret += "-n32:64";
153   else
154     Ret += "-n32";
155 
156   return Ret;
157 }
158 
159 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
160                                       const Triple &TT) {
161   std::string FullFS = FS;
162 
163   // Make sure 64-bit features are available when CPUname is generic
164   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
165     if (!FullFS.empty())
166       FullFS = "+64bit," + FullFS;
167     else
168       FullFS = "+64bit";
169   }
170 
171   if (OL >= CodeGenOpt::Default) {
172     if (!FullFS.empty())
173       FullFS = "+crbits," + FullFS;
174     else
175       FullFS = "+crbits";
176   }
177 
178   if (OL != CodeGenOpt::None) {
179     if (!FullFS.empty())
180       FullFS = "+invariant-function-descriptors," + FullFS;
181     else
182       FullFS = "+invariant-function-descriptors";
183   }
184 
185   return FullFS;
186 }
187 
188 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
189   if (TT.isOSDarwin())
190     return std::make_unique<TargetLoweringObjectFileMachO>();
191 
192   if (TT.isOSAIX())
193     return std::make_unique<TargetLoweringObjectFileXCOFF>();
194 
195   return std::make_unique<PPC64LinuxTargetObjectFile>();
196 }
197 
198 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
199                                                  const TargetOptions &Options) {
200   if (TT.isOSDarwin())
201     report_fatal_error("Darwin is no longer supported for PowerPC");
202 
203   if (Options.MCOptions.getABIName().startswith("elfv1"))
204     return PPCTargetMachine::PPC_ABI_ELFv1;
205   else if (Options.MCOptions.getABIName().startswith("elfv2"))
206     return PPCTargetMachine::PPC_ABI_ELFv2;
207 
208   assert(Options.MCOptions.getABIName().empty() &&
209          "Unknown target-abi option!");
210 
211   if (TT.isMacOSX())
212     return PPCTargetMachine::PPC_ABI_UNKNOWN;
213 
214   switch (TT.getArch()) {
215   case Triple::ppc64le:
216     return PPCTargetMachine::PPC_ABI_ELFv2;
217   case Triple::ppc64:
218     return PPCTargetMachine::PPC_ABI_ELFv1;
219   default:
220     return PPCTargetMachine::PPC_ABI_UNKNOWN;
221   }
222 }
223 
224 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
225                                            Optional<Reloc::Model> RM) {
226   if (RM.hasValue())
227     return *RM;
228 
229   // Darwin defaults to dynamic-no-pic.
230   if (TT.isOSDarwin())
231     return Reloc::DynamicNoPIC;
232 
233   // Big Endian PPC is PIC by default.
234   if (TT.getArch() == Triple::ppc64)
235     return Reloc::PIC_;
236 
237   // Rest are static by default.
238   return Reloc::Static;
239 }
240 
241 static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT,
242                                                  Optional<CodeModel::Model> CM,
243                                                  bool JIT) {
244   if (CM) {
245     if (*CM == CodeModel::Tiny)
246       report_fatal_error("Target does not support the tiny CodeModel", false);
247     if (*CM == CodeModel::Kernel)
248       report_fatal_error("Target does not support the kernel CodeModel", false);
249     return *CM;
250   }
251 
252   if (JIT)
253     return CodeModel::Small;
254   if (TT.isOSAIX())
255     return CodeModel::Small;
256 
257   assert(TT.isOSBinFormatELF() && "All remaining PPC OSes are ELF based.");
258 
259   if (TT.isArch32Bit())
260     return CodeModel::Small;
261 
262   assert(TT.isArch64Bit() && "Unsupported PPC architecture.");
263   return CodeModel::Medium;
264 }
265 
266 
267 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
268   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
269   ScheduleDAGMILive *DAG =
270     new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
271                           std::make_unique<PPCPreRASchedStrategy>(C) :
272                           std::make_unique<GenericScheduler>(C));
273   // add DAG Mutations here.
274   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
275   return DAG;
276 }
277 
278 static ScheduleDAGInstrs *createPPCPostMachineScheduler(
279   MachineSchedContext *C) {
280   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
281   ScheduleDAGMI *DAG =
282     new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
283                       std::make_unique<PPCPostRASchedStrategy>(C) :
284                       std::make_unique<PostGenericScheduler>(C), true);
285   // add DAG Mutations here.
286   return DAG;
287 }
288 
289 // The FeatureString here is a little subtle. We are modifying the feature
290 // string with what are (currently) non-function specific overrides as it goes
291 // into the LLVMTargetMachine constructor and then using the stored value in the
292 // Subtarget constructor below it.
293 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
294                                    StringRef CPU, StringRef FS,
295                                    const TargetOptions &Options,
296                                    Optional<Reloc::Model> RM,
297                                    Optional<CodeModel::Model> CM,
298                                    CodeGenOpt::Level OL, bool JIT)
299     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
300                         computeFSAdditions(FS, OL, TT), Options,
301                         getEffectiveRelocModel(TT, RM),
302                         getEffectivePPCCodeModel(TT, CM, JIT), OL),
303       TLOF(createTLOF(getTargetTriple())),
304       TargetABI(computeTargetABI(TT, Options)) {
305   initAsmInfo();
306 }
307 
308 PPCTargetMachine::~PPCTargetMachine() = default;
309 
310 const PPCSubtarget *
311 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
312   Attribute CPUAttr = F.getFnAttribute("target-cpu");
313   Attribute FSAttr = F.getFnAttribute("target-features");
314 
315   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
316                         ? CPUAttr.getValueAsString().str()
317                         : TargetCPU;
318   std::string FS = !FSAttr.hasAttribute(Attribute::None)
319                        ? FSAttr.getValueAsString().str()
320                        : TargetFS;
321 
322   // FIXME: This is related to the code below to reset the target options,
323   // we need to know whether or not the soft float flag is set on the
324   // function before we can generate a subtarget. We also need to use
325   // it as a key for the subtarget since that can be the only difference
326   // between two functions.
327   bool SoftFloat =
328       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
329   // If the soft float attribute is set on the function turn on the soft float
330   // subtarget feature.
331   if (SoftFloat)
332     FS += FS.empty() ? "-hard-float" : ",-hard-float";
333 
334   auto &I = SubtargetMap[CPU + FS];
335   if (!I) {
336     // This needs to be done before we create a new subtarget since any
337     // creation will depend on the TM and the code generation flags on the
338     // function that reside in TargetOptions.
339     resetTargetOptions(F);
340     I = std::make_unique<PPCSubtarget>(
341         TargetTriple, CPU,
342         // FIXME: It would be good to have the subtarget additions here
343         // not necessary. Anything that turns them on/off (overrides) ends
344         // up being put at the end of the feature string, but the defaults
345         // shouldn't require adding them. Fixing this means pulling Feature64Bit
346         // out of most of the target cpus in the .td file and making it set only
347         // as part of initialization via the TargetTriple.
348         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
349   }
350   return I.get();
351 }
352 
353 //===----------------------------------------------------------------------===//
354 // Pass Pipeline Configuration
355 //===----------------------------------------------------------------------===//
356 
357 namespace {
358 
359 /// PPC Code Generator Pass Configuration Options.
360 class PPCPassConfig : public TargetPassConfig {
361 public:
362   PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
363     : TargetPassConfig(TM, PM) {
364     // At any optimization level above -O0 we use the Machine Scheduler and not
365     // the default Post RA List Scheduler.
366     if (TM.getOptLevel() != CodeGenOpt::None)
367       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
368   }
369 
370   PPCTargetMachine &getPPCTargetMachine() const {
371     return getTM<PPCTargetMachine>();
372   }
373 
374   void addIRPasses() override;
375   bool addPreISel() override;
376   bool addILPOpts() override;
377   bool addInstSelector() override;
378   void addMachineSSAOptimization() override;
379   void addPreRegAlloc() override;
380   void addPreSched2() override;
381   void addPreEmitPass() override;
382   ScheduleDAGInstrs *
383   createMachineScheduler(MachineSchedContext *C) const override {
384     return createPPCMachineScheduler(C);
385   }
386   ScheduleDAGInstrs *
387   createPostMachineScheduler(MachineSchedContext *C) const override {
388     return createPPCPostMachineScheduler(C);
389   }
390 };
391 
392 } // end anonymous namespace
393 
394 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
395   return new PPCPassConfig(*this, PM);
396 }
397 
398 void PPCPassConfig::addIRPasses() {
399   if (TM->getOptLevel() != CodeGenOpt::None)
400     addPass(createPPCBoolRetToIntPass());
401   addPass(createAtomicExpandPass());
402 
403   // Lower generic MASSV routines to PowerPC subtarget-specific entries.
404   addPass(createPPCLowerMASSVEntriesPass());
405 
406   // For the BG/Q (or if explicitly requested), add explicit data prefetch
407   // intrinsics.
408   bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
409                         getOptLevel() != CodeGenOpt::None;
410   if (EnablePrefetch.getNumOccurrences() > 0)
411     UsePrefetching = EnablePrefetch;
412   if (UsePrefetching)
413     addPass(createLoopDataPrefetchPass());
414 
415   if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
416     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
417     // and lower a GEP with multiple indices to either arithmetic operations or
418     // multiple GEPs with single index.
419     addPass(createSeparateConstOffsetFromGEPPass(true));
420     // Call EarlyCSE pass to find and remove subexpressions in the lowered
421     // result.
422     addPass(createEarlyCSEPass());
423     // Do loop invariant code motion in case part of the lowered result is
424     // invariant.
425     addPass(createLICMPass());
426   }
427 
428   TargetPassConfig::addIRPasses();
429 }
430 
431 bool PPCPassConfig::addPreISel() {
432   if (!DisableInstrFormPrep && getOptLevel() != CodeGenOpt::None)
433     addPass(createPPCLoopInstrFormPrepPass(getPPCTargetMachine()));
434 
435   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
436     addPass(createHardwareLoopsPass());
437 
438   return false;
439 }
440 
441 bool PPCPassConfig::addILPOpts() {
442   addPass(&EarlyIfConverterID);
443 
444   if (EnableMachineCombinerPass)
445     addPass(&MachineCombinerID);
446 
447   return true;
448 }
449 
450 bool PPCPassConfig::addInstSelector() {
451   // Install an instruction selector.
452   addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
453 
454 #ifndef NDEBUG
455   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
456     addPass(createPPCCTRLoopsVerify());
457 #endif
458 
459   addPass(createPPCVSXCopyPass());
460   return false;
461 }
462 
463 void PPCPassConfig::addMachineSSAOptimization() {
464   // PPCBranchCoalescingPass need to be done before machine sinking
465   // since it merges empty blocks.
466   if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
467     addPass(createPPCBranchCoalescingPass());
468   TargetPassConfig::addMachineSSAOptimization();
469   // For little endian, remove where possible the vector swap instructions
470   // introduced at code generation to normalize vector element order.
471   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
472       !DisableVSXSwapRemoval)
473     addPass(createPPCVSXSwapRemovalPass());
474   // Reduce the number of cr-logical ops.
475   if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
476     addPass(createPPCReduceCRLogicalsPass());
477   // Target-specific peephole cleanups performed after instruction
478   // selection.
479   if (!DisableMIPeephole) {
480     addPass(createPPCMIPeepholePass());
481     addPass(&DeadMachineInstructionElimID);
482   }
483 }
484 
485 void PPCPassConfig::addPreRegAlloc() {
486   if (getOptLevel() != CodeGenOpt::None) {
487     initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
488     insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
489                &PPCVSXFMAMutateID);
490   }
491 
492   // FIXME: We probably don't need to run these for -fPIE.
493   if (getPPCTargetMachine().isPositionIndependent()) {
494     // FIXME: LiveVariables should not be necessary here!
495     // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
496     // LiveVariables. This (unnecessary) dependency has been removed now,
497     // however a stage-2 clang build fails without LiveVariables computed here.
498     addPass(&LiveVariablesID, false);
499     addPass(createPPCTLSDynamicCallPass());
500   }
501   if (EnableExtraTOCRegDeps)
502     addPass(createPPCTOCRegDepsPass());
503 
504   if (getOptLevel() != CodeGenOpt::None)
505     addPass(&MachinePipelinerID);
506 }
507 
508 void PPCPassConfig::addPreSched2() {
509   if (getOptLevel() != CodeGenOpt::None) {
510     addPass(&IfConverterID);
511 
512     // This optimization must happen after anything that might do store-to-load
513     // forwarding. Here we're after RA (and, thus, when spills are inserted)
514     // but before post-RA scheduling.
515     if (!DisableQPXLoadSplat)
516       addPass(createPPCQPXLoadSplatPass());
517   }
518 }
519 
520 void PPCPassConfig::addPreEmitPass() {
521   addPass(createPPCPreEmitPeepholePass());
522   addPass(createPPCExpandISELPass());
523 
524   if (getOptLevel() != CodeGenOpt::None)
525     addPass(createPPCEarlyReturnPass(), false);
526   // Must run branch selection immediately preceding the asm printer.
527   addPass(createPPCBranchSelectionPass(), false);
528 }
529 
530 TargetTransformInfo
531 PPCTargetMachine::getTargetTransformInfo(const Function &F) {
532   return TargetTransformInfo(PPCTTIImpl(this, F));
533 }
534 
535 static MachineSchedRegistry
536 PPCPreRASchedRegistry("ppc-prera",
537                       "Run PowerPC PreRA specific scheduler",
538                       createPPCMachineScheduler);
539 
540 static MachineSchedRegistry
541 PPCPostRASchedRegistry("ppc-postra",
542                        "Run PowerPC PostRA specific scheduler",
543                        createPPCPostMachineScheduler);
544