1 //===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone enum definitions for the RISC-V target
10 // useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15 
16 #include "MCTargetDesc/RISCVMCTargetDesc.h"
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/Support/RISCVISAInfo.h"
23 #include "llvm/TargetParser/SubtargetFeature.h"
24 
25 namespace llvm {
26 
27 // RISCVII - This namespace holds all of the target specific flags that
28 // instruction info tracks. All definitions must match RISCVInstrFormats.td.
29 namespace RISCVII {
30 enum {
31   InstFormatPseudo = 0,
32   InstFormatR = 1,
33   InstFormatR4 = 2,
34   InstFormatI = 3,
35   InstFormatS = 4,
36   InstFormatB = 5,
37   InstFormatU = 6,
38   InstFormatJ = 7,
39   InstFormatCR = 8,
40   InstFormatCI = 9,
41   InstFormatCSS = 10,
42   InstFormatCIW = 11,
43   InstFormatCL = 12,
44   InstFormatCS = 13,
45   InstFormatCA = 14,
46   InstFormatCB = 15,
47   InstFormatCJ = 16,
48   InstFormatCU = 17,
49   InstFormatCLB = 18,
50   InstFormatCLH = 19,
51   InstFormatCSB = 20,
52   InstFormatCSH = 21,
53   InstFormatOther = 22,
54 
55   InstFormatMask = 31,
56   InstFormatShift = 0,
57 
58   ConstraintShift = InstFormatShift + 5,
59   VS2Constraint = 0b001 << ConstraintShift,
60   VS1Constraint = 0b010 << ConstraintShift,
61   VMConstraint = 0b100 << ConstraintShift,
62   ConstraintMask = 0b111 << ConstraintShift,
63 
64   VLMulShift = ConstraintShift + 3,
65   VLMulMask = 0b111 << VLMulShift,
66 
67   // Force a tail agnostic policy even this instruction has a tied destination.
68   ForceTailAgnosticShift = VLMulShift + 3,
69   ForceTailAgnosticMask = 1 << ForceTailAgnosticShift,
70 
71   // Is this a _TIED vector pseudo instruction. For these instructions we
72   // shouldn't skip the tied operand when converting to MC instructions.
73   IsTiedPseudoShift = ForceTailAgnosticShift + 1,
74   IsTiedPseudoMask = 1 << IsTiedPseudoShift,
75 
76   // Does this instruction have a SEW operand. It will be the last explicit
77   // operand unless there is a vector policy operand. Used by RVV Pseudos.
78   HasSEWOpShift = IsTiedPseudoShift + 1,
79   HasSEWOpMask = 1 << HasSEWOpShift,
80 
81   // Does this instruction have a VL operand. It will be the second to last
82   // explicit operand unless there is a vector policy operand. Used by RVV
83   // Pseudos.
84   HasVLOpShift = HasSEWOpShift + 1,
85   HasVLOpMask = 1 << HasVLOpShift,
86 
87   // Does this instruction have a vector policy operand. It will be the last
88   // explicit operand. Used by RVV Pseudos.
89   HasVecPolicyOpShift = HasVLOpShift + 1,
90   HasVecPolicyOpMask = 1 << HasVecPolicyOpShift,
91 
92   // Is this instruction a vector widening reduction instruction. Used by RVV
93   // Pseudos.
94   IsRVVWideningReductionShift = HasVecPolicyOpShift + 1,
95   IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift,
96 
97   // Does this instruction care about mask policy. If it is not, the mask policy
98   // could be either agnostic or undisturbed. For example, unmasked, store, and
99   // reduction operations result would not be affected by mask policy, so
100   // compiler has free to select either one.
101   UsesMaskPolicyShift = IsRVVWideningReductionShift + 1,
102   UsesMaskPolicyMask = 1 << UsesMaskPolicyShift,
103 
104   // Indicates that the result can be considered sign extended from bit 31. Some
105   // instructions with this flag aren't W instructions, but are either sign
106   // extended from a smaller size, always outputs a small integer, or put zeros
107   // in bits 63:31. Used by the SExtWRemoval pass.
108   IsSignExtendingOpWShift = UsesMaskPolicyShift + 1,
109   IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift,
110 
111   HasRoundModeOpShift = IsSignExtendingOpWShift + 1,
112   HasRoundModeOpMask = 1 << HasRoundModeOpShift,
113 
114   UsesVXRMShift = HasRoundModeOpShift + 1,
115   UsesVXRMMask = 1 << UsesVXRMShift,
116 };
117 
118 enum VLMUL : uint8_t {
119   LMUL_1 = 0,
120   LMUL_2,
121   LMUL_4,
122   LMUL_8,
123   LMUL_RESERVED,
124   LMUL_F8,
125   LMUL_F4,
126   LMUL_F2
127 };
128 
129 enum {
130   TAIL_UNDISTURBED_MASK_UNDISTURBED = 0,
131   TAIL_AGNOSTIC = 1,
132   MASK_AGNOSTIC = 2,
133 };
134 
135 // Helper functions to read TSFlags.
136 /// \returns the format of the instruction.
137 static inline unsigned getFormat(uint64_t TSFlags) {
138   return (TSFlags & InstFormatMask) >> InstFormatShift;
139 }
140 /// \returns the LMUL for the instruction.
141 static inline VLMUL getLMul(uint64_t TSFlags) {
142   return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
143 }
144 /// \returns true if tail agnostic is enforced for the instruction.
145 static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
146   return TSFlags & ForceTailAgnosticMask;
147 }
148 /// \returns true if this a _TIED pseudo.
149 static inline bool isTiedPseudo(uint64_t TSFlags) {
150   return TSFlags & IsTiedPseudoMask;
151 }
152 /// \returns true if there is a SEW operand for the instruction.
153 static inline bool hasSEWOp(uint64_t TSFlags) {
154   return TSFlags & HasSEWOpMask;
155 }
156 /// \returns true if there is a VL operand for the instruction.
157 static inline bool hasVLOp(uint64_t TSFlags) {
158   return TSFlags & HasVLOpMask;
159 }
160 /// \returns true if there is a vector policy operand for this instruction.
161 static inline bool hasVecPolicyOp(uint64_t TSFlags) {
162   return TSFlags & HasVecPolicyOpMask;
163 }
164 /// \returns true if it is a vector widening reduction instruction.
165 static inline bool isRVVWideningReduction(uint64_t TSFlags) {
166   return TSFlags & IsRVVWideningReductionMask;
167 }
168 /// \returns true if mask policy is valid for the instruction.
169 static inline bool usesMaskPolicy(uint64_t TSFlags) {
170   return TSFlags & UsesMaskPolicyMask;
171 }
172 
173 /// \returns true if there is a rounding mode operand for this instruction
174 static inline bool hasRoundModeOp(uint64_t TSFlags) {
175   return TSFlags & HasRoundModeOpMask;
176 }
177 
178 /// \returns true if this instruction uses vxrm
179 static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
180 
181 static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
182   const uint64_t TSFlags = Desc.TSFlags;
183   // This method is only called if we expect to have a VL operand, and all
184   // instructions with VL also have SEW.
185   assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
186   unsigned Offset = 2;
187   if (hasVecPolicyOp(TSFlags))
188     Offset = 3;
189   return Desc.getNumOperands() - Offset;
190 }
191 
192 static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
193   const uint64_t TSFlags = Desc.TSFlags;
194   assert(hasSEWOp(TSFlags));
195   unsigned Offset = 1;
196   if (hasVecPolicyOp(TSFlags))
197     Offset = 2;
198   return Desc.getNumOperands() - Offset;
199 }
200 
201 static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
202   assert(hasVecPolicyOp(Desc.TSFlags));
203   return Desc.getNumOperands() - 1;
204 }
205 
206 /// \returns  the index to the rounding mode immediate value if any, otherwise
207 /// returns -1.
208 static inline int getFRMOpNum(const MCInstrDesc &Desc) {
209   const uint64_t TSFlags = Desc.TSFlags;
210   if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags))
211     return -1;
212 
213   // The operand order
214   // --------------------------------------
215   // | n-1 (if any)   | n-2  | n-3 | n-4 |
216   // | policy         | sew  | vl  | frm |
217   // --------------------------------------
218   return getVLOpNum(Desc) - 1;
219 }
220 
221 /// \returns  the index to the rounding mode immediate value if any, otherwise
222 /// returns -1.
223 static inline int getVXRMOpNum(const MCInstrDesc &Desc) {
224   const uint64_t TSFlags = Desc.TSFlags;
225   if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags))
226     return -1;
227   // The operand order
228   // --------------------------------------
229   // | n-1 (if any)   | n-2  | n-3 | n-4  |
230   // | policy         | sew  | vl  | vxrm |
231   // --------------------------------------
232   return getVLOpNum(Desc) - 1;
233 }
234 
235 // Is the first def operand tied to the first use operand. This is true for
236 // vector pseudo instructions that have a merge operand for tail/mask
237 // undisturbed. It's also true for vector FMA instructions where one of the
238 // operands is also the destination register.
239 static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
240   return Desc.getNumDefs() < Desc.getNumOperands() &&
241          Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0;
242 }
243 
244 // RISC-V Specific Machine Operand Flags
245 enum {
246   MO_None = 0,
247   MO_CALL = 1,
248   MO_PLT = 2,
249   MO_LO = 3,
250   MO_HI = 4,
251   MO_PCREL_LO = 5,
252   MO_PCREL_HI = 6,
253   MO_GOT_HI = 7,
254   MO_TPREL_LO = 8,
255   MO_TPREL_HI = 9,
256   MO_TPREL_ADD = 10,
257   MO_TLS_GOT_HI = 11,
258   MO_TLS_GD_HI = 12,
259 
260   // Used to differentiate between target-specific "direct" flags and "bitmask"
261   // flags. A machine operand can only have one "direct" flag, but can have
262   // multiple "bitmask" flags.
263   MO_DIRECT_FLAG_MASK = 15
264 };
265 } // namespace RISCVII
266 
267 namespace RISCVOp {
268 enum OperandType : unsigned {
269   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
270   OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM,
271   OPERAND_UIMM2,
272   OPERAND_UIMM2_LSB0,
273   OPERAND_UIMM3,
274   OPERAND_UIMM4,
275   OPERAND_UIMM5,
276   OPERAND_UIMM6,
277   OPERAND_UIMM7,
278   OPERAND_UIMM7_LSB00,
279   OPERAND_UIMM8_LSB00,
280   OPERAND_UIMM8,
281   OPERAND_UIMM8_LSB000,
282   OPERAND_UIMM8_GE32,
283   OPERAND_UIMM9_LSB000,
284   OPERAND_UIMM10_LSB00_NONZERO,
285   OPERAND_UIMM12,
286   OPERAND_ZERO,
287   OPERAND_SIMM5,
288   OPERAND_SIMM5_PLUS1,
289   OPERAND_SIMM6,
290   OPERAND_SIMM6_NONZERO,
291   OPERAND_SIMM10_LSB0000_NONZERO,
292   OPERAND_SIMM12,
293   OPERAND_SIMM12_LSB00000,
294   OPERAND_UIMM20,
295   OPERAND_UIMMLOG2XLEN,
296   OPERAND_UIMMLOG2XLEN_NONZERO,
297   OPERAND_CLUI_IMM,
298   OPERAND_VTYPEI10,
299   OPERAND_VTYPEI11,
300   OPERAND_RVKRNUM,
301   OPERAND_RVKRNUM_0_7,
302   OPERAND_RVKRNUM_1_10,
303   OPERAND_RVKRNUM_2_14,
304   OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM_2_14,
305   // Operand is either a register or uimm5, this is used by V extension pseudo
306   // instructions to represent a value that be passed as AVL to either vsetvli
307   // or vsetivli.
308   OPERAND_AVL,
309 };
310 } // namespace RISCVOp
311 
312 // Describes the predecessor/successor bits used in the FENCE instruction.
313 namespace RISCVFenceField {
314 enum FenceField {
315   I = 8,
316   O = 4,
317   R = 2,
318   W = 1
319 };
320 }
321 
322 // Describes the supported floating point rounding mode encodings.
323 namespace RISCVFPRndMode {
324 enum RoundingMode {
325   RNE = 0,
326   RTZ = 1,
327   RDN = 2,
328   RUP = 3,
329   RMM = 4,
330   DYN = 7,
331   Invalid
332 };
333 
334 inline static StringRef roundingModeToString(RoundingMode RndMode) {
335   switch (RndMode) {
336   default:
337     llvm_unreachable("Unknown floating point rounding mode");
338   case RISCVFPRndMode::RNE:
339     return "rne";
340   case RISCVFPRndMode::RTZ:
341     return "rtz";
342   case RISCVFPRndMode::RDN:
343     return "rdn";
344   case RISCVFPRndMode::RUP:
345     return "rup";
346   case RISCVFPRndMode::RMM:
347     return "rmm";
348   case RISCVFPRndMode::DYN:
349     return "dyn";
350   }
351 }
352 
353 inline static RoundingMode stringToRoundingMode(StringRef Str) {
354   return StringSwitch<RoundingMode>(Str)
355       .Case("rne", RISCVFPRndMode::RNE)
356       .Case("rtz", RISCVFPRndMode::RTZ)
357       .Case("rdn", RISCVFPRndMode::RDN)
358       .Case("rup", RISCVFPRndMode::RUP)
359       .Case("rmm", RISCVFPRndMode::RMM)
360       .Case("dyn", RISCVFPRndMode::DYN)
361       .Default(RISCVFPRndMode::Invalid);
362 }
363 
364 inline static bool isValidRoundingMode(unsigned Mode) {
365   switch (Mode) {
366   default:
367     return false;
368   case RISCVFPRndMode::RNE:
369   case RISCVFPRndMode::RTZ:
370   case RISCVFPRndMode::RDN:
371   case RISCVFPRndMode::RUP:
372   case RISCVFPRndMode::RMM:
373   case RISCVFPRndMode::DYN:
374     return true;
375   }
376 }
377 } // namespace RISCVFPRndMode
378 
379 //===----------------------------------------------------------------------===//
380 // Floating-point Immediates
381 //
382 
383 namespace RISCVLoadFPImm {
384 float getFPImm(unsigned Imm);
385 
386 /// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
387 /// immediate value. If the value cannot be represented as a 5-bit binary
388 /// encoding, then return -1.
389 int getLoadFPImm(APFloat FPImm);
390 } // namespace RISCVLoadFPImm
391 
392 namespace RISCVSysReg {
393 struct SysReg {
394   const char *Name;
395   const char *DeprecatedName;
396   unsigned Encoding;
397   // FIXME: add these additional fields when needed.
398   // Privilege Access: Read, Write, Read-Only.
399   // unsigned ReadWrite;
400   // Privilege Mode: User, System or Machine.
401   // unsigned Mode;
402   // Check field name.
403   // unsigned Extra;
404   // Register number without the privilege bits.
405   // unsigned Number;
406   FeatureBitset FeaturesRequired;
407   bool isRV32Only;
408 
409   bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
410     // Not in 32-bit mode.
411     if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
412       return false;
413     // No required feature associated with the system register.
414     if (FeaturesRequired.none())
415       return true;
416     return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
417   }
418 
419   bool haveVendorRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
420     // Not in 32-bit mode.
421     if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
422       return false;
423     // No required feature associated with the system register.
424     if (FeaturesRequired.none())
425       return false;
426     return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
427   }
428 };
429 
430 struct SiFiveReg : SysReg {};
431 
432 #define GET_SysRegsList_DECL
433 #define GET_SiFiveRegsList_DECL
434 #include "RISCVGenSearchableTables.inc"
435 } // end namespace RISCVSysReg
436 
437 namespace RISCVInsnOpcode {
438 struct RISCVOpcode {
439   const char *Name;
440   unsigned Value;
441 };
442 
443 #define GET_RISCVOpcodesList_DECL
444 #include "RISCVGenSearchableTables.inc"
445 } // end namespace RISCVInsnOpcode
446 
447 namespace RISCVABI {
448 
449 enum ABI {
450   ABI_ILP32,
451   ABI_ILP32F,
452   ABI_ILP32D,
453   ABI_ILP32E,
454   ABI_LP64,
455   ABI_LP64F,
456   ABI_LP64D,
457   ABI_LP64E,
458   ABI_Unknown
459 };
460 
461 // Returns the target ABI, or else a StringError if the requested ABIName is
462 // not supported for the given TT and FeatureBits combination.
463 ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
464                      StringRef ABIName);
465 
466 ABI getTargetABI(StringRef ABIName);
467 
468 // Returns the register used to hold the stack pointer after realignment.
469 MCRegister getBPReg();
470 
471 // Returns the register holding shadow call stack pointer.
472 MCRegister getSCSPReg();
473 
474 } // namespace RISCVABI
475 
476 namespace RISCVFeatures {
477 
478 // Validates if the given combination of features are valid for the target
479 // triple. Exits with report_fatal_error if not.
480 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
481 
482 llvm::Expected<std::unique_ptr<RISCVISAInfo>>
483 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
484 
485 } // namespace RISCVFeatures
486 
487 namespace RISCVVType {
488 // Is this a SEW value that can be encoded into the VTYPE format.
489 inline static bool isValidSEW(unsigned SEW) {
490   return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
491 }
492 
493 // Is this a LMUL value that can be encoded into the VTYPE format.
494 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
495   return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
496 }
497 
498 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
499                      bool MaskAgnostic);
500 
501 inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
502   unsigned VLMUL = VType & 0x7;
503   return static_cast<RISCVII::VLMUL>(VLMUL);
504 }
505 
506 // Decode VLMUL into 1,2,4,8 and fractional indicator.
507 std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
508 
509 inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
510   assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
511   unsigned LmulLog2 = Log2_32(LMUL);
512   return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
513 }
514 
515 inline static unsigned decodeVSEW(unsigned VSEW) {
516   assert(VSEW < 8 && "Unexpected VSEW value");
517   return 1 << (VSEW + 3);
518 }
519 
520 inline static unsigned encodeSEW(unsigned SEW) {
521   assert(isValidSEW(SEW) && "Unexpected SEW value");
522   return Log2_32(SEW) - 3;
523 }
524 
525 inline static unsigned getSEW(unsigned VType) {
526   unsigned VSEW = (VType >> 3) & 0x7;
527   return decodeVSEW(VSEW);
528 }
529 
530 inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
531 
532 inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
533 
534 void printVType(unsigned VType, raw_ostream &OS);
535 
536 unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
537 
538 std::optional<RISCVII::VLMUL>
539 getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
540 } // namespace RISCVVType
541 
542 namespace RISCVRVC {
543 bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
544 bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
545 } // namespace RISCVRVC
546 
547 namespace RISCVZC {
548 enum RLISTENCODE {
549   RA = 4,
550   RA_S0,
551   RA_S0_S1,
552   RA_S0_S2,
553   RA_S0_S3,
554   RA_S0_S4,
555   RA_S0_S5,
556   RA_S0_S6,
557   RA_S0_S7,
558   RA_S0_S8,
559   RA_S0_S9,
560   // note - to include s10, s11 must also be included
561   RA_S0_S11,
562   INVALID_RLIST,
563 };
564 
565 inline unsigned encodeRlist(MCRegister EndReg, bool IsRV32E = false) {
566   assert((!IsRV32E || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
567   switch (EndReg) {
568   case RISCV::X1:
569     return RLISTENCODE::RA;
570   case RISCV::X8:
571     return RLISTENCODE::RA_S0;
572   case RISCV::X9:
573     return RLISTENCODE::RA_S0_S1;
574   case RISCV::X18:
575     return RLISTENCODE::RA_S0_S2;
576   case RISCV::X19:
577     return RLISTENCODE::RA_S0_S3;
578   case RISCV::X20:
579     return RLISTENCODE::RA_S0_S4;
580   case RISCV::X21:
581     return RLISTENCODE::RA_S0_S5;
582   case RISCV::X22:
583     return RLISTENCODE::RA_S0_S6;
584   case RISCV::X23:
585     return RLISTENCODE::RA_S0_S7;
586   case RISCV::X24:
587     return RLISTENCODE::RA_S0_S8;
588   case RISCV::X25:
589     return RLISTENCODE::RA_S0_S9;
590   case RISCV::X26:
591     return RLISTENCODE::INVALID_RLIST;
592   case RISCV::X27:
593     return RLISTENCODE::RA_S0_S11;
594   default:
595     llvm_unreachable("Undefined input.");
596   }
597 }
598 
599 inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64,
600                                        bool IsEABI) {
601   assert(RlistVal != RLISTENCODE::INVALID_RLIST &&
602          "{ra, s0-s10} is not supported, s11 must be included.");
603   if (IsEABI)
604     return 16;
605   if (!IsRV64) {
606     switch (RlistVal) {
607     case RLISTENCODE::RA:
608     case RLISTENCODE::RA_S0:
609     case RLISTENCODE::RA_S0_S1:
610     case RLISTENCODE::RA_S0_S2:
611       return 16;
612     case RLISTENCODE::RA_S0_S3:
613     case RLISTENCODE::RA_S0_S4:
614     case RLISTENCODE::RA_S0_S5:
615     case RLISTENCODE::RA_S0_S6:
616       return 32;
617     case RLISTENCODE::RA_S0_S7:
618     case RLISTENCODE::RA_S0_S8:
619     case RLISTENCODE::RA_S0_S9:
620       return 48;
621     case RLISTENCODE::RA_S0_S11:
622       return 64;
623     }
624   } else {
625     switch (RlistVal) {
626     case RLISTENCODE::RA:
627     case RLISTENCODE::RA_S0:
628       return 16;
629     case RLISTENCODE::RA_S0_S1:
630     case RLISTENCODE::RA_S0_S2:
631       return 32;
632     case RLISTENCODE::RA_S0_S3:
633     case RLISTENCODE::RA_S0_S4:
634       return 48;
635     case RLISTENCODE::RA_S0_S5:
636     case RLISTENCODE::RA_S0_S6:
637       return 64;
638     case RLISTENCODE::RA_S0_S7:
639     case RLISTENCODE::RA_S0_S8:
640       return 80;
641     case RLISTENCODE::RA_S0_S9:
642       return 96;
643     case RLISTENCODE::RA_S0_S11:
644       return 112;
645     }
646   }
647   llvm_unreachable("Unexpected RlistVal");
648 }
649 
650 inline static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal,
651                             int64_t StackAdjustment, bool IsRV64, bool IsEABI) {
652   if (RlistVal == RLISTENCODE::INVALID_RLIST)
653     return false;
654   unsigned stackAdj = getStackAdjBase(RlistVal, IsRV64, IsEABI);
655   SpimmVal = (StackAdjustment - stackAdj) / 16;
656   if (SpimmVal > 3)
657     return false;
658   return true;
659 }
660 
661 void printRlist(unsigned SlistEncode, raw_ostream &OS);
662 void printSpimm(int64_t Spimm, raw_ostream &OS);
663 } // namespace RISCVZC
664 
665 } // namespace llvm
666 
667 #endif
668