1 //===-- RISCVInstPrinter.cpp - Convert RISC-V MCInst to asm syntax --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an RISC-V MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVInstPrinter.h"
14 #include "RISCVBaseInfo.h"
15 #include "RISCVMCExpr.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/MC/MCSymbol.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/FormattedStream.h"
25 using namespace llvm;
26 
27 #define DEBUG_TYPE "asm-printer"
28 
29 // Include the auto-generated portion of the assembly writer.
30 #define PRINT_ALIAS_INSTR
31 #include "RISCVGenAsmWriter.inc"
32 
33 static cl::opt<bool>
34     NoAliases("riscv-no-aliases",
35               cl::desc("Disable the emission of assembler pseudo instructions"),
36               cl::init(false), cl::Hidden);
37 
38 // Print architectural register names rather than the ABI names (such as x2
39 // instead of sp).
40 // TODO: Make RISCVInstPrinter::getRegisterName non-static so that this can a
41 // member.
42 static bool ArchRegNames;
43 
44 // The command-line flags above are used by llvm-mc and llc. They can be used by
45 // `llvm-objdump`, but we override their values here to handle options passed to
46 // `llvm-objdump` with `-M` (which matches GNU objdump). There did not seem to
47 // be an easier way to allow these options in all these tools, without doing it
48 // this way.
49 bool RISCVInstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
50   if (Opt == "no-aliases") {
51     PrintAliases = false;
52     return true;
53   }
54   if (Opt == "numeric") {
55     ArchRegNames = true;
56     return true;
57   }
58 
59   return false;
60 }
61 
62 void RISCVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
63                                  StringRef Annot, const MCSubtargetInfo &STI,
64                                  raw_ostream &O) {
65   bool Res = false;
66   const MCInst *NewMI = MI;
67   MCInst UncompressedMI;
68   if (PrintAliases && !NoAliases)
69     Res = RISCVRVC::uncompress(UncompressedMI, *MI, STI);
70   if (Res)
71     NewMI = const_cast<MCInst *>(&UncompressedMI);
72   if (!PrintAliases || NoAliases || !printAliasInstr(NewMI, Address, STI, O))
73     printInstruction(NewMI, Address, STI, O);
74   printAnnotation(O, Annot);
75 }
76 
77 void RISCVInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const {
78   O << getRegisterName(Reg);
79 }
80 
81 void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
82                                     const MCSubtargetInfo &STI, raw_ostream &O,
83                                     const char *Modifier) {
84   assert((Modifier == nullptr || Modifier[0] == 0) && "No modifiers supported");
85   const MCOperand &MO = MI->getOperand(OpNo);
86 
87   if (MO.isReg()) {
88     printRegName(O, MO.getReg());
89     return;
90   }
91 
92   if (MO.isImm()) {
93     O << MO.getImm();
94     return;
95   }
96 
97   assert(MO.isExpr() && "Unknown operand kind in printOperand");
98   MO.getExpr()->print(O, &MAI);
99 }
100 
101 void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
102                                           unsigned OpNo,
103                                           const MCSubtargetInfo &STI,
104                                           raw_ostream &O) {
105   const MCOperand &MO = MI->getOperand(OpNo);
106   if (!MO.isImm())
107     return printOperand(MI, OpNo, STI, O);
108 
109   if (PrintBranchImmAsAddress) {
110     uint64_t Target = Address + MO.getImm();
111     if (!STI.hasFeature(RISCV::Feature64Bit))
112       Target &= 0xffffffff;
113     O << formatHex(Target);
114   } else {
115     O << MO.getImm();
116   }
117 }
118 
119 void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
120                                               const MCSubtargetInfo &STI,
121                                               raw_ostream &O) {
122   unsigned Imm = MI->getOperand(OpNo).getImm();
123   auto SiFiveReg = RISCVSysReg::lookupSiFiveRegByEncoding(Imm);
124   auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm);
125   if (SiFiveReg && SiFiveReg->haveVendorRequiredFeatures(STI.getFeatureBits()))
126     O << SiFiveReg->Name;
127   else if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits()))
128     O << SysReg->Name;
129   else
130     O << Imm;
131 }
132 
133 void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
134                                      const MCSubtargetInfo &STI,
135                                      raw_ostream &O) {
136   unsigned FenceArg = MI->getOperand(OpNo).getImm();
137   assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg");
138 
139   if ((FenceArg & RISCVFenceField::I) != 0)
140     O << 'i';
141   if ((FenceArg & RISCVFenceField::O) != 0)
142     O << 'o';
143   if ((FenceArg & RISCVFenceField::R) != 0)
144     O << 'r';
145   if ((FenceArg & RISCVFenceField::W) != 0)
146     O << 'w';
147   if (FenceArg == 0)
148     O << "0";
149 }
150 
151 void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
152                                    const MCSubtargetInfo &STI, raw_ostream &O) {
153   auto FRMArg =
154       static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm());
155   if (PrintAliases && !NoAliases && FRMArg == RISCVFPRndMode::RoundingMode::DYN)
156     return;
157   O << ", " << RISCVFPRndMode::roundingModeToString(FRMArg);
158 }
159 
160 void RISCVInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNo,
161                                          const MCSubtargetInfo &STI,
162                                          raw_ostream &O) {
163   unsigned Imm = MI->getOperand(OpNo).getImm();
164   if (Imm == 1) {
165     O << "min";
166   } else if (Imm == 30) {
167     O << "inf";
168   } else if (Imm == 31) {
169     O << "nan";
170   } else {
171     float FPVal = RISCVLoadFPImm::getFPImm(Imm);
172     // If the value is an integer, print a .0 fraction. Otherwise, use %g to
173     // which will not print trailing zeros and will use scientific notation
174     // if it is shorter than printing as a decimal. The smallest value requires
175     // 12 digits of precision including the decimal.
176     if (FPVal == (int)(FPVal))
177       O << format("%.1f", FPVal);
178     else
179       O << format("%.12g", FPVal);
180   }
181 }
182 
183 void RISCVInstPrinter::printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo,
184                                             const MCSubtargetInfo &STI,
185                                             raw_ostream &O) {
186   const MCOperand &MO = MI->getOperand(OpNo);
187 
188   assert(MO.isReg() && "printZeroOffsetMemOp can only print register operands");
189   O << "(";
190   printRegName(O, MO.getReg());
191   O << ")";
192 }
193 
194 void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
195                                    const MCSubtargetInfo &STI, raw_ostream &O) {
196   unsigned Imm = MI->getOperand(OpNo).getImm();
197   // Print the raw immediate for reserved values: vlmul[2:0]=4, vsew[2:0]=0b1xx,
198   // or non-zero in bits 8 and above.
199   if (RISCVVType::getVLMUL(Imm) == RISCVII::VLMUL::LMUL_RESERVED ||
200       RISCVVType::getSEW(Imm) > 64 || (Imm >> 8) != 0) {
201     O << Imm;
202     return;
203   }
204   // Print the text form.
205   RISCVVType::printVType(Imm, O);
206 }
207 
208 void RISCVInstPrinter::printRlist(const MCInst *MI, unsigned OpNo,
209                                   const MCSubtargetInfo &STI, raw_ostream &O) {
210   unsigned Imm = MI->getOperand(OpNo).getImm();
211   O << "{";
212   switch (Imm) {
213   case RISCVZC::RLISTENCODE::RA:
214     O << (ArchRegNames ? "x1" : "ra");
215     break;
216   case RISCVZC::RLISTENCODE::RA_S0:
217     O << (ArchRegNames ? "x1, x8" : "ra, s0");
218     break;
219   case RISCVZC::RLISTENCODE::RA_S0_S1:
220     O << (ArchRegNames ? "x1, x8-x9" : "ra, s0-s1");
221     break;
222   case RISCVZC::RLISTENCODE::RA_S0_S2:
223     O << (ArchRegNames ? "x1, x8-x9, x18" : "ra, s0-s2");
224     break;
225   case RISCVZC::RLISTENCODE::RA_S0_S3:
226   case RISCVZC::RLISTENCODE::RA_S0_S4:
227   case RISCVZC::RLISTENCODE::RA_S0_S5:
228   case RISCVZC::RLISTENCODE::RA_S0_S6:
229   case RISCVZC::RLISTENCODE::RA_S0_S7:
230   case RISCVZC::RLISTENCODE::RA_S0_S8:
231   case RISCVZC::RLISTENCODE::RA_S0_S9:
232     O << (ArchRegNames ? "x1, x8-x9, x18-" : "ra, s0-")
233       << getRegisterName(RISCV::X19 + (Imm - RISCVZC::RLISTENCODE::RA_S0_S3));
234     break;
235   case RISCVZC::RLISTENCODE::RA_S0_S11:
236     O << (ArchRegNames ? "x1, x8-x9, x18-x27" : "ra, s0-s11");
237     break;
238   default:
239     llvm_unreachable("invalid register list");
240   }
241   O << "}";
242 }
243 
244 void RISCVInstPrinter::printSpimm(const MCInst *MI, unsigned OpNo,
245                                   const MCSubtargetInfo &STI, raw_ostream &O) {
246   int64_t Imm = MI->getOperand(OpNo).getImm();
247   unsigned Opcode = MI->getOpcode();
248   bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
249   bool IsEABI = STI.hasFeature(RISCV::FeatureRVE);
250   int64_t Spimm = 0;
251   auto RlistVal = MI->getOperand(0).getImm();
252   assert(RlistVal != 16 && "Incorrect rlist.");
253   auto Base = RISCVZC::getStackAdjBase(RlistVal, IsRV64, IsEABI);
254   Spimm = Imm + Base;
255   assert((Spimm >= Base && Spimm <= Base + 48) && "Incorrect spimm");
256   if (Opcode == RISCV::CM_PUSH)
257     Spimm = -Spimm;
258 
259   RISCVZC::printSpimm(Spimm, O);
260 }
261 
262 void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
263                                      const MCSubtargetInfo &STI,
264                                      raw_ostream &O) {
265   const MCOperand &MO = MI->getOperand(OpNo);
266 
267   assert(MO.isReg() && "printVMaskReg can only print register operands");
268   if (MO.getReg() == RISCV::NoRegister)
269     return;
270   O << ", ";
271   printRegName(O, MO.getReg());
272   O << ".t";
273 }
274 
275 const char *RISCVInstPrinter::getRegisterName(MCRegister Reg) {
276   return getRegisterName(Reg, ArchRegNames ? RISCV::NoRegAltName
277                                            : RISCV::ABIRegAltName);
278 }
279