1 //===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCVMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/RISCVBaseInfo.h"
14 #include "MCTargetDesc/RISCVFixupKinds.h"
15 #include "MCTargetDesc/RISCVMCExpr.h"
16 #include "MCTargetDesc/RISCVMCTargetDesc.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstBuilder.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/Support/Casting.h"
29 #include "llvm/Support/EndianStream.h"
30 #include "llvm/Support/raw_ostream.h"
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "mccodeemitter"
35 
36 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
37 STATISTIC(MCNumFixups, "Number of MC fixups created");
38 
39 namespace {
40 class RISCVMCCodeEmitter : public MCCodeEmitter {
41   RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete;
42   void operator=(const RISCVMCCodeEmitter &) = delete;
43   MCContext &Ctx;
44   MCInstrInfo const &MCII;
45 
46 public:
47   RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
48       : Ctx(ctx), MCII(MCII) {}
49 
50   ~RISCVMCCodeEmitter() override = default;
51 
52   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
53                          SmallVectorImpl<MCFixup> &Fixups,
54                          const MCSubtargetInfo &STI) const override;
55 
56   void expandFunctionCall(const MCInst &MI, raw_ostream &OS,
57                           SmallVectorImpl<MCFixup> &Fixups,
58                           const MCSubtargetInfo &STI) const;
59 
60   void expandAddTPRel(const MCInst &MI, raw_ostream &OS,
61                       SmallVectorImpl<MCFixup> &Fixups,
62                       const MCSubtargetInfo &STI) const;
63 
64   /// TableGen'erated function for getting the binary encoding for an
65   /// instruction.
66   uint64_t getBinaryCodeForInstr(const MCInst &MI,
67                                  SmallVectorImpl<MCFixup> &Fixups,
68                                  const MCSubtargetInfo &STI) const;
69 
70   /// Return binary encoding of operand. If the machine operand requires
71   /// relocation, record the relocation and return zero.
72   unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
73                              SmallVectorImpl<MCFixup> &Fixups,
74                              const MCSubtargetInfo &STI) const;
75 
76   unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
77                              SmallVectorImpl<MCFixup> &Fixups,
78                              const MCSubtargetInfo &STI) const;
79 
80   unsigned getImmOpValue(const MCInst &MI, unsigned OpNo,
81                          SmallVectorImpl<MCFixup> &Fixups,
82                          const MCSubtargetInfo &STI) const;
83 
84   unsigned getVMaskReg(const MCInst &MI, unsigned OpNo,
85                        SmallVectorImpl<MCFixup> &Fixups,
86                        const MCSubtargetInfo &STI) const;
87 };
88 } // end anonymous namespace
89 
90 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
91                                               MCContext &Ctx) {
92   return new RISCVMCCodeEmitter(Ctx, MCII);
93 }
94 
95 // Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with
96 // relocation types. We expand those pseudo-instructions while encoding them,
97 // meaning AUIPC and JALR won't go through RISCV MC to MC compressed
98 // instruction transformation. This is acceptable because AUIPC has no 16-bit
99 // form and C_JALR has no immediate operand field.  We let linker relaxation
100 // deal with it. When linker relaxation is enabled, AUIPC and JALR have a
101 // chance to relax to JAL.
102 // If the C extension is enabled, JAL has a chance relax to C_JAL.
103 void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
104                                             SmallVectorImpl<MCFixup> &Fixups,
105                                             const MCSubtargetInfo &STI) const {
106   MCInst TmpInst;
107   MCOperand Func;
108   MCRegister Ra;
109   if (MI.getOpcode() == RISCV::PseudoTAIL) {
110     Func = MI.getOperand(0);
111     Ra = RISCV::X6;
112   } else if (MI.getOpcode() == RISCV::PseudoCALLReg) {
113     Func = MI.getOperand(1);
114     Ra = MI.getOperand(0).getReg();
115   } else if (MI.getOpcode() == RISCV::PseudoCALL) {
116     Func = MI.getOperand(0);
117     Ra = RISCV::X1;
118   } else if (MI.getOpcode() == RISCV::PseudoJump) {
119     Func = MI.getOperand(1);
120     Ra = MI.getOperand(0).getReg();
121   }
122   uint32_t Binary;
123 
124   assert(Func.isExpr() && "Expected expression");
125 
126   const MCExpr *CallExpr = Func.getExpr();
127 
128   // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
129   TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addExpr(CallExpr);
130   Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
131   support::endian::write(OS, Binary, support::little);
132 
133   if (MI.getOpcode() == RISCV::PseudoTAIL ||
134       MI.getOpcode() == RISCV::PseudoJump)
135     // Emit JALR X0, Ra, 0
136     TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
137   else
138     // Emit JALR Ra, Ra, 0
139     TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
140   Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
141   support::endian::write(OS, Binary, support::little);
142 }
143 
144 // Expand PseudoAddTPRel to a simple ADD with the correct relocation.
145 void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS,
146                                         SmallVectorImpl<MCFixup> &Fixups,
147                                         const MCSubtargetInfo &STI) const {
148   MCOperand DestReg = MI.getOperand(0);
149   MCOperand SrcReg = MI.getOperand(1);
150   MCOperand TPReg = MI.getOperand(2);
151   assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 &&
152          "Expected thread pointer as second input to TP-relative add");
153 
154   MCOperand SrcSymbol = MI.getOperand(3);
155   assert(SrcSymbol.isExpr() &&
156          "Expected expression as third input to TP-relative add");
157 
158   const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
159   assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD &&
160          "Expected tprel_add relocation on TP-relative symbol");
161 
162   // Emit the correct tprel_add relocation for the symbol.
163   Fixups.push_back(MCFixup::create(
164       0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc()));
165 
166   // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled.
167   if (STI.getFeatureBits()[RISCV::FeatureRelax]) {
168     const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
169     Fixups.push_back(MCFixup::create(
170         0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc()));
171   }
172 
173   // Emit a normal ADD instruction with the given operands.
174   MCInst TmpInst = MCInstBuilder(RISCV::ADD)
175                        .addOperand(DestReg)
176                        .addOperand(SrcReg)
177                        .addOperand(TPReg);
178   uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
179   support::endian::write(OS, Binary, support::little);
180 }
181 
182 void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
183                                            SmallVectorImpl<MCFixup> &Fixups,
184                                            const MCSubtargetInfo &STI) const {
185   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
186   // Get byte count of instruction.
187   unsigned Size = Desc.getSize();
188 
189   // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
190   // expanded instructions for each pseudo is correct in the Size field of the
191   // tablegen definition for the pseudo.
192   if (MI.getOpcode() == RISCV::PseudoCALLReg ||
193       MI.getOpcode() == RISCV::PseudoCALL ||
194       MI.getOpcode() == RISCV::PseudoTAIL ||
195       MI.getOpcode() == RISCV::PseudoJump) {
196     expandFunctionCall(MI, OS, Fixups, STI);
197     MCNumEmitted += 2;
198     return;
199   }
200 
201   if (MI.getOpcode() == RISCV::PseudoAddTPRel) {
202     expandAddTPRel(MI, OS, Fixups, STI);
203     MCNumEmitted += 1;
204     return;
205   }
206 
207   switch (Size) {
208   default:
209     llvm_unreachable("Unhandled encodeInstruction length!");
210   case 2: {
211     uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
212     support::endian::write<uint16_t>(OS, Bits, support::little);
213     break;
214   }
215   case 4: {
216     uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
217     support::endian::write(OS, Bits, support::little);
218     break;
219   }
220   }
221 
222   ++MCNumEmitted; // Keep track of the # of mi's emitted.
223 }
224 
225 unsigned
226 RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
227                                       SmallVectorImpl<MCFixup> &Fixups,
228                                       const MCSubtargetInfo &STI) const {
229 
230   if (MO.isReg())
231     return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
232 
233   if (MO.isImm())
234     return static_cast<unsigned>(MO.getImm());
235 
236   llvm_unreachable("Unhandled expression!");
237   return 0;
238 }
239 
240 unsigned
241 RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
242                                       SmallVectorImpl<MCFixup> &Fixups,
243                                       const MCSubtargetInfo &STI) const {
244   const MCOperand &MO = MI.getOperand(OpNo);
245 
246   if (MO.isImm()) {
247     unsigned Res = MO.getImm();
248     assert((Res & 1) == 0 && "LSB is non-zero");
249     return Res >> 1;
250   }
251 
252   return getImmOpValue(MI, OpNo, Fixups, STI);
253 }
254 
255 unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
256                                            SmallVectorImpl<MCFixup> &Fixups,
257                                            const MCSubtargetInfo &STI) const {
258   bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax];
259   const MCOperand &MO = MI.getOperand(OpNo);
260 
261   MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
262   unsigned MIFrm = RISCVII::getFormat(Desc.TSFlags);
263 
264   // If the destination is an immediate, there is nothing to do.
265   if (MO.isImm())
266     return MO.getImm();
267 
268   assert(MO.isExpr() &&
269          "getImmOpValue expects only expressions or immediates");
270   const MCExpr *Expr = MO.getExpr();
271   MCExpr::ExprKind Kind = Expr->getKind();
272   RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid;
273   bool RelaxCandidate = false;
274   if (Kind == MCExpr::Target) {
275     const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
276 
277     switch (RVExpr->getKind()) {
278     case RISCVMCExpr::VK_RISCV_None:
279     case RISCVMCExpr::VK_RISCV_Invalid:
280     case RISCVMCExpr::VK_RISCV_32_PCREL:
281       llvm_unreachable("Unhandled fixup kind!");
282     case RISCVMCExpr::VK_RISCV_TPREL_ADD:
283       // tprel_add is only used to indicate that a relocation should be emitted
284       // for an add instruction used in TP-relative addressing. It should not be
285       // expanded as if representing an actual instruction operand and so to
286       // encounter it here is an error.
287       llvm_unreachable(
288           "VK_RISCV_TPREL_ADD should not represent an instruction operand");
289     case RISCVMCExpr::VK_RISCV_LO:
290       if (MIFrm == RISCVII::InstFormatI)
291         FixupKind = RISCV::fixup_riscv_lo12_i;
292       else if (MIFrm == RISCVII::InstFormatS)
293         FixupKind = RISCV::fixup_riscv_lo12_s;
294       else
295         llvm_unreachable("VK_RISCV_LO used with unexpected instruction format");
296       RelaxCandidate = true;
297       break;
298     case RISCVMCExpr::VK_RISCV_HI:
299       FixupKind = RISCV::fixup_riscv_hi20;
300       RelaxCandidate = true;
301       break;
302     case RISCVMCExpr::VK_RISCV_PCREL_LO:
303       if (MIFrm == RISCVII::InstFormatI)
304         FixupKind = RISCV::fixup_riscv_pcrel_lo12_i;
305       else if (MIFrm == RISCVII::InstFormatS)
306         FixupKind = RISCV::fixup_riscv_pcrel_lo12_s;
307       else
308         llvm_unreachable(
309             "VK_RISCV_PCREL_LO used with unexpected instruction format");
310       RelaxCandidate = true;
311       break;
312     case RISCVMCExpr::VK_RISCV_PCREL_HI:
313       FixupKind = RISCV::fixup_riscv_pcrel_hi20;
314       RelaxCandidate = true;
315       break;
316     case RISCVMCExpr::VK_RISCV_GOT_HI:
317       FixupKind = RISCV::fixup_riscv_got_hi20;
318       break;
319     case RISCVMCExpr::VK_RISCV_TPREL_LO:
320       if (MIFrm == RISCVII::InstFormatI)
321         FixupKind = RISCV::fixup_riscv_tprel_lo12_i;
322       else if (MIFrm == RISCVII::InstFormatS)
323         FixupKind = RISCV::fixup_riscv_tprel_lo12_s;
324       else
325         llvm_unreachable(
326             "VK_RISCV_TPREL_LO used with unexpected instruction format");
327       RelaxCandidate = true;
328       break;
329     case RISCVMCExpr::VK_RISCV_TPREL_HI:
330       FixupKind = RISCV::fixup_riscv_tprel_hi20;
331       RelaxCandidate = true;
332       break;
333     case RISCVMCExpr::VK_RISCV_TLS_GOT_HI:
334       FixupKind = RISCV::fixup_riscv_tls_got_hi20;
335       break;
336     case RISCVMCExpr::VK_RISCV_TLS_GD_HI:
337       FixupKind = RISCV::fixup_riscv_tls_gd_hi20;
338       break;
339     case RISCVMCExpr::VK_RISCV_CALL:
340       FixupKind = RISCV::fixup_riscv_call;
341       RelaxCandidate = true;
342       break;
343     case RISCVMCExpr::VK_RISCV_CALL_PLT:
344       FixupKind = RISCV::fixup_riscv_call_plt;
345       RelaxCandidate = true;
346       break;
347     }
348   } else if (Kind == MCExpr::SymbolRef &&
349              cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) {
350     if (MIFrm == RISCVII::InstFormatJ) {
351       FixupKind = RISCV::fixup_riscv_jal;
352     } else if (MIFrm == RISCVII::InstFormatB) {
353       FixupKind = RISCV::fixup_riscv_branch;
354     } else if (MIFrm == RISCVII::InstFormatCJ) {
355       FixupKind = RISCV::fixup_riscv_rvc_jump;
356     } else if (MIFrm == RISCVII::InstFormatCB) {
357       FixupKind = RISCV::fixup_riscv_rvc_branch;
358     }
359   }
360 
361   assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");
362 
363   Fixups.push_back(
364       MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
365   ++MCNumFixups;
366 
367   // Ensure an R_RISCV_RELAX relocation will be emitted if linker relaxation is
368   // enabled and the current fixup will result in a relocation that may be
369   // relaxed.
370   if (EnableRelax && RelaxCandidate) {
371     const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
372     Fixups.push_back(
373     MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax),
374                     MI.getLoc()));
375     ++MCNumFixups;
376   }
377 
378   return 0;
379 }
380 
381 unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo,
382                                          SmallVectorImpl<MCFixup> &Fixups,
383                                          const MCSubtargetInfo &STI) const {
384   MCOperand MO = MI.getOperand(OpNo);
385   assert(MO.isReg() && "Expected a register.");
386 
387   switch (MO.getReg()) {
388   default:
389     llvm_unreachable("Invalid mask register.");
390   case RISCV::V0:
391     return 0;
392   case RISCV::NoRegister:
393     return 1;
394   }
395 }
396 
397 #include "RISCVGenMCCodeEmitter.inc"
398