1 //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This file provides RISCV-specific target descriptions.
10 ///
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVMCTargetDesc.h"
14 #include "RISCVBaseInfo.h"
15 #include "RISCVELFStreamer.h"
16 #include "RISCVInstPrinter.h"
17 #include "RISCVMCAsmInfo.h"
18 #include "RISCVTargetStreamer.h"
19 #include "TargetInfo/RISCVTargetInfo.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/MC/MCAsmBackend.h"
22 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/MC/MCCodeEmitter.h"
24 #include "llvm/MC/MCInstrAnalysis.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCObjectWriter.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/MC/MCSubtargetInfo.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/TargetRegistry.h"
32 
33 #define GET_INSTRINFO_MC_DESC
34 #include "RISCVGenInstrInfo.inc"
35 
36 #define GET_REGINFO_MC_DESC
37 #include "RISCVGenRegisterInfo.inc"
38 
39 #define GET_SUBTARGETINFO_MC_DESC
40 #include "RISCVGenSubtargetInfo.inc"
41 
42 using namespace llvm;
43 
44 static MCInstrInfo *createRISCVMCInstrInfo() {
45   MCInstrInfo *X = new MCInstrInfo();
46   InitRISCVMCInstrInfo(X);
47   return X;
48 }
49 
50 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
51   MCRegisterInfo *X = new MCRegisterInfo();
52   InitRISCVMCRegisterInfo(X, RISCV::X1);
53   return X;
54 }
55 
56 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
57                                        const Triple &TT,
58                                        const MCTargetOptions &Options) {
59   MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
60 
61   MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true);
62   MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0);
63   MAI->addInitialFrameState(Inst);
64 
65   return MAI;
66 }
67 
68 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
69                                                    StringRef CPU, StringRef FS) {
70   if (CPU.empty())
71     CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
72   if (CPU == "generic")
73     report_fatal_error(Twine("CPU 'generic' is not supported. Use ") +
74                        (TT.isArch64Bit() ? "generic-rv64" : "generic-rv32"));
75   return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
76 }
77 
78 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
79                                                unsigned SyntaxVariant,
80                                                const MCAsmInfo &MAI,
81                                                const MCInstrInfo &MII,
82                                                const MCRegisterInfo &MRI) {
83   return new RISCVInstPrinter(MAI, MII, MRI);
84 }
85 
86 static MCTargetStreamer *
87 createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
88   const Triple &TT = STI.getTargetTriple();
89   if (TT.isOSBinFormatELF())
90     return new RISCVTargetELFStreamer(S, STI);
91   return nullptr;
92 }
93 
94 static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S,
95                                                       formatted_raw_ostream &OS,
96                                                       MCInstPrinter *InstPrint,
97                                                       bool isVerboseAsm) {
98   return new RISCVTargetAsmStreamer(S, OS);
99 }
100 
101 static MCTargetStreamer *createRISCVNullTargetStreamer(MCStreamer &S) {
102   return new RISCVTargetStreamer(S);
103 }
104 
105 namespace {
106 
107 class RISCVMCInstrAnalysis : public MCInstrAnalysis {
108 public:
109   explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
110       : MCInstrAnalysis(Info) {}
111 
112   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
113                       uint64_t &Target) const override {
114     if (isConditionalBranch(Inst)) {
115       int64_t Imm;
116       if (Size == 2)
117         Imm = Inst.getOperand(1).getImm();
118       else
119         Imm = Inst.getOperand(2).getImm();
120       Target = Addr + Imm;
121       return true;
122     }
123 
124     if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) {
125       Target = Addr + Inst.getOperand(0).getImm();
126       return true;
127     }
128 
129     if (Inst.getOpcode() == RISCV::JAL) {
130       Target = Addr + Inst.getOperand(1).getImm();
131       return true;
132     }
133 
134     return false;
135   }
136 };
137 
138 } // end anonymous namespace
139 
140 static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) {
141   return new RISCVMCInstrAnalysis(Info);
142 }
143 
144 namespace {
145 MCStreamer *createRISCVELFStreamer(const Triple &T, MCContext &Context,
146                                    std::unique_ptr<MCAsmBackend> &&MAB,
147                                    std::unique_ptr<MCObjectWriter> &&MOW,
148                                    std::unique_ptr<MCCodeEmitter> &&MCE,
149                                    bool RelaxAll) {
150   return createRISCVELFStreamer(Context, std::move(MAB), std::move(MOW),
151                                 std::move(MCE), RelaxAll);
152 }
153 } // end anonymous namespace
154 
155 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
156   for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
157     TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
158     TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
159     TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
160     TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
161     TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
162     TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
163     TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
164     TargetRegistry::RegisterELFStreamer(*T, createRISCVELFStreamer);
165     TargetRegistry::RegisterObjectTargetStreamer(
166         *T, createRISCVObjectTargetStreamer);
167     TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis);
168 
169     // Register the asm target streamer.
170     TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
171     // Register the null target streamer.
172     TargetRegistry::RegisterNullTargetStreamer(*T,
173                                                createRISCVNullTargetStreamer);
174   }
175 }
176