1e8d8bef9SDimitry Andric //===- RISCVMatInt.cpp - Immediate materialisation -------------*- C++ -*--===//
2e8d8bef9SDimitry Andric //
3e8d8bef9SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4e8d8bef9SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5e8d8bef9SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6e8d8bef9SDimitry Andric //
7e8d8bef9SDimitry Andric //===----------------------------------------------------------------------===//
8e8d8bef9SDimitry Andric
9e8d8bef9SDimitry Andric #include "RISCVMatInt.h"
10e8d8bef9SDimitry Andric #include "MCTargetDesc/RISCVMCTargetDesc.h"
11e8d8bef9SDimitry Andric #include "llvm/ADT/APInt.h"
12e8d8bef9SDimitry Andric #include "llvm/Support/MathExtras.h"
13fe6060f1SDimitry Andric using namespace llvm;
14e8d8bef9SDimitry Andric
getInstSeqCost(RISCVMatInt::InstSeq & Res,bool HasRVC)15fe6060f1SDimitry Andric static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
16fe6060f1SDimitry Andric if (!HasRVC)
17fe6060f1SDimitry Andric return Res.size();
18e8d8bef9SDimitry Andric
19fe6060f1SDimitry Andric int Cost = 0;
20fe6060f1SDimitry Andric for (auto Instr : Res) {
2181ad6265SDimitry Andric // Assume instructions that aren't listed aren't compressible.
2281ad6265SDimitry Andric bool Compressed = false;
23bdd1243dSDimitry Andric switch (Instr.getOpcode()) {
24fe6060f1SDimitry Andric case RISCV::SLLI:
25fe6060f1SDimitry Andric case RISCV::SRLI:
26fe6060f1SDimitry Andric Compressed = true;
27fe6060f1SDimitry Andric break;
28fe6060f1SDimitry Andric case RISCV::ADDI:
29fe6060f1SDimitry Andric case RISCV::ADDIW:
30fe6060f1SDimitry Andric case RISCV::LUI:
31bdd1243dSDimitry Andric Compressed = isInt<6>(Instr.getImm());
32fe6060f1SDimitry Andric break;
33fe6060f1SDimitry Andric }
34fe6060f1SDimitry Andric // Two RVC instructions take the same space as one RVI instruction, but
35fe6060f1SDimitry Andric // can take longer to execute than the single RVI instruction. Thus, we
36fe6060f1SDimitry Andric // consider that two RVC instruction are slightly more costly than one
37fe6060f1SDimitry Andric // RVI instruction. For longer sequences of RVC instructions the space
38fe6060f1SDimitry Andric // savings can be worth it, though. The costs below try to model that.
39fe6060f1SDimitry Andric if (!Compressed)
40fe6060f1SDimitry Andric Cost += 100; // Baseline cost of one RVI instruction: 100%.
41fe6060f1SDimitry Andric else
42fe6060f1SDimitry Andric Cost += 70; // 70% cost of baseline.
43fe6060f1SDimitry Andric }
44fe6060f1SDimitry Andric return Cost;
45fe6060f1SDimitry Andric }
46fe6060f1SDimitry Andric
47fe6060f1SDimitry Andric // Recursively generate a sequence for materializing an integer.
generateInstSeqImpl(int64_t Val,const MCSubtargetInfo & STI,RISCVMatInt::InstSeq & Res)48*5f757f3fSDimitry Andric static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
49fe6060f1SDimitry Andric RISCVMatInt::InstSeq &Res) {
50*5f757f3fSDimitry Andric bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
51fe6060f1SDimitry Andric
52bdd1243dSDimitry Andric // Use BSETI for a single bit that can't be expressed by a single LUI or ADDI.
53*5f757f3fSDimitry Andric if (STI.hasFeature(RISCV::FeatureStdExtZbs) && isPowerOf2_64(Val) &&
54bdd1243dSDimitry Andric (!isInt<32>(Val) || Val == 0x800)) {
55bdd1243dSDimitry Andric Res.emplace_back(RISCV::BSETI, Log2_64(Val));
56bdd1243dSDimitry Andric return;
57bdd1243dSDimitry Andric }
58bdd1243dSDimitry Andric
59e8d8bef9SDimitry Andric if (isInt<32>(Val)) {
60e8d8bef9SDimitry Andric // Depending on the active bits in the immediate Value v, the following
61e8d8bef9SDimitry Andric // instruction sequences are emitted:
62e8d8bef9SDimitry Andric //
63e8d8bef9SDimitry Andric // v == 0 : ADDI
64e8d8bef9SDimitry Andric // v[0,12) != 0 && v[12,32) == 0 : ADDI
65e8d8bef9SDimitry Andric // v[0,12) == 0 && v[12,32) != 0 : LUI
66e8d8bef9SDimitry Andric // v[0,32) != 0 : LUI+ADDI(W)
67e8d8bef9SDimitry Andric int64_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF;
68e8d8bef9SDimitry Andric int64_t Lo12 = SignExtend64<12>(Val);
69e8d8bef9SDimitry Andric
70e8d8bef9SDimitry Andric if (Hi20)
71bdd1243dSDimitry Andric Res.emplace_back(RISCV::LUI, Hi20);
72e8d8bef9SDimitry Andric
73e8d8bef9SDimitry Andric if (Lo12 || Hi20 == 0) {
74e8d8bef9SDimitry Andric unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI;
75bdd1243dSDimitry Andric Res.emplace_back(AddiOpc, Lo12);
76e8d8bef9SDimitry Andric }
77e8d8bef9SDimitry Andric return;
78e8d8bef9SDimitry Andric }
79e8d8bef9SDimitry Andric
80e8d8bef9SDimitry Andric assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target");
81e8d8bef9SDimitry Andric
82e8d8bef9SDimitry Andric // In the worst case, for a full 64-bit constant, a sequence of 8 instructions
83349cc55cSDimitry Andric // (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emitted. Note
84e8d8bef9SDimitry Andric // that the first two instructions (LUI+ADDIW) can contribute up to 32 bits
85e8d8bef9SDimitry Andric // while the following ADDI instructions contribute up to 12 bits each.
86e8d8bef9SDimitry Andric //
87e8d8bef9SDimitry Andric // On the first glance, implementing this seems to be possible by simply
88e8d8bef9SDimitry Andric // emitting the most significant 32 bits (LUI+ADDIW) followed by as many left
89e8d8bef9SDimitry Andric // shift (SLLI) and immediate additions (ADDI) as needed. However, due to the
90e8d8bef9SDimitry Andric // fact that ADDI performs a sign extended addition, doing it like that would
91e8d8bef9SDimitry Andric // only be possible when at most 11 bits of the ADDI instructions are used.
92e8d8bef9SDimitry Andric // Using all 12 bits of the ADDI instructions, like done by GAS, actually
93e8d8bef9SDimitry Andric // requires that the constant is processed starting with the least significant
94e8d8bef9SDimitry Andric // bit.
95e8d8bef9SDimitry Andric //
96e8d8bef9SDimitry Andric // In the following, constants are processed from LSB to MSB but instruction
97e8d8bef9SDimitry Andric // emission is performed from MSB to LSB by recursively calling
98e8d8bef9SDimitry Andric // generateInstSeq. In each recursion, first the lowest 12 bits are removed
99e8d8bef9SDimitry Andric // from the constant and the optimal shift amount, which can be greater than
100e8d8bef9SDimitry Andric // 12 bits if the constant is sparse, is determined. Then, the shifted
101e8d8bef9SDimitry Andric // remaining constant is processed recursively and gets emitted as soon as it
102e8d8bef9SDimitry Andric // fits into 32 bits. The emission of the shifts and additions is subsequently
103e8d8bef9SDimitry Andric // performed when the recursion returns.
104e8d8bef9SDimitry Andric
105e8d8bef9SDimitry Andric int64_t Lo12 = SignExtend64<12>(Val);
10681ad6265SDimitry Andric Val = (uint64_t)Val - (uint64_t)Lo12;
10781ad6265SDimitry Andric
10881ad6265SDimitry Andric int ShiftAmount = 0;
10981ad6265SDimitry Andric bool Unsigned = false;
11081ad6265SDimitry Andric
11181ad6265SDimitry Andric // Val might now be valid for LUI without needing a shift.
11281ad6265SDimitry Andric if (!isInt<32>(Val)) {
113bdd1243dSDimitry Andric ShiftAmount = llvm::countr_zero((uint64_t)Val);
11481ad6265SDimitry Andric Val >>= ShiftAmount;
115e8d8bef9SDimitry Andric
116fe6060f1SDimitry Andric // If the remaining bits don't fit in 12 bits, we might be able to reduce the
117fe6060f1SDimitry Andric // shift amount in order to use LUI which will zero the lower 12 bits.
11881ad6265SDimitry Andric if (ShiftAmount > 12 && !isInt<12>(Val)) {
11981ad6265SDimitry Andric if (isInt<32>((uint64_t)Val << 12)) {
120fe6060f1SDimitry Andric // Reduce the shift amount and add zeros to the LSBs so it will match LUI.
121fe6060f1SDimitry Andric ShiftAmount -= 12;
12281ad6265SDimitry Andric Val = (uint64_t)Val << 12;
12381ad6265SDimitry Andric } else if (isUInt<32>((uint64_t)Val << 12) &&
124*5f757f3fSDimitry Andric STI.hasFeature(RISCV::FeatureStdExtZba)) {
125349cc55cSDimitry Andric // Reduce the shift amount and add zeros to the LSBs so it will match
126349cc55cSDimitry Andric // LUI, then shift left with SLLI.UW to clear the upper 32 set bits.
127349cc55cSDimitry Andric ShiftAmount -= 12;
12881ad6265SDimitry Andric Val = ((uint64_t)Val << 12) | (0xffffffffull << 32);
129349cc55cSDimitry Andric Unsigned = true;
130349cc55cSDimitry Andric }
131349cc55cSDimitry Andric }
132349cc55cSDimitry Andric
13381ad6265SDimitry Andric // Try to use SLLI_UW for Val when it is uint32 but not int32.
13481ad6265SDimitry Andric if (isUInt<32>((uint64_t)Val) && !isInt<32>((uint64_t)Val) &&
135*5f757f3fSDimitry Andric STI.hasFeature(RISCV::FeatureStdExtZba)) {
1361fd87a68SDimitry Andric // Use LUI+ADDI or LUI to compose, then clear the upper 32 bits with
1371fd87a68SDimitry Andric // SLLI_UW.
13881ad6265SDimitry Andric Val = ((uint64_t)Val) | (0xffffffffull << 32);
139349cc55cSDimitry Andric Unsigned = true;
140e8d8bef9SDimitry Andric }
14181ad6265SDimitry Andric }
142e8d8bef9SDimitry Andric
143*5f757f3fSDimitry Andric generateInstSeqImpl(Val, STI, Res);
144fe6060f1SDimitry Andric
14581ad6265SDimitry Andric // Skip shift if we were able to use LUI directly.
14681ad6265SDimitry Andric if (ShiftAmount) {
147bdd1243dSDimitry Andric unsigned Opc = Unsigned ? RISCV::SLLI_UW : RISCV::SLLI;
148bdd1243dSDimitry Andric Res.emplace_back(Opc, ShiftAmount);
14981ad6265SDimitry Andric }
15081ad6265SDimitry Andric
151fe6060f1SDimitry Andric if (Lo12)
152bdd1243dSDimitry Andric Res.emplace_back(RISCV::ADDI, Lo12);
153fe6060f1SDimitry Andric }
154fe6060f1SDimitry Andric
extractRotateInfo(int64_t Val)15504eeddc0SDimitry Andric static unsigned extractRotateInfo(int64_t Val) {
15604eeddc0SDimitry Andric // for case: 0b111..1..xxxxxx1..1..
15706c3fb27SDimitry Andric unsigned LeadingOnes = llvm::countl_one((uint64_t)Val);
15806c3fb27SDimitry Andric unsigned TrailingOnes = llvm::countr_one((uint64_t)Val);
15904eeddc0SDimitry Andric if (TrailingOnes > 0 && TrailingOnes < 64 &&
16004eeddc0SDimitry Andric (LeadingOnes + TrailingOnes) > (64 - 12))
16104eeddc0SDimitry Andric return 64 - TrailingOnes;
16204eeddc0SDimitry Andric
16304eeddc0SDimitry Andric // for case: 0bxxx1..1..1...xxx
16406c3fb27SDimitry Andric unsigned UpperTrailingOnes = llvm::countr_one(Hi_32(Val));
16506c3fb27SDimitry Andric unsigned LowerLeadingOnes = llvm::countl_one(Lo_32(Val));
16604eeddc0SDimitry Andric if (UpperTrailingOnes < 32 &&
16704eeddc0SDimitry Andric (UpperTrailingOnes + LowerLeadingOnes) > (64 - 12))
16804eeddc0SDimitry Andric return 32 - UpperTrailingOnes;
16904eeddc0SDimitry Andric
17004eeddc0SDimitry Andric return 0;
17104eeddc0SDimitry Andric }
17204eeddc0SDimitry Andric
generateInstSeqLeadingZeros(int64_t Val,const MCSubtargetInfo & STI,RISCVMatInt::InstSeq & Res)173*5f757f3fSDimitry Andric static void generateInstSeqLeadingZeros(int64_t Val, const MCSubtargetInfo &STI,
174*5f757f3fSDimitry Andric RISCVMatInt::InstSeq &Res) {
175*5f757f3fSDimitry Andric assert(Val > 0 && "Expected postive val");
176*5f757f3fSDimitry Andric
177*5f757f3fSDimitry Andric unsigned LeadingZeros = llvm::countl_zero((uint64_t)Val);
178*5f757f3fSDimitry Andric uint64_t ShiftedVal = (uint64_t)Val << LeadingZeros;
179*5f757f3fSDimitry Andric // Fill in the bits that will be shifted out with 1s. An example where this
180*5f757f3fSDimitry Andric // helps is trailing one masks with 32 or more ones. This will generate
181*5f757f3fSDimitry Andric // ADDI -1 and an SRLI.
182*5f757f3fSDimitry Andric ShiftedVal |= maskTrailingOnes<uint64_t>(LeadingZeros);
183*5f757f3fSDimitry Andric
184*5f757f3fSDimitry Andric RISCVMatInt::InstSeq TmpSeq;
185*5f757f3fSDimitry Andric generateInstSeqImpl(ShiftedVal, STI, TmpSeq);
186*5f757f3fSDimitry Andric
187*5f757f3fSDimitry Andric // Keep the new sequence if it is an improvement or the original is empty.
188*5f757f3fSDimitry Andric if ((TmpSeq.size() + 1) < Res.size() ||
189*5f757f3fSDimitry Andric (Res.empty() && TmpSeq.size() < 8)) {
190*5f757f3fSDimitry Andric TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
191*5f757f3fSDimitry Andric Res = TmpSeq;
192*5f757f3fSDimitry Andric }
193*5f757f3fSDimitry Andric
194*5f757f3fSDimitry Andric // Some cases can benefit from filling the lower bits with zeros instead.
195*5f757f3fSDimitry Andric ShiftedVal &= maskTrailingZeros<uint64_t>(LeadingZeros);
196*5f757f3fSDimitry Andric TmpSeq.clear();
197*5f757f3fSDimitry Andric generateInstSeqImpl(ShiftedVal, STI, TmpSeq);
198*5f757f3fSDimitry Andric
199*5f757f3fSDimitry Andric // Keep the new sequence if it is an improvement or the original is empty.
200*5f757f3fSDimitry Andric if ((TmpSeq.size() + 1) < Res.size() ||
201*5f757f3fSDimitry Andric (Res.empty() && TmpSeq.size() < 8)) {
202*5f757f3fSDimitry Andric TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
203*5f757f3fSDimitry Andric Res = TmpSeq;
204*5f757f3fSDimitry Andric }
205*5f757f3fSDimitry Andric
206*5f757f3fSDimitry Andric // If we have exactly 32 leading zeros and Zba, we can try using zext.w at
207*5f757f3fSDimitry Andric // the end of the sequence.
208*5f757f3fSDimitry Andric if (LeadingZeros == 32 && STI.hasFeature(RISCV::FeatureStdExtZba)) {
209*5f757f3fSDimitry Andric // Try replacing upper bits with 1.
210*5f757f3fSDimitry Andric uint64_t LeadingOnesVal = Val | maskLeadingOnes<uint64_t>(LeadingZeros);
211*5f757f3fSDimitry Andric TmpSeq.clear();
212*5f757f3fSDimitry Andric generateInstSeqImpl(LeadingOnesVal, STI, TmpSeq);
213*5f757f3fSDimitry Andric
214*5f757f3fSDimitry Andric // Keep the new sequence if it is an improvement.
215*5f757f3fSDimitry Andric if ((TmpSeq.size() + 1) < Res.size() ||
216*5f757f3fSDimitry Andric (Res.empty() && TmpSeq.size() < 8)) {
217*5f757f3fSDimitry Andric TmpSeq.emplace_back(RISCV::ADD_UW, 0);
218*5f757f3fSDimitry Andric Res = TmpSeq;
219*5f757f3fSDimitry Andric }
220*5f757f3fSDimitry Andric }
221*5f757f3fSDimitry Andric }
222*5f757f3fSDimitry Andric
223bdd1243dSDimitry Andric namespace llvm::RISCVMatInt {
generateInstSeq(int64_t Val,const MCSubtargetInfo & STI)224*5f757f3fSDimitry Andric InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI) {
225fe6060f1SDimitry Andric RISCVMatInt::InstSeq Res;
226*5f757f3fSDimitry Andric generateInstSeqImpl(Val, STI, Res);
227fe6060f1SDimitry Andric
228bdd1243dSDimitry Andric // If the low 12 bits are non-zero, the first expansion may end with an ADDI
229bdd1243dSDimitry Andric // or ADDIW. If there are trailing zeros, try generating a sign extended
230bdd1243dSDimitry Andric // constant with no trailing zeros and use a final SLLI to restore them.
231bdd1243dSDimitry Andric if ((Val & 0xfff) != 0 && (Val & 1) == 0 && Res.size() >= 2) {
23206c3fb27SDimitry Andric unsigned TrailingZeros = llvm::countr_zero((uint64_t)Val);
23381ad6265SDimitry Andric int64_t ShiftedVal = Val >> TrailingZeros;
234bdd1243dSDimitry Andric // If we can use C.LI+C.SLLI instead of LUI+ADDI(W) prefer that since
235bdd1243dSDimitry Andric // its more compressible. But only if LUI+ADDI(W) isn't fusable.
236bdd1243dSDimitry Andric // NOTE: We don't check for C extension to minimize differences in generated
237bdd1243dSDimitry Andric // code.
238bdd1243dSDimitry Andric bool IsShiftedCompressible =
239*5f757f3fSDimitry Andric isInt<6>(ShiftedVal) && !STI.hasFeature(RISCV::TuneLUIADDIFusion);
24081ad6265SDimitry Andric RISCVMatInt::InstSeq TmpSeq;
241*5f757f3fSDimitry Andric generateInstSeqImpl(ShiftedVal, STI, TmpSeq);
24281ad6265SDimitry Andric
24381ad6265SDimitry Andric // Keep the new sequence if it is an improvement.
24406c3fb27SDimitry Andric if ((TmpSeq.size() + 1) < Res.size() || IsShiftedCompressible) {
24506c3fb27SDimitry Andric TmpSeq.emplace_back(RISCV::SLLI, TrailingZeros);
24681ad6265SDimitry Andric Res = TmpSeq;
24781ad6265SDimitry Andric }
24806c3fb27SDimitry Andric }
24906c3fb27SDimitry Andric
25006c3fb27SDimitry Andric // If we have a 1 or 2 instruction sequence this is the best we can do. This
25106c3fb27SDimitry Andric // will always be true for RV32 and will often be true for RV64.
25206c3fb27SDimitry Andric if (Res.size() <= 2)
25306c3fb27SDimitry Andric return Res;
25406c3fb27SDimitry Andric
255*5f757f3fSDimitry Andric assert(STI.hasFeature(RISCV::Feature64Bit) &&
25606c3fb27SDimitry Andric "Expected RV32 to only need 2 instructions");
25781ad6265SDimitry Andric
258*5f757f3fSDimitry Andric // If the lower 13 bits are something like 0x17ff, try to add 1 to change the
259*5f757f3fSDimitry Andric // lower 13 bits to 0x1800. We can restore this with an ADDI of -1 at the end
260*5f757f3fSDimitry Andric // of the sequence. Call generateInstSeqImpl on the new constant which may
261*5f757f3fSDimitry Andric // subtract 0xfffffffffffff800 to create another ADDI. This will leave a
262*5f757f3fSDimitry Andric // constant with more than 12 trailing zeros for the next recursive step.
263*5f757f3fSDimitry Andric if ((Val & 0xfff) != 0 && (Val & 0x1800) == 0x1000) {
264*5f757f3fSDimitry Andric int64_t Imm12 = -(0x800 - (Val & 0xfff));
265*5f757f3fSDimitry Andric int64_t AdjustedVal = Val - Imm12;
266*5f757f3fSDimitry Andric RISCVMatInt::InstSeq TmpSeq;
267*5f757f3fSDimitry Andric generateInstSeqImpl(AdjustedVal, STI, TmpSeq);
268*5f757f3fSDimitry Andric
269*5f757f3fSDimitry Andric // Keep the new sequence if it is an improvement.
270*5f757f3fSDimitry Andric if ((TmpSeq.size() + 1) < Res.size()) {
271*5f757f3fSDimitry Andric TmpSeq.emplace_back(RISCV::ADDI, Imm12);
272*5f757f3fSDimitry Andric Res = TmpSeq;
273*5f757f3fSDimitry Andric }
274*5f757f3fSDimitry Andric }
275*5f757f3fSDimitry Andric
276fe6060f1SDimitry Andric // If the constant is positive we might be able to generate a shifted constant
277fe6060f1SDimitry Andric // with no leading zeros and use a final SRLI to restore them.
278*5f757f3fSDimitry Andric if (Val > 0 && Res.size() > 2) {
279*5f757f3fSDimitry Andric generateInstSeqLeadingZeros(Val, STI, Res);
280*5f757f3fSDimitry Andric }
281fe6060f1SDimitry Andric
282*5f757f3fSDimitry Andric // If the constant is negative, trying inverting and using our trailing zero
283*5f757f3fSDimitry Andric // optimizations. Use an xori to invert the final value.
284*5f757f3fSDimitry Andric if (Val < 0 && Res.size() > 3) {
285*5f757f3fSDimitry Andric uint64_t InvertedVal = ~(uint64_t)Val;
286fe6060f1SDimitry Andric RISCVMatInt::InstSeq TmpSeq;
287*5f757f3fSDimitry Andric generateInstSeqLeadingZeros(InvertedVal, STI, TmpSeq);
288fe6060f1SDimitry Andric
289*5f757f3fSDimitry Andric // Keep it if we found a sequence that is smaller after inverting.
290*5f757f3fSDimitry Andric if (!TmpSeq.empty() && (TmpSeq.size() + 1) < Res.size()) {
291*5f757f3fSDimitry Andric TmpSeq.emplace_back(RISCV::XORI, -1);
292fe6060f1SDimitry Andric Res = TmpSeq;
29306c3fb27SDimitry Andric }
29406c3fb27SDimitry Andric }
29506c3fb27SDimitry Andric
29606c3fb27SDimitry Andric // If the Low and High halves are the same, use pack. The pack instruction
29706c3fb27SDimitry Andric // packs the XLEN/2-bit lower halves of rs1 and rs2 into rd, with rs1 in the
29806c3fb27SDimitry Andric // lower half and rs2 in the upper half.
299*5f757f3fSDimitry Andric if (Res.size() > 2 && STI.hasFeature(RISCV::FeatureStdExtZbkb)) {
30006c3fb27SDimitry Andric int64_t LoVal = SignExtend64<32>(Val);
30106c3fb27SDimitry Andric int64_t HiVal = SignExtend64<32>(Val >> 32);
30206c3fb27SDimitry Andric if (LoVal == HiVal) {
30306c3fb27SDimitry Andric RISCVMatInt::InstSeq TmpSeq;
304*5f757f3fSDimitry Andric generateInstSeqImpl(LoVal, STI, TmpSeq);
30506c3fb27SDimitry Andric if ((TmpSeq.size() + 1) < Res.size()) {
30606c3fb27SDimitry Andric TmpSeq.emplace_back(RISCV::PACK, 0);
30706c3fb27SDimitry Andric Res = TmpSeq;
30806c3fb27SDimitry Andric }
30906c3fb27SDimitry Andric }
31006c3fb27SDimitry Andric }
311fe6060f1SDimitry Andric
312349cc55cSDimitry Andric // Perform optimization with BCLRI/BSETI in the Zbs extension.
313*5f757f3fSDimitry Andric if (Res.size() > 2 && STI.hasFeature(RISCV::FeatureStdExtZbs)) {
314349cc55cSDimitry Andric // 1. For values in range 0xffffffff 7fffffff ~ 0xffffffff 00000000,
315349cc55cSDimitry Andric // call generateInstSeqImpl with Val|0x80000000 (which is expected be
316349cc55cSDimitry Andric // an int32), then emit (BCLRI r, 31).
317349cc55cSDimitry Andric // 2. For values in range 0x80000000 ~ 0xffffffff, call generateInstSeqImpl
318349cc55cSDimitry Andric // with Val&~0x80000000 (which is expected to be an int32), then
319349cc55cSDimitry Andric // emit (BSETI r, 31).
320349cc55cSDimitry Andric int64_t NewVal;
321349cc55cSDimitry Andric unsigned Opc;
322349cc55cSDimitry Andric if (Val < 0) {
323349cc55cSDimitry Andric Opc = RISCV::BCLRI;
324349cc55cSDimitry Andric NewVal = Val | 0x80000000ll;
325349cc55cSDimitry Andric } else {
326349cc55cSDimitry Andric Opc = RISCV::BSETI;
327349cc55cSDimitry Andric NewVal = Val & ~0x80000000ll;
328349cc55cSDimitry Andric }
329349cc55cSDimitry Andric if (isInt<32>(NewVal)) {
330349cc55cSDimitry Andric RISCVMatInt::InstSeq TmpSeq;
331*5f757f3fSDimitry Andric generateInstSeqImpl(NewVal, STI, TmpSeq);
33206c3fb27SDimitry Andric if ((TmpSeq.size() + 1) < Res.size()) {
333bdd1243dSDimitry Andric TmpSeq.emplace_back(Opc, 31);
334349cc55cSDimitry Andric Res = TmpSeq;
335349cc55cSDimitry Andric }
33606c3fb27SDimitry Andric }
337349cc55cSDimitry Andric
338349cc55cSDimitry Andric // Try to use BCLRI for upper 32 bits if the original lower 32 bits are
339349cc55cSDimitry Andric // negative int32, or use BSETI for upper 32 bits if the original lower
340349cc55cSDimitry Andric // 32 bits are positive int32.
341bdd1243dSDimitry Andric int32_t Lo = Lo_32(Val);
342bdd1243dSDimitry Andric uint32_t Hi = Hi_32(Val);
343349cc55cSDimitry Andric Opc = 0;
344349cc55cSDimitry Andric RISCVMatInt::InstSeq TmpSeq;
345*5f757f3fSDimitry Andric generateInstSeqImpl(Lo, STI, TmpSeq);
346349cc55cSDimitry Andric // Check if it is profitable to use BCLRI/BSETI.
347bdd1243dSDimitry Andric if (Lo > 0 && TmpSeq.size() + llvm::popcount(Hi) < Res.size()) {
348349cc55cSDimitry Andric Opc = RISCV::BSETI;
349bdd1243dSDimitry Andric } else if (Lo < 0 && TmpSeq.size() + llvm::popcount(~Hi) < Res.size()) {
350349cc55cSDimitry Andric Opc = RISCV::BCLRI;
351349cc55cSDimitry Andric Hi = ~Hi;
352349cc55cSDimitry Andric }
353349cc55cSDimitry Andric // Search for each bit and build corresponding BCLRI/BSETI.
354349cc55cSDimitry Andric if (Opc > 0) {
355349cc55cSDimitry Andric while (Hi != 0) {
356bdd1243dSDimitry Andric unsigned Bit = llvm::countr_zero(Hi);
357bdd1243dSDimitry Andric TmpSeq.emplace_back(Opc, Bit + 32);
358bdd1243dSDimitry Andric Hi &= (Hi - 1); // Clear lowest set bit.
359349cc55cSDimitry Andric }
360349cc55cSDimitry Andric if (TmpSeq.size() < Res.size())
361349cc55cSDimitry Andric Res = TmpSeq;
362349cc55cSDimitry Andric }
363349cc55cSDimitry Andric }
364349cc55cSDimitry Andric
365349cc55cSDimitry Andric // Perform optimization with SH*ADD in the Zba extension.
366*5f757f3fSDimitry Andric if (Res.size() > 2 && STI.hasFeature(RISCV::FeatureStdExtZba)) {
367349cc55cSDimitry Andric int64_t Div = 0;
368349cc55cSDimitry Andric unsigned Opc = 0;
369349cc55cSDimitry Andric RISCVMatInt::InstSeq TmpSeq;
370349cc55cSDimitry Andric // Select the opcode and divisor.
371349cc55cSDimitry Andric if ((Val % 3) == 0 && isInt<32>(Val / 3)) {
372349cc55cSDimitry Andric Div = 3;
373349cc55cSDimitry Andric Opc = RISCV::SH1ADD;
374349cc55cSDimitry Andric } else if ((Val % 5) == 0 && isInt<32>(Val / 5)) {
375349cc55cSDimitry Andric Div = 5;
376349cc55cSDimitry Andric Opc = RISCV::SH2ADD;
377349cc55cSDimitry Andric } else if ((Val % 9) == 0 && isInt<32>(Val / 9)) {
378349cc55cSDimitry Andric Div = 9;
379349cc55cSDimitry Andric Opc = RISCV::SH3ADD;
380349cc55cSDimitry Andric }
381349cc55cSDimitry Andric // Build the new instruction sequence.
382349cc55cSDimitry Andric if (Div > 0) {
383*5f757f3fSDimitry Andric generateInstSeqImpl(Val / Div, STI, TmpSeq);
38406c3fb27SDimitry Andric if ((TmpSeq.size() + 1) < Res.size()) {
385bdd1243dSDimitry Andric TmpSeq.emplace_back(Opc, 0);
386349cc55cSDimitry Andric Res = TmpSeq;
38706c3fb27SDimitry Andric }
3883a9a9c0cSDimitry Andric } else {
389349cc55cSDimitry Andric // Try to use LUI+SH*ADD+ADDI.
390349cc55cSDimitry Andric int64_t Hi52 = ((uint64_t)Val + 0x800ull) & ~0xfffull;
391349cc55cSDimitry Andric int64_t Lo12 = SignExtend64<12>(Val);
392349cc55cSDimitry Andric Div = 0;
393349cc55cSDimitry Andric if (isInt<32>(Hi52 / 3) && (Hi52 % 3) == 0) {
394349cc55cSDimitry Andric Div = 3;
395349cc55cSDimitry Andric Opc = RISCV::SH1ADD;
396349cc55cSDimitry Andric } else if (isInt<32>(Hi52 / 5) && (Hi52 % 5) == 0) {
397349cc55cSDimitry Andric Div = 5;
398349cc55cSDimitry Andric Opc = RISCV::SH2ADD;
399349cc55cSDimitry Andric } else if (isInt<32>(Hi52 / 9) && (Hi52 % 9) == 0) {
400349cc55cSDimitry Andric Div = 9;
401349cc55cSDimitry Andric Opc = RISCV::SH3ADD;
402349cc55cSDimitry Andric }
403349cc55cSDimitry Andric // Build the new instruction sequence.
404349cc55cSDimitry Andric if (Div > 0) {
405349cc55cSDimitry Andric // For Val that has zero Lo12 (implies Val equals to Hi52) should has
406349cc55cSDimitry Andric // already been processed to LUI+SH*ADD by previous optimization.
407349cc55cSDimitry Andric assert(Lo12 != 0 &&
408349cc55cSDimitry Andric "unexpected instruction sequence for immediate materialisation");
4093a9a9c0cSDimitry Andric assert(TmpSeq.empty() && "Expected empty TmpSeq");
410*5f757f3fSDimitry Andric generateInstSeqImpl(Hi52 / Div, STI, TmpSeq);
41106c3fb27SDimitry Andric if ((TmpSeq.size() + 2) < Res.size()) {
412bdd1243dSDimitry Andric TmpSeq.emplace_back(Opc, 0);
413bdd1243dSDimitry Andric TmpSeq.emplace_back(RISCV::ADDI, Lo12);
414349cc55cSDimitry Andric Res = TmpSeq;
415349cc55cSDimitry Andric }
416349cc55cSDimitry Andric }
4173a9a9c0cSDimitry Andric }
41806c3fb27SDimitry Andric }
419349cc55cSDimitry Andric
42006c3fb27SDimitry Andric // Perform optimization with rori in the Zbb and th.srri in the XTheadBb
42106c3fb27SDimitry Andric // extension.
422*5f757f3fSDimitry Andric if (Res.size() > 2 && (STI.hasFeature(RISCV::FeatureStdExtZbb) ||
423*5f757f3fSDimitry Andric STI.hasFeature(RISCV::FeatureVendorXTHeadBb))) {
42404eeddc0SDimitry Andric if (unsigned Rotate = extractRotateInfo(Val)) {
42504eeddc0SDimitry Andric RISCVMatInt::InstSeq TmpSeq;
42606c3fb27SDimitry Andric uint64_t NegImm12 = llvm::rotl<uint64_t>(Val, Rotate);
42704eeddc0SDimitry Andric assert(isInt<12>(NegImm12));
428bdd1243dSDimitry Andric TmpSeq.emplace_back(RISCV::ADDI, NegImm12);
429*5f757f3fSDimitry Andric TmpSeq.emplace_back(STI.hasFeature(RISCV::FeatureStdExtZbb)
43006c3fb27SDimitry Andric ? RISCV::RORI
43106c3fb27SDimitry Andric : RISCV::TH_SRRI,
43206c3fb27SDimitry Andric Rotate);
43304eeddc0SDimitry Andric Res = TmpSeq;
43404eeddc0SDimitry Andric }
43504eeddc0SDimitry Andric }
436fe6060f1SDimitry Andric return Res;
437fe6060f1SDimitry Andric }
438fe6060f1SDimitry Andric
generateTwoRegInstSeq(int64_t Val,const MCSubtargetInfo & STI,unsigned & ShiftAmt,unsigned & AddOpc)439*5f757f3fSDimitry Andric InstSeq generateTwoRegInstSeq(int64_t Val, const MCSubtargetInfo &STI,
440*5f757f3fSDimitry Andric unsigned &ShiftAmt, unsigned &AddOpc) {
441*5f757f3fSDimitry Andric int64_t LoVal = SignExtend64<32>(Val);
442*5f757f3fSDimitry Andric if (LoVal == 0)
443*5f757f3fSDimitry Andric return RISCVMatInt::InstSeq();
444*5f757f3fSDimitry Andric
445*5f757f3fSDimitry Andric // Subtract the LoVal to emulate the effect of the final ADD.
446*5f757f3fSDimitry Andric uint64_t Tmp = (uint64_t)Val - (uint64_t)LoVal;
447*5f757f3fSDimitry Andric assert(Tmp != 0);
448*5f757f3fSDimitry Andric
449*5f757f3fSDimitry Andric // Use trailing zero counts to figure how far we need to shift LoVal to line
450*5f757f3fSDimitry Andric // up with the remaining constant.
451*5f757f3fSDimitry Andric // TODO: This algorithm assumes all non-zero bits in the low 32 bits of the
452*5f757f3fSDimitry Andric // final constant come from LoVal.
453*5f757f3fSDimitry Andric unsigned TzLo = llvm::countr_zero((uint64_t)LoVal);
454*5f757f3fSDimitry Andric unsigned TzHi = llvm::countr_zero(Tmp);
455*5f757f3fSDimitry Andric assert(TzLo < 32 && TzHi >= 32);
456*5f757f3fSDimitry Andric ShiftAmt = TzHi - TzLo;
457*5f757f3fSDimitry Andric AddOpc = RISCV::ADD;
458*5f757f3fSDimitry Andric
459*5f757f3fSDimitry Andric if (Tmp == ((uint64_t)LoVal << ShiftAmt))
460*5f757f3fSDimitry Andric return RISCVMatInt::generateInstSeq(LoVal, STI);
461*5f757f3fSDimitry Andric
462*5f757f3fSDimitry Andric // If we have Zba, we can use (ADD_UW X, (SLLI X, 32)).
463*5f757f3fSDimitry Andric if (STI.hasFeature(RISCV::FeatureStdExtZba) && Lo_32(Val) == Hi_32(Val)) {
464*5f757f3fSDimitry Andric ShiftAmt = 32;
465*5f757f3fSDimitry Andric AddOpc = RISCV::ADD_UW;
466*5f757f3fSDimitry Andric return RISCVMatInt::generateInstSeq(LoVal, STI);
467*5f757f3fSDimitry Andric }
468*5f757f3fSDimitry Andric
469*5f757f3fSDimitry Andric return RISCVMatInt::InstSeq();
470*5f757f3fSDimitry Andric }
471*5f757f3fSDimitry Andric
getIntMatCost(const APInt & Val,unsigned Size,const MCSubtargetInfo & STI,bool CompressionCost)472*5f757f3fSDimitry Andric int getIntMatCost(const APInt &Val, unsigned Size, const MCSubtargetInfo &STI,
473*5f757f3fSDimitry Andric bool CompressionCost) {
474*5f757f3fSDimitry Andric bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
475*5f757f3fSDimitry Andric bool HasRVC = CompressionCost && (STI.hasFeature(RISCV::FeatureStdExtC) ||
476*5f757f3fSDimitry Andric STI.hasFeature(RISCV::FeatureStdExtZca));
477e8d8bef9SDimitry Andric int PlatRegSize = IsRV64 ? 64 : 32;
478e8d8bef9SDimitry Andric
479e8d8bef9SDimitry Andric // Split the constant into platform register sized chunks, and calculate cost
480e8d8bef9SDimitry Andric // of each chunk.
481e8d8bef9SDimitry Andric int Cost = 0;
482e8d8bef9SDimitry Andric for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) {
483e8d8bef9SDimitry Andric APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize);
484*5f757f3fSDimitry Andric InstSeq MatSeq = generateInstSeq(Chunk.getSExtValue(), STI);
485fe6060f1SDimitry Andric Cost += getInstSeqCost(MatSeq, HasRVC);
486e8d8bef9SDimitry Andric }
487e8d8bef9SDimitry Andric return std::max(1, Cost);
488e8d8bef9SDimitry Andric }
48981ad6265SDimitry Andric
getOpndKind() const49081ad6265SDimitry Andric OpndKind Inst::getOpndKind() const {
49181ad6265SDimitry Andric switch (Opc) {
49281ad6265SDimitry Andric default:
49381ad6265SDimitry Andric llvm_unreachable("Unexpected opcode!");
49481ad6265SDimitry Andric case RISCV::LUI:
49581ad6265SDimitry Andric return RISCVMatInt::Imm;
49681ad6265SDimitry Andric case RISCV::ADD_UW:
49781ad6265SDimitry Andric return RISCVMatInt::RegX0;
49881ad6265SDimitry Andric case RISCV::SH1ADD:
49981ad6265SDimitry Andric case RISCV::SH2ADD:
50081ad6265SDimitry Andric case RISCV::SH3ADD:
50106c3fb27SDimitry Andric case RISCV::PACK:
50281ad6265SDimitry Andric return RISCVMatInt::RegReg;
50381ad6265SDimitry Andric case RISCV::ADDI:
50481ad6265SDimitry Andric case RISCV::ADDIW:
505*5f757f3fSDimitry Andric case RISCV::XORI:
50681ad6265SDimitry Andric case RISCV::SLLI:
50781ad6265SDimitry Andric case RISCV::SRLI:
50881ad6265SDimitry Andric case RISCV::SLLI_UW:
50981ad6265SDimitry Andric case RISCV::RORI:
51081ad6265SDimitry Andric case RISCV::BSETI:
51181ad6265SDimitry Andric case RISCV::BCLRI:
51206c3fb27SDimitry Andric case RISCV::TH_SRRI:
51381ad6265SDimitry Andric return RISCVMatInt::RegImm;
51481ad6265SDimitry Andric }
51581ad6265SDimitry Andric }
51681ad6265SDimitry Andric
517bdd1243dSDimitry Andric } // namespace llvm::RISCVMatInt
518