1 //===- RISCVMatInt.h - Immediate materialisation ---------------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_MATINT_H
10 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_MATINT_H
11 
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/MC/MCSubtargetInfo.h"
14 #include <cstdint>
15 
16 namespace llvm {
17 class APInt;
18 
19 namespace RISCVMatInt {
20 
21 enum OpndKind {
22   RegImm, // ADDI/ADDIW/SLLI/SRLI/BSETI/BCLRI
23   Imm,    // LUI
24   RegReg, // SH1ADD/SH2ADD/SH3ADD
25   RegX0,  // ADD_UW
26 };
27 
28 class Inst {
29   unsigned Opc;
30   int32_t Imm; // The largest value we need to store is 20 bits.
31 
32 public:
Inst(unsigned Opc,int64_t I)33   Inst(unsigned Opc, int64_t I) : Opc(Opc), Imm(I) {
34     assert(I == Imm && "truncated");
35   }
36 
getOpcode()37   unsigned getOpcode() const { return Opc; }
getImm()38   int64_t getImm() const { return Imm; }
39 
40   OpndKind getOpndKind() const;
41 };
42 using InstSeq = SmallVector<Inst, 8>;
43 
44 // Helper to generate an instruction sequence that will materialise the given
45 // immediate value into a register. A sequence of instructions represented by a
46 // simple struct is produced rather than directly emitting the instructions in
47 // order to allow this helper to be used from both the MC layer and during
48 // instruction selection.
49 InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI);
50 
51 // Helper to generate an instruction sequence that can materialize the given
52 // immediate value into a register using an additional temporary register. This
53 // handles cases where the constant can be generated by (ADD (SLLI X, C), X) or
54 // (ADD_UW (SLLI X, C) X). The sequence to generate X is returned. ShiftAmt is
55 // provides the SLLI and AddOpc indicates ADD or ADD_UW.
56 InstSeq generateTwoRegInstSeq(int64_t Val, const MCSubtargetInfo &STI,
57                               unsigned &ShiftAmt, unsigned &AddOpc);
58 
59 // Helper to estimate the number of instructions required to materialise the
60 // given immediate value into a register. This estimate does not account for
61 // `Val` possibly fitting into an immediate, and so may over-estimate.
62 //
63 // This will attempt to produce instructions to materialise `Val` as an
64 // `Size`-bit immediate.
65 //
66 // If CompressionCost is true it will use a different cost calculation if RVC is
67 // enabled. This should be used to compare two different sequences to determine
68 // which is more compressible.
69 int getIntMatCost(const APInt &Val, unsigned Size, const MCSubtargetInfo &STI,
70                   bool CompressionCost = false);
71 } // namespace RISCVMatInt
72 } // namespace llvm
73 #endif
74