1 //===-- RISCVAsmPrinter.cpp - RISCV LLVM assembly writer ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to the RISCV assembly language.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MCTargetDesc/RISCVInstPrinter.h"
15 #include "MCTargetDesc/RISCVMCExpr.h"
16 #include "MCTargetDesc/RISCVTargetStreamer.h"
17 #include "RISCV.h"
18 #include "RISCVTargetMachine.h"
19 #include "TargetInfo/RISCVTargetInfo.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/CodeGen/AsmPrinter.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/MC/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "asm-printer"
35 
36 STATISTIC(RISCVNumInstrsCompressed,
37           "Number of RISC-V Compressed instructions emitted");
38 
39 namespace {
40 class RISCVAsmPrinter : public AsmPrinter {
41   const MCSubtargetInfo *MCSTI;
42   const RISCVSubtarget *STI;
43 
44 public:
45   explicit RISCVAsmPrinter(TargetMachine &TM,
46                            std::unique_ptr<MCStreamer> Streamer)
47       : AsmPrinter(TM, std::move(Streamer)), MCSTI(TM.getMCSubtargetInfo()) {}
48 
49   StringRef getPassName() const override { return "RISCV Assembly Printer"; }
50 
51   bool runOnMachineFunction(MachineFunction &MF) override;
52 
53   void emitInstruction(const MachineInstr *MI) override;
54 
55   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
56                        const char *ExtraCode, raw_ostream &OS) override;
57   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
58                              const char *ExtraCode, raw_ostream &OS) override;
59 
60   void EmitToStreamer(MCStreamer &S, const MCInst &Inst);
61   bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
62                                    const MachineInstr *MI);
63 
64   // Wrapper needed for tblgenned pseudo lowering.
65   bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
66     return lowerRISCVMachineOperandToMCOperand(MO, MCOp, *this);
67   }
68 
69   void emitStartOfAsmFile(Module &M) override;
70   void emitEndOfAsmFile(Module &M) override;
71 
72   void emitFunctionEntryLabel() override;
73 
74 private:
75   void emitAttributes();
76 };
77 }
78 
79 #define GEN_COMPRESS_INSTR
80 #include "RISCVGenCompressInstEmitter.inc"
81 void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
82   MCInst CInst;
83   bool Res = compressInst(CInst, Inst, *STI, OutStreamer->getContext());
84   if (Res)
85     ++RISCVNumInstrsCompressed;
86   AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst);
87 }
88 
89 // Simple pseudo-instructions have their lowering (with expansion to real
90 // instructions) auto-generated.
91 #include "RISCVGenMCPseudoLowering.inc"
92 
93 void RISCVAsmPrinter::emitInstruction(const MachineInstr *MI) {
94   // Do any auto-generated pseudo lowerings.
95   if (emitPseudoExpansionLowering(*OutStreamer, MI))
96     return;
97 
98   MCInst TmpInst;
99   if (!lowerRISCVMachineInstrToMCInst(MI, TmpInst, *this))
100     EmitToStreamer(*OutStreamer, TmpInst);
101 }
102 
103 bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
104                                       const char *ExtraCode, raw_ostream &OS) {
105   // First try the generic code, which knows about modifiers like 'c' and 'n'.
106   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS))
107     return false;
108 
109   const MachineOperand &MO = MI->getOperand(OpNo);
110   if (ExtraCode && ExtraCode[0]) {
111     if (ExtraCode[1] != 0)
112       return true; // Unknown modifier.
113 
114     switch (ExtraCode[0]) {
115     default:
116       return true; // Unknown modifier.
117     case 'z':      // Print zero register if zero, regular printing otherwise.
118       if (MO.isImm() && MO.getImm() == 0) {
119         OS << RISCVInstPrinter::getRegisterName(RISCV::X0);
120         return false;
121       }
122       break;
123     case 'i': // Literal 'i' if operand is not a register.
124       if (!MO.isReg())
125         OS << 'i';
126       return false;
127     }
128   }
129 
130   switch (MO.getType()) {
131   case MachineOperand::MO_Immediate:
132     OS << MO.getImm();
133     return false;
134   case MachineOperand::MO_Register:
135     OS << RISCVInstPrinter::getRegisterName(MO.getReg());
136     return false;
137   case MachineOperand::MO_GlobalAddress:
138     PrintSymbolOperand(MO, OS);
139     return false;
140   case MachineOperand::MO_BlockAddress: {
141     MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress());
142     Sym->print(OS, MAI);
143     return false;
144   }
145   default:
146     break;
147   }
148 
149   return true;
150 }
151 
152 bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
153                                             unsigned OpNo,
154                                             const char *ExtraCode,
155                                             raw_ostream &OS) {
156   if (!ExtraCode) {
157     const MachineOperand &MO = MI->getOperand(OpNo);
158     // For now, we only support register memory operands in registers and
159     // assume there is no addend
160     if (!MO.isReg())
161       return true;
162 
163     OS << "0(" << RISCVInstPrinter::getRegisterName(MO.getReg()) << ")";
164     return false;
165   }
166 
167   return AsmPrinter::PrintAsmMemoryOperand(MI, OpNo, ExtraCode, OS);
168 }
169 
170 bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
171   // Set the current MCSubtargetInfo to a copy which has the correct
172   // feature bits for the current MachineFunction
173   MCSubtargetInfo &NewSTI =
174     OutStreamer->getContext().getSubtargetCopy(*TM.getMCSubtargetInfo());
175   NewSTI.setFeatureBits(MF.getSubtarget().getFeatureBits());
176   MCSTI = &NewSTI;
177   STI = &MF.getSubtarget<RISCVSubtarget>();
178 
179   SetupMachineFunction(MF);
180   emitFunctionBody();
181   return false;
182 }
183 
184 void RISCVAsmPrinter::emitStartOfAsmFile(Module &M) {
185   if (TM.getTargetTriple().isOSBinFormatELF())
186     emitAttributes();
187 }
188 
189 void RISCVAsmPrinter::emitEndOfAsmFile(Module &M) {
190   RISCVTargetStreamer &RTS =
191       static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
192 
193   if (TM.getTargetTriple().isOSBinFormatELF())
194     RTS.finishAttributeSection();
195 }
196 
197 void RISCVAsmPrinter::emitAttributes() {
198   RISCVTargetStreamer &RTS =
199       static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
200   RTS.emitTargetAttributes(*MCSTI);
201 }
202 
203 void RISCVAsmPrinter::emitFunctionEntryLabel() {
204   AsmPrinter::emitFunctionEntryLabel();
205   RISCVTargetStreamer &RTS =
206       static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
207   RTS.setTargetABI(STI->getTargetABI());
208 }
209 
210 // Force static initialization.
211 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmPrinter() {
212   RegisterAsmPrinter<RISCVAsmPrinter> X(getTheRISCV32Target());
213   RegisterAsmPrinter<RISCVAsmPrinter> Y(getTheRISCV64Target());
214 }
215