1//===-- RISCVCallingConv.td - Calling Conventions RISC-V ---*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This describes the calling conventions for the RISC-V architecture.
10//
11//===----------------------------------------------------------------------===//
12
13// The RISC-V calling convention is handled with custom code in
14// RISCVISelLowering.cpp (CC_RISCV).
15
16def CSR_ILP32_LP64
17    : CalleeSavedRegs<(add X1, X3, X4, X8, X9, (sequence "X%u", 18, 27))>;
18
19def CSR_ILP32F_LP64F
20    : CalleeSavedRegs<(add CSR_ILP32_LP64,
21                       F8_F, F9_F, (sequence "F%u_F", 18, 27))>;
22
23def CSR_ILP32D_LP64D
24    : CalleeSavedRegs<(add CSR_ILP32_LP64,
25                       F8_D, F9_D, (sequence "F%u_D", 18, 27))>;
26
27// Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
28def CSR_NoRegs : CalleeSavedRegs<(add)>;
29
30// Interrupt handler needs to save/restore all registers that are used,
31// both Caller and Callee saved registers.
32def CSR_Interrupt : CalleeSavedRegs<(add X1, (sequence "X%u", 3, 31))>;
33
34// Same as CSR_Interrupt, but including all 32-bit FP registers.
35def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
36                                             (sequence "F%u_F", 0, 31))>;
37
38// Same as CSR_Interrupt, but including all 64-bit FP registers.
39def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
40                                             (sequence "F%u_D", 0, 31))>;
41