1//===-- RISCVFeatures.td - RISCV Features and Extensions ---*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// RISC-V subtarget features and instruction predicates.
11//===----------------------------------------------------------------------===//
12
13def FeatureStdExtM
14    : SubtargetFeature<"m", "HasStdExtM", "true",
15                       "'M' (Integer Multiplication and Division)">;
16def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
17                           AssemblerPredicate<(all_of FeatureStdExtM),
18                           "'M' (Integer Multiplication and Division)">;
19
20def FeatureStdExtZmmul
21    : SubtargetFeature<"zmmul", "HasStdExtZmmul", "true",
22                       "'Zmmul' (Integer Multiplication)">;
23
24def HasStdExtMOrZmmul
25    : Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
26                AssemblerPredicate<(any_of FeatureStdExtM, FeatureStdExtZmmul),
27                                   "'M' (Integer Multiplication and Division) or "
28                                   "'Zmmul' (Integer Multiplication)">;
29
30def FeatureStdExtA
31    : SubtargetFeature<"a", "HasStdExtA", "true",
32                       "'A' (Atomic Instructions)">;
33def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
34                           AssemblerPredicate<(all_of FeatureStdExtA),
35                           "'A' (Atomic Instructions)">;
36
37def FeatureStdExtF
38    : SubtargetFeature<"f", "HasStdExtF", "true",
39                       "'F' (Single-Precision Floating-Point)">;
40def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
41                           AssemblerPredicate<(all_of FeatureStdExtF),
42                           "'F' (Single-Precision Floating-Point)">;
43
44def FeatureStdExtD
45    : SubtargetFeature<"d", "HasStdExtD", "true",
46                       "'D' (Double-Precision Floating-Point)",
47                       [FeatureStdExtF]>;
48def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
49                           AssemblerPredicate<(all_of FeatureStdExtD),
50                           "'D' (Double-Precision Floating-Point)">;
51
52def FeatureStdExtH
53    : SubtargetFeature<"h", "HasStdExtH", "true",
54                       "'H' (Hypervisor)">;
55
56def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
57                           AssemblerPredicate<(all_of FeatureStdExtH),
58                           "'H' (Hypervisor)">;
59
60def FeatureStdExtZihintpause
61    : SubtargetFeature<"zihintpause", "HasStdExtZihintpause", "true",
62                       "'zihintpause' (Pause Hint)">;
63def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
64                                     AssemblerPredicate<(all_of FeatureStdExtZihintpause),
65                                     "'Zihintpause' (Pause Hint)">;
66
67def FeatureStdExtZihintntl
68    : SubtargetFeature<"experimental-zihintntl", "HasStdExtZihintntl", "true",
69                       "'zihintntl' (Non-Temporal Locality Hints)">;
70def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
71                                    AssemblerPredicate<(all_of FeatureStdExtZihintntl),
72                                    "'Zihintntl' (Non-Temporal Locality Hints)">;
73
74def FeatureStdExtZfhmin
75    : SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true",
76                       "'Zfhmin' (Half-Precision Floating-Point Minimal)",
77                       [FeatureStdExtF]>;
78def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
79                             AssemblerPredicate<(all_of FeatureStdExtZfhmin),
80                             "'Zfhmin' (Half-Precision Floating-Point Minimal)">;
81
82def FeatureStdExtZfh
83    : SubtargetFeature<"zfh", "HasStdExtZfh", "true",
84                       "'Zfh' (Half-Precision Floating-Point)",
85                       [FeatureStdExtF]>;
86def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
87                             AssemblerPredicate<(all_of FeatureStdExtZfh),
88                             "'Zfh' (Half-Precision Floating-Point)">;
89def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
90
91def HasStdExtZfhOrZfhmin
92    : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZfhmin()">,
93                AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin),
94                                   "'Zfh' (Half-Precision Floating-Point) or "
95                                   "'Zfhmin' (Half-Precision Floating-Point Minimal)">;
96
97def FeatureStdExtZfinx
98    : SubtargetFeature<"zfinx", "HasStdExtZfinx", "true",
99                       "'Zfinx' (Float in Integer)">;
100def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
101                               AssemblerPredicate<(all_of FeatureStdExtZfinx),
102                               "'Zfinx' (Float in Integer)">;
103
104def FeatureStdExtZdinx
105    : SubtargetFeature<"zdinx", "HasStdExtZdinx", "true",
106                       "'Zdinx' (Double in Integer)",
107                       [FeatureStdExtZfinx]>;
108def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
109                               AssemblerPredicate<(all_of FeatureStdExtZdinx),
110                               "'Zdinx' (Double in Integer)">;
111
112def FeatureStdExtZhinxmin
113    : SubtargetFeature<"zhinxmin", "HasStdExtZhinxmin", "true",
114                       "'Zhinxmin' (Half Float in Integer Minimal)",
115                       [FeatureStdExtZfinx]>;
116def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
117                                  AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
118                                  "'Zhinxmin' (Half Float in Integer Minimal)">;
119
120def FeatureStdExtZhinx
121    : SubtargetFeature<"zhinx", "HasStdExtZhinx", "true",
122                       "'Zhinx' (Half Float in Integer)",
123                       [FeatureStdExtZfinx]>;
124def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
125                               AssemblerPredicate<(all_of FeatureStdExtZhinx),
126                               "'Zhinx' (Half Float in Integer)">;
127
128def HasStdExtZhinxOrZhinxmin
129    : Predicate<"Subtarget->hasStdExtZhinx() || Subtarget->hasStdExtZhinxmin()">,
130                AssemblerPredicate<(any_of FeatureStdExtZhinx, FeatureStdExtZhinxmin),
131                                   "'Zhinx' (Half Float in Integer) or "
132                                   "'Zhinxmin' (Half Float in Integer Minimal)">;
133
134def FeatureStdExtC
135    : SubtargetFeature<"c", "HasStdExtC", "true",
136                       "'C' (Compressed Instructions)">;
137def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
138                           AssemblerPredicate<(all_of FeatureStdExtC),
139                           "'C' (Compressed Instructions)">;
140
141def FeatureStdExtZba
142    : SubtargetFeature<"zba", "HasStdExtZba", "true",
143                       "'Zba' (Address Generation Instructions)">;
144def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
145                             AssemblerPredicate<(all_of FeatureStdExtZba),
146                             "'Zba' (Address Generation Instructions)">;
147def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
148
149def FeatureStdExtZbb
150    : SubtargetFeature<"zbb", "HasStdExtZbb", "true",
151                       "'Zbb' (Basic Bit-Manipulation)">;
152def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
153                             AssemblerPredicate<(all_of FeatureStdExtZbb),
154                             "'Zbb' (Basic Bit-Manipulation)">;
155
156def FeatureStdExtZbc
157    : SubtargetFeature<"zbc", "HasStdExtZbc", "true",
158                       "'Zbc' (Carry-Less Multiplication)">;
159def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
160                             AssemblerPredicate<(all_of FeatureStdExtZbc),
161                             "'Zbc' (Carry-Less Multiplication)">;
162
163def FeatureStdExtZbs
164    : SubtargetFeature<"zbs", "HasStdExtZbs", "true",
165                       "'Zbs' (Single-Bit Instructions)">;
166def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
167                             AssemblerPredicate<(all_of FeatureStdExtZbs),
168                             "'Zbs' (Single-Bit Instructions)">;
169
170def FeatureStdExtZbkb
171    : SubtargetFeature<"zbkb", "HasStdExtZbkb", "true",
172                       "'Zbkb' (Bitmanip instructions for Cryptography)">;
173def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
174                             AssemblerPredicate<(all_of FeatureStdExtZbkb),
175                             "'Zbkb' (Bitmanip instructions for Cryptography)">;
176
177def FeatureStdExtZbkx
178    : SubtargetFeature<"zbkx", "HasStdExtZbkx", "true",
179                       "'Zbkx' (Crossbar permutation instructions)">;
180def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
181                             AssemblerPredicate<(all_of FeatureStdExtZbkx),
182                             "'Zbkx' (Crossbar permutation instructions)">;
183
184def HasStdExtZbbOrZbkb
185    : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()">,
186                AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb),
187                                   "'Zbb' (Basic Bit-Manipulation) or "
188                                   "'Zbkb' (Bitmanip instructions for Cryptography)">;
189
190// The Carry-less multiply subextension for cryptography is a subset of basic
191// carry-less multiply subextension. The former should be enabled if the latter
192// is enabled.
193def FeatureStdExtZbkc
194    : SubtargetFeature<"zbkc", "HasStdExtZbkc", "true",
195                       "'Zbkc' (Carry-less multiply instructions for "
196                       "Cryptography)">;
197def HasStdExtZbkc
198    : Predicate<"Subtarget->hasStdExtZbkc()">,
199                AssemblerPredicate<(all_of FeatureStdExtZbkc),
200                "'Zbkc' (Carry-less multiply instructions for Cryptography)">;
201
202def HasStdExtZbcOrZbkc
203    : Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">,
204                AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc),
205                                   "'Zbc' (Carry-Less Multiplication) or "
206                                   "'Zbkc' (Carry-less multiply instructions "
207                                   "for Cryptography)">;
208
209def FeatureStdExtZknd
210    : SubtargetFeature<"zknd", "HasStdExtZknd", "true",
211                       "'Zknd' (NIST Suite: AES Decryption)">;
212def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
213                              AssemblerPredicate<(all_of FeatureStdExtZknd),
214                              "'Zknd' (NIST Suite: AES Decryption)">;
215
216def FeatureStdExtZkne
217    : SubtargetFeature<"zkne", "HasStdExtZkne", "true",
218                       "'Zkne' (NIST Suite: AES Encryption)">;
219def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
220                              AssemblerPredicate<(all_of FeatureStdExtZkne),
221                              "'Zkne' (NIST Suite: AES Encryption)">;
222
223// Some instructions belong to both Zknd and Zkne subextensions.
224// They should be enabled if either has been specified.
225def HasStdExtZkndOrZkne
226    : Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">,
227                AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne),
228                                   "'Zknd' (NIST Suite: AES Decryption) or "
229                                   "'Zkne' (NIST Suite: AES Encryption)">;
230
231def FeatureStdExtZknh
232    : SubtargetFeature<"zknh", "HasStdExtZknh", "true",
233                       "'Zknh' (NIST Suite: Hash Function Instructions)">;
234def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
235                             AssemblerPredicate<(all_of FeatureStdExtZknh),
236                             "'Zknh' (NIST Suite: Hash Function Instructions)">;
237
238def FeatureStdExtZksed
239    : SubtargetFeature<"zksed", "HasStdExtZksed", "true",
240                       "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
241def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
242                             AssemblerPredicate<(all_of FeatureStdExtZksed),
243                             "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
244
245def FeatureStdExtZksh
246    : SubtargetFeature<"zksh", "HasStdExtZksh", "true",
247                       "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
248def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
249                              AssemblerPredicate<(all_of FeatureStdExtZksh),
250                              "'Zksh' (ShangMi Suite: SM3 Hash Function "
251                              "Instructions)">;
252
253def FeatureStdExtZkr
254    : SubtargetFeature<"zkr", "HasStdExtZkr", "true",
255                       "'Zkr' (Entropy Source Extension)">;
256def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
257                             AssemblerPredicate<(all_of FeatureStdExtZkr),
258                             "'Zkr' (Entropy Source Extension)">;
259
260def FeatureStdExtZkn
261    : SubtargetFeature<"zkn", "HasStdExtZkn", "true",
262                       "'Zkn' (NIST Algorithm Suite)",
263                       [FeatureStdExtZbkb,
264                        FeatureStdExtZbkc,
265                        FeatureStdExtZbkx,
266                        FeatureStdExtZkne,
267                        FeatureStdExtZknd,
268                        FeatureStdExtZknh]>;
269
270def FeatureStdExtZks
271    : SubtargetFeature<"zks", "HasStdExtZks", "true",
272                       "'Zks' (ShangMi Algorithm Suite)",
273                       [FeatureStdExtZbkb,
274                        FeatureStdExtZbkc,
275                        FeatureStdExtZbkx,
276                        FeatureStdExtZksed,
277                        FeatureStdExtZksh]>;
278
279def FeatureStdExtZkt
280    : SubtargetFeature<"zkt", "HasStdExtZkt", "true",
281                       "'Zkt' (Data Independent Execution Latency)">;
282
283def FeatureStdExtZk
284    : SubtargetFeature<"zk", "HasStdExtZk", "true",
285                       "'Zk' (Standard scalar cryptography extension)",
286                       [FeatureStdExtZkn,
287                        FeatureStdExtZkr,
288                        FeatureStdExtZkt]>;
289
290def FeatureExtZca
291    : SubtargetFeature<"experimental-zca", "HasStdExtZca", "true",
292                       "'Zca' (part of the C extension, excluding compressed "
293                       "floating point loads/stores)">;
294
295def HasStdExtCOrZca
296    : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZca()">,
297                AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZca),
298                                   "'C' (Compressed Instructions) or "
299                                   "'Zca' (part of the C extension, excluding "
300                                   "compressed floating point loads/stores)">;
301
302def FeatureExtZcd
303    : SubtargetFeature<"experimental-zcd", "HasStdExtZcd", "true",
304                       "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
305
306def HasStdExtCOrZcd
307    : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">,
308                AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZcd),
309                                   "'C' (Compressed Instructions) or "
310                                   "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
311
312def FeatureExtZcf
313    : SubtargetFeature<"experimental-zcf", "HasStdExtZcf", "true",
314                       "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
315
316def HasStdExtCOrZcf
317    : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf()">,
318                AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZcf),
319                                   "'C' (Compressed Instructions) or "
320                                   "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
321
322def FeatureNoRVCHints
323    : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
324                       "Disable RVC Hint Instructions.">;
325def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
326                  AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
327                                      "RVC Hint Instructions">;
328
329def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "32",
330                                           "'Zvl' (Minimum Vector Length) 32">;
331
332foreach i = { 6-16 } in {
333  defvar I = !shl(1, i);
334  def FeatureStdExtZvl#I#b :
335      SubtargetFeature<"zvl"#I#"b", "ZvlLen", !cast<string>(I),
336                       "'Zvl' (Minimum Vector Length) "#I,
337                       [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
338}
339
340def FeatureStdExtZve32x
341    : SubtargetFeature<"zve32x", "HasStdExtZve32x", "true",
342                       "'Zve32x' (Vector Extensions for Embedded Processors "
343                       "with maximal 32 EEW)",
344                       [FeatureStdExtZvl32b]>;
345
346def FeatureStdExtZve32f
347    : SubtargetFeature<"zve32f", "HasStdExtZve32f", "true",
348                       "'Zve32f' (Vector Extensions for Embedded Processors "
349                       "with maximal 32 EEW and F extension)",
350                       [FeatureStdExtZve32x]>;
351
352def FeatureStdExtZve64x
353    : SubtargetFeature<"zve64x", "HasStdExtZve64x", "true",
354                       "'Zve64x' (Vector Extensions for Embedded Processors "
355                       "with maximal 64 EEW)",
356                       [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
357
358def FeatureStdExtZve64f
359    : SubtargetFeature<"zve64f", "HasStdExtZve64f", "true",
360                       "'Zve64f' (Vector Extensions for Embedded Processors "
361                       "with maximal 64 EEW and F extension)",
362                       [FeatureStdExtZve32f, FeatureStdExtZve64x]>;
363
364def FeatureStdExtZve64d
365    : SubtargetFeature<"zve64d", "HasStdExtZve64d", "true",
366                       "'Zve64d' (Vector Extensions for Embedded Processors "
367                       "with maximal 64 EEW, F and D extension)",
368                       [FeatureStdExtZve64f]>;
369
370def FeatureStdExtV
371    : SubtargetFeature<"v", "HasStdExtV", "true",
372                       "'V' (Vector Extension for Application Processors)",
373                       [FeatureStdExtZvl128b, FeatureStdExtZve64d,
374                        FeatureStdExtF, FeatureStdExtD]>;
375
376def HasVInstructions    : Predicate<"Subtarget->hasVInstructions()">,
377      AssemblerPredicate<
378          (any_of FeatureStdExtZve32x),
379          "'V' (Vector Extension for Application Processors), 'Zve32x' or "
380          "'Zve64x' (Vector Extensions for Embedded Processors)">;
381def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">,
382      AssemblerPredicate<
383          (any_of FeatureStdExtZve64x),
384          "'V' (Vector Extension for Application Processors) or 'Zve64x' "
385          "(Vector Extensions for Embedded Processors)">;
386def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">,
387      AssemblerPredicate<
388          (any_of FeatureStdExtZve32f),
389          "'V' (Vector Extension for Application Processors), 'Zve32f', "
390          "'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors)">;
391
392def FeatureStdExtZvfh
393    : SubtargetFeature<"experimental-zvfh", "HasStdExtZvfh", "true",
394                       "'Zvfh' (Vector Half-Precision Floating-Point)",
395                       [FeatureStdExtZve32f]>;
396
397def FeatureStdExtZicbom
398    : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
399                       "'Zicbom' (Cache-Block Management Instructions)">;
400def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
401                                AssemblerPredicate<(all_of FeatureStdExtZicbom),
402                                "'Zicbom' (Cache-Block Management Instructions)">;
403
404def FeatureStdExtZicboz
405    : SubtargetFeature<"zicboz", "HasStdExtZicboz", "true",
406                       "'Zicboz' (Cache-Block Zero Instructions)">;
407def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
408                                AssemblerPredicate<(all_of FeatureStdExtZicboz),
409                                "'Zicboz' (Cache-Block Zero Instructions)">;
410
411def FeatureStdExtZicbop
412    : SubtargetFeature<"zicbop", "HasStdExtZicbop", "true",
413                       "'Zicbop' (Cache-Block Prefetch Instructions)">;
414def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
415                                AssemblerPredicate<(all_of FeatureStdExtZicbop),
416                                "'Zicbop' (Cache-Block Prefetch Instructions)">;
417
418def FeatureStdExtSvnapot
419    : SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
420                       "'Svnapot' (NAPOT Translation Contiguity)">;
421
422def FeatureStdExtSvpbmt
423    : SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
424                       "'Svpbmt' (Page-Based Memory Types)">;
425
426def FeatureStdExtSvinval
427    : SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
428                       "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
429def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,
430                                AssemblerPredicate<(all_of FeatureStdExtSvinval),
431                                "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
432
433def FeatureStdExtZtso
434    : SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
435                       "'Ztso' (Memory Model - Total Store Order)">;
436def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZTso()">,
437                              AssemblerPredicate<(all_of FeatureStdExtZtso),
438                              "'Ztso' (Memory Model - Total Store Order)">;
439
440def FeatureStdExtZawrs
441    : SubtargetFeature<"experimental-zawrs", "HasStdExtZawrs", "true",
442                       "'Zawrs' (Wait on Reservation Set)">;
443def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
444                               AssemblerPredicate<(all_of FeatureStdExtZawrs),
445                               "'Zawrs' (Wait on Reservation Set)">;
446
447//===----------------------------------------------------------------------===//
448// Vendor extensions
449//===----------------------------------------------------------------------===//
450
451def FeatureVendorXVentanaCondOps
452    : SubtargetFeature<"xventanacondops", "HasVendorXVentanaCondOps", "true",
453                       "'XVentanaCondOps' (Ventana Conditional Ops)">;
454def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">,
455                                AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps),
456                                "'XVentanaCondOps' (Ventana Conditional Ops)">;
457
458def FeatureVendorXTHeadVdot
459    : SubtargetFeature<"xtheadvdot", "HasVendorXTHeadVdot", "true",
460                       "'xtheadvdot' (T-Head Vector Extensions for Dot)",
461                       [FeatureStdExtV]>;
462def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
463                                    AssemblerPredicate<(all_of FeatureVendorXTHeadVdot),
464                                    "'xtheadvdot' (T-Head Vector Extensions for Dot)">;
465
466//===----------------------------------------------------------------------===//
467// LLVM specific features and extensions
468//===----------------------------------------------------------------------===//
469
470// Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
471// tuning CPU names.
472def Feature32Bit
473    : SubtargetFeature<"32bit", "HasRV32", "true", "Implements RV32">;
474def Feature64Bit
475    : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
476def IsRV64 : Predicate<"Subtarget->is64Bit()">,
477                       AssemblerPredicate<(all_of Feature64Bit),
478                                         "RV64I Base Instruction Set">;
479def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
480                       AssemblerPredicate<(all_of (not Feature64Bit)),
481                                          "RV32I Base Instruction Set">;
482
483defvar RV32 = DefaultMode;
484def RV64           : HwMode<"+64bit">;
485
486def FeatureRV32E
487    : SubtargetFeature<"e", "IsRV32E", "true",
488                       "Implements RV32E (provides 16 rather than 32 GPRs)">;
489def IsRV32E : Predicate<"Subtarget->isRV32E()">,
490                        AssemblerPredicate<(all_of FeatureRV32E)>;
491
492def FeatureRelax
493    : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
494                       "Enable Linker relaxation.">;
495
496foreach i = {1-31} in
497  def FeatureReserveX#i :
498      SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
499                       "true", "Reserve X"#i>;
500
501def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
502                                          "true", "Enable save/restore.">;
503
504def FeatureUnalignedScalarMem
505   : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",
506                      "true", "Has reasonably performant unaligned scalar "
507                      "loads and stores">;
508
509def TuneNoOptimizedZeroStrideLoad
510   : SubtargetFeature<"no-optimized-zero-stride-load", "HasOptimizedZeroStrideLoad",
511                      "false", "Hasn't optimized (perform fewer memory operations)"
512                      "zero-stride vector load">;
513
514def TuneLUIADDIFusion
515    : SubtargetFeature<"lui-addi-fusion", "HasLUIADDIFusion",
516                       "true", "Enable LUI+ADDI macrofusion">;
517
518def TuneNoDefaultUnroll
519    : SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false",
520                       "Disable default unroll preference.">;
521
522// SiFive 7 is able to fuse integer ALU operations with a preceding branch
523// instruction.
524def TuneShortForwardBranchOpt
525    : SubtargetFeature<"short-forward-branch-opt", "HasShortForwardBranchOpt",
526                       "true", "Enable short forward branch optimization">;
527def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">;
528def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">;
529
530def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
531                                   "SiFive 7-Series processors",
532                                   [TuneNoDefaultUnroll,
533                                    TuneShortForwardBranchOpt]>;
534
535// Assume that lock-free native-width atomics are available, even if the target
536// and operating system combination would not usually provide them. The user
537// is responsible for providing any necessary __sync implementations. Code
538// built with this feature is not ABI-compatible with code built without this
539// feature, if atomic variables are exposed across the ABI boundary.
540def FeatureForcedAtomics : SubtargetFeature<
541    "forced-atomics", "HasForcedAtomics", "true",
542    "Assume that lock-free native-width atomics are available">;
543def HasAtomicLdSt
544    : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">;
545
546def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
547    "AllowTaggedGlobals",
548    "true", "Use an instruction sequence for taking the address of a global "
549    "that allows a memory tag in the upper address bits">;
550