1//===-- RISCVFeatures.td - RISC-V Features and Extensions --*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// RISC-V subtarget features and instruction predicates.
11//===----------------------------------------------------------------------===//
12
13def FeatureStdExtZicsr
14    : SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
15                       "'zicsr' (CSRs)">;
16def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
17                                AssemblerPredicate<(all_of FeatureStdExtZicsr),
18                                "'Zicsr' (CSRs)">;
19
20def FeatureStdExtM
21    : SubtargetFeature<"m", "HasStdExtM", "true",
22                       "'M' (Integer Multiplication and Division)">;
23def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
24                           AssemblerPredicate<(all_of FeatureStdExtM),
25                           "'M' (Integer Multiplication and Division)">;
26
27def FeatureStdExtZmmul
28    : SubtargetFeature<"zmmul", "HasStdExtZmmul", "true",
29                       "'Zmmul' (Integer Multiplication)">;
30
31def HasStdExtMOrZmmul
32    : Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
33                AssemblerPredicate<(any_of FeatureStdExtM, FeatureStdExtZmmul),
34                                   "'M' (Integer Multiplication and Division) or "
35                                   "'Zmmul' (Integer Multiplication)">;
36
37def FeatureStdExtA
38    : SubtargetFeature<"a", "HasStdExtA", "true",
39                       "'A' (Atomic Instructions)">;
40def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
41                           AssemblerPredicate<(all_of FeatureStdExtA),
42                           "'A' (Atomic Instructions)">;
43
44def FeatureStdExtF
45    : SubtargetFeature<"f", "HasStdExtF", "true",
46                       "'F' (Single-Precision Floating-Point)",
47                       [FeatureStdExtZicsr]>;
48def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
49                           AssemblerPredicate<(all_of FeatureStdExtF),
50                           "'F' (Single-Precision Floating-Point)">;
51
52def FeatureStdExtD
53    : SubtargetFeature<"d", "HasStdExtD", "true",
54                       "'D' (Double-Precision Floating-Point)",
55                       [FeatureStdExtF]>;
56def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
57                           AssemblerPredicate<(all_of FeatureStdExtD),
58                           "'D' (Double-Precision Floating-Point)">;
59
60def FeatureStdExtH
61    : SubtargetFeature<"h", "HasStdExtH", "true",
62                       "'H' (Hypervisor)">;
63
64def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
65                           AssemblerPredicate<(all_of FeatureStdExtH),
66                           "'H' (Hypervisor)">;
67
68def FeatureStdExtZihintpause
69    : SubtargetFeature<"zihintpause", "HasStdExtZihintpause", "true",
70                       "'Zihintpause' (Pause Hint)">;
71def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
72                                     AssemblerPredicate<(all_of FeatureStdExtZihintpause),
73                                     "'Zihintpause' (Pause Hint)">;
74
75def FeatureStdExtZihintntl
76    : SubtargetFeature<"zihintntl", "HasStdExtZihintntl", "true",
77                       "'Zihintntl' (Non-Temporal Locality Hints)">;
78def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
79                                    AssemblerPredicate<(all_of FeatureStdExtZihintntl),
80                                    "'Zihintntl' (Non-Temporal Locality Hints)">;
81
82def FeatureStdExtZifencei
83    : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
84                       "'Zifencei' (fence.i)">;
85def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
86                                   AssemblerPredicate<(all_of FeatureStdExtZifencei),
87                                   "'Zifencei' (fence.i)">;
88
89def FeatureStdExtZicntr
90    : SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
91                       "'Zicntr' (Base Counters and Timers)",
92                       [FeatureStdExtZicsr]>;
93
94def FeatureStdExtZihpm
95    : SubtargetFeature<"zihpm", "HasStdExtZihpm", "true",
96                       "'Zihpm' (Hardware Performance Counters)",
97                       [FeatureStdExtZicsr]>;
98
99def FeatureStdExtZfhmin
100    : SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true",
101                       "'Zfhmin' (Half-Precision Floating-Point Minimal)",
102                       [FeatureStdExtF]>;
103def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
104                             AssemblerPredicate<(all_of FeatureStdExtZfhmin),
105                             "'Zfhmin' (Half-Precision Floating-Point Minimal)">;
106
107def FeatureStdExtZfh
108    : SubtargetFeature<"zfh", "HasStdExtZfh", "true",
109                       "'Zfh' (Half-Precision Floating-Point)",
110                       [FeatureStdExtZfhmin]>;
111def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
112                             AssemblerPredicate<(all_of FeatureStdExtZfh),
113                             "'Zfh' (Half-Precision Floating-Point)">;
114def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
115
116def HasStdExtZfhOrZfhmin
117    : Predicate<"Subtarget->hasStdExtZfhmin()">,
118                AssemblerPredicate<(all_of FeatureStdExtZfhmin),
119                                   "'Zfh' (Half-Precision Floating-Point) or "
120                                   "'Zfhmin' (Half-Precision Floating-Point Minimal)">;
121
122def FeatureStdExtZfinx
123    : SubtargetFeature<"zfinx", "HasStdExtZfinx", "true",
124                       "'Zfinx' (Float in Integer)",
125                       [FeatureStdExtZicsr]>;
126def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
127                               AssemblerPredicate<(all_of FeatureStdExtZfinx),
128                               "'Zfinx' (Float in Integer)">;
129
130def FeatureStdExtZdinx
131    : SubtargetFeature<"zdinx", "HasStdExtZdinx", "true",
132                       "'Zdinx' (Double in Integer)",
133                       [FeatureStdExtZfinx]>;
134def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
135                               AssemblerPredicate<(all_of FeatureStdExtZdinx),
136                               "'Zdinx' (Double in Integer)">;
137
138def FeatureStdExtZhinxmin
139    : SubtargetFeature<"zhinxmin", "HasStdExtZhinxmin", "true",
140                       "'Zhinxmin' (Half Float in Integer Minimal)",
141                       [FeatureStdExtZfinx]>;
142def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
143                                  AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
144                                  "'Zhinxmin' (Half Float in Integer Minimal)">;
145
146def FeatureStdExtZhinx
147    : SubtargetFeature<"zhinx", "HasStdExtZhinx", "true",
148                       "'Zhinx' (Half Float in Integer)",
149                       [FeatureStdExtZhinxmin]>;
150def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
151                               AssemblerPredicate<(all_of FeatureStdExtZhinx),
152                               "'Zhinx' (Half Float in Integer)">;
153def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
154
155def HasStdExtZhinxOrZhinxmin
156    : Predicate<"Subtarget->hasStdExtZhinxmin()">,
157                AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
158                                   "'Zhinx' (Half Float in Integer) or "
159                                   "'Zhinxmin' (Half Float in Integer Minimal)">;
160
161def FeatureStdExtZfa
162    : SubtargetFeature<"zfa", "HasStdExtZfa", "true",
163                       "'Zfa' (Additional Floating-Point)",
164                       [FeatureStdExtF]>;
165def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
166                             AssemblerPredicate<(all_of FeatureStdExtZfa),
167                             "'Zfa' (Additional Floating-Point)">;
168
169def FeatureStdExtC
170    : SubtargetFeature<"c", "HasStdExtC", "true",
171                       "'C' (Compressed Instructions)">;
172def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
173                           AssemblerPredicate<(all_of FeatureStdExtC),
174                           "'C' (Compressed Instructions)">;
175
176def FeatureStdExtZba
177    : SubtargetFeature<"zba", "HasStdExtZba", "true",
178                       "'Zba' (Address Generation Instructions)">;
179def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
180                             AssemblerPredicate<(all_of FeatureStdExtZba),
181                             "'Zba' (Address Generation Instructions)">;
182def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
183
184def FeatureStdExtZbb
185    : SubtargetFeature<"zbb", "HasStdExtZbb", "true",
186                       "'Zbb' (Basic Bit-Manipulation)">;
187def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
188                             AssemblerPredicate<(all_of FeatureStdExtZbb),
189                             "'Zbb' (Basic Bit-Manipulation)">;
190
191def FeatureStdExtZbc
192    : SubtargetFeature<"zbc", "HasStdExtZbc", "true",
193                       "'Zbc' (Carry-Less Multiplication)">;
194def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
195                             AssemblerPredicate<(all_of FeatureStdExtZbc),
196                             "'Zbc' (Carry-Less Multiplication)">;
197
198def FeatureStdExtZbs
199    : SubtargetFeature<"zbs", "HasStdExtZbs", "true",
200                       "'Zbs' (Single-Bit Instructions)">;
201def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
202                             AssemblerPredicate<(all_of FeatureStdExtZbs),
203                             "'Zbs' (Single-Bit Instructions)">;
204
205def FeatureStdExtZbkb
206    : SubtargetFeature<"zbkb", "HasStdExtZbkb", "true",
207                       "'Zbkb' (Bitmanip instructions for Cryptography)">;
208def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
209                             AssemblerPredicate<(all_of FeatureStdExtZbkb),
210                             "'Zbkb' (Bitmanip instructions for Cryptography)">;
211
212def FeatureStdExtZbkx
213    : SubtargetFeature<"zbkx", "HasStdExtZbkx", "true",
214                       "'Zbkx' (Crossbar permutation instructions)">;
215def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
216                             AssemblerPredicate<(all_of FeatureStdExtZbkx),
217                             "'Zbkx' (Crossbar permutation instructions)">;
218
219def HasStdExtZbbOrZbkb
220    : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()">,
221                AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb),
222                                   "'Zbb' (Basic Bit-Manipulation) or "
223                                   "'Zbkb' (Bitmanip instructions for Cryptography)">;
224
225// The Carry-less multiply subextension for cryptography is a subset of basic
226// carry-less multiply subextension. The former should be enabled if the latter
227// is enabled.
228def FeatureStdExtZbkc
229    : SubtargetFeature<"zbkc", "HasStdExtZbkc", "true",
230                       "'Zbkc' (Carry-less multiply instructions for "
231                       "Cryptography)">;
232def HasStdExtZbkc
233    : Predicate<"Subtarget->hasStdExtZbkc()">,
234                AssemblerPredicate<(all_of FeatureStdExtZbkc),
235                "'Zbkc' (Carry-less multiply instructions for Cryptography)">;
236
237def HasStdExtZbcOrZbkc
238    : Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">,
239                AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc),
240                                   "'Zbc' (Carry-Less Multiplication) or "
241                                   "'Zbkc' (Carry-less multiply instructions "
242                                   "for Cryptography)">;
243
244def FeatureStdExtZknd
245    : SubtargetFeature<"zknd", "HasStdExtZknd", "true",
246                       "'Zknd' (NIST Suite: AES Decryption)">;
247def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
248                              AssemblerPredicate<(all_of FeatureStdExtZknd),
249                              "'Zknd' (NIST Suite: AES Decryption)">;
250
251def FeatureStdExtZkne
252    : SubtargetFeature<"zkne", "HasStdExtZkne", "true",
253                       "'Zkne' (NIST Suite: AES Encryption)">;
254def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
255                              AssemblerPredicate<(all_of FeatureStdExtZkne),
256                              "'Zkne' (NIST Suite: AES Encryption)">;
257
258// Some instructions belong to both Zknd and Zkne subextensions.
259// They should be enabled if either has been specified.
260def HasStdExtZkndOrZkne
261    : Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">,
262                AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne),
263                                   "'Zknd' (NIST Suite: AES Decryption) or "
264                                   "'Zkne' (NIST Suite: AES Encryption)">;
265
266def FeatureStdExtZknh
267    : SubtargetFeature<"zknh", "HasStdExtZknh", "true",
268                       "'Zknh' (NIST Suite: Hash Function Instructions)">;
269def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
270                             AssemblerPredicate<(all_of FeatureStdExtZknh),
271                             "'Zknh' (NIST Suite: Hash Function Instructions)">;
272
273def FeatureStdExtZksed
274    : SubtargetFeature<"zksed", "HasStdExtZksed", "true",
275                       "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
276def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
277                             AssemblerPredicate<(all_of FeatureStdExtZksed),
278                             "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
279
280def FeatureStdExtZksh
281    : SubtargetFeature<"zksh", "HasStdExtZksh", "true",
282                       "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
283def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
284                              AssemblerPredicate<(all_of FeatureStdExtZksh),
285                              "'Zksh' (ShangMi Suite: SM3 Hash Function "
286                              "Instructions)">;
287
288def FeatureStdExtZkr
289    : SubtargetFeature<"zkr", "HasStdExtZkr", "true",
290                       "'Zkr' (Entropy Source Extension)">;
291def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
292                             AssemblerPredicate<(all_of FeatureStdExtZkr),
293                             "'Zkr' (Entropy Source Extension)">;
294
295def FeatureStdExtZkn
296    : SubtargetFeature<"zkn", "HasStdExtZkn", "true",
297                       "'Zkn' (NIST Algorithm Suite)",
298                       [FeatureStdExtZbkb,
299                        FeatureStdExtZbkc,
300                        FeatureStdExtZbkx,
301                        FeatureStdExtZkne,
302                        FeatureStdExtZknd,
303                        FeatureStdExtZknh]>;
304
305def FeatureStdExtZks
306    : SubtargetFeature<"zks", "HasStdExtZks", "true",
307                       "'Zks' (ShangMi Algorithm Suite)",
308                       [FeatureStdExtZbkb,
309                        FeatureStdExtZbkc,
310                        FeatureStdExtZbkx,
311                        FeatureStdExtZksed,
312                        FeatureStdExtZksh]>;
313
314def FeatureStdExtZkt
315    : SubtargetFeature<"zkt", "HasStdExtZkt", "true",
316                       "'Zkt' (Data Independent Execution Latency)">;
317
318def FeatureStdExtZk
319    : SubtargetFeature<"zk", "HasStdExtZk", "true",
320                       "'Zk' (Standard scalar cryptography extension)",
321                       [FeatureStdExtZkn,
322                        FeatureStdExtZkr,
323                        FeatureStdExtZkt]>;
324
325def FeatureStdExtZca
326    : SubtargetFeature<"zca", "HasStdExtZca", "true",
327                       "'Zca' (part of the C extension, excluding compressed "
328                       "floating point loads/stores)">;
329
330def HasStdExtCOrZca
331    : Predicate<"Subtarget->hasStdExtCOrZca()">,
332                AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZca),
333                                   "'C' (Compressed Instructions) or "
334                                   "'Zca' (part of the C extension, excluding "
335                                   "compressed floating point loads/stores)">;
336
337def FeatureStdExtZcb
338    : SubtargetFeature<"zcb", "HasStdExtZcb", "true",
339                       "'Zcb' (Compressed basic bit manipulation instructions)",
340                       [FeatureStdExtZca]>;
341def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
342                             AssemblerPredicate<(all_of FeatureStdExtZcb),
343                             "'Zcb' (Compressed basic bit manipulation instructions)">;
344
345def FeatureStdExtZcd
346    : SubtargetFeature<"zcd", "HasStdExtZcd", "true",
347                       "'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
348                       [FeatureStdExtZca]>;
349
350def HasStdExtCOrZcd
351    : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">,
352                AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd),
353                                   "'C' (Compressed Instructions) or "
354                                   "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
355
356def FeatureStdExtZcf
357    : SubtargetFeature<"zcf", "HasStdExtZcf", "true",
358                       "'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
359                       [FeatureStdExtZca]>;
360
361def FeatureStdExtZcmp
362    : SubtargetFeature<"zcmp", "HasStdExtZcmp", "true",
363                       "'Zcmp' (sequenced instuctions for code-size reduction)",
364                       [FeatureStdExtZca]>;
365def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
366                               AssemblerPredicate<(all_of FeatureStdExtZcmp),
367                               "'Zcmp' (sequenced instuctions for code-size reduction)">;
368
369def FeatureStdExtZcmt
370    : SubtargetFeature<"zcmt", "HasStdExtZcmt", "true",
371                       "'Zcmt' (table jump instuctions for code-size reduction)",
372                       [FeatureStdExtZca, FeatureStdExtZicsr]>;
373def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
374                           AssemblerPredicate<(all_of FeatureStdExtZcmt),
375                           "'Zcmt' (table jump instuctions for code-size reduction)">;
376
377def FeatureStdExtZce
378    : SubtargetFeature<"zce", "HasStdExtZce", "true",
379                       "'Zce' (Compressed extensions for microcontrollers)",
380                       [FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp,
381                        FeatureStdExtZcmt]>;
382
383def HasStdExtCOrZcfOrZce
384    : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() "
385                "Subtarget->hasStdExtZce()">,
386                AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf,
387                                           FeatureStdExtZce),
388                                   "'C' (Compressed Instructions) or "
389                                   "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
390
391def FeatureNoRVCHints
392    : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
393                       "Disable RVC Hint Instructions.">;
394def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
395                  AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
396                                      "RVC Hint Instructions">;
397
398def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "32",
399                                           "'Zvl' (Minimum Vector Length) 32">;
400
401foreach i = { 6-16 } in {
402  defvar I = !shl(1, i);
403  def FeatureStdExtZvl#I#b :
404      SubtargetFeature<"zvl"#I#"b", "ZvlLen", !cast<string>(I),
405                       "'Zvl' (Minimum Vector Length) "#I,
406                       [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
407}
408
409def FeatureStdExtZve32x
410    : SubtargetFeature<"zve32x", "HasStdExtZve32x", "true",
411                       "'Zve32x' (Vector Extensions for Embedded Processors "
412                       "with maximal 32 EEW)",
413                       [FeatureStdExtZicsr, FeatureStdExtZvl32b]>;
414
415def FeatureStdExtZve32f
416    : SubtargetFeature<"zve32f", "HasStdExtZve32f", "true",
417                       "'Zve32f' (Vector Extensions for Embedded Processors "
418                       "with maximal 32 EEW and F extension)",
419                       [FeatureStdExtZve32x, FeatureStdExtF]>;
420
421def FeatureStdExtZve64x
422    : SubtargetFeature<"zve64x", "HasStdExtZve64x", "true",
423                       "'Zve64x' (Vector Extensions for Embedded Processors "
424                       "with maximal 64 EEW)",
425                       [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
426
427def FeatureStdExtZve64f
428    : SubtargetFeature<"zve64f", "HasStdExtZve64f", "true",
429                       "'Zve64f' (Vector Extensions for Embedded Processors "
430                       "with maximal 64 EEW and F extension)",
431                       [FeatureStdExtZve32f, FeatureStdExtZve64x]>;
432
433def FeatureStdExtZve64d
434    : SubtargetFeature<"zve64d", "HasStdExtZve64d", "true",
435                       "'Zve64d' (Vector Extensions for Embedded Processors "
436                       "with maximal 64 EEW, F and D extension)",
437                       [FeatureStdExtZve64f, FeatureStdExtD]>;
438
439def FeatureStdExtV
440    : SubtargetFeature<"v", "HasStdExtV", "true",
441                       "'V' (Vector Extension for Application Processors)",
442                       [FeatureStdExtZvl128b, FeatureStdExtZve64d]>;
443
444def HasVInstructions    : Predicate<"Subtarget->hasVInstructions()">,
445      AssemblerPredicate<
446          (any_of FeatureStdExtZve32x),
447          "'V' (Vector Extension for Application Processors), 'Zve32x' "
448          "(Vector Extensions for Embedded Processors)">;
449def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">,
450      AssemblerPredicate<
451          (any_of FeatureStdExtZve64x),
452          "'V' (Vector Extension for Application Processors) or 'Zve64x' "
453          "(Vector Extensions for Embedded Processors)">;
454def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">,
455      AssemblerPredicate<
456          (any_of FeatureStdExtZve32f),
457          "'V' (Vector Extension for Application Processors), 'Zve32f' "
458          "(Vector Extensions for Embedded Processors)">;
459
460def HasVInstructionsF64 : Predicate<"Subtarget->hasVInstructionsF64()">;
461
462def HasVInstructionsFullMultiply : Predicate<"Subtarget->hasVInstructionsFullMultiply()">;
463
464def FeatureStdExtZfbfmin
465    : SubtargetFeature<"experimental-zfbfmin", "HasStdExtZfbfmin", "true",
466                       "'Zfbfmin' (Scalar BF16 Converts)",
467                       [FeatureStdExtF]>;
468def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
469                                 AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
470                                 "'Zfbfmin' (Scalar BF16 Converts)">;
471
472def FeatureStdExtZvfbfmin
473    : SubtargetFeature<"experimental-zvfbfmin", "HasStdExtZvfbfmin", "true",
474                       "'Zvbfmin' (Vector BF16 Converts)",
475                       [FeatureStdExtZve32f]>;
476def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
477                                  AssemblerPredicate<(all_of FeatureStdExtZvfbfmin),
478                                  "'Zvfbfmin' (Vector BF16 Converts)">;
479
480def FeatureStdExtZvfbfwma
481    : SubtargetFeature<"experimental-zvfbfwma", "HasStdExtZvfbfwma", "true",
482                       "'Zvfbfwma' (Vector BF16 widening mul-add)",
483                       [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>;
484def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
485                                  AssemblerPredicate<(all_of FeatureStdExtZvfbfwma),
486                                  "'Zvfbfwma' (Vector BF16 widening mul-add)">;
487
488def HasVInstructionsBF16 : Predicate<"Subtarget->hasVInstructionsBF16()">;
489
490def FeatureStdExtZvfhmin
491    : SubtargetFeature<"zvfhmin", "HasStdExtZvfhmin", "true",
492                       "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
493                       [FeatureStdExtZve32f]>;
494
495def FeatureStdExtZvfh
496    : SubtargetFeature<"zvfh", "HasStdExtZvfh", "true",
497                       "'Zvfh' (Vector Half-Precision Floating-Point)",
498                       [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>;
499
500def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">;
501
502def HasVInstructionsF16Minimal : Predicate<"Subtarget->hasVInstructionsF16Minimal()">,
503      AssemblerPredicate<(any_of FeatureStdExtZvfhmin, FeatureStdExtZvfh),
504                         "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or "
505                         "'Zvfh' (Vector Half-Precision Floating-Point)">;
506
507def HasStdExtZfhOrZvfh
508    : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
509                AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZvfh),
510                                   "'Zfh' (Half-Precision Floating-Point) or "
511                                   "'Zvfh' (Vector Half-Precision Floating-Point)">;
512
513def FeatureStdExtZicbom
514    : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
515                       "'Zicbom' (Cache-Block Management Instructions)">;
516def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
517                                AssemblerPredicate<(all_of FeatureStdExtZicbom),
518                                "'Zicbom' (Cache-Block Management Instructions)">;
519
520def FeatureStdExtZicboz
521    : SubtargetFeature<"zicboz", "HasStdExtZicboz", "true",
522                       "'Zicboz' (Cache-Block Zero Instructions)">;
523def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
524                                AssemblerPredicate<(all_of FeatureStdExtZicboz),
525                                "'Zicboz' (Cache-Block Zero Instructions)">;
526
527def FeatureStdExtZicbop
528    : SubtargetFeature<"zicbop", "HasStdExtZicbop", "true",
529                       "'Zicbop' (Cache-Block Prefetch Instructions)">;
530def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
531                                AssemblerPredicate<(all_of FeatureStdExtZicbop),
532                                "'Zicbop' (Cache-Block Prefetch Instructions)">;
533
534def FeatureStdExtSvnapot
535    : SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
536                       "'Svnapot' (NAPOT Translation Contiguity)">;
537
538def FeatureStdExtSvpbmt
539    : SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
540                       "'Svpbmt' (Page-Based Memory Types)">;
541
542def FeatureStdExtSvinval
543    : SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
544                       "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
545def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,
546                                AssemblerPredicate<(all_of FeatureStdExtSvinval),
547                                "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
548
549def FeatureStdExtZtso
550    : SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
551                       "'Ztso' (Memory Model - Total Store Order)">;
552def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
553                              AssemblerPredicate<(all_of FeatureStdExtZtso),
554                              "'Ztso' (Memory Model - Total Store Order)">;
555def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
556
557def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
558                                          "'Zawrs' (Wait on Reservation Set)">;
559def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
560                               AssemblerPredicate<(all_of FeatureStdExtZawrs),
561                               "'Zawrs' (Wait on Reservation Set)">;
562
563def FeatureStdExtZvkb
564    : SubtargetFeature<"zvkb", "HasStdExtZvkb", "true",
565                       "'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
566def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
567                              AssemblerPredicate<(all_of FeatureStdExtZvkb),
568                              "'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
569
570def FeatureStdExtZvbb
571    : SubtargetFeature<"zvbb", "HasStdExtZvbb", "true",
572                       "'Zvbb' (Vector basic bit-manipulation instructions.)",
573                       [FeatureStdExtZvkb]>;
574def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
575                              AssemblerPredicate<(all_of FeatureStdExtZvbb),
576                              "'Zvbb' (Vector basic bit-manipulation instructions.)">;
577
578def FeatureStdExtZvbc
579    : SubtargetFeature<"zvbc", "HasStdExtZvbc", "true",
580                       "'Zvbc' (Vector Carryless Multiplication)">;
581def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
582                              AssemblerPredicate<(all_of FeatureStdExtZvbc),
583                              "'Zvbc' (Vector Carryless Multiplication)">;
584
585def FeatureStdExtZvkg
586    : SubtargetFeature<"zvkg", "HasStdExtZvkg", "true",
587                       "'Zvkg' (Vector GCM instructions for Cryptography)">;
588def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
589                              AssemblerPredicate<(all_of FeatureStdExtZvkg),
590                              "'Zvkg' (Vector GCM instructions for Cryptography)">;
591
592def FeatureStdExtZvkned
593    : SubtargetFeature<"zvkned", "HasStdExtZvkned", "true",
594                       "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
595def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
596                                AssemblerPredicate<(all_of FeatureStdExtZvkned),
597                                "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
598
599def FeatureStdExtZvknha
600    : SubtargetFeature<"zvknha", "HasStdExtZvknha", "true",
601                       "'Zvknha' (Vector SHA-2 (SHA-256 only))">;
602def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
603                                AssemblerPredicate<(all_of FeatureStdExtZvknha),
604                                "'Zvknha' (Vector SHA-2 (SHA-256 only))">;
605
606def FeatureStdExtZvknhb
607    : SubtargetFeature<"zvknhb", "HasStdExtZvknhb", "true",
608                       "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
609                       [FeatureStdExtZve64x]>;
610def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">,
611                                AssemblerPredicate<(all_of FeatureStdExtZvknhb),
612                                "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">;
613
614def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarget->hasStdExtZvknhb()">,
615                                        AssemblerPredicate<(any_of FeatureStdExtZvknha, FeatureStdExtZvknhb),
616                                        "'Zvknha' or 'Zvknhb' (Vector SHA-2)">;
617
618def FeatureStdExtZvksed
619    : SubtargetFeature<"zvksed", "HasStdExtZvksed", "true",
620                       "'Zvksed' (SM4 Block Cipher Instructions)">;
621def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
622                                AssemblerPredicate<(all_of FeatureStdExtZvksed),
623                                "'Zvksed' (SM4 Block Cipher Instructions)">;
624
625def FeatureStdExtZvksh
626    : SubtargetFeature<"zvksh", "HasStdExtZvksh", "true",
627                       "'Zvksh' (SM3 Hash Function Instructions)">;
628def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
629                               AssemblerPredicate<(all_of FeatureStdExtZvksh),
630                               "'Zvksh' (SM3 Hash Function Instructions)">;
631
632def FeatureStdExtZvkt
633    : SubtargetFeature<"zvkt", "HasStdExtZvkt", "true",
634                       "'Zvkt' (Vector Data-Independent Execution Latency)">;
635
636// Zvk short-hand extensions
637
638def FeatureStdExtZvkn
639    : SubtargetFeature<"zvkn", "HasStdExtZvkn", "true",
640                       "This extension is shorthand for the following set of "
641                       "other extensions: Zvkned, Zvknhb, Zvkb and Zvkt.",
642                       [FeatureStdExtZvkned, FeatureStdExtZvknhb,
643                        FeatureStdExtZvkb, FeatureStdExtZvkt]>;
644
645def FeatureStdExtZvknc
646    : SubtargetFeature<"zvknc", "HasStdExtZvknc", "true",
647                       "This extension is shorthand for the following set of "
648                       "other extensions: Zvkn and Zvbc.",
649                       [FeatureStdExtZvkn, FeatureStdExtZvbc]>;
650
651def FeatureStdExtZvkng
652    : SubtargetFeature<"zvkng", "HasStdExtZvkng", "true",
653                       "This extension is shorthand for the following set of "
654                       "other extensions: Zvkn and Zvkg.",
655                       [FeatureStdExtZvkn, FeatureStdExtZvkg]>;
656
657def FeatureStdExtZvks
658    : SubtargetFeature<"zvks", "HasStdExtZvks", "true",
659                       "This extension is shorthand for the following set of "
660                       "other extensions: Zvksed, Zvksh, Zvkb and Zvkt.",
661                       [FeatureStdExtZvksed, FeatureStdExtZvksh,
662                        FeatureStdExtZvkb, FeatureStdExtZvkt]>;
663
664def FeatureStdExtZvksc
665    : SubtargetFeature<"zvksc", "HasStdExtZvksc", "true",
666                       "This extension is shorthand for the following set of "
667                       "other extensions: Zvks and Zvbc.",
668                       [FeatureStdExtZvks, FeatureStdExtZvbc]>;
669
670def FeatureStdExtZvksg
671    : SubtargetFeature<"zvksg", "HasStdExtZvksg", "true",
672                       "This extension is shorthand for the following set of "
673                       "other extensions: Zvks and Zvkg.",
674                       [FeatureStdExtZvks, FeatureStdExtZvkg]>;
675
676def FeatureStdExtZicfilp
677    : SubtargetFeature<"experimental-zicfilp", "HasStdExtZicfilp", "true",
678                       "'Zicfilp' (Landing pad)">;
679def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
680                                 AssemblerPredicate<(all_of FeatureStdExtZicfilp),
681                                 "'Zicfilp' (Landing pad)">;
682
683def FeatureStdExtZicond
684    : SubtargetFeature<"experimental-zicond", "HasStdExtZicond", "true",
685                       "'Zicond' (Integer Conditional Operations)">;
686def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
687                                AssemblerPredicate<(all_of FeatureStdExtZicond),
688                                "'Zicond' (Integer Conditional Operations)">;
689
690def FeatureStdExtSmaia
691    : SubtargetFeature<"smaia", "HasStdExtSmaia", "true",
692                       "'Smaia' (Smaia encompasses all added CSRs and all "
693                       "modifications to interrupt response behavior that the "
694                       "AIA specifies for a hart, over all privilege levels.)",
695                       []>;
696
697def FeatureStdExtSsaia
698    : SubtargetFeature<"ssaia", "HasStdExtSsaia", "true",
699                       "'Ssaia' (Ssaia is essentially the same as Smaia except "
700                       "excluding the machine-level CSRs and behavior not "
701                       "directly visible to supervisor level.)", []>;
702
703def HasHalfFPLoadStoreMove
704    : Predicate<"Subtarget->hasHalfFPLoadStoreMove()">,
705                AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin,
706                                    FeatureStdExtZfbfmin),
707                                    "'Zfh' (Half-Precision Floating-Point) or "
708                                    "'Zfhmin' (Half-Precision Floating-Point Minimal) or "
709                                    "'Zfbfmin' (Scalar BF16 Converts)">;
710
711def FeatureStdExtZacas
712    : SubtargetFeature<"experimental-zacas", "HasStdExtZacas", "true",
713                       "'Zacas' (Atomic Compare-And-Swap Instructions)">;
714def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
715                               AssemblerPredicate<(all_of FeatureStdExtZacas),
716                               "'Zacas' (Atomic Compare-And-Swap Instructions)">;
717
718//===----------------------------------------------------------------------===//
719// Vendor extensions
720//===----------------------------------------------------------------------===//
721
722def FeatureVendorXVentanaCondOps
723    : SubtargetFeature<"xventanacondops", "HasVendorXVentanaCondOps", "true",
724                       "'XVentanaCondOps' (Ventana Conditional Ops)">;
725def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">,
726                                AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps),
727                                "'XVentanaCondOps' (Ventana Conditional Ops)">;
728
729def FeatureVendorXTHeadBa
730    : SubtargetFeature<"xtheadba", "HasVendorXTHeadBa", "true",
731                       "'xtheadba' (T-Head address calculation instructions)">;
732def HasVendorXTHeadBa : Predicate<"Subtarget->hasVendorXTHeadBa()">,
733                                  AssemblerPredicate<(all_of FeatureVendorXTHeadBa),
734                                  "'xtheadba' (T-Head address calculation instructions)">;
735
736def FeatureVendorXTHeadBb
737    : SubtargetFeature<"xtheadbb", "HasVendorXTHeadBb", "true",
738                       "'xtheadbb' (T-Head basic bit-manipulation instructions)">;
739def HasVendorXTHeadBb : Predicate<"Subtarget->hasVendorXTHeadBb()">,
740                                  AssemblerPredicate<(all_of FeatureVendorXTHeadBb),
741                                  "'xtheadbb' (T-Head basic bit-manipulation instructions)">;
742
743def FeatureVendorXTHeadBs
744    : SubtargetFeature<"xtheadbs", "HasVendorXTHeadBs", "true",
745                       "'xtheadbs' (T-Head single-bit instructions)">;
746def HasVendorXTHeadBs : Predicate<"Subtarget->hasVendorXTHeadBs()">,
747                                  AssemblerPredicate<(all_of FeatureVendorXTHeadBs),
748                                  "'xtheadbs' (T-Head single-bit instructions)">;
749
750def FeatureVendorXTHeadCondMov
751    : SubtargetFeature<"xtheadcondmov", "HasVendorXTHeadCondMov", "true",
752                       "'xtheadcondmov' (T-Head conditional move instructions)">;
753def HasVendorXTHeadCondMov : Predicate<"Subtarget->hasVendorXTHeadCondMov()">,
754                                       AssemblerPredicate<(all_of FeatureVendorXTHeadCondMov),
755                                       "'xtheadcondmov' (T-Head conditional move instructions)">;
756
757def FeatureVendorXTHeadCmo
758    : SubtargetFeature<"xtheadcmo", "HasVendorXTHeadCmo", "true",
759                       "'xtheadcmo' (T-Head cache management instructions)">;
760def HasVendorXTHeadCmo : Predicate<"Subtarget->hasVendorXTHeadCmo()">,
761                                   AssemblerPredicate<(all_of FeatureVendorXTHeadCmo),
762                                   "'xtheadcmo' (T-Head cache management instructions)">;
763
764def FeatureVendorXTHeadFMemIdx
765    : SubtargetFeature<"xtheadfmemidx", "HasVendorXTHeadFMemIdx", "true",
766                       "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)",
767                       [FeatureStdExtF]>;
768def HasVendorXTHeadFMemIdx : Predicate<"Subtarget->hasVendorXTHeadFMemIdx()">,
769                                       AssemblerPredicate<(all_of FeatureVendorXTHeadFMemIdx),
770                                       "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)">;
771
772def FeatureVendorXTHeadMac
773    : SubtargetFeature<"xtheadmac", "HasVendorXTHeadMac", "true",
774                       "'xtheadmac' (T-Head Multiply-Accumulate Instructions)">;
775def HasVendorXTHeadMac : Predicate<"Subtarget->hasVendorXTHeadMac()">,
776                                   AssemblerPredicate<(all_of FeatureVendorXTHeadMac),
777                                   "'xtheadmac' (T-Head Multiply-Accumulate Instructions)">;
778
779def FeatureVendorXTHeadMemIdx
780    : SubtargetFeature<"xtheadmemidx", "HasVendorXTHeadMemIdx", "true",
781                       "'xtheadmemidx' (T-Head Indexed Memory Operations)">;
782def HasVendorXTHeadMemIdx : Predicate<"Subtarget->hasVendorXTHeadMemIdx()">,
783                                      AssemblerPredicate<(all_of FeatureVendorXTHeadMemIdx),
784                                      "'xtheadmemidx' (T-Head Indexed Memory Operations)">;
785
786def FeatureVendorXTHeadMemPair
787    : SubtargetFeature<"xtheadmempair", "HasVendorXTHeadMemPair", "true",
788                       "'xtheadmempair' (T-Head two-GPR Memory Operations)">;
789def HasVendorXTHeadMemPair : Predicate<"Subtarget->hasVendorXTHeadMemPair()">,
790                                    AssemblerPredicate<(all_of FeatureVendorXTHeadMemPair),
791                                    "'xtheadmempair' (T-Head two-GPR Memory Operations)">;
792
793def FeatureVendorXTHeadSync
794    : SubtargetFeature<"xtheadsync", "HasVendorXTHeadSync", "true",
795                       "'xtheadsync' (T-Head multicore synchronization instructions)">;
796def HasVendorXTHeadSync : Predicate<"Subtarget->hasVendorXTHeadSync()">,
797                                    AssemblerPredicate<(all_of FeatureVendorXTHeadSync),
798                                    "'xtheadsync' (T-Head multicore synchronization instructions)">;
799
800def FeatureVendorXTHeadVdot
801    : SubtargetFeature<"xtheadvdot", "HasVendorXTHeadVdot", "true",
802                       "'xtheadvdot' (T-Head Vector Extensions for Dot)",
803                       [FeatureStdExtV]>;
804def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
805                                    AssemblerPredicate<(all_of FeatureVendorXTHeadVdot),
806                                    "'xtheadvdot' (T-Head Vector Extensions for Dot)">;
807
808def FeatureVendorXSfvcp
809    : SubtargetFeature<"xsfvcp", "HasVendorXSfvcp", "true",
810                       "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)",
811                       [FeatureStdExtZve32x]>;
812def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">,
813                                AssemblerPredicate<(all_of FeatureVendorXSfvcp),
814                                "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">;
815
816def FeatureVendorXSfcie
817    : SubtargetFeature<"xsfcie", "HasVendorXSfcie", "true",
818                       "'XSfcie' (SiFive Custom Instruction Extension SCIE.)">;
819def HasVendorXSfcie : Predicate<"Subtarget->hasVendorXSfcie()">,
820                        AssemblerPredicate<(all_of FeatureVendorXSfcie),
821                        "'XSfcie' (SiFive Custom Instruction Extension SCIE.)">;
822
823def FeatureVendorXSfvqmaccdod
824    : SubtargetFeature<"xsfvqmaccdod", "HasVendorXSfvqmaccdod", "true",
825                       "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))",
826                       [FeatureStdExtZve32x]>;
827def HasVendorXSfvqmaccdod : Predicate<"Subtarget->hasVendorXSfvqmaccdod()">,
828                         AssemblerPredicate<(all_of FeatureVendorXSfvqmaccdod),
829                         "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))">;
830
831def FeatureVendorXSfvqmaccqoq
832    : SubtargetFeature<"xsfvqmaccqoq", "HasVendorXSfvqmaccqoq", "true",
833                       "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))",
834                       [FeatureStdExtZve32x]>;
835def HasVendorXSfvqmaccqoq : Predicate<"Subtarget->hasVendorXSfvqmaccqoq()">,
836                         AssemblerPredicate<(all_of FeatureVendorXSfvqmaccqoq),
837                         "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))">;
838
839def FeatureVendorXSfvfwmaccqqq
840    : SubtargetFeature<"xsfvfwmaccqqq", "HasVendorXSfvfwmaccqqq", "true",
841                       "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))",
842                       [FeatureStdExtZve32f, FeatureStdExtZvfbfmin]>;
843def HasVendorXSfvfwmaccqqq : Predicate<"Subtarget->hasVendorXSfvfwmaccqqq()">,
844                         AssemblerPredicate<(all_of FeatureVendorXSfvfwmaccqqq),
845                         "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))">;
846
847def FeatureVendorXSfvfnrclipxfqf
848    : SubtargetFeature<"xsfvfnrclipxfqf", "HasVendorXSfvfnrclipxfqf", "true",
849                       "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)",
850                       [FeatureStdExtZve32f]>;
851def HasVendorXSfvfnrclipxfqf : Predicate<"Subtarget->hasVendorXSfvfnrclipxfqf()">,
852                               AssemblerPredicate<(all_of FeatureVendorXSfvfnrclipxfqf),
853                               "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">;
854def FeatureVendorXCVelw
855   : SubtargetFeature<"xcvelw", "HasVendorXCVelw", "true",
856                      "'XCVelw' (CORE-V Event Load Word)">;
857def HasVendorXCVelw
858   : Predicate<"Subtarget->hasVendorXCVelw()">,
859              AssemblerPredicate<(any_of FeatureVendorXCVelw),
860              "'XCVelw' (CORE-V Event Load Word)">;
861
862def FeatureVendorXCVbitmanip
863    : SubtargetFeature<"xcvbitmanip", "HasVendorXCVbitmanip", "true",
864                       "'XCVbitmanip' (CORE-V Bit Manipulation)">;
865def HasVendorXCVbitmanip : Predicate<"Subtarget->hasVendorXCVbitmanip()">,
866                                AssemblerPredicate<(all_of FeatureVendorXCVbitmanip),
867                                "'XCVbitmanip' (CORE-V Bit Manipulation)">;
868
869def FeatureVendorXCVmac
870    : SubtargetFeature<"xcvmac", "HasVendorXCVmac", "true",
871                       "'XCVmac' (CORE-V Multiply-Accumulate)">;
872def HasVendorXCVmac : Predicate<"Subtarget->hasVendorXCVmac()">,
873                                AssemblerPredicate<(all_of FeatureVendorXCVmac),
874                                "'XCVmac' (CORE-V Multiply-Accumulate)">;
875
876def FeatureVendorXCVmem
877    : SubtargetFeature<"xcvmem", "HasVendorXCVmem", "true",
878                       "'XCVmem' (CORE-V Post-incrementing Load & Store)">;
879def HasVendorXCVmem
880    : Predicate<"Subtarget->hasVendorXCVmem()">,
881               AssemblerPredicate<(any_of FeatureVendorXCVmem),
882               "'XCVmem' (CORE-V Post-incrementing Load & Store)">;
883
884def FeatureVendorXCValu
885    : SubtargetFeature<"xcvalu", "HasVendorXCValu", "true",
886                       "'XCValu' (CORE-V ALU Operations)">;
887def HasVendorXCValu : Predicate<"Subtarget->hasVendorXCValu()">,
888                                AssemblerPredicate<(all_of FeatureVendorXCValu),
889                                "'XCValu' (CORE-V ALU Operations)">;
890
891def FeatureVendorXCVsimd
892    : SubtargetFeature<"xcvsimd", "HasVendorXCvsimd", "true",
893                       "'XCVsimd' (CORE-V SIMD ALU)">;
894def HasVendorXCVsimd
895    : Predicate<"Subtarget->hasVendorXCVsimd()">,
896                AssemblerPredicate<(any_of FeatureVendorXCVsimd),
897                "'XCVsimd' (CORE-V SIMD ALU)">;
898
899def FeatureVendorXCVbi
900    : SubtargetFeature<"xcvbi", "HasVendorXCVbi", "true",
901                       "'XCVbi' (CORE-V Immediate Branching)">;
902def HasVendorXCVbi : Predicate<"Subtarget->hasVendorXCVbi()">,
903                               AssemblerPredicate<(all_of FeatureVendorXCVbi),
904                               "'XCVbi' (CORE-V Immediate Branching)">;
905
906//===----------------------------------------------------------------------===//
907// LLVM specific features and extensions
908//===----------------------------------------------------------------------===//
909
910// Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
911// tuning CPU names.
912def Feature32Bit
913    : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
914def Feature64Bit
915    : SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">;
916def IsRV64 : Predicate<"Subtarget->is64Bit()">,
917                       AssemblerPredicate<(all_of Feature64Bit),
918                                         "RV64I Base Instruction Set">;
919def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
920                       AssemblerPredicate<(all_of (not Feature64Bit)),
921                                          "RV32I Base Instruction Set">;
922
923defvar RV32 = DefaultMode;
924def RV64           : HwMode<"+64bit", [IsRV64]>;
925
926def FeatureRVE
927    : SubtargetFeature<"e", "IsRVE", "true",
928                       "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">;
929def IsRVE : Predicate<"Subtarget->isRVE()">,
930                        AssemblerPredicate<(all_of FeatureRVE)>;
931
932def FeatureRelax
933    : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
934                       "Enable Linker relaxation.">;
935
936foreach i = {1-31} in
937  def FeatureReserveX#i :
938      SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
939                       "true", "Reserve X"#i>;
940
941def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
942                                          "true", "Enable save/restore.">;
943
944def FeatureTrailingSeqCstFence : SubtargetFeature<"seq-cst-trailing-fence",
945                                          "EnableSeqCstTrailingFence",
946                                          "true",
947                                          "Enable trailing fence for seq-cst store.">;
948
949def FeatureFastUnalignedAccess
950   : SubtargetFeature<"fast-unaligned-access", "HasFastUnalignedAccess",
951                      "true", "Has reasonably performant unaligned "
952                      "loads and stores (both scalar and vector)">;
953
954def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
955    "UsePostRAScheduler", "true", "Schedule again after register allocation">;
956
957def TuneNoOptimizedZeroStrideLoad
958   : SubtargetFeature<"no-optimized-zero-stride-load", "HasOptimizedZeroStrideLoad",
959                      "false", "Hasn't optimized (perform fewer memory operations)"
960                      "zero-stride vector load">;
961
962def Experimental
963   : SubtargetFeature<"experimental", "HasExperimental",
964                      "true", "Experimental intrinsics">;
965
966// Some vector hardware implementations do not process all VLEN bits in parallel
967// and instead split over multiple cycles. DLEN refers to the datapath width
968// that can be done in parallel.
969def TuneDLenFactor2
970   : SubtargetFeature<"dlen-factor-2", "DLenFactor2", "true",
971                      "Vector unit DLEN(data path width) is half of VLEN">;
972
973def TuneLUIADDIFusion
974    : SubtargetFeature<"lui-addi-fusion", "HasLUIADDIFusion",
975                       "true", "Enable LUI+ADDI macrofusion">;
976
977def TuneAUIPCADDIFusion
978    : SubtargetFeature<"auipc-addi-fusion", "HasAUIPCADDIFusion",
979                       "true", "Enable AUIPC+ADDI macrofusion">;
980
981def TuneZExtHFusion
982    : SubtargetFeature<"zexth-fusion", "HasZExtHFusion",
983                       "true", "Enable SLLI+SRLI to be fused to zero extension of halfword">;
984
985def TuneZExtWFusion
986    : SubtargetFeature<"zextw-fusion", "HasZExtWFusion",
987                       "true", "Enable SLLI+SRLI to be fused to zero extension of word">;
988
989def TuneShiftedZExtWFusion
990    : SubtargetFeature<"shifted-zextw-fusion", "HasShiftedZExtWFusion",
991                       "true", "Enable SLLI+SRLI to be fused when computing (shifted) zero extension of word">;
992
993def TuneLDADDFusion
994    : SubtargetFeature<"ld-add-fusion", "HasLDADDFusion",
995                       "true", "Enable LD+ADD macrofusion.">;
996
997def TuneNoDefaultUnroll
998    : SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false",
999                       "Disable default unroll preference.">;
1000
1001// SiFive 7 is able to fuse integer ALU operations with a preceding branch
1002// instruction.
1003def TuneShortForwardBranchOpt
1004    : SubtargetFeature<"short-forward-branch-opt", "HasShortForwardBranchOpt",
1005                       "true", "Enable short forward branch optimization">;
1006def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">;
1007def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">;
1008
1009def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
1010                                   "SiFive 7-Series processors",
1011                                   [TuneNoDefaultUnroll,
1012                                    TuneShortForwardBranchOpt]>;
1013
1014def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",
1015                                         "Ventana Veyron-Series processors">;
1016
1017// Assume that lock-free native-width atomics are available, even if the target
1018// and operating system combination would not usually provide them. The user
1019// is responsible for providing any necessary __sync implementations. Code
1020// built with this feature is not ABI-compatible with code built without this
1021// feature, if atomic variables are exposed across the ABI boundary.
1022def FeatureForcedAtomics : SubtargetFeature<
1023    "forced-atomics", "HasForcedAtomics", "true",
1024    "Assume that lock-free native-width atomics are available">;
1025def HasAtomicLdSt
1026    : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">;
1027
1028def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
1029    "AllowTaggedGlobals",
1030    "true", "Use an instruction sequence for taking the address of a global "
1031    "that allows a memory tag in the upper address bits">;
1032