1//===-- RISCVInstrFormats.td - RISCV Instruction Formats ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// 11// These instruction format definitions are structured to match the 12// description in the RISC-V User-Level ISA specification as closely as 13// possible. For instance, the specification describes instructions with the 14// MSB (31st bit) on the left and the LSB (0th bit) on the right. This is 15// reflected in the order of parameters to each instruction class. 16// 17// One area of divergence is in the description of immediates. The 18// specification describes immediate encoding in terms of bit-slicing 19// operations on the logical value represented. The immediate argument to 20// these instruction formats instead represents the bit sequence that will be 21// inserted into the instruction. e.g. although JAL's immediate is logically 22// a 21-bit value (where the LSB is always zero), we describe it as an imm20 23// to match how it is encoded. 24// 25//===----------------------------------------------------------------------===// 26 27// Format specifies the encoding used by the instruction. This is used by 28// RISCVMCCodeEmitter to determine which form of fixup to use. These 29// definitions must be kept in-sync with RISCVBaseInfo.h. 30class InstFormat<bits<5> val> { 31 bits<5> Value = val; 32} 33def InstFormatPseudo : InstFormat<0>; 34def InstFormatR : InstFormat<1>; 35def InstFormatR4 : InstFormat<2>; 36def InstFormatI : InstFormat<3>; 37def InstFormatS : InstFormat<4>; 38def InstFormatB : InstFormat<5>; 39def InstFormatU : InstFormat<6>; 40def InstFormatJ : InstFormat<7>; 41def InstFormatCR : InstFormat<8>; 42def InstFormatCI : InstFormat<9>; 43def InstFormatCSS : InstFormat<10>; 44def InstFormatCIW : InstFormat<11>; 45def InstFormatCL : InstFormat<12>; 46def InstFormatCS : InstFormat<13>; 47def InstFormatCA : InstFormat<14>; 48def InstFormatCB : InstFormat<15>; 49def InstFormatCJ : InstFormat<16>; 50def InstFormatOther : InstFormat<17>; 51 52class RISCVVConstraint<bits<3> val> { 53 bits<3> Value = val; 54} 55def NoConstraint : RISCVVConstraint<0b000>; 56def VS2Constraint : RISCVVConstraint<0b001>; 57def VS1Constraint : RISCVVConstraint<0b010>; 58def VMConstraint : RISCVVConstraint<0b100>; 59 60// Illegal instructions: 61// 62// * The destination vector register group for a masked vector instruction 63// cannot overlap the source mask register (v0), unless the destination vector 64// register is being written with a mask value (e.g., comparisons) or the 65// scalar result of a reduction. 66// 67// * Widening: The destination EEW is greater than the source EEW, the source 68// EMUL is at least 1. The destination vector register group cannot overlap 69// with the source vector register groups besides the highest-numbered part of 70// the destination register group. 71// 72// * Narrowing: The destination EEW is smaller than the source EEW. The 73// destination vector register group cannot overlap with the source vector 74// register groups besides the lowest-numbered part of the source register 75// group. 76// 77// * vmsbf.m/vmsif.m/vmsof.m: The destination register cannot overlap the 78// source register and, if masked, cannot overlap the mask register ('v0'). 79// 80// * viota: The destination register cannot overlap the source register and, 81// if masked, cannot overlap the mask register ('v0'). 82// 83// * v[f]slide[1]up: The destination vector register group for vslideup cannot 84// overlap the source vector register group. 85// 86// * vrgather: The destination vector register group cannot overlap with the 87// source vector register groups. 88// 89// * vcompress: The destination vector register group cannot overlap the 90// source vector register group or the source mask register 91def WidenV : RISCVVConstraint<!or(VS2Constraint.Value, 92 VS1Constraint.Value, 93 VMConstraint.Value)>; 94def WidenW : RISCVVConstraint<!or(VS1Constraint.Value, 95 VMConstraint.Value)>; 96def WidenCvt : RISCVVConstraint<!or(VS2Constraint.Value, 97 VMConstraint.Value)>; 98def Iota : RISCVVConstraint<!or(VS2Constraint.Value, 99 VMConstraint.Value)>; 100def SlideUp : RISCVVConstraint<!or(VS2Constraint.Value, 101 VMConstraint.Value)>; 102def Vrgather : RISCVVConstraint<!or(VS2Constraint.Value, 103 VS1Constraint.Value, 104 VMConstraint.Value)>; 105def Vcompress : RISCVVConstraint<!or(VS2Constraint.Value, 106 VS1Constraint.Value)>; 107 108// The following opcode names match those given in Table 19.1 in the 109// RISC-V User-level ISA specification ("RISC-V base opcode map"). 110class RISCVOpcode<string name, bits<7> val> { 111 string Name = name; 112 bits<7> Value = val; 113} 114def RISCVOpcodesList : GenericTable { 115 let FilterClass = "RISCVOpcode"; 116 let Fields = [ 117 "Name", "Value" 118 ]; 119 let PrimaryKey = [ "Value" ]; 120 let PrimaryKeyName = "lookupRISCVOpcodeByValue"; 121} 122def lookupRISCVOpcodeByName : SearchIndex { 123 let Table = RISCVOpcodesList; 124 let Key = [ "Name" ]; 125} 126def OPC_LOAD : RISCVOpcode<"LOAD", 0b0000011>; 127def OPC_LOAD_FP : RISCVOpcode<"LOAD_FP", 0b0000111>; 128def OPC_MISC_MEM : RISCVOpcode<"MISC_MEM", 0b0001111>; 129def OPC_OP_IMM : RISCVOpcode<"OP_IMM", 0b0010011>; 130def OPC_AUIPC : RISCVOpcode<"AUIPC", 0b0010111>; 131def OPC_OP_IMM_32 : RISCVOpcode<"OP_IMM_32", 0b0011011>; 132def OPC_STORE : RISCVOpcode<"STORE", 0b0100011>; 133def OPC_STORE_FP : RISCVOpcode<"STORE_FP", 0b0100111>; 134def OPC_AMO : RISCVOpcode<"AMO", 0b0101111>; 135def OPC_OP : RISCVOpcode<"OP", 0b0110011>; 136def OPC_LUI : RISCVOpcode<"LUI", 0b0110111>; 137def OPC_OP_32 : RISCVOpcode<"OP_32", 0b0111011>; 138def OPC_MADD : RISCVOpcode<"MADD", 0b1000011>; 139def OPC_MSUB : RISCVOpcode<"MSUB", 0b1000111>; 140def OPC_NMSUB : RISCVOpcode<"NMSUB", 0b1001011>; 141def OPC_NMADD : RISCVOpcode<"NMADD", 0b1001111>; 142def OPC_OP_FP : RISCVOpcode<"OP_FP", 0b1010011>; 143def OPC_OP_V : RISCVOpcode<"OP_V", 0b1010111>; 144def OPC_BRANCH : RISCVOpcode<"BRANCH", 0b1100011>; 145def OPC_JALR : RISCVOpcode<"JALR", 0b1100111>; 146def OPC_JAL : RISCVOpcode<"JAL", 0b1101111>; 147def OPC_SYSTEM : RISCVOpcode<"SYSTEM", 0b1110011>; 148 149class RVInst<dag outs, dag ins, string opcodestr, string argstr, 150 list<dag> pattern, InstFormat format> 151 : Instruction { 152 field bits<32> Inst; 153 // SoftFail is a field the disassembler can use to provide a way for 154 // instructions to not match without killing the whole decode process. It is 155 // mainly used for ARM, but Tablegen expects this field to exist or it fails 156 // to build the decode table. 157 field bits<32> SoftFail = 0; 158 let Size = 4; 159 160 bits<7> Opcode = 0; 161 162 let Inst{6-0} = Opcode; 163 164 let Namespace = "RISCV"; 165 166 dag OutOperandList = outs; 167 dag InOperandList = ins; 168 let AsmString = opcodestr # "\t" # argstr; 169 let Pattern = pattern; 170 171 let TSFlags{4-0} = format.Value; 172 173 // Defaults 174 RISCVVConstraint RVVConstraint = NoConstraint; 175 let TSFlags{7-5} = RVVConstraint.Value; 176 177 bits<3> VLMul = 0; 178 let TSFlags{10-8} = VLMul; 179 180 bit HasDummyMask = 0; 181 let TSFlags{11} = HasDummyMask; 182 183 bit ForceTailAgnostic = false; 184 let TSFlags{12} = ForceTailAgnostic; 185 186 bit HasMergeOp = 0; 187 let TSFlags{13} = HasMergeOp; 188 189 bit HasSEWOp = 0; 190 let TSFlags{14} = HasSEWOp; 191 192 bit HasVLOp = 0; 193 let TSFlags{15} = HasVLOp; 194 195 bit HasVecPolicyOp = 0; 196 let TSFlags{16} = HasVecPolicyOp; 197 198 bit IsRVVWideningReduction = 0; 199 let TSFlags{17} = IsRVVWideningReduction; 200 201 bit UsesMaskPolicy = 0; 202 let TSFlags{18} = UsesMaskPolicy; 203} 204 205// Pseudo instructions 206class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = ""> 207 : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo> { 208 let isPseudo = 1; 209 let isCodeGenOnly = 1; 210} 211 212class PseudoQuietFCMP<RegisterClass Ty> 213 : Pseudo<(outs GPR:$rd), (ins Ty:$rs1, Ty:$rs2), []> { 214 let hasSideEffects = 1; 215 let mayLoad = 0; 216 let mayStore = 0; 217} 218 219// Pseudo load instructions. 220class PseudoLoad<string opcodestr, RegisterClass rdty = GPR> 221 : Pseudo<(outs rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr"> { 222 let hasSideEffects = 0; 223 let mayLoad = 1; 224 let mayStore = 0; 225 let isCodeGenOnly = 0; 226 let isAsmParserOnly = 1; 227} 228 229class PseudoFloatLoad<string opcodestr, RegisterClass rdty = GPR> 230 : Pseudo<(outs GPR:$tmp, rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr, $tmp"> { 231 let hasSideEffects = 0; 232 let mayLoad = 1; 233 let mayStore = 0; 234 let isCodeGenOnly = 0; 235 let isAsmParserOnly = 1; 236} 237 238// Pseudo store instructions. 239class PseudoStore<string opcodestr, RegisterClass rsty = GPR> 240 : Pseudo<(outs GPR:$tmp), (ins rsty:$rs, bare_symbol:$addr), [], opcodestr, "$rs, $addr, $tmp"> { 241 let hasSideEffects = 0; 242 let mayLoad = 0; 243 let mayStore = 1; 244 let isCodeGenOnly = 0; 245 let isAsmParserOnly = 1; 246} 247 248// Instruction formats are listed in the order they appear in the RISC-V 249// instruction set manual (R, I, S, B, U, J) with sub-formats (e.g. RVInstR4, 250// RVInstRAtomic) sorted alphabetically. 251 252class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs, 253 dag ins, string opcodestr, string argstr> 254 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 255 bits<5> rs2; 256 bits<5> rs1; 257 bits<5> rd; 258 259 let Inst{31-25} = funct7; 260 let Inst{24-20} = rs2; 261 let Inst{19-15} = rs1; 262 let Inst{14-12} = funct3; 263 let Inst{11-7} = rd; 264 let Opcode = opcode.Value; 265} 266 267class RVInstR4<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode, dag outs, 268 dag ins, string opcodestr, string argstr> 269 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> { 270 bits<5> rs3; 271 bits<5> rs2; 272 bits<5> rs1; 273 bits<5> rd; 274 275 let Inst{31-27} = rs3; 276 let Inst{26-25} = funct2; 277 let Inst{24-20} = rs2; 278 let Inst{19-15} = rs1; 279 let Inst{14-12} = funct3; 280 let Inst{11-7} = rd; 281 let Opcode = opcode.Value; 282} 283 284class RVInstR4Frm<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins, 285 string opcodestr, string argstr> 286 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> { 287 bits<5> rs3; 288 bits<5> rs2; 289 bits<5> rs1; 290 bits<3> frm; 291 bits<5> rd; 292 293 let Inst{31-27} = rs3; 294 let Inst{26-25} = funct2; 295 let Inst{24-20} = rs2; 296 let Inst{19-15} = rs1; 297 let Inst{14-12} = frm; 298 let Inst{11-7} = rd; 299 let Opcode = opcode.Value; 300} 301 302class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3, 303 RISCVOpcode opcode, dag outs, dag ins, string opcodestr, 304 string argstr> 305 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 306 bits<5> rs2; 307 bits<5> rs1; 308 bits<5> rd; 309 310 let Inst{31-27} = funct5; 311 let Inst{26} = aq; 312 let Inst{25} = rl; 313 let Inst{24-20} = rs2; 314 let Inst{19-15} = rs1; 315 let Inst{14-12} = funct3; 316 let Inst{11-7} = rd; 317 let Opcode = opcode.Value; 318} 319 320class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins, 321 string opcodestr, string argstr> 322 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 323 bits<5> rs2; 324 bits<5> rs1; 325 bits<3> frm; 326 bits<5> rd; 327 328 let Inst{31-25} = funct7; 329 let Inst{24-20} = rs2; 330 let Inst{19-15} = rs1; 331 let Inst{14-12} = frm; 332 let Inst{11-7} = rd; 333 let Opcode = opcode.Value; 334} 335 336class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins, 337 string opcodestr, string argstr> 338 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> { 339 bits<12> imm12; 340 bits<5> rs1; 341 bits<5> rd; 342 343 let Inst{31-20} = imm12; 344 let Inst{19-15} = rs1; 345 let Inst{14-12} = funct3; 346 let Inst{11-7} = rd; 347 let Opcode = opcode.Value; 348} 349 350class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode, 351 dag outs, dag ins, string opcodestr, string argstr> 352 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> { 353 bits<6> shamt; 354 bits<5> rs1; 355 bits<5> rd; 356 357 let Inst{31-27} = imm11_7; 358 let Inst{26} = 0; 359 let Inst{25-20} = shamt; 360 let Inst{19-15} = rs1; 361 let Inst{14-12} = funct3; 362 let Inst{11-7} = rd; 363 let Opcode = opcode.Value; 364} 365 366class RVInstIShiftW<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode, 367 dag outs, dag ins, string opcodestr, string argstr> 368 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> { 369 bits<5> shamt; 370 bits<5> rs1; 371 bits<5> rd; 372 373 let Inst{31-25} = imm11_5; 374 let Inst{24-20} = shamt; 375 let Inst{19-15} = rs1; 376 let Inst{14-12} = funct3; 377 let Inst{11-7} = rd; 378 let Opcode = opcode.Value; 379} 380 381class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins, 382 string opcodestr, string argstr> 383 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatS> { 384 bits<12> imm12; 385 bits<5> rs2; 386 bits<5> rs1; 387 388 let Inst{31-25} = imm12{11-5}; 389 let Inst{24-20} = rs2; 390 let Inst{19-15} = rs1; 391 let Inst{14-12} = funct3; 392 let Inst{11-7} = imm12{4-0}; 393 let Opcode = opcode.Value; 394} 395 396class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins, 397 string opcodestr, string argstr> 398 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatB> { 399 bits<12> imm12; 400 bits<5> rs2; 401 bits<5> rs1; 402 403 let Inst{31} = imm12{11}; 404 let Inst{30-25} = imm12{9-4}; 405 let Inst{24-20} = rs2; 406 let Inst{19-15} = rs1; 407 let Inst{14-12} = funct3; 408 let Inst{11-8} = imm12{3-0}; 409 let Inst{7} = imm12{10}; 410 let Opcode = opcode.Value; 411} 412 413class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr, 414 string argstr> 415 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatU> { 416 bits<20> imm20; 417 bits<5> rd; 418 419 let Inst{31-12} = imm20; 420 let Inst{11-7} = rd; 421 let Opcode = opcode.Value; 422} 423 424class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr, 425 string argstr> 426 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatJ> { 427 bits<20> imm20; 428 bits<5> rd; 429 430 let Inst{31} = imm20{19}; 431 let Inst{30-21} = imm20{9-0}; 432 let Inst{20} = imm20{10}; 433 let Inst{19-12} = imm20{18-11}; 434 let Inst{11-7} = rd; 435 let Opcode = opcode.Value; 436} 437 438//===----------------------------------------------------------------------===// 439// Instruction classes for .insn directives 440//===----------------------------------------------------------------------===// 441 442class DirectiveInsnR<dag outs, dag ins, string argstr> 443 : RVInst<outs, ins, "", "", [], InstFormatR> { 444 bits<7> opcode; 445 bits<7> funct7; 446 bits<3> funct3; 447 448 bits<5> rs2; 449 bits<5> rs1; 450 bits<5> rd; 451 452 let Inst{31-25} = funct7; 453 let Inst{24-20} = rs2; 454 let Inst{19-15} = rs1; 455 let Inst{14-12} = funct3; 456 let Inst{11-7} = rd; 457 let Opcode = opcode; 458 459 let AsmString = ".insn r " # argstr; 460} 461 462class DirectiveInsnR4<dag outs, dag ins, string argstr> 463 : RVInst<outs, ins, "", "", [], InstFormatR4> { 464 bits<7> opcode; 465 bits<2> funct2; 466 bits<3> funct3; 467 468 bits<5> rs3; 469 bits<5> rs2; 470 bits<5> rs1; 471 bits<5> rd; 472 473 let Inst{31-27} = rs3; 474 let Inst{26-25} = funct2; 475 let Inst{24-20} = rs2; 476 let Inst{19-15} = rs1; 477 let Inst{14-12} = funct3; 478 let Inst{11-7} = rd; 479 let Opcode = opcode; 480 481 let AsmString = ".insn r4 " # argstr; 482} 483 484class DirectiveInsnI<dag outs, dag ins, string argstr> 485 : RVInst<outs, ins, "", "", [], InstFormatI> { 486 bits<7> opcode; 487 bits<3> funct3; 488 489 bits<12> imm12; 490 bits<5> rs1; 491 bits<5> rd; 492 493 let Inst{31-20} = imm12; 494 let Inst{19-15} = rs1; 495 let Inst{14-12} = funct3; 496 let Inst{11-7} = rd; 497 let Opcode = opcode; 498 499 let AsmString = ".insn i " # argstr; 500} 501 502class DirectiveInsnS<dag outs, dag ins, string argstr> 503 : RVInst<outs, ins, "", "", [], InstFormatS> { 504 bits<7> opcode; 505 bits<3> funct3; 506 507 bits<12> imm12; 508 bits<5> rs2; 509 bits<5> rs1; 510 511 let Inst{31-25} = imm12{11-5}; 512 let Inst{24-20} = rs2; 513 let Inst{19-15} = rs1; 514 let Inst{14-12} = funct3; 515 let Inst{11-7} = imm12{4-0}; 516 let Opcode = opcode; 517 518 let AsmString = ".insn s " # argstr; 519} 520 521class DirectiveInsnB<dag outs, dag ins, string argstr> 522 : RVInst<outs, ins, "", "", [], InstFormatB> { 523 bits<7> opcode; 524 bits<3> funct3; 525 526 bits<12> imm12; 527 bits<5> rs2; 528 bits<5> rs1; 529 530 let Inst{31} = imm12{11}; 531 let Inst{30-25} = imm12{9-4}; 532 let Inst{24-20} = rs2; 533 let Inst{19-15} = rs1; 534 let Inst{14-12} = funct3; 535 let Inst{11-8} = imm12{3-0}; 536 let Inst{7} = imm12{10}; 537 let Opcode = opcode; 538 539 let AsmString = ".insn b " # argstr; 540} 541 542class DirectiveInsnU<dag outs, dag ins, string argstr> 543 : RVInst<outs, ins, "", "", [], InstFormatU> { 544 bits<7> opcode; 545 546 bits<20> imm20; 547 bits<5> rd; 548 549 let Inst{31-12} = imm20; 550 let Inst{11-7} = rd; 551 let Opcode = opcode; 552 553 let AsmString = ".insn u " # argstr; 554} 555 556class DirectiveInsnJ<dag outs, dag ins, string argstr> 557 : RVInst<outs, ins, "", "", [], InstFormatJ> { 558 bits<7> opcode; 559 560 bits<20> imm20; 561 bits<5> rd; 562 563 let Inst{31-12} = imm20; 564 let Inst{11-7} = rd; 565 let Opcode = opcode; 566 567 let AsmString = ".insn j " # argstr; 568} 569