1//===-- RISCVInstrFormats.td - RISCV Instruction Formats ---*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10//
11//  These instruction format definitions are structured to match the
12//  description in the RISC-V User-Level ISA specification as closely as
13//  possible. For instance, the specification describes instructions with the
14//  MSB (31st bit) on the left and the LSB (0th bit) on the right. This is
15//  reflected in the order of parameters to each instruction class.
16//
17//  One area of divergence is in the description of immediates. The
18//  specification describes immediate encoding in terms of bit-slicing
19//  operations on the logical value represented. The immediate argument to
20//  these instruction formats instead represents the bit sequence that will be
21//  inserted into the instruction. e.g. although JAL's immediate is logically
22//  a 21-bit value (where the LSB is always zero), we describe it as an imm20
23//  to match how it is encoded.
24//
25//===----------------------------------------------------------------------===//
26
27// Format specifies the encoding used by the instruction. This is used by
28// RISCVMCCodeEmitter to determine which form of fixup to use. These
29// definitions must be kept in-sync with RISCVBaseInfo.h.
30class InstFormat<bits<5> val> {
31  bits<5> Value = val;
32}
33def InstFormatPseudo : InstFormat<0>;
34def InstFormatR      : InstFormat<1>;
35def InstFormatR4     : InstFormat<2>;
36def InstFormatI      : InstFormat<3>;
37def InstFormatS      : InstFormat<4>;
38def InstFormatB      : InstFormat<5>;
39def InstFormatU      : InstFormat<6>;
40def InstFormatJ      : InstFormat<7>;
41def InstFormatCR     : InstFormat<8>;
42def InstFormatCI     : InstFormat<9>;
43def InstFormatCSS    : InstFormat<10>;
44def InstFormatCIW    : InstFormat<11>;
45def InstFormatCL     : InstFormat<12>;
46def InstFormatCS     : InstFormat<13>;
47def InstFormatCA     : InstFormat<14>;
48def InstFormatCB     : InstFormat<15>;
49def InstFormatCJ     : InstFormat<16>;
50def InstFormatOther  : InstFormat<17>;
51
52class RISCVVConstraint<bits<3> val> {
53  bits<3> Value = val;
54}
55def NoConstraint  : RISCVVConstraint<0b000>;
56def VS2Constraint : RISCVVConstraint<0b001>;
57def VS1Constraint : RISCVVConstraint<0b010>;
58def VMConstraint  : RISCVVConstraint<0b100>;
59
60// Illegal instructions:
61//
62// * The destination vector register group for a masked vector instruction
63// cannot overlap the source mask register (v0), unless the destination vector
64// register is being written with a mask value (e.g., comparisons) or the
65// scalar result of a reduction.
66//
67// * Widening: The destination EEW is greater than the source EEW, the source
68// EMUL is at least 1. The destination vector register group cannot overlap
69// with the source vector register groups besides the highest-numbered part of
70// the destination register group.
71//
72// * Narrowing: The destination EEW is smaller than the source EEW. The
73// destination vector register group cannot overlap with the source vector
74// register groups besides the lowest-numbered part of the source register
75// group.
76//
77// * vmsbf.m/vmsif.m/vmsof.m: The destination register cannot overlap the
78// source register and, if masked, cannot overlap the mask register ('v0').
79//
80// * viota: The destination register cannot overlap the source register and,
81// if masked, cannot overlap the mask register ('v0').
82//
83// * v[f]slide[1]up: The destination vector register group for vslideup cannot
84// overlap the source vector register group.
85//
86// * vrgather: The destination vector register group cannot overlap with the
87// source vector register groups.
88//
89// * vcompress: The destination vector register group cannot overlap the
90// source vector register group or the source mask register
91def WidenV       : RISCVVConstraint<!or(VS2Constraint.Value,
92                                        VS1Constraint.Value,
93                                        VMConstraint.Value)>;
94def WidenW       : RISCVVConstraint<!or(VS1Constraint.Value,
95                                        VMConstraint.Value)>;
96def WidenCvt     : RISCVVConstraint<!or(VS2Constraint.Value,
97                                        VMConstraint.Value)>;
98def Iota         : RISCVVConstraint<!or(VS2Constraint.Value,
99                                        VMConstraint.Value)>;
100def SlideUp      : RISCVVConstraint<!or(VS2Constraint.Value,
101                                        VMConstraint.Value)>;
102def Vrgather     : RISCVVConstraint<!or(VS2Constraint.Value,
103                                        VS1Constraint.Value,
104                                        VMConstraint.Value)>;
105def Vcompress    : RISCVVConstraint<!or(VS2Constraint.Value,
106                                        VS1Constraint.Value)>;
107
108// The following opcode names match those given in Table 19.1 in the
109// RISC-V User-level ISA specification ("RISC-V base opcode map").
110class RISCVOpcode<bits<7> val> {
111  bits<7> Value = val;
112}
113def OPC_LOAD      : RISCVOpcode<0b0000011>;
114def OPC_LOAD_FP   : RISCVOpcode<0b0000111>;
115def OPC_MISC_MEM  : RISCVOpcode<0b0001111>;
116def OPC_OP_IMM    : RISCVOpcode<0b0010011>;
117def OPC_AUIPC     : RISCVOpcode<0b0010111>;
118def OPC_OP_IMM_32 : RISCVOpcode<0b0011011>;
119def OPC_STORE     : RISCVOpcode<0b0100011>;
120def OPC_STORE_FP  : RISCVOpcode<0b0100111>;
121def OPC_AMO       : RISCVOpcode<0b0101111>;
122def OPC_OP        : RISCVOpcode<0b0110011>;
123def OPC_LUI       : RISCVOpcode<0b0110111>;
124def OPC_OP_32     : RISCVOpcode<0b0111011>;
125def OPC_MADD      : RISCVOpcode<0b1000011>;
126def OPC_MSUB      : RISCVOpcode<0b1000111>;
127def OPC_NMSUB     : RISCVOpcode<0b1001011>;
128def OPC_NMADD     : RISCVOpcode<0b1001111>;
129def OPC_OP_FP     : RISCVOpcode<0b1010011>;
130def OPC_OP_V      : RISCVOpcode<0b1010111>;
131def OPC_BRANCH    : RISCVOpcode<0b1100011>;
132def OPC_JALR      : RISCVOpcode<0b1100111>;
133def OPC_JAL       : RISCVOpcode<0b1101111>;
134def OPC_SYSTEM    : RISCVOpcode<0b1110011>;
135
136class RVInst<dag outs, dag ins, string opcodestr, string argstr,
137             list<dag> pattern, InstFormat format>
138    : Instruction {
139  field bits<32> Inst;
140  // SoftFail is a field the disassembler can use to provide a way for
141  // instructions to not match without killing the whole decode process. It is
142  // mainly used for ARM, but Tablegen expects this field to exist or it fails
143  // to build the decode table.
144  field bits<32> SoftFail = 0;
145  let Size = 4;
146
147  bits<7> Opcode = 0;
148
149  let Inst{6-0} = Opcode;
150
151  let Namespace = "RISCV";
152
153  dag OutOperandList = outs;
154  dag InOperandList = ins;
155  let AsmString = opcodestr # "\t" # argstr;
156  let Pattern = pattern;
157
158  let TSFlags{4-0} = format.Value;
159
160  // Defaults
161  RISCVVConstraint RVVConstraint = NoConstraint;
162  let TSFlags{7-5} = RVVConstraint.Value;
163
164  bits<3> VLMul = 0;
165  let TSFlags{10-8} = VLMul;
166
167  bit HasDummyMask = 0;
168  let TSFlags{11} = HasDummyMask;
169
170  bit WritesElement0 = 0;
171  let TSFlags{12} = WritesElement0;
172
173  bit HasMergeOp = 0;
174  let TSFlags{13} = HasMergeOp;
175
176  bit HasSEWOp = 0;
177  let TSFlags{14} = HasSEWOp;
178
179  bit HasVLOp = 0;
180  let TSFlags{15} = HasVLOp;
181}
182
183// Pseudo instructions
184class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = "">
185    : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo>,
186      Sched<[]> {
187  let isPseudo = 1;
188  let isCodeGenOnly = 1;
189}
190
191// Pseudo load instructions.
192class PseudoLoad<string opcodestr, RegisterClass rdty = GPR>
193    : Pseudo<(outs rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr"> {
194  let hasSideEffects = 0;
195  let mayLoad = 1;
196  let mayStore = 0;
197  let isCodeGenOnly = 0;
198  let isAsmParserOnly = 1;
199}
200
201class PseudoFloatLoad<string opcodestr, RegisterClass rdty = GPR>
202    : Pseudo<(outs rdty:$rd, GPR:$tmp), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr, $tmp"> {
203  let hasSideEffects = 0;
204  let mayLoad = 1;
205  let mayStore = 0;
206  let isCodeGenOnly = 0;
207  let isAsmParserOnly = 1;
208}
209
210// Pseudo store instructions.
211class PseudoStore<string opcodestr, RegisterClass rsty = GPR>
212    : Pseudo<(outs rsty:$rs, GPR:$tmp), (ins bare_symbol:$addr), [], opcodestr, "$rs, $addr, $tmp"> {
213  let hasSideEffects = 0;
214  let mayLoad = 0;
215  let mayStore = 1;
216  let isCodeGenOnly = 0;
217  let isAsmParserOnly = 1;
218}
219
220// Instruction formats are listed in the order they appear in the RISC-V
221// instruction set manual (R, I, S, B, U, J) with sub-formats (e.g. RVInstR4,
222// RVInstRAtomic) sorted alphabetically.
223
224class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,
225              dag ins, string opcodestr, string argstr>
226    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
227  bits<5> rs2;
228  bits<5> rs1;
229  bits<5> rd;
230
231  let Inst{31-25} = funct7;
232  let Inst{24-20} = rs2;
233  let Inst{19-15} = rs1;
234  let Inst{14-12} = funct3;
235  let Inst{11-7} = rd;
236  let Opcode = opcode.Value;
237}
238
239class RVInstR4<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
240               string opcodestr, string argstr>
241    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> {
242  bits<5> rs3;
243  bits<5> rs2;
244  bits<5> rs1;
245  bits<3> funct3;
246  bits<5> rd;
247
248  let Inst{31-27} = rs3;
249  let Inst{26-25} = funct2;
250  let Inst{24-20} = rs2;
251  let Inst{19-15} = rs1;
252  let Inst{14-12} = funct3;
253  let Inst{11-7} = rd;
254  let Opcode = opcode.Value;
255}
256
257class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
258                    RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
259                    string argstr>
260    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
261  bits<5> rs2;
262  bits<5> rs1;
263  bits<5> rd;
264
265  let Inst{31-27} = funct5;
266  let Inst{26} = aq;
267  let Inst{25} = rl;
268  let Inst{24-20} = rs2;
269  let Inst{19-15} = rs1;
270  let Inst{14-12} = funct3;
271  let Inst{11-7} = rd;
272  let Opcode = opcode.Value;
273}
274
275class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
276                 string opcodestr, string argstr>
277    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
278  bits<5> rs2;
279  bits<5> rs1;
280  bits<3> funct3;
281  bits<5> rd;
282
283  let Inst{31-25} = funct7;
284  let Inst{24-20} = rs2;
285  let Inst{19-15} = rs1;
286  let Inst{14-12} = funct3;
287  let Inst{11-7} = rd;
288  let Opcode = opcode.Value;
289}
290
291class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
292              string opcodestr, string argstr>
293    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
294  bits<12> imm12;
295  bits<5> rs1;
296  bits<5> rd;
297
298  let Inst{31-20} = imm12;
299  let Inst{19-15} = rs1;
300  let Inst{14-12} = funct3;
301  let Inst{11-7} = rd;
302  let Opcode = opcode.Value;
303}
304
305class RVInstIShift<bit arithshift, bits<3> funct3, RISCVOpcode opcode,
306                   dag outs, dag ins, string opcodestr, string argstr>
307    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
308  bits<6> shamt;
309  bits<5> rs1;
310  bits<5> rd;
311
312  let Inst{31} = 0;
313  let Inst{30} = arithshift;
314  let Inst{29-26} = 0;
315  let Inst{25-20} = shamt;
316  let Inst{19-15} = rs1;
317  let Inst{14-12} = funct3;
318  let Inst{11-7} = rd;
319  let Opcode = opcode.Value;
320}
321
322class RVInstIShiftW<bit arithshift, bits<3> funct3, RISCVOpcode opcode,
323                    dag outs, dag ins, string opcodestr, string argstr>
324    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
325  bits<5> shamt;
326  bits<5> rs1;
327  bits<5> rd;
328
329  let Inst{31} = 0;
330  let Inst{30} = arithshift;
331  let Inst{29-25} = 0;
332  let Inst{24-20} = shamt;
333  let Inst{19-15} = rs1;
334  let Inst{14-12} = funct3;
335  let Inst{11-7} = rd;
336  let Opcode = opcode.Value;
337}
338
339class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
340              string opcodestr, string argstr>
341    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatS> {
342  bits<12> imm12;
343  bits<5> rs2;
344  bits<5> rs1;
345
346  let Inst{31-25} = imm12{11-5};
347  let Inst{24-20} = rs2;
348  let Inst{19-15} = rs1;
349  let Inst{14-12} = funct3;
350  let Inst{11-7} = imm12{4-0};
351  let Opcode = opcode.Value;
352}
353
354class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
355              string opcodestr, string argstr>
356    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatB> {
357  bits<12> imm12;
358  bits<5> rs2;
359  bits<5> rs1;
360
361  let Inst{31} = imm12{11};
362  let Inst{30-25} = imm12{9-4};
363  let Inst{24-20} = rs2;
364  let Inst{19-15} = rs1;
365  let Inst{14-12} = funct3;
366  let Inst{11-8} = imm12{3-0};
367  let Inst{7} = imm12{10};
368  let Opcode = opcode.Value;
369}
370
371class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
372              string argstr>
373    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatU> {
374  bits<20> imm20;
375  bits<5> rd;
376
377  let Inst{31-12} = imm20;
378  let Inst{11-7} = rd;
379  let Opcode = opcode.Value;
380}
381
382class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
383              string argstr>
384    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatJ> {
385  bits<20> imm20;
386  bits<5> rd;
387
388  let Inst{31} = imm20{19};
389  let Inst{30-21} = imm20{9-0};
390  let Inst{20} = imm20{10};
391  let Inst{19-12} = imm20{18-11};
392  let Inst{11-7} = rd;
393  let Opcode = opcode.Value;
394}
395