106c3fb27SDimitry Andric//===-- RISCVInstrFormatsC.td - RISC-V C Instruction Formats -*- tablegen -*-=// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file describes the RISC-V C extension instruction formats. 100b57cec5SDimitry Andric// 110b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andricclass RVInst16<dag outs, dag ins, string opcodestr, string argstr, 140b57cec5SDimitry Andric list<dag> pattern, InstFormat format> 1506c3fb27SDimitry Andric : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> { 160b57cec5SDimitry Andric field bits<16> Inst; 170b57cec5SDimitry Andric // SoftFail is a field the disassembler can use to provide a way for 180b57cec5SDimitry Andric // instructions to not match without killing the whole decode process. It is 190b57cec5SDimitry Andric // mainly used for ARM, but Tablegen expects this field to exist or it fails 200b57cec5SDimitry Andric // to build the decode table. 210b57cec5SDimitry Andric field bits<16> SoftFail = 0; 220b57cec5SDimitry Andric let Size = 2; 230b57cec5SDimitry Andric} 240b57cec5SDimitry Andric 250b57cec5SDimitry Andricclass RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins, 260b57cec5SDimitry Andric string opcodestr, string argstr> 270b57cec5SDimitry Andric : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCR> { 280b57cec5SDimitry Andric bits<5> rs1; 290b57cec5SDimitry Andric bits<5> rs2; 300b57cec5SDimitry Andric 310b57cec5SDimitry Andric let Inst{15-12} = funct4; 320b57cec5SDimitry Andric let Inst{11-7} = rs1; 330b57cec5SDimitry Andric let Inst{6-2} = rs2; 340b57cec5SDimitry Andric let Inst{1-0} = opcode; 350b57cec5SDimitry Andric} 360b57cec5SDimitry Andric 370b57cec5SDimitry Andric// The immediate value encoding differs for each instruction, so each subclass 380b57cec5SDimitry Andric// is responsible for setting the appropriate bits in the Inst field. 390b57cec5SDimitry Andric// The bits Inst{6-2} must be set for each instruction. 400b57cec5SDimitry Andricclass RVInst16CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 410b57cec5SDimitry Andric string opcodestr, string argstr> 420b57cec5SDimitry Andric : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCI> { 430b57cec5SDimitry Andric bits<10> imm; 440b57cec5SDimitry Andric bits<5> rd; 450b57cec5SDimitry Andric 460b57cec5SDimitry Andric let Inst{15-13} = funct3; 470b57cec5SDimitry Andric let Inst{12} = imm{5}; 480b57cec5SDimitry Andric let Inst{11-7} = rd; 490b57cec5SDimitry Andric let Inst{1-0} = opcode; 500b57cec5SDimitry Andric} 510b57cec5SDimitry Andric 520b57cec5SDimitry Andric// The immediate value encoding differs for each instruction, so each subclass 530b57cec5SDimitry Andric// is responsible for setting the appropriate bits in the Inst field. 540b57cec5SDimitry Andric// The bits Inst{12-7} must be set for each instruction. 550b57cec5SDimitry Andricclass RVInst16CSS<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 560b57cec5SDimitry Andric string opcodestr, string argstr> 570b57cec5SDimitry Andric : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSS> { 580b57cec5SDimitry Andric bits<10> imm; 590b57cec5SDimitry Andric bits<5> rs2; 600b57cec5SDimitry Andric bits<5> rs1; 610b57cec5SDimitry Andric 620b57cec5SDimitry Andric let Inst{15-13} = funct3; 630b57cec5SDimitry Andric let Inst{6-2} = rs2; 640b57cec5SDimitry Andric let Inst{1-0} = opcode; 650b57cec5SDimitry Andric} 660b57cec5SDimitry Andric 670b57cec5SDimitry Andricclass RVInst16CIW<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 680b57cec5SDimitry Andric string opcodestr, string argstr> 690b57cec5SDimitry Andric : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCIW> { 700b57cec5SDimitry Andric bits<10> imm; 710b57cec5SDimitry Andric bits<3> rd; 720b57cec5SDimitry Andric 730b57cec5SDimitry Andric let Inst{15-13} = funct3; 740b57cec5SDimitry Andric let Inst{4-2} = rd; 750b57cec5SDimitry Andric let Inst{1-0} = opcode; 760b57cec5SDimitry Andric} 770b57cec5SDimitry Andric 780b57cec5SDimitry Andric// The immediate value encoding differs for each instruction, so each subclass 790b57cec5SDimitry Andric// is responsible for setting the appropriate bits in the Inst field. 800b57cec5SDimitry Andric// The bits Inst{12-10} and Inst{6-5} must be set for each instruction. 810b57cec5SDimitry Andricclass RVInst16CL<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 820b57cec5SDimitry Andric string opcodestr, string argstr> 830b57cec5SDimitry Andric : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCL> { 840b57cec5SDimitry Andric bits<3> rd; 850b57cec5SDimitry Andric bits<3> rs1; 860b57cec5SDimitry Andric 870b57cec5SDimitry Andric let Inst{15-13} = funct3; 880b57cec5SDimitry Andric let Inst{9-7} = rs1; 890b57cec5SDimitry Andric let Inst{4-2} = rd; 900b57cec5SDimitry Andric let Inst{1-0} = opcode; 910b57cec5SDimitry Andric} 920b57cec5SDimitry Andric 930b57cec5SDimitry Andric// The immediate value encoding differs for each instruction, so each subclass 940b57cec5SDimitry Andric// is responsible for setting the appropriate bits in the Inst field. 950b57cec5SDimitry Andric// The bits Inst{12-10} and Inst{6-5} must be set for each instruction. 960b57cec5SDimitry Andricclass RVInst16CS<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 970b57cec5SDimitry Andric string opcodestr, string argstr> 980b57cec5SDimitry Andric : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCS> { 990b57cec5SDimitry Andric bits<3> rs2; 1000b57cec5SDimitry Andric bits<3> rs1; 1010b57cec5SDimitry Andric 1020b57cec5SDimitry Andric let Inst{15-13} = funct3; 1030b57cec5SDimitry Andric let Inst{9-7} = rs1; 1040b57cec5SDimitry Andric let Inst{4-2} = rs2; 1050b57cec5SDimitry Andric let Inst{1-0} = opcode; 1060b57cec5SDimitry Andric} 1070b57cec5SDimitry Andric 1080b57cec5SDimitry Andricclass RVInst16CA<bits<6> funct6, bits<2> funct2, bits<2> opcode, dag outs, 1090b57cec5SDimitry Andric dag ins, string opcodestr, string argstr> 1100b57cec5SDimitry Andric : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCA> { 1110b57cec5SDimitry Andric bits<3> rs2; 1120b57cec5SDimitry Andric bits<3> rs1; 1130b57cec5SDimitry Andric 1140b57cec5SDimitry Andric let Inst{15-10} = funct6; 1150b57cec5SDimitry Andric let Inst{9-7} = rs1; 1160b57cec5SDimitry Andric let Inst{6-5} = funct2; 1170b57cec5SDimitry Andric let Inst{4-2} = rs2; 1180b57cec5SDimitry Andric let Inst{1-0} = opcode; 1190b57cec5SDimitry Andric} 1200b57cec5SDimitry Andric 1210b57cec5SDimitry Andricclass RVInst16CB<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 1220b57cec5SDimitry Andric string opcodestr, string argstr> 1230b57cec5SDimitry Andric : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCB> { 1240b57cec5SDimitry Andric bits<9> imm; 1250b57cec5SDimitry Andric bits<3> rs1; 1260b57cec5SDimitry Andric 1270b57cec5SDimitry Andric let Inst{15-13} = funct3; 1280b57cec5SDimitry Andric let Inst{9-7} = rs1; 1290b57cec5SDimitry Andric let Inst{1-0} = opcode; 1300b57cec5SDimitry Andric} 1310b57cec5SDimitry Andric 1320b57cec5SDimitry Andricclass RVInst16CJ<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 1330b57cec5SDimitry Andric string opcodestr, string argstr> 1340b57cec5SDimitry Andric : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCJ> { 1350b57cec5SDimitry Andric bits<11> offset; 1360b57cec5SDimitry Andric 1370b57cec5SDimitry Andric let Inst{15-13} = funct3; 1380b57cec5SDimitry Andric let Inst{12} = offset{10}; 1390b57cec5SDimitry Andric let Inst{11} = offset{3}; 1400b57cec5SDimitry Andric let Inst{10-9} = offset{8-7}; 1410b57cec5SDimitry Andric let Inst{8} = offset{9}; 1420b57cec5SDimitry Andric let Inst{7} = offset{5}; 1430b57cec5SDimitry Andric let Inst{6} = offset{6}; 1440b57cec5SDimitry Andric let Inst{5-3} = offset{2-0}; 1450b57cec5SDimitry Andric let Inst{2} = offset{4}; 1460b57cec5SDimitry Andric let Inst{1-0} = opcode; 1470b57cec5SDimitry Andric} 14806c3fb27SDimitry Andric 14906c3fb27SDimitry Andricclass RVInst16CU<bits<6> funct6, bits<5> funct5, bits<2> opcode, dag outs, 15006c3fb27SDimitry Andric dag ins, string opcodestr, string argstr> 15106c3fb27SDimitry Andric : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCU>{ 15206c3fb27SDimitry Andric bits<3> rd; 15306c3fb27SDimitry Andric 15406c3fb27SDimitry Andric let Inst{15-10} = funct6; 15506c3fb27SDimitry Andric let Inst{9-7} = rd; 15606c3fb27SDimitry Andric let Inst{6-2} = funct5; 15706c3fb27SDimitry Andric let Inst{1-0} = opcode; 15806c3fb27SDimitry Andric} 15906c3fb27SDimitry Andric 16006c3fb27SDimitry Andric// The immediate value encoding differs for each instruction, so each subclass 16106c3fb27SDimitry Andric// is responsible for setting the appropriate bits in the Inst field. 16206c3fb27SDimitry Andric// The bits Inst{6-5} must be set for each instruction. 16306c3fb27SDimitry Andricclass RVInst16CLB<bits<6> funct6, bits<2> opcode, dag outs, dag ins, 16406c3fb27SDimitry Andric string opcodestr, string argstr> 16506c3fb27SDimitry Andric : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCLB> { 16606c3fb27SDimitry Andric bits<3> rd; 16706c3fb27SDimitry Andric bits<3> rs1; 16806c3fb27SDimitry Andric 16906c3fb27SDimitry Andric let Inst{15-10} = funct6; 17006c3fb27SDimitry Andric let Inst{9-7} = rs1; 17106c3fb27SDimitry Andric let Inst{4-2} = rd; 17206c3fb27SDimitry Andric let Inst{1-0} = opcode; 17306c3fb27SDimitry Andric} 17406c3fb27SDimitry Andric 17506c3fb27SDimitry Andric// The immediate value encoding differs for each instruction, so each subclass 17606c3fb27SDimitry Andric// is responsible for setting the appropriate bits in the Inst field. 17706c3fb27SDimitry Andric// The bits Inst{5} must be set for each instruction. 17806c3fb27SDimitry Andricclass RVInst16CLH<bits<6> funct6, bit funct1, bits<2> opcode, dag outs, 17906c3fb27SDimitry Andric dag ins, string opcodestr, string argstr> 18006c3fb27SDimitry Andric : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCLH> { 18106c3fb27SDimitry Andric bits<3> rd; 18206c3fb27SDimitry Andric bits<3> rs1; 18306c3fb27SDimitry Andric 18406c3fb27SDimitry Andric let Inst{15-10} = funct6; 18506c3fb27SDimitry Andric let Inst{9-7} = rs1; 18606c3fb27SDimitry Andric let Inst{6} = funct1; 18706c3fb27SDimitry Andric let Inst{4-2} = rd; 18806c3fb27SDimitry Andric let Inst{1-0} = opcode; 18906c3fb27SDimitry Andric} 19006c3fb27SDimitry Andric 19106c3fb27SDimitry Andric// The immediate value encoding differs for each instruction, so each subclass 19206c3fb27SDimitry Andric// is responsible for setting the appropriate bits in the Inst field. 19306c3fb27SDimitry Andric// The bits Inst{6-5} must be set for each instruction. 19406c3fb27SDimitry Andricclass RVInst16CSB<bits<6> funct6, bits<2> opcode, dag outs, dag ins, 19506c3fb27SDimitry Andric string opcodestr, string argstr> 19606c3fb27SDimitry Andric : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSB> { 19706c3fb27SDimitry Andric bits<3> rs2; 19806c3fb27SDimitry Andric bits<3> rs1; 19906c3fb27SDimitry Andric 20006c3fb27SDimitry Andric let Inst{15-10} = funct6; 20106c3fb27SDimitry Andric let Inst{9-7} = rs1; 20206c3fb27SDimitry Andric let Inst{4-2} = rs2; 20306c3fb27SDimitry Andric let Inst{1-0} = opcode; 20406c3fb27SDimitry Andric} 20506c3fb27SDimitry Andric 20606c3fb27SDimitry Andric// The immediate value encoding differs for each instruction, so each subclass 20706c3fb27SDimitry Andric// is responsible for setting the appropriate bits in the Inst field. 20806c3fb27SDimitry Andric// The bits Inst{5} must be set for each instruction. 20906c3fb27SDimitry Andricclass RVInst16CSH<bits<6> funct6, bit funct1, bits<2> opcode, dag outs, 21006c3fb27SDimitry Andric dag ins, string opcodestr, string argstr> 21106c3fb27SDimitry Andric : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSH> { 21206c3fb27SDimitry Andric bits<3> rs2; 21306c3fb27SDimitry Andric bits<3> rs1; 21406c3fb27SDimitry Andric 21506c3fb27SDimitry Andric let Inst{15-10} = funct6; 21606c3fb27SDimitry Andric let Inst{9-7} = rs1; 21706c3fb27SDimitry Andric let Inst{6} = funct1; 21806c3fb27SDimitry Andric let Inst{4-2} = rs2; 21906c3fb27SDimitry Andric let Inst{1-0} = opcode; 22006c3fb27SDimitry Andric} 22106c3fb27SDimitry Andric 22206c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 22306c3fb27SDimitry Andric// Instruction classes for .insn directives 22406c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 22506c3fb27SDimitry Andric 22606c3fb27SDimitry Andricclass DirectiveInsnCR<dag outs, dag ins, string argstr> 22706c3fb27SDimitry Andric : RVInst16<outs, ins, "", "", [], InstFormatCR> { 22806c3fb27SDimitry Andric bits<2> opcode; 22906c3fb27SDimitry Andric bits<4> funct4; 23006c3fb27SDimitry Andric 23106c3fb27SDimitry Andric bits<5> rs2; 23206c3fb27SDimitry Andric bits<5> rd; 23306c3fb27SDimitry Andric 23406c3fb27SDimitry Andric let Inst{15-12} = funct4; 23506c3fb27SDimitry Andric let Inst{11-7} = rd; 23606c3fb27SDimitry Andric let Inst{6-2} = rs2; 23706c3fb27SDimitry Andric let Inst{1-0} = opcode; 23806c3fb27SDimitry Andric 23906c3fb27SDimitry Andric let AsmString = ".insn cr " # argstr; 24006c3fb27SDimitry Andric} 24106c3fb27SDimitry Andric 24206c3fb27SDimitry Andricclass DirectiveInsnCI<dag outs, dag ins, string argstr> 24306c3fb27SDimitry Andric : RVInst16<outs, ins, "", "", [], InstFormatCI> { 24406c3fb27SDimitry Andric bits<2> opcode; 24506c3fb27SDimitry Andric bits<3> funct3; 24606c3fb27SDimitry Andric 24706c3fb27SDimitry Andric bits<6> imm6; 24806c3fb27SDimitry Andric bits<5> rd; 24906c3fb27SDimitry Andric 25006c3fb27SDimitry Andric let Inst{15-13} = funct3; 25106c3fb27SDimitry Andric let Inst{12} = imm6{5}; 25206c3fb27SDimitry Andric let Inst{11-7} = rd; 25306c3fb27SDimitry Andric let Inst{6-2} = imm6{4-0}; 25406c3fb27SDimitry Andric let Inst{1-0} = opcode; 25506c3fb27SDimitry Andric 25606c3fb27SDimitry Andric let AsmString = ".insn ci " # argstr; 25706c3fb27SDimitry Andric} 25806c3fb27SDimitry Andric 25906c3fb27SDimitry Andricclass DirectiveInsnCIW<dag outs, dag ins, string argstr> 26006c3fb27SDimitry Andric : RVInst16<outs, ins, "", "", [], InstFormatCIW> { 26106c3fb27SDimitry Andric bits<2> opcode; 26206c3fb27SDimitry Andric bits<3> funct3; 26306c3fb27SDimitry Andric 26406c3fb27SDimitry Andric bits<8> imm8; 26506c3fb27SDimitry Andric bits<3> rd; 26606c3fb27SDimitry Andric 26706c3fb27SDimitry Andric let Inst{15-13} = funct3; 26806c3fb27SDimitry Andric let Inst{12-5} = imm8; 26906c3fb27SDimitry Andric let Inst{4-2} = rd; 27006c3fb27SDimitry Andric let Inst{1-0} = opcode; 27106c3fb27SDimitry Andric 27206c3fb27SDimitry Andric let AsmString = ".insn ciw " # argstr; 27306c3fb27SDimitry Andric} 27406c3fb27SDimitry Andric 27506c3fb27SDimitry Andricclass DirectiveInsnCSS<dag outs, dag ins, string argstr> 27606c3fb27SDimitry Andric : RVInst16<outs, ins, "", "", [], InstFormatCSS> { 27706c3fb27SDimitry Andric bits<2> opcode; 27806c3fb27SDimitry Andric bits<3> funct3; 27906c3fb27SDimitry Andric 28006c3fb27SDimitry Andric bits<6> imm6; 28106c3fb27SDimitry Andric bits<5> rs2; 28206c3fb27SDimitry Andric 28306c3fb27SDimitry Andric let Inst{15-13} = funct3; 28406c3fb27SDimitry Andric let Inst{12-7} = imm6; 28506c3fb27SDimitry Andric let Inst{6-2} = rs2; 28606c3fb27SDimitry Andric let Inst{1-0} = opcode; 28706c3fb27SDimitry Andric 28806c3fb27SDimitry Andric let AsmString = ".insn css " # argstr; 28906c3fb27SDimitry Andric} 29006c3fb27SDimitry Andric 29106c3fb27SDimitry Andricclass DirectiveInsnCL<dag outs, dag ins, string argstr> 29206c3fb27SDimitry Andric : RVInst16<outs, ins, "", "", [], InstFormatCL> { 29306c3fb27SDimitry Andric bits<2> opcode; 29406c3fb27SDimitry Andric bits<3> funct3; 29506c3fb27SDimitry Andric 29606c3fb27SDimitry Andric bits<5> imm5; 29706c3fb27SDimitry Andric bits<3> rd; 29806c3fb27SDimitry Andric bits<3> rs1; 29906c3fb27SDimitry Andric 30006c3fb27SDimitry Andric let Inst{15-13} = funct3; 30106c3fb27SDimitry Andric let Inst{12-10} = imm5{4-2}; 30206c3fb27SDimitry Andric let Inst{9-7} = rs1; 30306c3fb27SDimitry Andric let Inst{6-5} = imm5{1-0}; 30406c3fb27SDimitry Andric let Inst{4-2} = rd; 30506c3fb27SDimitry Andric let Inst{1-0} = opcode; 30606c3fb27SDimitry Andric 30706c3fb27SDimitry Andric let AsmString = ".insn cl " # argstr; 30806c3fb27SDimitry Andric} 30906c3fb27SDimitry Andric 31006c3fb27SDimitry Andricclass DirectiveInsnCS<dag outs, dag ins, string argstr> 31106c3fb27SDimitry Andric : RVInst16<outs, ins, "", "", [], InstFormatCS> { 31206c3fb27SDimitry Andric bits<2> opcode; 31306c3fb27SDimitry Andric bits<3> funct3; 31406c3fb27SDimitry Andric 31506c3fb27SDimitry Andric bits<5> imm5; 31606c3fb27SDimitry Andric bits<3> rs2; 31706c3fb27SDimitry Andric bits<3> rs1; 31806c3fb27SDimitry Andric 31906c3fb27SDimitry Andric let Inst{15-13} = funct3; 32006c3fb27SDimitry Andric let Inst{12-10} = imm5{4-2}; 32106c3fb27SDimitry Andric let Inst{9-7} = rs1; 32206c3fb27SDimitry Andric let Inst{6-5} = imm5{1-0}; 32306c3fb27SDimitry Andric let Inst{4-2} = rs2; 32406c3fb27SDimitry Andric let Inst{1-0} = opcode; 32506c3fb27SDimitry Andric 32606c3fb27SDimitry Andric let AsmString = ".insn cs " # argstr; 32706c3fb27SDimitry Andric} 32806c3fb27SDimitry Andric 32906c3fb27SDimitry Andricclass DirectiveInsnCA<dag outs, dag ins, string argstr> 33006c3fb27SDimitry Andric : RVInst16<outs, ins, "", "", [], InstFormatCA> { 33106c3fb27SDimitry Andric bits<2> opcode; 33206c3fb27SDimitry Andric bits<6> funct6; 33306c3fb27SDimitry Andric bits<2> funct2; 33406c3fb27SDimitry Andric 33506c3fb27SDimitry Andric bits<3> rd; 33606c3fb27SDimitry Andric bits<3> rs2; 33706c3fb27SDimitry Andric 33806c3fb27SDimitry Andric let Inst{15-10} = funct6; 33906c3fb27SDimitry Andric let Inst{9-7} = rd; 34006c3fb27SDimitry Andric let Inst{6-5} = funct2; 34106c3fb27SDimitry Andric let Inst{4-2} = rs2; 34206c3fb27SDimitry Andric let Inst{1-0} = opcode; 34306c3fb27SDimitry Andric 34406c3fb27SDimitry Andric let AsmString = ".insn ca " # argstr; 34506c3fb27SDimitry Andric} 34606c3fb27SDimitry Andric 34706c3fb27SDimitry Andricclass DirectiveInsnCB<dag outs, dag ins, string argstr> 34806c3fb27SDimitry Andric : RVInst16<outs, ins, "", "", [], InstFormatCB> { 34906c3fb27SDimitry Andric bits<2> opcode; 35006c3fb27SDimitry Andric bits<3> funct3; 35106c3fb27SDimitry Andric 35206c3fb27SDimitry Andric bits<8> imm8; 35306c3fb27SDimitry Andric bits<3> rs1; 35406c3fb27SDimitry Andric 35506c3fb27SDimitry Andric let Inst{15-13} = funct3; 35606c3fb27SDimitry Andric let Inst{12} = imm8{7}; 35706c3fb27SDimitry Andric let Inst{11-10} = imm8{3-2}; 35806c3fb27SDimitry Andric let Inst{9-7} = rs1; 35906c3fb27SDimitry Andric let Inst{6-5} = imm8{6-5}; 36006c3fb27SDimitry Andric let Inst{4-3} = imm8{1-0}; 36106c3fb27SDimitry Andric let Inst{2} = imm8{4}; 36206c3fb27SDimitry Andric let Inst{1-0} = opcode; 36306c3fb27SDimitry Andric 36406c3fb27SDimitry Andric let AsmString = ".insn cb " # argstr; 36506c3fb27SDimitry Andric} 36606c3fb27SDimitry Andric 36706c3fb27SDimitry Andricclass DirectiveInsnCJ<dag outs, dag ins, string argstr> 36806c3fb27SDimitry Andric : RVInst16<outs, ins, "", "", [], InstFormatCJ> { 36906c3fb27SDimitry Andric bits<2> opcode; 37006c3fb27SDimitry Andric bits<3> funct3; 37106c3fb27SDimitry Andric 37206c3fb27SDimitry Andric bits<11> imm11; 37306c3fb27SDimitry Andric 37406c3fb27SDimitry Andric let Inst{15-13} = funct3; 37506c3fb27SDimitry Andric let Inst{12} = imm11{10}; 37606c3fb27SDimitry Andric let Inst{11} = imm11{3}; 37706c3fb27SDimitry Andric let Inst{10-9} = imm11{8-7}; 37806c3fb27SDimitry Andric let Inst{8} = imm11{9}; 37906c3fb27SDimitry Andric let Inst{7} = imm11{5}; 38006c3fb27SDimitry Andric let Inst{6} = imm11{6}; 38106c3fb27SDimitry Andric let Inst{5-3} = imm11{2-0}; 38206c3fb27SDimitry Andric let Inst{2} = imm11{4}; 38306c3fb27SDimitry Andric let Inst{1-0} = opcode; 38406c3fb27SDimitry Andric 38506c3fb27SDimitry Andric let AsmString = ".insn cj " # argstr; 38606c3fb27SDimitry Andric} 387