1//===-- RISCVInstrFormatsC.td - RISC-V C Instruction Formats -*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//  This file describes the RISC-V C extension instruction formats.
10//
11//===----------------------------------------------------------------------===//
12
13class RVInst16<dag outs, dag ins, string opcodestr, string argstr,
14               list<dag> pattern, InstFormat format>
15    : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
16  field bits<16> Inst;
17  // SoftFail is a field the disassembler can use to provide a way for
18  // instructions to not match without killing the whole decode process. It is
19  // mainly used for ARM, but Tablegen expects this field to exist or it fails
20  // to build the decode table.
21  field bits<16> SoftFail = 0;
22  let Size = 2;
23}
24
25class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,
26                 string opcodestr, string argstr>
27    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCR> {
28  bits<5> rs1;
29  bits<5> rs2;
30
31  let Inst{15-12} = funct4;
32  let Inst{11-7} = rs1;
33  let Inst{6-2} = rs2;
34  let Inst{1-0} = opcode;
35}
36
37// The immediate value encoding differs for each instruction, so each subclass
38// is responsible for setting the appropriate bits in the Inst field.
39// The bits Inst{6-2} must be set for each instruction.
40class RVInst16CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
41                 string opcodestr, string argstr>
42    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCI> {
43  bits<10> imm;
44  bits<5> rd;
45
46  let Inst{15-13} = funct3;
47  let Inst{12} = imm{5};
48  let Inst{11-7} = rd;
49  let Inst{1-0} = opcode;
50}
51
52// The immediate value encoding differs for each instruction, so each subclass
53// is responsible for setting the appropriate bits in the Inst field.
54// The bits Inst{12-7} must be set for each instruction.
55class RVInst16CSS<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
56                  string opcodestr, string argstr>
57    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSS> {
58  bits<10> imm;
59  bits<5> rs2;
60  bits<5> rs1;
61
62  let Inst{15-13} = funct3;
63  let Inst{6-2} = rs2;
64  let Inst{1-0} = opcode;
65}
66
67class RVInst16CIW<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
68                  string opcodestr, string argstr>
69    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCIW> {
70  bits<10> imm;
71  bits<3> rd;
72
73  let Inst{15-13} = funct3;
74  let Inst{4-2} = rd;
75  let Inst{1-0} = opcode;
76}
77
78// The immediate value encoding differs for each instruction, so each subclass
79// is responsible for setting the appropriate bits in the Inst field.
80// The bits Inst{12-10} and Inst{6-5} must be set for each instruction.
81class RVInst16CL<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
82                 string opcodestr, string argstr>
83    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCL> {
84  bits<3> rd;
85  bits<3> rs1;
86
87  let Inst{15-13} = funct3;
88  let Inst{9-7} = rs1;
89  let Inst{4-2} = rd;
90  let Inst{1-0} = opcode;
91}
92
93// The immediate value encoding differs for each instruction, so each subclass
94// is responsible for setting the appropriate bits in the Inst field.
95// The bits Inst{12-10} and Inst{6-5} must be set for each instruction.
96class RVInst16CS<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
97                 string opcodestr, string argstr>
98    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCS> {
99  bits<3> rs2;
100  bits<3> rs1;
101
102  let Inst{15-13} = funct3;
103  let Inst{9-7} = rs1;
104  let Inst{4-2} = rs2;
105  let Inst{1-0} = opcode;
106}
107
108class RVInst16CA<bits<6> funct6, bits<2> funct2, bits<2> opcode, dag outs,
109                 dag ins, string opcodestr, string argstr>
110    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCA> {
111  bits<3> rs2;
112  bits<3> rs1;
113
114  let Inst{15-10} = funct6;
115  let Inst{9-7} = rs1;
116  let Inst{6-5} = funct2;
117  let Inst{4-2} = rs2;
118  let Inst{1-0} = opcode;
119}
120
121class RVInst16CB<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
122                 string opcodestr, string argstr>
123    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCB> {
124  bits<9> imm;
125  bits<3> rs1;
126
127  let Inst{15-13} = funct3;
128  let Inst{9-7} = rs1;
129  let Inst{1-0} = opcode;
130}
131
132class RVInst16CJ<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
133                 string opcodestr, string argstr>
134    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCJ> {
135  bits<11> offset;
136
137  let Inst{15-13} = funct3;
138  let Inst{12} = offset{10};
139  let Inst{11} = offset{3};
140  let Inst{10-9} = offset{8-7};
141  let Inst{8} = offset{9};
142  let Inst{7} = offset{5};
143  let Inst{6} = offset{6};
144  let Inst{5-3} = offset{2-0};
145  let Inst{2} = offset{4};
146  let Inst{1-0} = opcode;
147}
148
149class RVInst16CU<bits<6> funct6, bits<5> funct5, bits<2> opcode, dag outs,
150                 dag ins, string opcodestr, string argstr>
151    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCU>{
152  bits<3> rd;
153
154  let Inst{15-10} = funct6;
155  let Inst{9-7} = rd;
156  let Inst{6-2} = funct5;
157  let Inst{1-0} = opcode;
158}
159
160// The immediate value encoding differs for each instruction, so each subclass
161// is responsible for setting the appropriate bits in the Inst field.
162// The bits Inst{6-5} must be set for each instruction.
163class RVInst16CLB<bits<6> funct6, bits<2> opcode, dag outs, dag ins,
164                  string opcodestr, string argstr>
165    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCLB> {
166  bits<3> rd;
167  bits<3> rs1;
168
169  let Inst{15-10} = funct6;
170  let Inst{9-7} = rs1;
171  let Inst{4-2} = rd;
172  let Inst{1-0} = opcode;
173}
174
175// The immediate value encoding differs for each instruction, so each subclass
176// is responsible for setting the appropriate bits in the Inst field.
177// The bits Inst{5} must be set for each instruction.
178class RVInst16CLH<bits<6> funct6, bit funct1, bits<2> opcode, dag outs,
179                  dag ins, string opcodestr, string argstr>
180    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCLH> {
181  bits<3> rd;
182  bits<3> rs1;
183
184  let Inst{15-10} = funct6;
185  let Inst{9-7} = rs1;
186  let Inst{6} = funct1;
187  let Inst{4-2} = rd;
188  let Inst{1-0} = opcode;
189}
190
191// The immediate value encoding differs for each instruction, so each subclass
192// is responsible for setting the appropriate bits in the Inst field.
193// The bits Inst{6-5} must be set for each instruction.
194class RVInst16CSB<bits<6> funct6, bits<2> opcode, dag outs, dag ins,
195                  string opcodestr, string argstr>
196    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSB> {
197  bits<3> rs2;
198  bits<3> rs1;
199
200  let Inst{15-10} = funct6;
201  let Inst{9-7} = rs1;
202  let Inst{4-2} = rs2;
203  let Inst{1-0} = opcode;
204}
205
206// The immediate value encoding differs for each instruction, so each subclass
207// is responsible for setting the appropriate bits in the Inst field.
208// The bits Inst{5} must be set for each instruction.
209class RVInst16CSH<bits<6> funct6, bit funct1, bits<2> opcode, dag outs,
210                  dag ins, string opcodestr, string argstr>
211    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSH> {
212  bits<3> rs2;
213  bits<3> rs1;
214
215  let Inst{15-10} = funct6;
216  let Inst{9-7} = rs1;
217  let Inst{6} = funct1;
218  let Inst{4-2} = rs2;
219  let Inst{1-0} = opcode;
220}
221
222//===----------------------------------------------------------------------===//
223// Instruction classes for .insn directives
224//===----------------------------------------------------------------------===//
225
226class DirectiveInsnCR<dag outs, dag ins, string argstr>
227  : RVInst16<outs, ins, "", "", [], InstFormatCR> {
228  bits<2> opcode;
229  bits<4> funct4;
230
231  bits<5> rs2;
232  bits<5> rd;
233
234  let Inst{15-12} = funct4;
235  let Inst{11-7} = rd;
236  let Inst{6-2} = rs2;
237  let Inst{1-0} = opcode;
238
239  let AsmString = ".insn cr " # argstr;
240}
241
242class DirectiveInsnCI<dag outs, dag ins, string argstr>
243  : RVInst16<outs, ins, "", "", [], InstFormatCI> {
244  bits<2> opcode;
245  bits<3> funct3;
246
247  bits<6> imm6;
248  bits<5> rd;
249
250  let Inst{15-13} = funct3;
251  let Inst{12} = imm6{5};
252  let Inst{11-7} = rd;
253  let Inst{6-2} = imm6{4-0};
254  let Inst{1-0} = opcode;
255
256  let AsmString = ".insn ci " # argstr;
257}
258
259class DirectiveInsnCIW<dag outs, dag ins, string argstr>
260  : RVInst16<outs, ins, "", "", [], InstFormatCIW> {
261  bits<2> opcode;
262  bits<3> funct3;
263
264  bits<8> imm8;
265  bits<3> rd;
266
267  let Inst{15-13} = funct3;
268  let Inst{12-5} = imm8;
269  let Inst{4-2} = rd;
270  let Inst{1-0} = opcode;
271
272  let AsmString = ".insn ciw " # argstr;
273}
274
275class DirectiveInsnCSS<dag outs, dag ins, string argstr>
276  : RVInst16<outs, ins, "", "", [], InstFormatCSS> {
277  bits<2> opcode;
278  bits<3> funct3;
279
280  bits<6> imm6;
281  bits<5> rs2;
282
283  let Inst{15-13} = funct3;
284  let Inst{12-7} = imm6;
285  let Inst{6-2} = rs2;
286  let Inst{1-0} = opcode;
287
288  let AsmString = ".insn css " # argstr;
289}
290
291class DirectiveInsnCL<dag outs, dag ins, string argstr>
292  : RVInst16<outs, ins, "", "", [], InstFormatCL> {
293  bits<2> opcode;
294  bits<3> funct3;
295
296  bits<5> imm5;
297  bits<3> rd;
298  bits<3> rs1;
299
300  let Inst{15-13} = funct3;
301  let Inst{12-10} = imm5{4-2};
302  let Inst{9-7} = rs1;
303  let Inst{6-5} = imm5{1-0};
304  let Inst{4-2} = rd;
305  let Inst{1-0} = opcode;
306
307  let AsmString = ".insn cl " # argstr;
308}
309
310class DirectiveInsnCS<dag outs, dag ins, string argstr>
311  : RVInst16<outs, ins, "", "", [], InstFormatCS> {
312  bits<2> opcode;
313  bits<3> funct3;
314
315  bits<5> imm5;
316  bits<3> rs2;
317  bits<3> rs1;
318
319  let Inst{15-13} = funct3;
320  let Inst{12-10} = imm5{4-2};
321  let Inst{9-7} = rs1;
322  let Inst{6-5} = imm5{1-0};
323  let Inst{4-2} = rs2;
324  let Inst{1-0} = opcode;
325
326  let AsmString = ".insn cs " # argstr;
327}
328
329class DirectiveInsnCA<dag outs, dag ins, string argstr>
330  : RVInst16<outs, ins, "", "", [], InstFormatCA> {
331  bits<2> opcode;
332  bits<6> funct6;
333  bits<2> funct2;
334
335  bits<3> rd;
336  bits<3> rs2;
337
338  let Inst{15-10} = funct6;
339  let Inst{9-7} = rd;
340  let Inst{6-5} = funct2;
341  let Inst{4-2} = rs2;
342  let Inst{1-0} = opcode;
343
344  let AsmString = ".insn ca " # argstr;
345}
346
347class DirectiveInsnCB<dag outs, dag ins, string argstr>
348  : RVInst16<outs, ins, "", "", [], InstFormatCB> {
349  bits<2> opcode;
350  bits<3> funct3;
351
352  bits<8> imm8;
353  bits<3> rs1;
354
355  let Inst{15-13} = funct3;
356  let Inst{12} = imm8{7};
357  let Inst{11-10} = imm8{3-2};
358  let Inst{9-7} = rs1;
359  let Inst{6-5} = imm8{6-5};
360  let Inst{4-3} = imm8{1-0};
361  let Inst{2} = imm8{4};
362  let Inst{1-0} = opcode;
363
364  let AsmString = ".insn cb " # argstr;
365}
366
367class DirectiveInsnCJ<dag outs, dag ins, string argstr>
368  : RVInst16<outs, ins, "", "", [], InstFormatCJ> {
369  bits<2> opcode;
370  bits<3> funct3;
371
372  bits<11> imm11;
373
374  let Inst{15-13} = funct3;
375  let Inst{12} = imm11{10};
376  let Inst{11} = imm11{3};
377  let Inst{10-9} = imm11{8-7};
378  let Inst{8} = imm11{9};
379  let Inst{7} = imm11{5};
380  let Inst{6} = imm11{6};
381  let Inst{5-3} = imm11{2-0};
382  let Inst{2} = imm11{4};
383  let Inst{1-0} = opcode;
384
385  let AsmString = ".insn cj " # argstr;
386}
387