1 //===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the RISCV implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 14 #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 15 16 #include "RISCVRegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 #include "llvm/IR/DiagnosticInfo.h" 19 20 #define GET_INSTRINFO_HEADER 21 #include "RISCVGenInstrInfo.inc" 22 23 namespace llvm { 24 25 class RISCVSubtarget; 26 27 class RISCVInstrInfo : public RISCVGenInstrInfo { 28 29 public: 30 explicit RISCVInstrInfo(RISCVSubtarget &STI); 31 32 MCInst getNop() const override; 33 34 unsigned isLoadFromStackSlot(const MachineInstr &MI, 35 int &FrameIndex) const override; 36 unsigned isStoreToStackSlot(const MachineInstr &MI, 37 int &FrameIndex) const override; 38 39 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 40 const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, 41 bool KillSrc) const override; 42 43 void storeRegToStackSlot(MachineBasicBlock &MBB, 44 MachineBasicBlock::iterator MBBI, Register SrcReg, 45 bool IsKill, int FrameIndex, 46 const TargetRegisterClass *RC, 47 const TargetRegisterInfo *TRI) const override; 48 49 void loadRegFromStackSlot(MachineBasicBlock &MBB, 50 MachineBasicBlock::iterator MBBI, Register DstReg, 51 int FrameIndex, const TargetRegisterClass *RC, 52 const TargetRegisterInfo *TRI) const override; 53 54 // Materializes the given integer Val into DstReg. 55 void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 56 const DebugLoc &DL, Register DstReg, uint64_t Val, 57 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; 58 59 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 60 61 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 62 MachineBasicBlock *&FBB, 63 SmallVectorImpl<MachineOperand> &Cond, 64 bool AllowModify) const override; 65 66 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 67 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 68 const DebugLoc &dl, 69 int *BytesAdded = nullptr) const override; 70 71 unsigned insertIndirectBranch(MachineBasicBlock &MBB, 72 MachineBasicBlock &NewDestBB, 73 const DebugLoc &DL, int64_t BrOffset, 74 RegScavenger *RS = nullptr) const override; 75 76 unsigned removeBranch(MachineBasicBlock &MBB, 77 int *BytesRemoved = nullptr) const override; 78 79 bool 80 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 81 82 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; 83 84 bool isBranchOffsetInRange(unsigned BranchOpc, 85 int64_t BrOffset) const override; 86 87 bool isAsCheapAsAMove(const MachineInstr &MI) const override; 88 89 Optional<DestSourcePair> 90 isCopyInstrImpl(const MachineInstr &MI) const override; 91 92 bool verifyInstruction(const MachineInstr &MI, 93 StringRef &ErrInfo) const override; 94 95 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, 96 const MachineOperand *&BaseOp, 97 int64_t &Offset, unsigned &Width, 98 const TargetRegisterInfo *TRI) const; 99 100 bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 101 const MachineInstr &MIb) const override; 102 103 104 std::pair<unsigned, unsigned> 105 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 106 107 ArrayRef<std::pair<unsigned, const char *>> 108 getSerializableDirectMachineOperandTargetFlags() const override; 109 110 // Return true if the function can safely be outlined from. 111 virtual bool 112 isFunctionSafeToOutlineFrom(MachineFunction &MF, 113 bool OutlineFromLinkOnceODRs) const override; 114 115 // Return true if MBB is safe to outline from, and return any target-specific 116 // information in Flags. 117 virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, 118 unsigned &Flags) const override; 119 120 // Calculate target-specific information for a set of outlining candidates. 121 outliner::OutlinedFunction getOutliningCandidateInfo( 122 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; 123 124 // Return if/how a given MachineInstr should be outlined. 125 virtual outliner::InstrType 126 getOutliningType(MachineBasicBlock::iterator &MBBI, 127 unsigned Flags) const override; 128 129 // Insert a custom frame for outlined functions. 130 virtual void 131 buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 132 const outliner::OutlinedFunction &OF) const override; 133 134 // Insert a call to an outlined function into a given basic block. 135 virtual MachineBasicBlock::iterator 136 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 137 MachineBasicBlock::iterator &It, MachineFunction &MF, 138 const outliner::Candidate &C) const override; 139 140 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 141 unsigned &SrcOpIdx2) const override; 142 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 143 unsigned OpIdx1, 144 unsigned OpIdx2) const override; 145 146 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MBB, 147 MachineInstr &MI, 148 LiveVariables *LV) const override; 149 150 Register getVLENFactoredAmount( 151 MachineFunction &MF, MachineBasicBlock &MBB, 152 MachineBasicBlock::iterator II, const DebugLoc &DL, int64_t Amount, 153 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; 154 155 // Returns true if the given MI is an RVV instruction opcode for which we may 156 // expect to see a FrameIndex operand. When CheckFIs is true, the instruction 157 // must contain at least one FrameIndex operand. 158 bool isRVVSpill(const MachineInstr &MI, bool CheckFIs) const; 159 160 Optional<std::pair<unsigned, unsigned>> 161 isRVVSpillForZvlsseg(unsigned Opcode) const; 162 163 protected: 164 const RISCVSubtarget &STI; 165 }; 166 167 namespace RISCVVPseudosTable { 168 169 struct PseudoInfo { 170 uint16_t Pseudo; 171 uint16_t BaseInstr; 172 }; 173 174 #define GET_RISCVVPseudosTable_DECL 175 #include "RISCVGenSearchableTables.inc" 176 177 } // end namespace RISCVVPseudosTable 178 179 } // end namespace llvm 180 #endif 181